MODULE2-Routing ADVANVECD VLSI VTU2024.pdf
- 1. Routing
- 2. Introduction ❖ Once the designer has ❖ Floorplanned a chip ❖ The logic cells within the flexible blocks have been placed ❖ Time to make the connections by routing the chip. ❖ This is still a hard problem that is made easier by dividing it into smaller problems. ❖ Routing is usually split into ❖ Global routing followed by detailed routing . •241
- 3. •-collection of standard cells with no room set aside yet for routing The Starting Point of Floor planning and lacement steps for the vertbi decoder
- 4. •243 The starting point of floorplaning and placement steps for the viterbi decoder • Small boxes that look like bricks - outlines of the standard cells. • Largest standard cells, at the bottom of the display (labeled dfctnb) - 188 D flipflops. • '+' symbols -drawing origins of the standard cells—for the D flip-flops they are shifted to the left and below the logic cell bottom left-hand corner. • Large box surrounding all the logic cells - estimated chip size. • (This is a screen shot from Cadence Cell Ensemble.)
- 5. The viterbi decoder after floorplanning •244
- 6. •FIGURE 17.1 The core of the Viterbi decoder chip after placement (a screen shot from Cadence Cell Ensemble) •245
- 7. •FIGURE 17.2 The core of the Viterbi decoder chip after the completion of global and detailed routing (a screen shot from Cadence Cell Ensemble). This chip uses two-level metal. Although you cannot see the difference, m1 runs in the horizontal direction and m2 in the vertical direction. •246
- 8. •247 Global Routing • The details of global routing differ slightly between – cell-based ASICs, gate arrays, and FPGAs, but the principles are the same. • A global router does not make any connections, it just plans them. • Global route the whole chip (or large pieces if it is a large chip) before detail routing the whole chip (or the pieces).
- 9. •248 Goals and Objectives • Input to routing – Floorplan that includes the locations of all the fixed and flexible blocks; – Placement information for flexible blocks; • Locations of all the logic cells. • Goal of global routing – To provide complete instructions to the detailed router on where to route every net. • Objectives of global routing – Minimize the total interconnect length. – Maximize the probability that the detailed router can complete the routing. – Minimize the critical path delay.
- 10. •257 Global Routing Methods • Many of the methods used in global routing are based on the solutions to the tree on a graph problem. • Sequential routing : One approach to global routing takes each net in turn and calculates the shortest path using tree on graph algorithms—with the added restriction of using the available channels. Disadvantage: • As a sequential routing algorithm proceeds, some channels will become more congested since they hold more interconnects than others. • In the case of FPGAs and channeled gate arrays, the channels have a fixed channel capacity and can only hold a certain number of interconnects.
- 11. •258 Global Routing Methods (contd.,) • There are two different ways that a global router normally handles this problem. 1. Order independent Routing 2. Order dependent Routing • Order-independent routing, a global router proceeds by routing each net, ignoring how crowded the channels are. Whether a particular net is processed first or last does not matter, the channel assignment will be the same. • Order-independent routing, after all the interconnects are assigned to channels, the global router returns to those channels that are the most crowded and reassigns some interconnects to other, less crowded, channels. • Order dependent :A global router can consider the number of interconnects already placed in various channels as it proceeds. In this case the global routing is order dependent —the routing is still sequential, but now the order of processing the nets will affect the results. • Iterative improvement or simulated annealing may be applied to the solutions found from both order-dependent and order-independent
- 12. •259 Global Routing Methods (contd.,) • Hierarchical routing handles all nets at a particular level at once. • Rather than handling all of the nets on the chip at the same time, the global- routing problem is made more tractable by dividing the chip area into levels of hierarchy. • By considering only one level of hierarchy at a time the size of the problem is reduced at each level. • There are two ways to traverse the levels of hierarchy. • top-down approach :- Starting at the whole chip, or highest level, and proceeding down to the logic cells. • The bottom-up approach starts at the lowest level of
- 13. •260 Global Routing • There are two types of areas to global route: – between blocks – inside the flexible blocks
- 14. Global Routing Between Blocks •FIGURE 17.4 Global routing for a cell-based ASIC formulated as a graph problem. (a) A cell-based ASIC with numbered channels. (b) The channels form the edges of a graph. (c) The channel-intersection graph. Each channel corresponds to an edge on a graph whose weight corresponds to the channel length. •261
- 15. Global Routing Between Blocks ( contd.,) •FIGURE 17.5 Finding paths in global routing. (a) A cell-based ASIC showing a single net with a fanout of four (five terminals). We have to order the numbered channels to complete the interconnect path for terminals A1 through F1. (b) The terminals are projected to the center of the nearest channel, forming a graph. A minimum-length tree for the net that uses the channels and takes into account the channel capacities. (c) The minimum-length tree does not necessarily correspond to minimum delay. If we wish to minimize the delay from terminal A1 to D1, a different tree might be better. •262
- 16. Global Routing Between Blocks ( contd.,) • Global routing is very similar for cell-based ASICs and gate arrays, but there is a very important difference between the types of channels in these ASICs. • In channeled gate-arrays and FPGAs the size, number, and location of channels are fixed. • Advantage - the global router can allocate as many interconnects to each channel as it likes, since that space is committed anyway. • Disadvantage - there is a maximum number of interconnects that each channel can hold. • If the global router needs more room, even in just one channel on the whole chip, the designer has to repeat the placement-and-routing steps and try again (or use a bigger chip). •263
- 17. •268 Back-annotation • The global router can give not just an estimate of the total net length (which was all we knew at the placement stage), but the resistance and capacitance of each path in each net. This RC information is used to calculate net delays. • Back-annotate this net delay information – to the synthesis tool for in-place optimization or – to a timing verifier to make sure there are no timing surprises. • Differences in timing predictions at this point arise due to the different ways in which the placement algorithms estimate the paths and the way the global router actually builds the paths.