Principles of Combinational Logic: Definition of combinational logic, canonical forms, Generation of switching equations from truth tables, Karnaugh maps-3,4,5 variables, Incompletely specified functions (Don‘t care terms) Simplifying Max term equations
This document discusses combinational logic circuits using MSI (Medium Scale Integration) and LSI (Large Scale Integration) components. It covers various MSI components like adders, decoders, encoders, multiplexers that are used as basic building blocks. Specific circuits discussed include 4-bit parallel adder, BCD adder, magnitude comparator, priority encoder, octal to binary encoder, decoder and their applications in implementing Boolean functions using multiplexers.
This document provides an overview of logic gates and digital logic circuits. It defines common logic gates like AND, OR, NOT, NAND and NOR. It describes transistor-transistor logic (TTL) and complementary metal-oxide-semiconductor (CMOS) logic families and their characteristics. Examples of logic circuits using TTL and CMOS gates are also presented.
Encoders convert decimal input to binary coded decimal (BCD) output, while decoders convert BCD input to decimal output displayed on a 7-segment display. An example encoder converts decimal numbers to their BCD coded form, while an example decoder converts BCD codes into the decimal numbers they represent, which are then shown on a 7-segment LED display. The document provides examples of encodings and decoding between decimal, BCD, and 7-segment display representations and tests the reader with questions about decoding BCD inputs.
Programmable logic devices (PLDs) allow users to implement digital logic designs on a single chip. PLDs have advantages over traditional integrated circuits like lower costs for lower production volumes and shorter design times. Common types of PLDs include simple programmable logic devices like PALs, GALs, and CPLDs. PLDs are configured using memory like SRAM, EPROM, EEPROM, or flash to store the programmed logic pattern. Reprogrammability allows PLDs to be reused for different logic functions.
The document discusses various techniques for line coding used to transmit digital data over communication channels. It describes several line coding schemes including unipolar, polar, and bipolar coding, as well as specific schemes like non-return to zero, return to zero, and Manchester coding. These coding techniques are used to represent digital signals for transmission and help address issues like inter-symbol interference caused by the band-limited nature of communication channels.
The document discusses different types of flow control instructions in assembly language including conditional jump instructions, unconditional jump instructions, compare instructions, and looping structures. Conditional jump instructions like JG transfer control based on condition flags. Looping structures include for, while, and repeat loops. High-level language equivalents like if-then, if-then-else, and case statements are also covered.
Question bank on digital electronics. Total 194 questions. Covering questions on basics of digital electronics, number systems, digital gates, logic families, the sum of product, the product of sum, boolean theorem, karnaugh map, coders, etc.
This document presents Booth's radix-4 algorithm for performing binary multiplication using an ALU. It explains that Booth's algorithm reduces the number of partial products generated during multiplication by grouping consecutive zeros and ones. It then describes the radix-2 Booth's algorithm and provides an example. The drawbacks of radix-2 are discussed, such as its inefficiency with isolated ones. Next, the radix-4 coding technique is presented and an example is shown. Finally, VHDL simulation code is presented to simulate multiplication using radix-4 algorithm.
This document discusses hardware description languages used in electronics design. It describes how HDLs like VHDL and Verilog are used to program digital and mixed-signal circuits. Simulation allows validation of the design against specifications. The document also discusses formal verification using property specification languages and different modeling styles for Verilog like gate-level, dataflow, and behavioral modeling.
The document discusses various techniques for accelerating the multiplication process, including shift-and-add, Booth's recoding, and higher radix multipliers. Booth's recoding maps digit sets to [-1,1] to skip additions when partial products are zero. Modified Booth's recoding improves on this by considering three adjacent bits to encode multipliers into [-2,2], allowing the use of radix-4 grouping to reduce the number of partial product additions. Modern multipliers apply Modified Booth's Recoding to take advantage of its higher radix structure.
The document discusses encoders, decoders, multiplexers (MUX), and how they can be used to implement digital logic functions. It provides examples of using 4-to-1, 8-to-1 and 10-to-1 MUX to implement functions. It also gives examples of 4-to-2, 8-to-3 and 10-to-4 encoders. Decoder examples include a 2-to-4 and 3-to-8 binary decoder. The document explains how decoders can be used as logic building blocks to realize Boolean functions. It poses questions to be answered using terms like MUX, DEMUX, encoder, decoder.
The Quine-McCluskey method is an algorithm for minimization of Boolean functions that was developed in 1956. It can be used to minimize functions with more than 5 bits, where Karnaugh maps are limited to 5 bits. The method has 4 main steps: 1) generate prime implicants, 2) construct a prime implicants table, 3) reduce prime implicants, and 4) solve the prime implicants table. An example is provided to illustrate the application of the method, starting with a list of minterms and ending with the minimized sum of products expression.
Here are the key points about NMOS transistor operation in the subthreshold region:
- When 0 < Vgs < Vt, a depletion region forms in the channel due to the electric field repelling majority carriers (holes).
- This depletion region means there are no carriers to conduct current through the channel.
- Only a small leakage current flows, as the channel is not fully "turned on".
- The transistor is not fully on or off in this region - it is said to be weakly inverted. Current has an exponential relationship with Vgs.
- Some applications exploit this behavior for very low power analog/digital circuits.
So in summary, a small current flows due to weak inversion in the
The slide covers the basic concepts and designs of artificial neural networks. It explains and justifies the use of McCulloh Pitts Model, Adaline network, Perceptron algorithm, Backpropagation algorithm, Hopfield network and Kohonen network; along with its practical applications.
This document discusses multiplexers and de-multiplexers. It defines a multiplexer as a circuit that accepts multiple input signals but provides a single output signal, selecting one input using control signals. A de-multiplexer is the opposite, accepting one input and providing multiple outputs. Examples of 4-to-1 multiplexers and 1-to-4 de-multiplexers are described. Applications include communication systems, computer memory, and transmitting satellite data. Multiplexers and de-multiplexers are commonly used together and are important combinational logic circuits.
The document is a lab report that discusses arithmetic instructions in 8086 assembly language. It provides objectives and outcomes for the lab, describes different arithmetic instructions like addition, subtraction, multiplication and division. It then gives two tasks - the first asks to write a program performing various arithmetic operations on values in registers, the second asks to add two BCD numbers and handle carries. Code snippets are provided as examples to add BCD values with and without carry.
The document discusses reduced ordered binary decision diagrams (ROBDDs), which are a compact data structure for representing Boolean functions. It explains that ROBDDs are derived from binary decision diagrams (BDDs) and Shannon's expansion. An ROBDD is constructed by first building an ordered binary decision tree (OBDT) and then applying reduction rules to remove redundant tests and merge isomorphic subgraphs, resulting in a reduced, acyclic graph. The document provides examples of constructing ROBDDs from truth tables and discusses properties like canonical representation and efficient manipulation.
The document discusses the transport layer of the OSI model. It describes how the transport layer is responsible for end-to-end communication over a network by managing error correction and reliability. The two main protocols of the transport layer are UDP and TCP. UDP provides unreliable data transmission while TCP establishes connections and provides reliable in-order delivery through mechanisms like acknowledgments and flow control.
An adder is a digital logic circuit in electronics that implements addition of numbers. In many computers and other types of processors, adders are used to calculate addresses, similar operations and table indices in the ALU and also in other parts of the processors. These can be built for many numerical representations like excess-3 or binary coded decimal
Here are the steps to construct an NFA-ε equivalent to the given regular expressions:
1. ε + a b (a+b)*
- States: q0, q1, q2
- Transitions: q0 -> q1 on ε, q0 -> q2 on a, q1 -> q1 on a/b, q1 -> q2 on b
- Start state: q0
- Final states: q2
2. (0+1)* (00+11)
- States: q0, q1, q2, q3
- Transitions: q0 -> q0 on 0/1, q0 -> q1 on 0/1
Digital logic gates and Boolean algebraSARITHA REDDY
The document discusses digital logic gates and Boolean algebra. It defines logic gates as electronic circuits that make logic decisions. Common logic gates include OR, AND, and NOT gates. Boolean algebra uses truth values of 0 and 1 instead of numbers, and has fundamental laws and operations for AND, OR, and NOT. Boolean algebra can be used to simplify logical expressions and save gates in digital circuit design.
This document discusses low power VLSI design challenges and solutions. It motivates the need for low power design due to increasing power densities in VLSI chips and limited battery capacities. Sources of power dissipation in CMOS VLSI circuits are discussed including dynamic power during switching, static leakage power, and short circuit power. The document outlines various low power design methodologies at circuit, logic, architecture and software levels like reducing switching activity, glitch power reduction, gated clocking, reducing switched capacitance, using variable threshold voltages, and software optimizations.
Types of delay (Nodal, Queuing, Transmission and Propagation)rachanabuch
There are four types of network delay: processing delay, queuing delay, transmission delay, and propagation delay. Processing delay refers to the time taken to examine a packet's header and determine where to send it. Queuing delay is the time a packet spends waiting in a queue for transmission. Transmission delay is the time taken to push all packets in the queue onto the link. Propagation delay is the time it takes for a packet to travel from one node to the next along the physical medium of the link. The total delay is the sum of all four individual delays.
Boolean algebra and logic circuits were introduced. Boolean algebra uses binary numbers (0,1) and logical operations like AND, OR, and NOT to simplify logic expressions. Basic logic gates like AND, OR, and NOT were explained. Logic circuits can be built using combinations of logic gates to perform complex logical functions. Boolean algebra is used to simplify logic circuits and increase the efficiency of digital devices like computers.
This document describes the contents of a course on digital system design. The course covers topics like Boolean algebra, minimization techniques, combinational and sequential circuits, and finite state machines. It lists the course code, instructor details, textbook references, and outlines the topics to be covered in each of the 5 units of the course. These include Boolean algebra, minimization techniques like Karnaugh maps, combinational circuits, sequential circuits, and digital logic families.
This document discusses simplification of Boolean functions using Karnaugh maps. It describes two methods for simplification - algebraic and graphical. The graphical method uses Karnaugh maps, which arrange variables in a two-dimensional grid with 2n cells. Each cell represents a minterm. Adjacent minterms that are identical except for one variable can be combined. Several examples demonstrate constructing K-maps and simplifying functions down to prime implicants by grouping adjacent 1s. Don't care conditions are also introduced, where certain input combinations do not affect the output. The document concludes by showing a two-stage logic network example where K-maps are used to design the logic for each stage.
The document discusses different types of flow control instructions in assembly language including conditional jump instructions, unconditional jump instructions, compare instructions, and looping structures. Conditional jump instructions like JG transfer control based on condition flags. Looping structures include for, while, and repeat loops. High-level language equivalents like if-then, if-then-else, and case statements are also covered.
Question bank on digital electronics. Total 194 questions. Covering questions on basics of digital electronics, number systems, digital gates, logic families, the sum of product, the product of sum, boolean theorem, karnaugh map, coders, etc.
This document presents Booth's radix-4 algorithm for performing binary multiplication using an ALU. It explains that Booth's algorithm reduces the number of partial products generated during multiplication by grouping consecutive zeros and ones. It then describes the radix-2 Booth's algorithm and provides an example. The drawbacks of radix-2 are discussed, such as its inefficiency with isolated ones. Next, the radix-4 coding technique is presented and an example is shown. Finally, VHDL simulation code is presented to simulate multiplication using radix-4 algorithm.
This document discusses hardware description languages used in electronics design. It describes how HDLs like VHDL and Verilog are used to program digital and mixed-signal circuits. Simulation allows validation of the design against specifications. The document also discusses formal verification using property specification languages and different modeling styles for Verilog like gate-level, dataflow, and behavioral modeling.
The document discusses various techniques for accelerating the multiplication process, including shift-and-add, Booth's recoding, and higher radix multipliers. Booth's recoding maps digit sets to [-1,1] to skip additions when partial products are zero. Modified Booth's recoding improves on this by considering three adjacent bits to encode multipliers into [-2,2], allowing the use of radix-4 grouping to reduce the number of partial product additions. Modern multipliers apply Modified Booth's Recoding to take advantage of its higher radix structure.
The document discusses encoders, decoders, multiplexers (MUX), and how they can be used to implement digital logic functions. It provides examples of using 4-to-1, 8-to-1 and 10-to-1 MUX to implement functions. It also gives examples of 4-to-2, 8-to-3 and 10-to-4 encoders. Decoder examples include a 2-to-4 and 3-to-8 binary decoder. The document explains how decoders can be used as logic building blocks to realize Boolean functions. It poses questions to be answered using terms like MUX, DEMUX, encoder, decoder.
The Quine-McCluskey method is an algorithm for minimization of Boolean functions that was developed in 1956. It can be used to minimize functions with more than 5 bits, where Karnaugh maps are limited to 5 bits. The method has 4 main steps: 1) generate prime implicants, 2) construct a prime implicants table, 3) reduce prime implicants, and 4) solve the prime implicants table. An example is provided to illustrate the application of the method, starting with a list of minterms and ending with the minimized sum of products expression.
Here are the key points about NMOS transistor operation in the subthreshold region:
- When 0 < Vgs < Vt, a depletion region forms in the channel due to the electric field repelling majority carriers (holes).
- This depletion region means there are no carriers to conduct current through the channel.
- Only a small leakage current flows, as the channel is not fully "turned on".
- The transistor is not fully on or off in this region - it is said to be weakly inverted. Current has an exponential relationship with Vgs.
- Some applications exploit this behavior for very low power analog/digital circuits.
So in summary, a small current flows due to weak inversion in the
The slide covers the basic concepts and designs of artificial neural networks. It explains and justifies the use of McCulloh Pitts Model, Adaline network, Perceptron algorithm, Backpropagation algorithm, Hopfield network and Kohonen network; along with its practical applications.
This document discusses multiplexers and de-multiplexers. It defines a multiplexer as a circuit that accepts multiple input signals but provides a single output signal, selecting one input using control signals. A de-multiplexer is the opposite, accepting one input and providing multiple outputs. Examples of 4-to-1 multiplexers and 1-to-4 de-multiplexers are described. Applications include communication systems, computer memory, and transmitting satellite data. Multiplexers and de-multiplexers are commonly used together and are important combinational logic circuits.
The document is a lab report that discusses arithmetic instructions in 8086 assembly language. It provides objectives and outcomes for the lab, describes different arithmetic instructions like addition, subtraction, multiplication and division. It then gives two tasks - the first asks to write a program performing various arithmetic operations on values in registers, the second asks to add two BCD numbers and handle carries. Code snippets are provided as examples to add BCD values with and without carry.
The document discusses reduced ordered binary decision diagrams (ROBDDs), which are a compact data structure for representing Boolean functions. It explains that ROBDDs are derived from binary decision diagrams (BDDs) and Shannon's expansion. An ROBDD is constructed by first building an ordered binary decision tree (OBDT) and then applying reduction rules to remove redundant tests and merge isomorphic subgraphs, resulting in a reduced, acyclic graph. The document provides examples of constructing ROBDDs from truth tables and discusses properties like canonical representation and efficient manipulation.
The document discusses the transport layer of the OSI model. It describes how the transport layer is responsible for end-to-end communication over a network by managing error correction and reliability. The two main protocols of the transport layer are UDP and TCP. UDP provides unreliable data transmission while TCP establishes connections and provides reliable in-order delivery through mechanisms like acknowledgments and flow control.
An adder is a digital logic circuit in electronics that implements addition of numbers. In many computers and other types of processors, adders are used to calculate addresses, similar operations and table indices in the ALU and also in other parts of the processors. These can be built for many numerical representations like excess-3 or binary coded decimal
Here are the steps to construct an NFA-ε equivalent to the given regular expressions:
1. ε + a b (a+b)*
- States: q0, q1, q2
- Transitions: q0 -> q1 on ε, q0 -> q2 on a, q1 -> q1 on a/b, q1 -> q2 on b
- Start state: q0
- Final states: q2
2. (0+1)* (00+11)
- States: q0, q1, q2, q3
- Transitions: q0 -> q0 on 0/1, q0 -> q1 on 0/1
Digital logic gates and Boolean algebraSARITHA REDDY
The document discusses digital logic gates and Boolean algebra. It defines logic gates as electronic circuits that make logic decisions. Common logic gates include OR, AND, and NOT gates. Boolean algebra uses truth values of 0 and 1 instead of numbers, and has fundamental laws and operations for AND, OR, and NOT. Boolean algebra can be used to simplify logical expressions and save gates in digital circuit design.
This document discusses low power VLSI design challenges and solutions. It motivates the need for low power design due to increasing power densities in VLSI chips and limited battery capacities. Sources of power dissipation in CMOS VLSI circuits are discussed including dynamic power during switching, static leakage power, and short circuit power. The document outlines various low power design methodologies at circuit, logic, architecture and software levels like reducing switching activity, glitch power reduction, gated clocking, reducing switched capacitance, using variable threshold voltages, and software optimizations.
Types of delay (Nodal, Queuing, Transmission and Propagation)rachanabuch
There are four types of network delay: processing delay, queuing delay, transmission delay, and propagation delay. Processing delay refers to the time taken to examine a packet's header and determine where to send it. Queuing delay is the time a packet spends waiting in a queue for transmission. Transmission delay is the time taken to push all packets in the queue onto the link. Propagation delay is the time it takes for a packet to travel from one node to the next along the physical medium of the link. The total delay is the sum of all four individual delays.
Boolean algebra and logic circuits were introduced. Boolean algebra uses binary numbers (0,1) and logical operations like AND, OR, and NOT to simplify logic expressions. Basic logic gates like AND, OR, and NOT were explained. Logic circuits can be built using combinations of logic gates to perform complex logical functions. Boolean algebra is used to simplify logic circuits and increase the efficiency of digital devices like computers.
This document describes the contents of a course on digital system design. The course covers topics like Boolean algebra, minimization techniques, combinational and sequential circuits, and finite state machines. It lists the course code, instructor details, textbook references, and outlines the topics to be covered in each of the 5 units of the course. These include Boolean algebra, minimization techniques like Karnaugh maps, combinational circuits, sequential circuits, and digital logic families.
This document discusses simplification of Boolean functions using Karnaugh maps. It describes two methods for simplification - algebraic and graphical. The graphical method uses Karnaugh maps, which arrange variables in a two-dimensional grid with 2n cells. Each cell represents a minterm. Adjacent minterms that are identical except for one variable can be combined. Several examples demonstrate constructing K-maps and simplifying functions down to prime implicants by grouping adjacent 1s. Don't care conditions are also introduced, where certain input combinations do not affect the output. The document concludes by showing a two-stage logic network example where K-maps are used to design the logic for each stage.
This document provides information about Boolean algebra and canonical and standard forms. It defines key terms like product term, sum term, sum of products (SOP) form, product of sums (POS) form. It discusses how to obtain the canonical SOP form and POS form of a function. It also introduces Karnaugh maps as a graphical technique to simplify Boolean expressions into minimal SOP or POS form.
The document provides an overview of digital logic circuits. It begins with an introduction to logic gates and Boolean algebra. Common logic gates like AND, OR, NAND, NOR, XOR and XNOR are described along with their truth tables. Boolean algebra is introduced as an algebra used for analysis and synthesis of digital logic circuits. Standard forms like sum of products and product of sums are discussed. Karnaugh maps are then described as a method for simplifying Boolean functions to minimize logic circuits. The document concludes with examples of map simplification using adjacent cells and combinations of multiple cells.
This document provides an introduction to Boolean algebra and its applications in digital logic. It discusses how Boolean algebra was developed by George Boole in the 1800s as an algebra of logic to represent logical statements as either true or false. The document then explains how Boolean algebra is used to perform logical operations in digital computers by representing true as 1 and false as 0. It introduces the basic logical operators of AND, OR, and NOT and provides their truth tables. The rest of the document discusses topics such as logic gates, truth tables, minterms, maxterms, and how to realize Boolean functions using sum of products and product of sums forms.
boolean algebra and logic simplificationUnsa Shakir
The document provides an overview of Boolean algebra and logic simplification. It covers topics such as Boolean variables that can take true/false or 1/0 values, basic logic gates like AND, OR, NOT, NAND and NOR gates, canonical forms including sum-of-products and product-of-sums, De Morgan's laws, and examples of simplifying Boolean expressions and implementing logic circuits.
The document discusses Boolean algebra and its applications in switching theory and logic design. It defines the basic postulates of Boolean algebra including associativity, commutativity, distributivity, identity, and complement. It also discusses Boolean functions, canonical forms, Karnaugh maps, and the Quine-McCluskey method for minimizing Boolean functions.
The document discusses minterms, maxterms, and their representation using shorthand notation in digital logic. It also covers the steps to obtain the shorthand notation for minterms and maxterms. Standard forms such as SOP and POS are introduced along with methods to simplify boolean functions into canonical forms using Karnaugh maps. The implementation of boolean functions using NAND and NOR gates is also described through examples.
This document provides information on combinational logic circuits and summarizes steps for analyzing combinational logic problems using truth tables and Karnaugh maps. It begins by defining combinational circuits as those whose outputs solely depend on current inputs, as opposed to sequential circuits which use memory elements. It then provides examples of writing truth tables and deriving Boolean expressions from problem statements. The document also covers standard forms of sum of products and product of sums, and methods for simplifying expressions using Karnaugh maps including grouping cells and rules for grouping.
This document provides information on combinational logic circuits and techniques for analyzing them, including:
1. Combinational circuits have outputs that solely depend on current inputs, unlike sequential circuits which use memory elements.
2. Truth tables are used to represent the relationships between inputs and outputs, and techniques like Karnaugh maps can simplify Boolean expressions.
3. Karnaugh maps arrange minterms or maxterms in a grid, allowing groups of redundant variables to be identified and simplified. Standard forms like sum of products can be plotted and minimized on the map.
This document discusses logic gates and Boolean algebra. It begins by defining basic logic gates like AND, OR, and NOT. It then covers more advanced gates like NAND, NOR, XOR, and XNOR and provides their truth tables. The document explains how to implement logic functions using gates. It also covers Boolean algebra topics like Boolean functions, minterms, maxterms, SOP, POS, Karnaugh maps, and their use in minimizing logic expressions. Worked examples are provided for implementing functions with gates and simplifying expressions using K-maps.
The document discusses Boolean expressions and their use in computer programming. It defines Boolean expressions as expressions that evaluate to true or false. Boolean expressions are composed of logical operators like AND, OR, and NOT. The document then discusses different logical operators and their truth tables. It also covers Boolean algebra identities and theorems. Finally, it introduces concepts like minterms, maxterms, sum of products, and product of sums and how Karnaugh maps can be used to simplify Boolean expressions.
George Boole developed Boolean algebra between 1815-1864 as an algebra of logic to represent logical statements as algebraic expressions. Boolean algebra uses two values, True and False (represented by 1 and 0 respectively) and logical operators like AND, OR, and NOT to represent logical statements and perform operations on them. Boolean algebra finds application in digital circuits where it is used to perform logical operations. Canonical forms and Karnaugh maps are techniques used to simplify Boolean expressions into their minimal forms.
Boolean algebra is an algebra of logic developed by George Boole between 1815-1864 to represent logical statements as an algebra of true and false. It is used to perform logical operations in digital computers by representing true as 1 and false as 0. The fundamental logical operators are AND, OR, and NOT. Boolean algebra expressions can be represented in sum of products (SOP) form or product of sums (POS) form and minimized using algebraic rules or Karnaugh maps. Minterms and maxterms are used to derive Boolean functions from truth tables in canonical SOP or POS form.
18 pc09 1.2_ digital logic gates _ boolean algebra_basic theoremsarunachalamr16
Digital logic gates are basic building blocks of digital circuits that make logical decisions based on input combinations. There are three basic logic gates: OR, AND, and NOT. Other common gates such as NAND, NOR, XOR, and XNOR are derived from these. Boolean algebra uses variables that can be 1 or 0, and logical operators like AND, OR, and NOT to represent logic functions. Logic functions can be expressed in canonical forms such as sum of minterms or product of maxterms. Standard forms like SOP and POS are also used. Conversions between these forms allow simplifying logic functions.
Karnaugh maps are a graphical method used to minimize logic functions. They arrange the minterms of a function in a grid based on the number of variables. Groupings of adjacent 1s in the map correspond to simplified logic terms. The largest possible groupings are used to find a minimum logic expression for the function. Don't cares can also be grouped and treated as 0s or 1s to further simplify expressions.
Forensic Science – Digital Forensics – Digital Evidence – The Digital Forensi...ManiMaran230751
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"The Enigmas of the Riemann Hypothesis" by Julio ChaiJulio Chai
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1. LOGIC DESIGN
PART A
Unit 1:
PRINCIPLES OF COMBINATIONAL LOGIC-1
Definition of Combinational logic:
It deals with the techniques of combining
basic gates into circuits that perform
some desired function.
2. Outputs are functions of (present)
inputs.
No memory element. (like flipflops)
Do not have feedback from output
to input.
Egs. Adder, subtractor, decoder,
encoder, multiplexer.
COMBINATIONAL LOGIC
3. BASICS OF DIGITAL ELECTRONICS
Digital Electronics represents information (0, 1) with only
two discrete values.
Ideally
“no voltage” (e.g., 0v) represents a 0 and
“full source voltage” (e.g., 5v) represents a 1
Realistically
“low voltage” (e.g., <1v) represents a 0 and
“high voltage” (e.g., >4v) represents a 1
We achieve these discrete values by using switches.
We use transistor switches, which operates at high speed,
electronically, and small in size.
4. GATES
The most basic digital devices are called
gates.
Gates got their name from their function
of allowing or blocking (gating) the flow of
digital information.
A gate has one or more inputs and
produces an output depending on the
input(s).
A gate is called a combinational circuit.
Three most important gates are: AND, OR,
5. GATES
Simple gates
AND
OR
NOT
Functionality can be
expressed by a truth table
A truth table lists output for
each possible input
combination
Precedence
NOT > AND > OR
F = A B + A B
= (A (B)) + ((A) B)
7. GATES
Additional useful gates
NAND
NOR
XOR
NAND = AND + NOT
NOR = OR + NOT
XOR implements
exclusive-OR function
NAND and NOR gates
require only 2 transistors
AND and OR need 3
transistors!
15. LOGIC FUNCTIONS
Logical functions can be expressed in
several ways:
Truth table
Logical expressions
Graphical form
Example:
Majority function
Output is one whenever majority of inputs is 1
We use 3-input majority function
16. LOGIC FUNCTIONS (CONT.)
3-input majority function
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Logical expression form
after simplification:
F = A B + B C + A C
17. LOGIC CIRCUIT DESIGN PROCESS
A simple logic design process involves
Problem specification
Truth table derivation
Derivation of logical expression
Simplification of logical expression
Implementation
18. DERIVING LOGICAL EXPRESSIONS
Derivation of logical expressions from truth
tables
Sum-of-products (SOP) form
Product-of-sums (POS) form
SOP form
Write an AND term for each input combination that
produces a 1 output
Write the variable if its value is 1; complement otherwise
OR the AND terms to get the final expression
POS form
Dual of the SOP form
19. SUM OF PRODUCT (SOP) FORM
3-input majority
function
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
SOP logical expression
F = A B C + A B C +
A B C + A B C
Four product terms
Because there are 4
rows with a 1 output
20. PRODUCT OF SUM (POS) FORM
3-input majority function
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
POS logical expression
F = (A + B + C) (A + B + C)
(A + B + C) (A + B + C)
• Four sum terms
Because there are 4 rows with
a 0 output
21. DEFINITIONS:
1) Literal:
It is a Boolean variable or its complement.
Eg. A, B ,C, B
2) Product term:
It is a logical AND of literals or is a literal.
Eg. A B C , B C , AB
3) Sum term:
It is a logical OR of literals or is a literal.
Eg. (A + B + C), (A + B )
4) SOP:
It is the logical OR of multiple product terms.
5) POS:
It is the logical AND of multiple Sum terms.
22. Definitions: 6) Minterm
A minterm is a special case product term which
contains all the input variables (each literal occuring
only once) of the function.
• A function with n variables has 2n minterms
• A three-variable function, such as f(x,y,z), has
23 = 8 minterms.
Minterm Is true when… Shorthand
x’y’z’
x’y’z
x’yz’
x’yz
xy’z’
xy’z
xyz’
xyz
x=0, y=0, z=0
x=0, y=0, z=1
x=0, y=1, z=0
x=0, y=1, z=1
x=1, y=0, z=0
x=1, y=0, z=1
x=1, y=1, z=0
x=1, y=1, z=1
m0
m1
m2
m3
m4
m5
m6
m7
23. DEFINITIONS: 7) MAXTERM
It is a special case Sum term which contains all the
input variables of the function, occurring only once.
A function with n variables has 2n minterms
A three-variable function, such as f(x,y,z), has
23 = 8 minterms.
Maxterm Is false when… Shorthand
x + y + z x=0, y=0, z=0 M0
x + y + z’ x=0, y=0, z=1 M1
x + y’ + z x=0, y=1, z=0 M2
x + y’ + z’ x=0, y=1, z=1 M3
x’ + y + z x=1, y=0, z=0 M4
x’ + y + z’ x=1, y=0, z=1 M5
x’ + y’ + z x=1, y=1, z=0 M6
x’ + y’ + z’ x=1, y=1, z=1 M7
25. DEFINITIONS:
8) Canonical SOP
• It is a complete set of minterms that defines when an
O/P variable is a logical 1.
• Canonical or Standard SOP form is an SOP form of
expression in which each product term contains all the
literals.
Eg. A B C + A B C + A B C + A B C
9) Canonical POS
It is a POS form in which each Sum term contains all the
literals.
Eg. (A + B + C) (A + B + C)(A + B + C)
26. CANONICAL SOP FORM & MINTERM NOTATION
Every function can be written as a unique sum of
minterms. You can obtain the canonical SOP form by
picking the rows having O/P =1.
)6,3,2,1,0(
63210
m
mmmmm
CABBCACBACBACBAf
33. LOGICAL EXPRESSION SIMPLIFICATION
Methods:
Algebraic manipulation
Use Boolean laws to simplify the expression
Difficult to use
Don’t know if you have the simplified form
Karnaugh map (K-map) method
Graphical method
Easy to use
Can be used to simplify logical expressions with a few
variables.
Quine Mc-Cluskey method
Used for more than 6 variable functions
Tedious procedure
34. 1) ALGEBRAIC MANIPULATION METHOD
Majority function example
A B C + A B C + A B C + A B C =
A B C + A B C + A B C + A B C + A B C + A
B C
We can now simplify this expression as
B C + A C + A B
A difficult method to use for complex
expressions
Added extra
37. DEFINITIONS
Implicant: Any single minterm(cell) or permitted group
of minterms. Eg.
Implicants are:
)6,4,2,0(mY
1 0 0 1
1 0 0 1
c
cbcbcaca
cabcbacbacba
,,,,
,,,,
0
1
00 01 11 10
A
BC
38. DEFINITIONS
Prime Implicant: A group of minterms which
cannot be combined with any other minterms or
groups.
P.I is c
P.Is are:
x z, y
1 0 0 1
1 0 0 1
0
1
00 01 11 10
0 1 1 1
0 0 1 1
0
1
00 01 11 10
A
BC
A
BC
39. DEFINITIONS
Essential Prime Implicant:
A prime implicant in which one or more minterms are
unique i.e, it contains atleast one minterm that is not
contained in any other prime implicant.
E.P.Is are:
a c & b c
The simplified exprn. must
contain all EPIs & may or may
not contain non-essential PIs.
The aim is to choose the PI’s so that no cell with ‘1’ is left uncovered.
1 0 1 1
0 0 1 0
0
1
00 01 11 10
Unique ‘1’ cells
A
BC
40. GENERAL RULES FOR USING THE K-
MAP
Combine ones into groups of (1, 2, 4, 8, …)
squares
Form the largest group size.(PIs)
Form the min number of groups.
Two groups should not intersect unless this will
enable a small group to be larger in size.
41. For every Minterm in the given expression, put a ‘1’
into the corresponding cell & ‘0’ in the other cells.
Check for logical adjacency for the minterm cells.
( Cells are said to be logically adjacent if there occurs
change in only 1 bit b/w them)
Eg. Cells 0 & 4 are adjacent 000 100 Arrow shows
changed bit.
Group logically adjacent 1-cells to form subcubes
such that their size = 2n cells (2,4,8,16..) and it is as
large as possible.
Then each group represents a product term with
reduced no. of variables.
42. PROBLEM 1: SIMPLIFY USING K-MAPS
)7,6,3,2,1(),,( zyxfD
0 1 1 1
0 0 1 1
0
1
00 01 11 10
x
yz
PI’s : xz, y
EPI’s: xz, y
Minimal form of D = x z + y
43. PROBLEM 2: SIMPLIFY USING K-MAPS
)7,5,4,3,2,0(),,( zyxfD
0
1
00 01 11 10
x
yz
1 0 1 1
1 1 1 0
PI’s : y z, x z, x y, x z, x y, yz
EPI’s: none ( because no unique ‘1’ cells)
Minimal form of D = y z + x z + x y OR
D = x z + x y + yz
There are 2 solutions because in each case, all ‘1’ cells
are covered with the chosen set of groups.
44. PROBLEM 3: SIMPLIFY USING K-MAPS
)15,13,11,9,5,4,1,0(),,,( dcbafK
PI’s : a c, c d, a d
EPI’s: a c, a d
Non-essential PI: c d
Minimal form of K = a c + a d
1 1 0 0
1 1 0 0
0 1 1 0
0 1 1 0
cd
ab 00 01 11 10
00
01
11
10
Unique ‘1’ cells
45. PROBLEM 4: SIMPLIFY USING K-MAPS
)15,13,10,8,7,5,2,0(),,,( dcbafX
PI’s : b d, b d
EPI’s: b d, b d
Minimal form of X = b d + b d = b d
1 0 0 1
0 1 1 0
0 1 1 0
1 0 0 1
cd
ab 00 01 11 10
00
01
11
10
46. PROBLEM 5: SIMPLIFY USING K-MAPS
)14,12,11,9,6,4,3,1(),,,( dcbafX
PI’s : b d, b d
EPI’s: b d, b d
Minimal form of X = b d + b d = b d
0 1 1 0
1 0 0 1
1 0 0 1
0 1 1 0
cd
ab 00 01 11 10
00
01
11
10
47. PROBLEM 6: SIMPLIFY USING K-MAPS
)13,7,6,5,2(),,,( dcbafX
PI’s : a b d, b c d, a c d, a b c
EPI’s: a b d, a b c
Minimal form of X = a b d + a b c + a c d OR
X= a b d + a b c + b c d
0 0 0 1
0 1 1 1
0 1 0 0
0 0 0 0
cd
ab 00 01 11 10
00
01
11
10
Unique ‘1’ cells
48. PROBLEM 7: SIMPLIFY USING K-MAPS
)14,13,12,9,8,6,5,4,2,1,0(),,,( dcbafX
PI’s : c , a d, b d
EPI’s: c , a d, b d
Minimal form of X = c + a d + b d
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 0
cd
ab 00 01 11 10
00
01
11
10
Unique ‘1’ cells
49. PROBLEM 8: SIMPLIFY USING K-MAPS
PI’s : cd , a b c, a b c, b d, a d
EPI’s: cd , a b c, a b c
Minimal form of X = cd + a b c + a b c + b d OR
X= cd + a b c + a b c + a d
0 1 1 0
1 1 1 0
0 0 1 0
1 1 1 0
cd
ab 00 01 11 10
00
01
11
10
Unique ‘1’ cells
50. PROBLEM 9: SIMPLIFY USING K-MAPS
)15,13,11,10,9,8,7,5,1(),,,( dcbafX
0 1 0 0
0 1 1 0
0 1 1 0
1 1 1 1
cd
ab 00 01 11 10
00
01
11
10
Unique ‘1’ cells
PI’s : cd , a d, a b , b d
EPI’s: cd , b d, a b
Minimal form of X = cd + b d + a b
51. PROBLEM 10: SIMPLIFY USING K-MAPS
).......(),,,( OPformcanonicalStoconvertzxyzwxywzyxwfT
)14,12,10,8,7,6(mT
0 0 0 0
0 0 1 1
1 0 0 1
1 0 0 1
wx 00 01 11 10
00
01
11
10
Unique ‘1’ cells
yz
PI’s : x y z, w z , w x y.
EPI’s: w z , w x y.
Minimal form of T = w z + w x y.
52. PROBLEM 11: SIMPLIFY USING K-MAPS
)14,13,12,11,9,6,5,4,3,1(),,,( mzyxwfT
0 1 1 0
1 1 0 1
1 1 0 1
0 1 1 0
wx 00 01 11 10
00
01
11
10
Unique ‘1’ cells
yz
PI’s : y z, x z , x y, x z
EPI’s: x z , x z
Minimal form of T = x z + x z + y z OR
T = x z + x z + x y
53. PROBLEM 12: SIMPLIFY USING K-MAPS
)15,13,12,11,10,8,7,6,5,2,1,0(),,,( mzyxwfT
1 1 0 1
0 1 1 1
1 1 1 0
1 0 1 1
wx 00 01 11 10
00
01
11
10
yz
PI’s: x z , w y z, w x y , w y z , w x y, xz, w y z,w y z, w x y
w x y
EPI’s: none
Minimal form of T = x z + w y z + w x y + w y z + w x y OR
T = x z + w y z + w x y + w y z + w x y
1 1 0 1
0 1 1 1
1 1 1 0
1 0 1 1
1 1 0 1
0 1 1 1
1 1 1 0
1 0 1 1
54. PROBLEM 13: SIMPLIFY USING K-MAPS. WRITE THE
SIMPLIFIED SOP & POS EXPRESSIONS.
)15,13,12,11,9,8,7,5,4,0(),,,( Mzyxwf
0 1 1 1
0 0 0 1
0 0 0 1
0 0 0 1
wx 00 01 11 10
00
01
11
10
yz
PI’s: w x y , w x z, y z
EPI’s: w x z , y z
0 1 1 1
0 0 0 1
0 0 0 1
0 0 0 1
wx 00 01 11 10
00
01
11
10
yz
Minimal SOP form of T = w x z + y z
PI’s: w +z , x +z,y+z,w+y,x+y
EPI’s: w +z , x +z, y+z
Minimal POS form of T =(w +z ).(x +z ).(y+z)
55. PROBLEM 14: SIMPLIFY USING K-MAPS & IDENTIFY
PRIME IMPLICANTS & ESSENTIAL PRIME IMPLICANTS
DCBACBADCBCDADCADCBAf ),,,(
1 1 1 1
0 1 1 0
0 0 0 0
1 0 1 1
AB 00 01 11 10
00
01
11
10
CD
PI’s: B D ,B C, A B , A D
EPI’s: B D ,B C, A D
Minimal form of T = B D + B C+ A D
After converting to Canonical SOP form, write in Minterm notation.
)11,10,8,7,5,3,2,1,0(),,,( mDCBAf
56. PROBLEM 15: SIMPLIFY USING K-MAPS & IDENTIFY
PRIME IMPLICANTS & ESSENTIAL PRIME IMPLICANTS
))()()()((),,,( DCBADCBADCBADBADBADCBAf
1 0 0 1
1 1 1 0
1 1 0 0
1 0 0 1
AB 00 01 11 10
00
01
11
10
CD
Minimal POS form of T =
After converting to Canonical POS form, write in Maxterm notation.
)15,14,11,9,6,3,1(),,,( MDCBAf
B+D (EPI)
A+B+C (EPI)
B+C+D (EPI)
))()(( DCBCBADB
DBBDACBT
If u group 1’s, u can get Minimal POS form as
57. PROBLEM 16: SIMPLIFY USING K-MAPS & IMPLEMENT
USING BASIC GATES
)12,11,10,7,6,4,3,2(),,,( MDCBAf
1 1 0 0
0 1 0 0
0 1 1 1
1 1 0 0
AB 00 01 11 10
00
01
11
10
CD
PI’s: B C, A B C, C D, ABD PI’s: B+C, A+C, B+C+D, A+B+D
EPI’s: B C, A B C, C D EPI’s: B+C, A+C, B+C+D
Minimal SOPform of R= B C+A B C+ C D
Minimal POSform of R =(B+C)(A+C)(B+C+D)
1 1 0 0
0 1 0 0
0 1 1 1
1 1 0 0
AB 00 01 11 10
00
01
11
10
CD
60. PROBLEM 18: SIMPLIFY USING K-MAPS
)31,30,27,26,25,17,15,14,11,10,9,1(),,,,( mEDCBAf
0 1 0 0
0 1 1 1
0 1 1 1
0 1 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 0 0
AB 000 001 011
00
01
11
10
CDE
110111101100010
NOTE THIS
BD
C D E
B C E
BDEDCYofformMinimal
61. PROBLEM 19: SIMPLIFY USING K-MAPS
)31,29,27,25,21,19,15,14,13,11,10,9,5,3(),,,,( mEDCBAf
0 0 1 0
0 1 1 1
0 1 1 0
0 0 1 0
0 1 0 0
0 1 1 1
0 1 1 0
0 1 0 0
AB 000 001 011
00
01
11
10
CDE
110111101100010
BE
C D E
A B D
BDABEEDCDECYofformMinimal
C D E
62. PROBLEM 20: SIMPLIFY USING K-MAPS
)31,19,11,3(can writeWe
),,,,(
T
decbaabcdedecbadecbaedcbafT
ABCDEDECBDECAYofformMinimal
0 0 1 0
0 0 1 0
0 0 0 0
0 0 1 0
0 0 0 0
0 0 0 0
0 0 1 0
0 0 0 0
AB 000 001 011
00
01
11
10
CDE
110111101100010
B C D E
A C D E
ABCDE
65. INCOMPLETELY SPECIFIED FUNCTIONS(DON’T CARE TERMS)
When an O/P is not known for
every combination of I/P variables,
the function is said to be
incompletely specified.
Eg. BCD (B3B2B1B0)
to Excess-3 BCD (X3X2X1X0)
Code Converter
B3 B2 B1 B0 X3 X2 X1 X0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X
66. 1 0 1 0
1 0 1 0
x x x x
1 0 x x
BCD (B3B2B1B0) to Excess-3 BCD (X3X2X1X0) Code Converter eg.
We have 4 O/Ps here & hence we need to get 4 expressions.
1 0 0 1
1 0 0 1
x x x x
1 0 x x
B3B2
00 01 11 10
00
01
11
10
00 BX
B1B0
2) K-map for X1
B3B2
00 01 11 10
00
01
11
10
B1B0
0101011 BBBBBBX
1) K-map for X0
67. 0 0 0 0
0 1 1 1
x x x x
1 1 x x
0 1 1 1
1 0 0 0
x x x x
0 1 x x
B3B2
00 01 11 10
00
01
11
10
)10(2
)01(2)10(2
01202122
BBB
BBBBBB
BBBBBBBX
B1B0
4) K-map for X3
B3B2
00 01 11 10
00
01
11
10
B1B0
120233 BBBBBX
BCD (B3B2B1B0) to Excess-3 BCD (X3X2X1X0) Code Converter eg.
3) K-map for X2
68. 0 0 1 1
1 1 0 0
0 1 1 0
X X X X
00 01 11 10
00
01
11
10
B1B0
Simplify using K-maps
)10,8,7,5,0()15,14,13,11,4,2,1(),,,()2
)11,10,9,8()15,13,5,4,3,2(),,,()1
dmDCBAf
dmDCBAfV
CBAADCBV
X 1 0 1
1 X X 0
0 1 1 1
X 0 1 X
00 01 11 10
00
01
11
10
B1B0
B3B2 B3B2
DBACBDCAf
71. PROBLEMS ON DESIGN
1) Design a logic circuit which has a single O/P variable z which
is to be true when I/P variables a & b are true or when b is
false but a & c are true.
a b c Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
OPCanonicalSabccabcbaz
0 0 0 0
0 1 1 1
00 01 11 10
0
1
a
bc
)( bcaz
SOPMinimalabacz
a
b
c
z
72. 2) Design a logic circuit whose O/P is to be true when the value
if I/P s exceeds 3. The weighting for each I/P variable is as
follows.
w=3, x=3, y=2, z=1. (Left as an exercise)
3) Design a logic circuit that controls the passage of a signal ‘A’
according to the following requirement.
i. O/P ‘X’ will = ‘A’ when control I/Ps B & C are the same.
ii. ‘X’ will remain ‘HIGH’ when B & C are different.
Implement the ckt using suitable gates.
PROBLEMS ON DESIGN
A B C X
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
0 0 1
1 1 1 1
00 01 11 10
0
1
a
bc
CBAX
A
B
C
X
73. 1. Difficult to use when no. of variables is > 6.
2. The recognition of groups that form EPI’s becomes
difficult for large K-maps.
3. The technique does not involve a systematic
algorithmic procedure that is suitable for computers.
Since it is a manual technique, simplification
process depends on human abilities.