Programmable Logic Array(PLA) & Programmable Array Logic(PAL)
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The document discusses Programmable Logic Arrays (PLAs) and Programmable Array Logic (PALs). It explains that a PLA is similar to a PROM but does not provide full decoding and generates only some minterms. It has three sets of fuses to program the AND gates, OR gates, and output function. A PAL has a fixed OR array and programmable AND array, making it easier to program but less flexible than a PLA. The differences between PLA and PAL are described, along with an example and implementation details.
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Counter based design of dpll for wireless communicationeSAT Journals Abstract For proper reception of the transmitted data, the design of effective demodulation schemes plays a very crucial role. In the earlier times, some of the traditional techniques like envelope detection etc were utilized for demodulation purposes. However, these techniques, although could be implemented without much difficulty, but at times, when the extent of interference due to the surroundings, system noise and other degrading parameters were very significant, these traditional techniques were found to be non-sensitive to these large-scale effects. To overcome these shortcomings, over the years, the device called phase locked loop has gained much popularity. This device, having the capacity to recover the phase of the transmitted pulse, is capable of yielding very accurate approximations of the transmitted pulses and thus accounts for very low values of bit error rates. Considering the utility of the device, in the recent times, it has been attempted to provide a sound digital design for the device so that the design complexity of the device could be overcome by replacing its integral parts with simplified digital circuits and also would improve the noise performance of the device. With this view in mind, in this piece, we put forward a design of the Digital Phase Locked Loop (DPLL) using a counter based logic. Here, the essential components of the DPLL have been implemented using logic circuits and counters and further, while doing so, the requirement of the components of a traditional PLL has also been minimized.
Counter based design of dpll for wireless communication
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- The build process for embedded systems involves selecting a processor, compiling and linking software, and programming the final binary image into memory to load on the target hardware. Common hardware components include power sources, clocks, timers, memory, and I/O devices.
Inter intergrated circuits-communication protocol
Inter intergrated circuits-communication protocolRevathi Subramaniam I2C is a popular serial bus standard developed by Philips for connecting integrated circuits. There are three I2C standards with different speeds. The I2C bus uses two lines - one for a clock signal and one for bidirectional data. Communication on the I2C bus follows a specific protocol with defined fields for the start bit, address, read/write control bits, data, and acknowledgement bits. A master device generates the clock signal and initiates data transfers by addressing slave devices to read from or write to.
Application of embeddd system
Application of embeddd systemRevathi Subramaniam The document describes the different modes of operation for an automatic washing machine: fully automatic, semi-automatic, and manual. In fully automatic mode, the washing machine senses the load and performs the wash cycle independently without user input. In semi-automatic mode, washing conditions like time and temperature are predefined. In manual mode, the user must specify each operation like wash time and load amount. The document also provides a block diagram and explains the working of components like sensors, motors, pumps, and the system controller that manages the wash cycles.
Embedded development life cycle
Embedded development life cycleRevathi Subramaniam The document discusses the Embedded Development Life Cycle (EDLC), which is an analysis-design-implementation approach to product development. The EDLC involves analyzing customer needs, designing solutions, and implementing products. It aims to ensure high quality, minimize risks, and maximize productivity. The key phases of the EDLC include requirements analysis, design, development and testing, deployment, and support. Modeling approaches for the EDLC include iterative, incremental, fountain, prototyping, evolutionary, and spiral models. The EDLC process is essential for understanding complexities in embedded product development and defining interactions among project teams.
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Adaptive cruise control accRevathi Subramaniam The document summarizes an adaptive cruise control system for vehicles. It describes how the system uses radar (or laser) to measure the distance to the front vehicle and controls the vehicle speed to maintain a safe distance. It lists the required inputs like radar alignment, speed, throttle position, and brake status. It then explains the main functions of measuring distance and speed differences, with microcontrollers controlling components like the speedometer, throttle, and transceiver. The system activates or deactivates based on user inputs and can issue alarms or apply the brakes in unsafe situations to maintain adaptive and automated cruise control.
Unsymmetrical fault analysis
Unsymmetrical fault analysisRevathi Subramaniam The document discusses unsymmetrical faults in power systems. It defines different types of unsymmetrical faults like line-to-ground, line-to-line, and double line-to-ground faults. It explains sequence components and the sequence operator a which is used to resolve unbalanced three-phase quantities into balanced sequence components. The symmetrical component transformation and inverse transformation matrices are provided to convert between phase and sequence domains. Sequence impedances for different fault types are also described.
Structure of power system
Structure of power systemRevathi Subramaniam The document discusses the components and structure of an electric power system. It describes how power is generated at power stations and stepped up in voltage for transmission over long distances before being stepped down for distribution to consumers. The key components are generators, transformers, transmission lines, control equipment, and distribution systems. Power flows from generation through transmission and distribution before reaching ultimate consumers.
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RestructuringRevathi Subramaniam The document discusses the restructuring of power systems from monopolistic to deregulated markets. It explains that restructuring separates generation, transmission, distribution and supply functions. This creates new business opportunities and lower costs for consumers. Various restructuring models are presented including poolco, bilateral contracts and hybrid models. The poolco model uses a centralized market to set prices while bilateral contracts allow direct negotiations. The hybrid model combines features of the first two. An independent system operator maintains grid operations.
Power flow analysis
Power flow analysisRevathi Subramaniam The document discusses power flow analysis, which determines the voltage, current, real power, and reactive power at points in an electrical network under normal operating conditions. It provides three key points:
1. Power flow analysis is important for planning, operations, and future expansion of power systems by studying the effects of new loads, generators, or transmission lines.
2. The analysis involves classifying buses as slack, generator, or load buses and formulating the network equations based on the bus admittance matrix.
3. Solving the load flow problem involves determining the complex voltages across all buses given the network configuration and bus demands. This provides critical information for monitoring overloads and voltage deviations.
Per unit analysis
Per unit analysisRevathi Subramaniam This document discusses per-unit analysis and impedance/reactance diagrams of power systems. It provides examples of calculating the per-unit values of components in a sample power system using given base values, and drawing the corresponding reactance diagram. It also works through another example of determining new per-unit values when changing the base values, and drawing the updated reactance diagram. The document is intended to teach per-phase and per-unit analysis techniques.
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Newton raphson methodRevathi Subramaniam newton raphson method of load flow analysis is discussed with flowchart ,algorithmic steps with example problem
Introduction to power system analysis
Introduction to power system analysisRevathi Subramaniam The document provides an introduction to power system analysis. It discusses the components of a power system including generators, transformers, transmission lines and loads. It explains that power system analysis involves monitoring the system through load flow analysis, short circuit analysis and stability analysis in order to maintain the system safely and economically. It also discusses the need for power system analysis in planning and operating the system, and ensuring power demand is met through reliable generation and transmission of electricity.
Gauss seidel method
Gauss seidel methodRevathi Subramaniam the gauss seidel method of load flow analysis is explained with detailed flowchart and algorithmic steps with an design problem
Fault analysis
Fault analysisRevathi Subramaniam The document discusses short circuit analysis and fault calculations. It describes the different types of faults including three phase, line to ground, and line to line faults. It also discusses the need for short circuit studies to select proper circuit breakers. The document explains how to calculate short circuit currents using the bus impedance matrix and the z-bus building algorithm through adding network elements one by one.
Fault analysis using z bus
Fault analysis using z busRevathi Subramaniam This document describes the method of fault analysis using a Z-bus matrix. It involves the following steps:
1) Drawing the pre-fault positive sequence network and obtaining the initial bus voltages
2) Forming the Z-bus matrix using the bus building algorithm
3) Calculating the fault current using Thevenin's theorem by inserting a voltage source in series with the fault impedance
4) Obtaining the post-fault bus voltages through superposition of the pre-fault voltages and voltage changes
5) Calculating the post-fault line currents based on the voltage differences and line impedances
Two examples applying this method on different systems are provided to illustrate the calculation of fault currents.
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VHDL-Behavioral-Programs-Structure of VHDLRevathi Subramaniam The document discusses the structure and behavioral modeling of VHDL. It explains the main components of VHDL structure including entity, architecture, package, and configuration. It provides examples of how to write behavioral models for half adder, full adder, AND gate, and D flip flop in VHDL. The document concludes with references for further reading on VHDL design.
Flip flops
Flip flopsRevathi Subramaniam This document discusses various types of flip-flops including SR, D, JK, and T flip-flops. It provides details on their structure and operation through descriptions and truth tables. The SR flip-flop uses an edge detector circuit to trigger on clock pulses. The D flip-flop is built from an SR flip-flop. The JK flip-flop eliminates uncertainty when the SR inputs are both 1. The T flip-flop is a modification of the JK flip-flop that toggles its output when the input T is 1. References are provided for additional information on digital electronics and flip-flop principles.
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Counters
CountersRevathi Subramaniam Counters ,its types, modulo counters, design of synchronous and asynchronous counters are given a detailed view
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Digital logic familiesRevathi Subramaniam This document discusses different digital logic families and characteristics. It describes Resistor-Transistor Logic (RTL) which consists of resistors and transistors, with the emitters connected to ground and collectors tied through a resistor. Transistor-Transistor Logic (TTL) is also discussed, which depends solely on transistors. TTL uses multiple emitter transistors for inputs and a totem-pole output for high speed and low impedance. The document provides details on RTL and TTL gate operations.
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Programmable Logic Array(PLA) & Programmable Array Logic(PAL)
- 1. Review: General Structure Problems based on PLA & PAL Kongunadu College of Engineering & Technology PLA & PAL 1
- 2. PLA(Programmable Logic Array) PLA is similar to PROM but it does not provide full decoding of the variables and does not generates all the minterms. The PLA replaces decoder by a group of AND gates, each of which can be programmed to generate a product term of the input variables. There are three set of fuses present: between n-inputs & their complement values between the output of the AND gates and input of the OR gates. third set allows the output function to be generated either in AND- OR-INVERT form or in the AND-OR form. 2Kongunadu College of Engineering & Technology PLA & PAL
- 3. Block Diagram 3Kongunadu College of Engineering & Technology PLA & PAL
- 4. PAL(Programmable Array Logic) It is a programmable logic device with a fixed OR array and a programmable AND array. Since only AND gates are programmable, the PAL is easier to program but it is not flexible as PLA. 4Kongunadu College of Engineering & Technology PLA & PAL
- 5. 5Kongunadu College of Engineering & Technology PLA & PAL
- 6. Difference between PAL & PLA PAL PLA Both AND and OR arrays are programmable. OR array is fixed and AND array is programmable. Only desired minterms are programmed using AND array. Only desired minterms are programmed using AND array. Cheaper and Simpler Costliest and complex than PAL and PROMs 6Kongunadu College of Engineering & Technology PLA & PAL
- 7. Example 7Kongunadu College of Engineering & Technology PLA & PAL
- 8. 8Kongunadu College of Engineering & Technology PLA & PAL
- 9. 9Kongunadu College of Engineering & Technology PLA & PAL
- 10. Implementation 10Kongunadu College of Engineering & Technology PLA & PAL
- 11. References: Mandal, “Digital Electronics Principles & Application, McGraw Hill Edu, 2013. William Keitz, Digital Electronics-A Practical Approach with VHDL, Pearson, 2013. Thomas L.Floyd, ‘Digital Fundamentals’, 11th edition, Pearson Education, 2015. Charles H.Roth, Jr, Lizy Lizy Kurian John, ‘Digital System Design using VHDL, Cengage,2013. D.P.Kothari,J.S.Dhillon, ‘Digital circuits and Design’,Pearson Education, 2016. A.P.Godse., Dr.D.A.Godse, ‘Digital Logic Circuits’ , Technical Publications Third Edition 2016 Other Web Sources 11Kongunadu College of Engineering & Technology PLA & PAL