SlideShare a Scribd company logo

Programming The Arm Microprocessor For Embedded Systems

J
joshparrish13

This document provides an outline for a training course on programming the ARM microprocessor for embedded systems. The outline covers topics such as ARM technology overview, ARM tools and products, the ARM processor, instruction sets, exceptions and interrupts, firmware, caches, and memory management. The goal is to help students develop an understanding of ARM processor execution needed to develop and debug embedded software with or without an operating system.

1 of 131
Downloaded 1,658 times
1
Programming the ARM Microprocessor for Embedded Systems Ajay Dudani ajaydudani@gmail.com Version 0.1
2
Copyrights • This document is available under the terms of Creative Commons Attribution- NonCommercial-NoDerivs 2.5 License • In simpler terms, you may – Reproduce and redistribute this document as- is for non-commercial use Copyright (c) 2006 by Ajay Dudani 2 May not be reproduced or redistributed for commercial use.
3
Goals • Develop a good understanding of execution of ARM processor required to develop and debug embedded software with or without an operating system • Students should have prior knowledge about programming, operating system concepts and understanding of embedded systems Copyright (c) 2006 by Ajay Dudani 3 May not be reproduced or redistributed for commercial use.
4
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • Embedded operating system • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 4 May not be reproduced or redistributed for commercial use.
5
Why ARM? • Low power consumption • Fast execution per Watt • Good backward compatibility • Inexpensive • Variety of core offerings • … and other advantages we will see in upcoming slides Copyright (c) 2006 by Ajay Dudani 5 May not be reproduced or redistributed for commercial use.
6
Why ARM? • And … Marketing ☺ Copyright (c) 2006 by Ajay Dudani 6 May not be reproduced or redistributed for commercial use.
7
Detailed Outline • ARM Technology – History – The competition Copyright (c) 2006 by Ajay Dudani 7 May not be reproduced or redistributed for commercial use.
8
Detailed Outline • ARM Tools and products – Microprocessors – Compilers and debuggers – Single board computers – Documents and reference text Copyright (c) 2006 by Ajay Dudani 8 May not be reproduced or redistributed for commercial use.
9
Detailed Outline • ARM Processor – Programming model – General purpose registers – Program control registers – Pipelining – Memory protection Copyright (c) 2006 by Ajay Dudani 9 May not be reproduced or redistributed for commercial use.
10
Detailed Outline • Toolchain – ARM Toolchain – GNU Toolchain – Others Copyright (c) 2006 by Ajay Dudani 10 May not be reproduced or redistributed for commercial use.
11
Detailed Outline • ARM Instruction Set – Instruction set encoding – Conditional field – Data processing instructions – Branch instructions – Load-store instructions – Software interrupt instruction – Program status register instructions – Semaphore instructions – Coprocessor instructions – Extending instructions Copyright (c) 2006 by Ajay Dudani 11 May not be reproduced or redistributed for commercial use.
12
Detailed Outline • ARM Thumb Mode – Why Thumb? – Instruction set encoding – Branch instructions – Data processing instructions – Load and store instructions – Switching between ARM and Thumb mode Copyright (c) 2006 by Ajay Dudani 12 May not be reproduced or redistributed for commercial use.
13
Detailed Outline • ARM Exceptions and Interrupts – Exception vector table – Exception modes – Exception and interrupt handling Copyright (c) 2006 by Ajay Dudani 13 May not be reproduced or redistributed for commercial use.
14
Detailed Outline • ARM Firmware – Bootloader – Standalone code – Example of initialization Copyright (c) 2006 by Ajay Dudani 14 May not be reproduced or redistributed for commercial use.
15
Detailed Outline • ARM Caches – Memory hierarchy – Cache policy – Flushing policy – Software performance Copyright (c) 2006 by Ajay Dudani 15 May not be reproduced or redistributed for commercial use.
16
Detailed Outline • ARM MMU and MPU – Protected memory – Example of memory protection – Virtual memory concepts – Example of virtual memory system Copyright (c) 2006 by Ajay Dudani 16 May not be reproduced or redistributed for commercial use.
17
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 17 May not be reproduced or redistributed for commercial use.
18
ARM Technology Overview • ARM: “The Architecture For The Digital World” • ARM is a physical hardware design and intellectual property company • ARM licenses its cores out and other companies make processors based on its cores • ARM also provides toolchain and debugging tools for its cores Copyright (c) 2006 by Ajay Dudani 18 May not be reproduced or redistributed for commercial use.
19
ARM Technology Overview (2) Companies licensing ARM IP: 3Com Motorola Agilent Technologies Panasonic Altera Qualcomm Epson Sharp Freescale Sanyo Fijitsu Sun Microsystems NEC Sony Nokia Symbian Intel Texas Instruments IBM Toshiba Microsoft Wipro Source: ARM Website … and many more Copyright (c) 2006 by Ajay Dudani 19 May not be reproduced or redistributed for commercial use.
20
ARM History • Acorn Computer Group developed world’s first RISC processor in 1985 • Roger Wilson and Steve Furber were the principle developers • ARM (Advanced RISC Machines) was a spin out from Acorn in 1990 with goal of defining a new microprocessor standard Copyright (c) 2006 by Ajay Dudani 20 May not be reproduced or redistributed for commercial use.
21
ARM History (2) • Acorn Computer Group Source: Wikipedia Copyright (c) 2006 by Ajay Dudani 21 May not be reproduced or redistributed for commercial use.
22
ARM History (3) • ARM delivered ARM6 in 1991 – Introduced 32 bit addressing support – New instruction for program status registers – Variant used in Apple Newton PDA • By 1996 ARM7 was being widely used – Microsoft started port of WinCE to ARM – Added multimedia extensions • Exponential growth from then on… Copyright (c) 2006 by Ajay Dudani 22 May not be reproduced or redistributed for commercial use.
23
ARM and StrongARM • Intel gained certain IP from ARM as part of lawsuit settlement and modified ARM architecture branding it as StrongARM • StrongARM name was changed to XScale – Processor SA1000 , SA1100 • XScale is close to ARMv5 instruction set • XScale division of Intel was sold to Marvel Inc. in 2006 Copyright (c) 2006 by Ajay Dudani 23 May not be reproduced or redistributed for commercial use.
24
ARM Today • ARM7xxx – 3 stage pipeline – Integer processor – MMU support for WinCE, Linux and Symbian – Used in entry level mobiles, mp3 players, pagers • ARM9xxx – 5 stage pipeline – Separate data and instruction cache – Higher end mobile and communication devices – Telematic and infotainment systems – ARM and Thumb instruction set Copyright (c) 2006 by Ajay Dudani 24 May not be reproduced or redistributed for commercial use.
25
ARM Today (2) • ARM11xxx – 7 stage pipeline – Trustzone security related extensions – Reduced power consumption – Speed improvements – More DSP and SIMD extensions – Used in PDA, smartphones, industrial controllers, mobile gaming Copyright (c) 2006 by Ajay Dudani 25 May not be reproduced or redistributed for commercial use.
26
ARM Processor Family • ARM has devised a naming convention for its processors • Revisions: ARMv1, v2 … v6, v7 • Core implementation: – ARM1, ARM2, ARM7, StrongARM, ARM926EJ, ARM11, Cortex • ARM11 is based on ARMv6 • Cortex is based on ARMv7 Copyright (c) 2006 by Ajay Dudani 26 May not be reproduced or redistributed for commercial use.
27
ARM Processor Family (2) • Differences between cores – Processor modes – Pipeline – Architecture – Memory protection unit – Memory management unit – Cache – Hardware accelerated Java – … and others Copyright (c) 2006 by Ajay Dudani 27 May not be reproduced or redistributed for commercial use.
28
ARM Processor Family (3) • Examples: – ARM7TDMI • No MMU, No MPU, No cache, No Java, Thumb mode – ARM922T • MMU, No MPU, 8K+8K data and instruction cache, No Java, Thumb mode – ARM1136J-S • MMU, No MPU, configurable caches, with accelerated Java and Thumb mode Copyright (c) 2006 by Ajay Dudani 28 May not be reproduced or redistributed for commercial use.
29
ARM Processor Family (4) • Naming convention • ARM [x][y][z][T][D][M][I][E][J][F][S] – x – Family – y – memory management/protection – z – cache – T – Thumb mode – D – JTAG debugging – M – fast multiplier – I – Embedded ICE macrocell – E – Enhanced instruction (implies TDMI) – J – Jazelle, hardware accelerated Java – F – Floating point unit – S – Synthesizable version Copyright (c) 2006 by Ajay Dudani 29 May not be reproduced or redistributed for commercial use.
30
Outline • ARM Technology • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 30 May not be reproduced or redistributed for commercial use.
31
ARM Tools & Products Disclaimer: All owners own their respective trademarks Copyright (c) 2006 by Ajay Dudani 31 May not be reproduced or redistributed for commercial use.
32
ARM Chips • ARM Ltd – Provides ARM cores – Intellectual property • Analog Devices – ADuC7019, ADuC7020, ADuC7021, ADuC7022, ADuC7024, ADuC7025, ADuC7026, ADuC7027, ADuC7128, ADuC7129 • Atmel – AT91C140, AT91F40416, AT91F40816, AT91FR40162 • Freescale – MAC7101, MAC7104, MAC7105, MAC7106 • Samsung – S3C44B0X, S3C4510B • Sharp – LH75400, LH75401, LH75410, LH75411 • Texas Instruments – TMS470R1A128, TMS470R1A256, TMS470R1A288 • And others… Copyright (c) 2006 by Ajay Dudani 32 May not be reproduced or redistributed for commercial use.
33
ARM Development Tools • Compilers: – GNU Compiler – ADS from ARM (older version) – RVCT Real View compiler tools from ARM – 3rd Party • Debugging – GNU gdb – Lauterbach JTAG/Trace32 tools – ETM hardware debugging & profilingmodules – Windriver tools Copyright (c) 2006 by Ajay Dudani 33 May not be reproduced or redistributed for commercial use.
34
ARM Single Board Computers • TS-7200 ARM Single board computer – 200 MHz ARM9 processor with MMU – 32 MB RAM – 8 MB Flash – Compact flash – 10/100 Ethernet Copyright (c) 2006 by Ajay Dudani 34 May not be reproduced or redistributed for commercial use.
35
ARM Single Board Computers (2) • Cirrus Logic ARM CS98712 – 16 MB RAM – 1MB Flash – 1 Serial port – LED lights Copyright (c) 2006 by Ajay Dudani 35 May not be reproduced or redistributed for commercial use.
36
ARM Single Board Computers (3) • LN24x0/LP64 – 200 Mhz ARM9 processor – LCD controller – Touchscreen – USB, IrDA ports – HDD and CD-ROM support – Speaker – JTAG ports Copyright (c) 2006 by Ajay Dudani 36 May not be reproduced or redistributed for commercial use.
37
Recommended Text • “ARM System Developer’s Guide” – Sloss, et. al. – ISBN 1-55860-874-5 • “ARM Architecture Reference Manual” – David Seal – ISBN 0-201-737191 – Softcopy available at www.arm.com • “ARM system-on-chip architecture” – Steve Fuber – ISBN 0-201-67519-6 Copyright (c) 2006 by Ajay Dudani 37 May not be reproduced or redistributed for commercial use.
38
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 38 May not be reproduced or redistributed for commercial use.
39
ARM Design Philosophy • ARM core uses RISC architecture – Reduced instruction set – Load store architecture – Large number of general purpose registers – Parallel executions with pipelines • But some differences from RISC – Enhanced instructions for • Thumb mode • DSP instructions • Conditional execution instruction • 32 bit barrel shifter Copyright (c) 2006 by Ajay Dudani 39 May not be reproduced or redistributed for commercial use.
40
ARM Programming Model • A=B+C • To evaluate the above expression – Load A to a general purpose register R1 – Load B to a general purpose register R2 – Load C to a general purpose register R3 – ADD R1, R2, R3 – Store R1 to A Copyright (c) 2006 by Ajay Dudani 40 May not be reproduced or redistributed for commercial use.
41
Registers • ARM has a load store architecture • General purpose registers can hold data or address • Total of 37 registers each 32 bit wide • There are 18 active registers – 16 data registers – 2 status registers Copyright (c) 2006 by Ajay Dudani 41 May not be reproduced or redistributed for commercial use.
42
Registers (2) • Registers R0 thru R12 are general R0 R1 purpose registers R2 R3 • R13 is used as stack pointer (sp) R4 R5 R6 • R14 is used as link register (lr) R7 R8 • R15 is used a program counter (pc) R9 R10 • CPSR – Current program status R11 R12 register R13 (sp) R14 (lr) R15 (pc) • SPSR – Stored program status register CPSR SPSR Copyright (c) 2006 by Ajay Dudani 42 May not be reproduced or redistributed for commercial use.
43
Registers (3) • Program status register – CPSR is used to control and store CPU states – CPSR is divided in four 8 bit fields • Flags • Status • Extension • Control Copyright (c) 2006 by Ajay Dudani 43 May not be reproduced or redistributed for commercial use.
44
Registers (4) • Program status register flags – N:1 – Negative result – Z:1 – Result is zero – C:1 – Carry in addition operation – C:0 – Borrow in subtraction operation – V:1 – Overflow or underflow Copyright (c) 2006 by Ajay Dudani 44 May not be reproduced or redistributed for commercial use.
45
Registers (5) • Program status register controls – I:1 – IRQ interrupts disabled – F:1 – FIQ interrupts disabled – T:0 – ARM Mode – T:1 – Thumb Mode Copyright (c) 2006 by Ajay Dudani 45 May not be reproduced or redistributed for commercial use.
46
Registers (6) • Program status register control modes – 0b10000 – User mode – 0b10001 – FIQ mode – 0b10010 – IRQ mode – 0b10011 – Supervisor mode – 0b10111 – Abort mode – 0b11011 – Undefined mode – 0b11111 – System mode Copyright (c) 2006 by Ajay Dudani 46 May not be reproduced or redistributed for commercial use.
47
Processor Modes • Processor modes are execution modes which determines active registers and privileges • List of modes – Abort mode – Fast interrupt mode – Interrupt mode – Supervisor mode – System mode – Undefined mode – User mode • All except User mode are privileged modes – User mode is used for normal execution of programs and applications – Privileged modes allow full read/write to CPSR Copyright (c) 2006 by Ajay Dudani 47 May not be reproduced or redistributed for commercial use.
48
Banked Registers • Of total 37 registers only 18 are active in a given register mode User/System Supervisor Abort FIQ IRQ Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R8_fiq R9 R9_fiq R10 R10_fiq R11 R11_fiq R12 R12_fiq R13 (sp) R13_svc (sp) R13_abt (sp) R13_fiq (sp) R13_irq (sp) R13_und (sp) R14 (lr) R14_svc (lr) R14_abt (lr) R14_fiq (lr) R14_irq (lr) R14_und (lr) R15 (pc) CPSR SPSR SPSR_svc SPSR_abt SPSR_fiq SPSR_irq SPSR_und Copyright (c) 2006 by Ajay Dudani 48 May not be reproduced or redistributed for commercial use.
49
Pipeline • Pipelining is breaking down execution into multiple steps, and executing each step in parallel • Basic 3 stage pipeline – Fetch – Load from memory – Decode – Identify instruction to execute – Execute – Process instruction and write back result Copyright (c) 2006 by Ajay Dudani 49 May not be reproduced or redistributed for commercial use.
50
Pipeline (2) • Fetch Decode Execute Cycle 1 ADD Cycle 2 SUB ADD Time Cycle 3 CMP SUB ADD Copyright (c) 2006 by Ajay Dudani 50 May not be reproduced or redistributed for commercial use.
51
Pipeline (3) • ARM7 has a 3 stage pipeline – Fetch, Decode, Execute • ARM9 has a 5 stage pipeline – Fetch, Decode, Execute, Memory, Write • ARM10 has a 6 stage pipeline – Fetch, Issue, Decode, Execute, Memory, Write Copyright (c) 2006 by Ajay Dudani 51 May not be reproduced or redistributed for commercial use.
52
Pipeline (4) • In theory, each instruction is one instruction cycle • In practice, there is interdependency between instructions – Solution: instruction scheduling Copyright (c) 2006 by Ajay Dudani 52 May not be reproduced or redistributed for commercial use.
53
Memory Protection • Two modes for ARM memory protection – Unprotected mode • No hardware protection, software does protection of data between tasks – Protected mode • Hardware protects areas of memory and raises exceptions when policy is voilated • ARM divides memory to regions and programmer can set attributes on regions • ARM provides mechanisms to define and set attributes of regions programmatically Copyright (c) 2006 by Ajay Dudani 53 May not be reproduced or redistributed for commercial use.
54
Memory Management • ARM supports memory management and virtual memory • Programmatically access translation look- aside buffers • ARM memory management unit also supports Fast Context Switching Extensions that optimizes use of caches in multitasking environments • Details in later section Copyright (c) 2006 by Ajay Dudani 54 May not be reproduced or redistributed for commercial use.
55
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 55 May not be reproduced or redistributed for commercial use.
56
Toolchain • GNU Tools – gcc – Front end to GNU compiler – binutils – Binary tools • ld – GNU Linker • as – GNU assembler • And others – gdb – GNU Debugger – uClib – Small footprint C Library Copyright (c) 2006 by Ajay Dudani 56 May not be reproduced or redistributed for commercial use.
57
Toolchain (2) • GCC – Invoked language specific modules – Invoked assembler and linker – arm-elf-gcc command • arm-elf-gcc test.c –o test • arm-elf-gcc test.S –o test Copyright (c) 2006 by Ajay Dudani 57 May not be reproduced or redistributed for commercial use.
58
Toolchain (3) • GCC ARM specific options – mapcs-frame: Generate ARM procedure call compliant stack frame – mbig-endian: Generate big endian code – mno-alignment-traps: Generate code that assumes that MMU does not trap on handling misaligned data – mcpu=name : Specify CPU name; gcc can determine what instructions it can use to generate output accordingly – mthumb: Generate code for ARM Thumb mode – msoft-float: Generate code assuming floating point hardware is not present. Do floating point operation optimization in software – Refer to GCC manual page for more on compiler options Copyright (c) 2006 by Ajay Dudani 58 May not be reproduced or redistributed for commercial use.
59
Inline assembly • Developer can insert ARM assembly code in C code – for example printf (“Hello ARM GCC”); __asm__ (“ldr r15, r0”); printf (“Program may have crashed”); Above code will corrupt program counter, so use inline assembly carefully Also, it may lead to non portable code Copyright (c) 2006 by Ajay Dudani 59 May not be reproduced or redistributed for commercial use.
60
Inline assembly (2) • Developer can force use of certain registers using extended assembly asm ( assembler template : output operands /* optional */ : input operands /* optional */ : list of clobbered registers /* optional */ ); • Example: int a = 10, b; __asm__ (“mov %0, %1” : “=r”(b) : “=r”(a)); Copyright (c) 2006 by Ajay Dudani 60 May not be reproduced or redistributed for commercial use.
61
Inline assembly (3) • Developer can request variable to be assigned to specific register register int regVar __asm__(“%r4”); • Can be used with local and global variables • Need –ffixed-<reg> compiler option for global variables • Refer to GCC Inline Assembly reference for more examples Copyright (c) 2006 by Ajay Dudani 61 May not be reproduced or redistributed for commercial use.
62
GNU Toolchain • Reference: – www.gnuarm.org – www.sourceware.org/binutils/ – www.gnu.org/software/gdb/ – www.sourceware.org/insight/ – www.uclibc.org – GCC improvements for ARM • www.inf.u-szeged.hu/gcc-arm/ Copyright (c) 2006 by Ajay Dudani 62 May not be reproduced or redistributed for commercial use.
63
ARM Toolchain • ADS: ARM Developer Suite is older version of compiler, assembler and linker tools from ARM • RCVT: Latest ARM compiler, assembler and linker Copyright (c) 2006 by Ajay Dudani 63 May not be reproduced or redistributed for commercial use.
64
ARM Toolchain • ARM also provides support for RealView tools it acquired as part of Keil acquisition • JTAG Support: ARM provides debugging tools to be used with JTAG supported hardware • ETM Support: Embedded Trace Module is hardware debug unit that extends on-target debugging capabilities by providing extra memory and registers for debugging purpose • Refer to www.arm.com and www.keil.com/arm/ for details on ARM tools Copyright (c) 2006 by Ajay Dudani 64 May not be reproduced or redistributed for commercial use.
65
Other Toolchains • GNU X-Tools – www.microcross.com • IAR ARM Kit – www.iar.com • Intel Development Suite for XScale – www.intel.com Copyright (c) 2006 by Ajay Dudani 65 May not be reproduced or redistributed for commercial use.
66
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 66 May not be reproduced or redistributed for commercial use.
67
ARM Instruction Set • Overview Copyright (c) 2006 by Ajay Dudani 67 May not be reproduced or redistributed for commercial use.
68
ARM Instruction Set (2) • Condition fields Copyright (c) 2006 by Ajay Dudani 68 May not be reproduced or redistributed for commercial use.
69
ARM Instruction Set (3) • Add • Subract • Multiply Copyright (c) 2006 by Ajay Dudani 69 May not be reproduced or redistributed for commercial use.
70
ARM Instruction Set (4) • Bit shifting Copyright (c) 2006 by Ajay Dudani 70 May not be reproduced or redistributed for commercial use.
71
ARM Instruction Set (5) • Status register operation Copyright (c) 2006 by Ajay Dudani 71 May not be reproduced or redistributed for commercial use.
72
ARM Instruction Set (6) • Semaphore instruction Copyright (c) 2006 by Ajay Dudani 72 May not be reproduced or redistributed for commercial use.
73
ARM Instruction Set (7) • Placeholder page Copyright (c) 2006 by Ajay Dudani 73 May not be reproduced or redistributed for commercial use.
74
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 74 May not be reproduced or redistributed for commercial use.
75
Thumb Instruction Set • Overview of 16 bit mode Copyright (c) 2006 by Ajay Dudani 75 May not be reproduced or redistributed for commercial use.
76
Thumb Instruction Set (2) • Thumb Instruction set details Copyright (c) 2006 by Ajay Dudani 76 May not be reproduced or redistributed for commercial use.
77
Thumb Instruction Set (3) • Switching between ARM and Thumb mode Copyright (c) 2006 by Ajay Dudani 77 May not be reproduced or redistributed for commercial use.
78
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 78 May not be reproduced or redistributed for commercial use.
79
Exceptions • Exception handling is a programming language or hardware mechanism to catch runtime errors • C++ and Java support exception handling in software 1. void func() 2. { 3. try 4. { 5. int a = 100/0; 6. } 7. catch(...) 8. { 9. cout << "Caught exception" << endl; 10. return; 11. } 12. cout << "No exception detected!" << endl; 13. return; 14. } Copyright (c) 2006 by Ajay Dudani 79 May not be reproduced or redistributed for commercial use.
80
Exceptions (2) • ARM support 7 exception modes • Developers can write custom exception handlers to deal with exception conditions • For example: – Consider a system that crashes if PC is corrupted. This will cause an exception. In corresponding exception handler, programmer can save state of all registers to file system for debugging and reset Copyright (c) 2006 by Ajay Dudani 80 May not be reproduced or redistributed for commercial use.
81
Exceptions (3) • ARM Exceptions in order of priority – Reset – Data abort – FIQ – IRQ – Prefetch abort – Undefined instruction – Software interrupt Copyright (c) 2006 by Ajay Dudani 81 May not be reproduced or redistributed for commercial use.
82
Reset exception • Highest priority exception • The reset handler runs in supervisor mode • Handler is generally located at 0x00000000 • In Reset handler, FIQ and IRQ are disabled • Other exceptions are not likely to occur when in reset handler Copyright (c) 2006 by Ajay Dudani 82 May not be reproduced or redistributed for commercial use.
83
Reset exception (2) • Actions performed when reset is de-asserted – R14_svc is set to unpredictable value – SPSR_svc is set to unpredictable value – CPSR[4:0] is 0b10011 – supervisor mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is 1 – disable fast interrupts – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000000 Copyright (c) 2006 by Ajay Dudani 83 May not be reproduced or redistributed for commercial use.
84
Data abort exception • Data abort exception mean software is trying to read/write an illegal memory location • Data abort has higher priority than FIQ • While handling this more, IRQ is disabled • The abort handler should not cause further aborts – Consider case of prefetch abort in abort handler – This will cause abort handler to be reentered • Abort handler is generally located at 0x00000010 Copyright (c) 2006 by Ajay Dudani 84 May not be reproduced or redistributed for commercial use.
85
Data abort exception (2) • Actions performed on data abort – R14_abt = address of abort instruction + 8 – SPSR_svc = CPSR – CPSR[4:0] is 0b10111 – abort mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000010 Copyright (c) 2006 by Ajay Dudani 85 May not be reproduced or redistributed for commercial use.
86
Fast interrupt • FIQ exception mode exists if developer wants to handle certain interrupts faster • Additional banked registers in FIQ mode make execution fast • Higher priority in IRQ • Disabled IRQ and FIQ • Default ARM cores do not handle nested interrupts • FIQ handler is generally located at 0x0000001C Copyright (c) 2006 by Ajay Dudani 86 May not be reproduced or redistributed for commercial use.
87
Fast interrupt (2) • Actions performed on fast interrupt – R14_fiq = address of next instruction to execute + 4 – SPSR_fiq = CPSR – CPSR[4:0] is 0b10111 – FIQ mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is 1 – disable fast interrupts – CPSR[7] is 1 – disable normal interrupts – PC = 0x0000001C Copyright (c) 2006 by Ajay Dudani 87 May not be reproduced or redistributed for commercial use.
88
Normal interrupt • Normal interrupt is lower priority than fast interrupts • Disabled IRQ when handling normal interrupts • Default ARM cores do not handle nested interrupts • IRQ handler is generally located at 0x00000018 Copyright (c) 2006 by Ajay Dudani 88 May not be reproduced or redistributed for commercial use.
89
Normal interrupt (2) • Actions performed on normal interrupt – R14_irq = address of next instruction to execute + 4 – SPSR_irq = CPSR – CPSR[4:0] is 0b10010 – IRQ mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000018 Copyright (c) 2006 by Ajay Dudani 89 May not be reproduced or redistributed for commercial use.
90
Prefetch abort • If processor reads instruction from undefined memory, it causes a prefetch abort exception • Prefetch abort occurs when instruction reaches execution stage of pipeline • Disabled normal interrupts when handling prefetch abort • Prefetch abort handler is generally located at 0x0000000C Copyright (c) 2006 by Ajay Dudani 90 May not be reproduced or redistributed for commercial use.
91
Prefetch abort (2) • Actions performed on prefetch abort – R14_abt = address of next instruction to execute + 4 – SPSR_irq = CPSR – CPSR[4:0] is 0b10111 – abort mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x0000000C Copyright (c) 2006 by Ajay Dudani 91 May not be reproduced or redistributed for commercial use.
92
Undefined instruction • When executing coprocessor instructions, ARM waits for coprocessor to acknowledge that it can execute the instruction • If no coprocessor can handle given instruction, undefined instruction exception is raised • In simulators, this can be used to simulate coprocessor in software • Undefined instruction handler can parse instructions and process them in software simulator • Undefined instruction handler is generally located at 0x00000004 Copyright (c) 2006 by Ajay Dudani 92 May not be reproduced or redistributed for commercial use.
93
Undefined instruction (2) • Actions performed on undefined instruction – R14_und = address of next instruction to execute – SPSR_und = CPSR – CPSR[4:0] is 0b11011 – undefined mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000004 Copyright (c) 2006 by Ajay Dudani 93 May not be reproduced or redistributed for commercial use.
94
Software interrupt • Software interrupt exception is used to enter supervisor mode to execute a privileged OS function • Typically applications run in user mode and kernel in supervisor mode • Execution of any system call will cause SWI software interrupt to change mode to supervisor mode • Software interrupt handler is generally located at 0x00000008 Copyright (c) 2006 by Ajay Dudani 94 May not be reproduced or redistributed for commercial use.
95
Software interrupt (2) • Actions performed on software interrupt – R14_svc = address of next instruction to execute after SWI – SPSR_irq = CPSR – CPSR[4:0] is 0b10011 – supervisor mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000008 Copyright (c) 2006 by Ajay Dudani 95 May not be reproduced or redistributed for commercial use.
96
Exception table • Memory layout 0x00000000 – reset exception handler 0x00000004 – undefined instruction handler 0x00000008 – software interrupt handler 0x0000000C – prefetch abort handler 0x00000010 – data abort handler 0x00000018 – normal interrupt handler 0x0000001C – fast interrupt handler • High vectors – Some implementation keep this table in 0xFFFF0000 to 0xFFFF001C range which is known as high vector location Copyright (c) 2006 by Ajay Dudani 96 May not be reproduced or redistributed for commercial use.
97
Exception handling 1. Exception is raised 2. Lookup to exception table to find exception handler 3. Exception handler is executed 4. Return from exception handler Exception Vector Table SWI Handler Application 0x00 Reset_Handler MOV r0, r1 0x04 Undef_Handler SWI 0x1D 0x08 SWI_Handler ... ADD r0,r2,r0 0x0c PAbt_Handler ... DAbt_Handler ... 0x10 0x14 ... IRQ_Handler MOV PC, R14_svc 0x18 FIQ_Handler 0x1c Copyright (c) 2006 by Ajay Dudani 97 May not be reproduced or redistributed for commercial use.
98
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 98 May not be reproduced or redistributed for commercial use.
99
ARM Firmware • “Now the earth was formless and empty. Darkness was on the surface of the deep. God's Spirit was hovering over the surface of the waters.” “God said, “Let there be light”, and there was light.” • For the processor, someone needs to read application and copy it into RAM to start execution – What address to copy it to RAM – Setup stack and heap – Transfer control to application Copyright (c) 2006 by Ajay Dudani 99 May not be reproduced or redistributed for commercial use.
100
System initialization • Two stages of initialization: 1. Initialize stack, vectors and I/O system 2. Initialize application and associated libraries – The system set up could be – With an RTOS, in which case it does initialization of system environment (stack, vectors etc.). User application then starts with main() or RTOS specific entry point – Without an RTOS, ROM code handles transferring control to user application. User application need additional code to setup system environment Copyright (c) 2006 by Ajay Dudani 100 May not be reproduced or redistributed for commercial use.
101
Initialization • Execution environment: 1. At reset • Processor is in SVC mode • Interrupts are disabled • Running in ARM mode 2. Entry point on powerup • Use assember directive ENTRY to specify entry point • ROM code usually has entry point 0x00 Copyright (c) 2006 by Ajay Dudani 101 May not be reproduced or redistributed for commercial use.
102
Initialization (2) • Execution environment: 3. Setup exception vector table • If ROM is mapped to address 0x00, it contains hard coded exception vector table • If ROM is mapped elsewhere, exception table is copied to RAM address 0x00 4. Initialize memory system • Initialize memory management and memory protection before running any application code • Setup stack pointers, sp_SYS, sp_IRQ etc. • Initialize I/O devices. Note interrupts are still disabled • Change processor mode to user mode. At this stage we are ready to initialize application Copyright (c) 2006 by Ajay Dudani 102 May not be reproduced or redistributed for commercial use.
103
Initialization (3) • Application environment: 1. Initialize ZI writable region with zeroes 2. Initialize non zero data by copying initialization values 3. Pass on control to main function Copyright (c) 2006 by Ajay Dudani 103 May not be reproduced or redistributed for commercial use.
104
Initialization Example • Consider user code: 1. int main (void) 2. { 3. printf (“Hello ARM World”); 4. return 0; 5. } Copyright (c) 2006 by Ajay Dudani 104 May not be reproduced or redistributed for commercial use.
105
Initialization Example (2) • Consider ROM mapped at address 0x24000 RW Data Application Code 0x24000000 Vector table & Init Code • Above image shows setup before application has been loaded Copyright (c) 2006 by Ajay Dudani 105 May not be reproduced or redistributed for commercial use.
106
Initialization Example (3) • At initialization, ROM code at 0x24000000 is in flash. Flash is mapped at 0x24000000 address • On Reset, Flash will be remapped by hardware to address 0x00 – ROM init code performs certain initialization – Initialized vector tables and data regions to RAM – Copies application code from ROM to RAM – Sets REMAP bit to map RAM to address 0x00 Copyright (c) 2006 by Ajay Dudani 106 May not be reproduced or redistributed for commercial use.
107
Initialization Example (4) Code (RO+RW) Code (RO+RW) Flash 0x24000000 I/O Addresses UART Stack Heap RAM ZI data Initialized RW data Code aliased from Code (RO+RW) 0x24000000 Vector table Copyright (c) 2006 by Ajay Dudani 107 May not be reproduced or redistributed for commercial use.
108
Firmware • Typically the ROM code is bootloader – Developers configure the bootloader as per their requirements to specify memory map, bootup address, policy to copy code to RAM • Application code can – Either be single binary with RTOS in which case RTOS provides basic OS services – For simple applications there may be no RTOS, just application compiled with simplified C library Copyright (c) 2006 by Ajay Dudani 108 May not be reproduced or redistributed for commercial use.
109
Firmware (2) • Some examples of bootloaders – Grub – Lilo – RedBoot • Some examples of RTOS – Linux – eCos – vxWorks • Some examples of embedded libraries – Busybox – ucLib Copyright (c) 2006 by Ajay Dudani 109 May not be reproduced or redistributed for commercial use.
110
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 110 May not be reproduced or redistributed for commercial use.
111
Memory hierarchy Registers Caches RAM Memory Hard disk External & network storage Copyright (c) 2006 by Ajay Dudani 111 May not be reproduced or redistributed for commercial use.
112
Caches • A cache is high speed memory location generally used to reduce latency in memory access for data and instructions • Whenever CPU reads data from (slower) RAM, a copy is stored in (faster) cache • If CPU access the same data again, it can be served from cache. This is a hit • A write buffer speeds up writing to main memory Copyright (c) 2006 by Ajay Dudani 112 May not be reproduced or redistributed for commercial use.
113
Cache properties • Set associativity – Fully associative – Direct mapped • Cache size • Unified or separate – Caches for data and instruction • Write through or write back – Property associated with mechanism to write data back to main memory • Read allocate or write allocate – Property associated dealing with cache miss • Replacement strategy – Property associated with replacing cache data with newer ones Copyright (c) 2006 by Ajay Dudani 113 May not be reproduced or redistributed for commercial use.
114
Cache issues • Address mapping changes – Virtual or physical address can get remapped • Cache coherence and invalidation • Direct Memory Access (DMA) operation can update main memory without going through cache Copyright (c) 2006 by Ajay Dudani 114 May not be reproduced or redistributed for commercial use.
115
ARM and caches • Cache and write buffers are controlled with coprocessor registers • Register 1: – C bit: Cache enable/disable – W bit: Enable/disable write buffer – I bit: Enable/disable instruction cache – RR bit: Cache replacement strategy Copyright (c) 2006 by Ajay Dudani 115 May not be reproduced or redistributed for commercial use.
116
ARM and caches (2) • Register 7: – Controls cache and write buffers – Different opcodes written to this register result in different behavior. Some examples: • Invalidate entire instruction/data cache • Flush prefetch buffer • Writeback outstanding cache data to main memory Copyright (c) 2006 by Ajay Dudani 116 May not be reproduced or redistributed for commercial use.
117
ARM and caches (3) • Register 9: – Controls cache lockdown – Caches can slow down worst case execution time of code and be undeterministic because • It needs to handle cache misses • Write back of data to main memory can take time • Cache mechanism can load more data than request by process – Cache lockdown helps control these parameters to remove undeterministic behavior in critical code Copyright (c) 2006 by Ajay Dudani 117 May not be reproduced or redistributed for commercial use.
118
Caches • Caches can provide huge performance improvements to the system • As a developer, one should do profiling by changing various caching options when developing board support package Copyright (c) 2006 by Ajay Dudani 118 May not be reproduced or redistributed for commercial use.
119
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 119 May not be reproduced or redistributed for commercial use.
120
Memory Management • We saw earlier that during initialization, code from ROM is copied to RAM • But what is code size is larger than RAM available? Options: – Do not allow program to be loaded – Load only part of program and swap parts of program as requested – Or allow program to see large virtual memory Copyright (c) 2006 by Ajay Dudani 120 May not be reproduced or redistributed for commercial use.
121
Virtual Memory • Program is loaded into RAM until full • Application starts running with partial program loaded in memory • When program wants to access virtual memory address that is not in physical memory it generated a page fault • Page fault handler is responsible to get new page of memory into RAM Copyright (c) 2006 by Ajay Dudani 121 May not be reproduced or redistributed for commercial use.
122
ARM MMU • MMU handles translation from virtual to physical memory • Presents 4 GB address space • Supports 3 options for memory granularity: – 1 MB sections – 64 KB pages – 4 KB pages • Page fault is indicate by abort • Abort handler is responsible for fetching pages Copyright (c) 2006 by Ajay Dudani 122 May not be reproduced or redistributed for commercial use.
123
ARM Memory Protection • Memory protection is required to prevent one application from overwriting other application’s code • This facility can be enabled by using MMU • Using MMU, system goes to abort mode when application accesses memory to which it does not have permissions Copyright (c) 2006 by Ajay Dudani 123 May not be reproduced or redistributed for commercial use.
124
ARM Memory Protection (2) • ARM MPU allows memory protection without using MMU facilities • ARM defines up to 8 protection regions which can be configured through MPU registers • MPU offers good memory protection option for cases – Where 8 protection regions are enough – Virtual memory is not required Copyright (c) 2006 by Ajay Dudani 124 May not be reproduced or redistributed for commercial use.
125
MPU Registers • CP15 – M bit: enable/disable memory protection – Cache bits: control if cache buffer is enabled/disabled – Buffer bits: control if write buffer is enabled/disabled – Access control bits: control access rights of 8 regions – Mechanism to define 8 memory regions Copyright (c) 2006 by Ajay Dudani 125 May not be reproduced or redistributed for commercial use.
126
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 126 May not be reproduced or redistributed for commercial use.
127
ARM Future Development • ARMv7 based processors – ARM Cortex-M3 – TI OMAP – Qualcomm Scorpion • In embedded systems its not just speed, its about speed/watt • Approximately 2 billion ARM based devices selling each year… and growing! Copyright (c) 2006 by Ajay Dudani 127 May not be reproduced or redistributed for commercial use.
128
ARM Future Development (2) • Qualcomm’s SnapDragon based on Scorpion: – 1 GHz microprocessor – CDMA and UMTS network support – Upto 12 mega pixels camera support – Enhanced multimedia support – DVD quality display support – GPS support – Support for various peripherals like hard disk, monitor, USB devices, bluetooth etc. Copyright (c) 2006 by Ajay Dudani 128 May not be reproduced or redistributed for commercial use.
129
ARM Future Development (3) • Its ARM v/s x86 for UMPC and mobile devices market Copyright (c) 2006 by Ajay Dudani 129 May not be reproduced or redistributed for commercial use.
130
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 130 May not be reproduced or redistributed for commercial use.
131
Questions & Comments Copyright (c) 2006 by Ajay Dudani 131 May not be reproduced or redistributed for commercial use.
Programming the ARM Microprocessor for Embedded Systems Ajay Dudani ajaydudani@gmail.com Version 0.1
Copyrights • This document is available under the terms of Creative Commons Attribution- NonCommercial-NoDerivs 2.5 License • In simpler terms, you may – Reproduce and redistribute this document as- is for non-commercial use Copyright (c) 2006 by Ajay Dudani 2 May not be reproduced or redistributed for commercial use.
Goals • Develop a good understanding of execution of ARM processor required to develop and debug embedded software with or without an operating system • Students should have prior knowledge about programming, operating system concepts and understanding of embedded systems Copyright (c) 2006 by Ajay Dudani 3 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • Embedded operating system • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 4 May not be reproduced or redistributed for commercial use.
Why ARM? • Low power consumption • Fast execution per Watt • Good backward compatibility • Inexpensive • Variety of core offerings • … and other advantages we will see in upcoming slides Copyright (c) 2006 by Ajay Dudani 5 May not be reproduced or redistributed for commercial use.
Why ARM? • And … Marketing ☺ Copyright (c) 2006 by Ajay Dudani 6 May not be reproduced or redistributed for commercial use.
Detailed Outline • ARM Technology – History – The competition Copyright (c) 2006 by Ajay Dudani 7 May not be reproduced or redistributed for commercial use.
Detailed Outline • ARM Tools and products – Microprocessors – Compilers and debuggers – Single board computers – Documents and reference text Copyright (c) 2006 by Ajay Dudani 8 May not be reproduced or redistributed for commercial use.
Detailed Outline • ARM Processor – Programming model – General purpose registers – Program control registers – Pipelining – Memory protection Copyright (c) 2006 by Ajay Dudani 9 May not be reproduced or redistributed for commercial use.
Detailed Outline • Toolchain – ARM Toolchain – GNU Toolchain – Others Copyright (c) 2006 by Ajay Dudani 10 May not be reproduced or redistributed for commercial use.
Detailed Outline • ARM Instruction Set – Instruction set encoding – Conditional field – Data processing instructions – Branch instructions – Load-store instructions – Software interrupt instruction – Program status register instructions – Semaphore instructions – Coprocessor instructions – Extending instructions Copyright (c) 2006 by Ajay Dudani 11 May not be reproduced or redistributed for commercial use.
Detailed Outline • ARM Thumb Mode – Why Thumb? – Instruction set encoding – Branch instructions – Data processing instructions – Load and store instructions – Switching between ARM and Thumb mode Copyright (c) 2006 by Ajay Dudani 12 May not be reproduced or redistributed for commercial use.
Detailed Outline • ARM Exceptions and Interrupts – Exception vector table – Exception modes – Exception and interrupt handling Copyright (c) 2006 by Ajay Dudani 13 May not be reproduced or redistributed for commercial use.
Detailed Outline • ARM Firmware – Bootloader – Standalone code – Example of initialization Copyright (c) 2006 by Ajay Dudani 14 May not be reproduced or redistributed for commercial use.
Detailed Outline • ARM Caches – Memory hierarchy – Cache policy – Flushing policy – Software performance Copyright (c) 2006 by Ajay Dudani 15 May not be reproduced or redistributed for commercial use.
Detailed Outline • ARM MMU and MPU – Protected memory – Example of memory protection – Virtual memory concepts – Example of virtual memory system Copyright (c) 2006 by Ajay Dudani 16 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 17 May not be reproduced or redistributed for commercial use.
ARM Technology Overview • ARM: “The Architecture For The Digital World” • ARM is a physical hardware design and intellectual property company • ARM licenses its cores out and other companies make processors based on its cores • ARM also provides toolchain and debugging tools for its cores Copyright (c) 2006 by Ajay Dudani 18 May not be reproduced or redistributed for commercial use.
ARM Technology Overview (2) Companies licensing ARM IP: 3Com Motorola Agilent Technologies Panasonic Altera Qualcomm Epson Sharp Freescale Sanyo Fijitsu Sun Microsystems NEC Sony Nokia Symbian Intel Texas Instruments IBM Toshiba Microsoft Wipro Source: ARM Website … and many more Copyright (c) 2006 by Ajay Dudani 19 May not be reproduced or redistributed for commercial use.
ARM History • Acorn Computer Group developed world’s first RISC processor in 1985 • Roger Wilson and Steve Furber were the principle developers • ARM (Advanced RISC Machines) was a spin out from Acorn in 1990 with goal of defining a new microprocessor standard Copyright (c) 2006 by Ajay Dudani 20 May not be reproduced or redistributed for commercial use.
ARM History (2) • Acorn Computer Group Source: Wikipedia Copyright (c) 2006 by Ajay Dudani 21 May not be reproduced or redistributed for commercial use.
ARM History (3) • ARM delivered ARM6 in 1991 – Introduced 32 bit addressing support – New instruction for program status registers – Variant used in Apple Newton PDA • By 1996 ARM7 was being widely used – Microsoft started port of WinCE to ARM – Added multimedia extensions • Exponential growth from then on… Copyright (c) 2006 by Ajay Dudani 22 May not be reproduced or redistributed for commercial use.
ARM and StrongARM • Intel gained certain IP from ARM as part of lawsuit settlement and modified ARM architecture branding it as StrongARM • StrongARM name was changed to XScale – Processor SA1000 , SA1100 • XScale is close to ARMv5 instruction set • XScale division of Intel was sold to Marvel Inc. in 2006 Copyright (c) 2006 by Ajay Dudani 23 May not be reproduced or redistributed for commercial use.
ARM Today • ARM7xxx – 3 stage pipeline – Integer processor – MMU support for WinCE, Linux and Symbian – Used in entry level mobiles, mp3 players, pagers • ARM9xxx – 5 stage pipeline – Separate data and instruction cache – Higher end mobile and communication devices – Telematic and infotainment systems – ARM and Thumb instruction set Copyright (c) 2006 by Ajay Dudani 24 May not be reproduced or redistributed for commercial use.
ARM Today (2) • ARM11xxx – 7 stage pipeline – Trustzone security related extensions – Reduced power consumption – Speed improvements – More DSP and SIMD extensions – Used in PDA, smartphones, industrial controllers, mobile gaming Copyright (c) 2006 by Ajay Dudani 25 May not be reproduced or redistributed for commercial use.
ARM Processor Family • ARM has devised a naming convention for its processors • Revisions: ARMv1, v2 … v6, v7 • Core implementation: – ARM1, ARM2, ARM7, StrongARM, ARM926EJ, ARM11, Cortex • ARM11 is based on ARMv6 • Cortex is based on ARMv7 Copyright (c) 2006 by Ajay Dudani 26 May not be reproduced or redistributed for commercial use.
ARM Processor Family (2) • Differences between cores – Processor modes – Pipeline – Architecture – Memory protection unit – Memory management unit – Cache – Hardware accelerated Java – … and others Copyright (c) 2006 by Ajay Dudani 27 May not be reproduced or redistributed for commercial use.
ARM Processor Family (3) • Examples: – ARM7TDMI • No MMU, No MPU, No cache, No Java, Thumb mode – ARM922T • MMU, No MPU, 8K+8K data and instruction cache, No Java, Thumb mode – ARM1136J-S • MMU, No MPU, configurable caches, with accelerated Java and Thumb mode Copyright (c) 2006 by Ajay Dudani 28 May not be reproduced or redistributed for commercial use.
ARM Processor Family (4) • Naming convention • ARM [x][y][z][T][D][M][I][E][J][F][S] – x – Family – y – memory management/protection – z – cache – T – Thumb mode – D – JTAG debugging – M – fast multiplier – I – Embedded ICE macrocell – E – Enhanced instruction (implies TDMI) – J – Jazelle, hardware accelerated Java – F – Floating point unit – S – Synthesizable version Copyright (c) 2006 by Ajay Dudani 29 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 30 May not be reproduced or redistributed for commercial use.
ARM Tools & Products Disclaimer: All owners own their respective trademarks Copyright (c) 2006 by Ajay Dudani 31 May not be reproduced or redistributed for commercial use.
ARM Chips • ARM Ltd – Provides ARM cores – Intellectual property • Analog Devices – ADuC7019, ADuC7020, ADuC7021, ADuC7022, ADuC7024, ADuC7025, ADuC7026, ADuC7027, ADuC7128, ADuC7129 • Atmel – AT91C140, AT91F40416, AT91F40816, AT91FR40162 • Freescale – MAC7101, MAC7104, MAC7105, MAC7106 • Samsung – S3C44B0X, S3C4510B • Sharp – LH75400, LH75401, LH75410, LH75411 • Texas Instruments – TMS470R1A128, TMS470R1A256, TMS470R1A288 • And others… Copyright (c) 2006 by Ajay Dudani 32 May not be reproduced or redistributed for commercial use.
ARM Development Tools • Compilers: – GNU Compiler – ADS from ARM (older version) – RVCT Real View compiler tools from ARM – 3rd Party • Debugging – GNU gdb – Lauterbach JTAG/Trace32 tools – ETM hardware debugging & profilingmodules – Windriver tools Copyright (c) 2006 by Ajay Dudani 33 May not be reproduced or redistributed for commercial use.
ARM Single Board Computers • TS-7200 ARM Single board computer – 200 MHz ARM9 processor with MMU – 32 MB RAM – 8 MB Flash – Compact flash – 10/100 Ethernet Copyright (c) 2006 by Ajay Dudani 34 May not be reproduced or redistributed for commercial use.
ARM Single Board Computers (2) • Cirrus Logic ARM CS98712 – 16 MB RAM – 1MB Flash – 1 Serial port – LED lights Copyright (c) 2006 by Ajay Dudani 35 May not be reproduced or redistributed for commercial use.
ARM Single Board Computers (3) • LN24x0/LP64 – 200 Mhz ARM9 processor – LCD controller – Touchscreen – USB, IrDA ports – HDD and CD-ROM support – Speaker – JTAG ports Copyright (c) 2006 by Ajay Dudani 36 May not be reproduced or redistributed for commercial use.
Recommended Text • “ARM System Developer’s Guide” – Sloss, et. al. – ISBN 1-55860-874-5 • “ARM Architecture Reference Manual” – David Seal – ISBN 0-201-737191 – Softcopy available at www.arm.com • “ARM system-on-chip architecture” – Steve Fuber – ISBN 0-201-67519-6 Copyright (c) 2006 by Ajay Dudani 37 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 38 May not be reproduced or redistributed for commercial use.
ARM Design Philosophy • ARM core uses RISC architecture – Reduced instruction set – Load store architecture – Large number of general purpose registers – Parallel executions with pipelines • But some differences from RISC – Enhanced instructions for • Thumb mode • DSP instructions • Conditional execution instruction • 32 bit barrel shifter Copyright (c) 2006 by Ajay Dudani 39 May not be reproduced or redistributed for commercial use.
ARM Programming Model • A=B+C • To evaluate the above expression – Load A to a general purpose register R1 – Load B to a general purpose register R2 – Load C to a general purpose register R3 – ADD R1, R2, R3 – Store R1 to A Copyright (c) 2006 by Ajay Dudani 40 May not be reproduced or redistributed for commercial use.
Registers • ARM has a load store architecture • General purpose registers can hold data or address • Total of 37 registers each 32 bit wide • There are 18 active registers – 16 data registers – 2 status registers Copyright (c) 2006 by Ajay Dudani 41 May not be reproduced or redistributed for commercial use.
Registers (2) • Registers R0 thru R12 are general R0 R1 purpose registers R2 R3 • R13 is used as stack pointer (sp) R4 R5 R6 • R14 is used as link register (lr) R7 R8 • R15 is used a program counter (pc) R9 R10 • CPSR – Current program status R11 R12 register R13 (sp) R14 (lr) R15 (pc) • SPSR – Stored program status register CPSR SPSR Copyright (c) 2006 by Ajay Dudani 42 May not be reproduced or redistributed for commercial use.
Registers (3) • Program status register – CPSR is used to control and store CPU states – CPSR is divided in four 8 bit fields • Flags • Status • Extension • Control Copyright (c) 2006 by Ajay Dudani 43 May not be reproduced or redistributed for commercial use.
Registers (4) • Program status register flags – N:1 – Negative result – Z:1 – Result is zero – C:1 – Carry in addition operation – C:0 – Borrow in subtraction operation – V:1 – Overflow or underflow Copyright (c) 2006 by Ajay Dudani 44 May not be reproduced or redistributed for commercial use.
Registers (5) • Program status register controls – I:1 – IRQ interrupts disabled – F:1 – FIQ interrupts disabled – T:0 – ARM Mode – T:1 – Thumb Mode Copyright (c) 2006 by Ajay Dudani 45 May not be reproduced or redistributed for commercial use.
Registers (6) • Program status register control modes – 0b10000 – User mode – 0b10001 – FIQ mode – 0b10010 – IRQ mode – 0b10011 – Supervisor mode – 0b10111 – Abort mode – 0b11011 – Undefined mode – 0b11111 – System mode Copyright (c) 2006 by Ajay Dudani 46 May not be reproduced or redistributed for commercial use.
Processor Modes • Processor modes are execution modes which determines active registers and privileges • List of modes – Abort mode – Fast interrupt mode – Interrupt mode – Supervisor mode – System mode – Undefined mode – User mode • All except User mode are privileged modes – User mode is used for normal execution of programs and applications – Privileged modes allow full read/write to CPSR Copyright (c) 2006 by Ajay Dudani 47 May not be reproduced or redistributed for commercial use.
Banked Registers • Of total 37 registers only 18 are active in a given register mode User/System Supervisor Abort FIQ IRQ Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R8_fiq R9 R9_fiq R10 R10_fiq R11 R11_fiq R12 R12_fiq R13 (sp) R13_svc (sp) R13_abt (sp) R13_fiq (sp) R13_irq (sp) R13_und (sp) R14 (lr) R14_svc (lr) R14_abt (lr) R14_fiq (lr) R14_irq (lr) R14_und (lr) R15 (pc) CPSR SPSR SPSR_svc SPSR_abt SPSR_fiq SPSR_irq SPSR_und Copyright (c) 2006 by Ajay Dudani 48 May not be reproduced or redistributed for commercial use.
Pipeline • Pipelining is breaking down execution into multiple steps, and executing each step in parallel • Basic 3 stage pipeline – Fetch – Load from memory – Decode – Identify instruction to execute – Execute – Process instruction and write back result Copyright (c) 2006 by Ajay Dudani 49 May not be reproduced or redistributed for commercial use.
Pipeline (2) • Fetch Decode Execute Cycle 1 ADD Cycle 2 SUB ADD Time Cycle 3 CMP SUB ADD Copyright (c) 2006 by Ajay Dudani 50 May not be reproduced or redistributed for commercial use.
Pipeline (3) • ARM7 has a 3 stage pipeline – Fetch, Decode, Execute • ARM9 has a 5 stage pipeline – Fetch, Decode, Execute, Memory, Write • ARM10 has a 6 stage pipeline – Fetch, Issue, Decode, Execute, Memory, Write Copyright (c) 2006 by Ajay Dudani 51 May not be reproduced or redistributed for commercial use.
Pipeline (4) • In theory, each instruction is one instruction cycle • In practice, there is interdependency between instructions – Solution: instruction scheduling Copyright (c) 2006 by Ajay Dudani 52 May not be reproduced or redistributed for commercial use.
Memory Protection • Two modes for ARM memory protection – Unprotected mode • No hardware protection, software does protection of data between tasks – Protected mode • Hardware protects areas of memory and raises exceptions when policy is voilated • ARM divides memory to regions and programmer can set attributes on regions • ARM provides mechanisms to define and set attributes of regions programmatically Copyright (c) 2006 by Ajay Dudani 53 May not be reproduced or redistributed for commercial use.
Memory Management • ARM supports memory management and virtual memory • Programmatically access translation look- aside buffers • ARM memory management unit also supports Fast Context Switching Extensions that optimizes use of caches in multitasking environments • Details in later section Copyright (c) 2006 by Ajay Dudani 54 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 55 May not be reproduced or redistributed for commercial use.
Toolchain • GNU Tools – gcc – Front end to GNU compiler – binutils – Binary tools • ld – GNU Linker • as – GNU assembler • And others – gdb – GNU Debugger – uClib – Small footprint C Library Copyright (c) 2006 by Ajay Dudani 56 May not be reproduced or redistributed for commercial use.
Toolchain (2) • GCC – Invoked language specific modules – Invoked assembler and linker – arm-elf-gcc command • arm-elf-gcc test.c –o test • arm-elf-gcc test.S –o test Copyright (c) 2006 by Ajay Dudani 57 May not be reproduced or redistributed for commercial use.
Toolchain (3) • GCC ARM specific options – mapcs-frame: Generate ARM procedure call compliant stack frame – mbig-endian: Generate big endian code – mno-alignment-traps: Generate code that assumes that MMU does not trap on handling misaligned data – mcpu=name : Specify CPU name; gcc can determine what instructions it can use to generate output accordingly – mthumb: Generate code for ARM Thumb mode – msoft-float: Generate code assuming floating point hardware is not present. Do floating point operation optimization in software – Refer to GCC manual page for more on compiler options Copyright (c) 2006 by Ajay Dudani 58 May not be reproduced or redistributed for commercial use.
Inline assembly • Developer can insert ARM assembly code in C code – for example printf (“Hello ARM GCC”); __asm__ (“ldr r15, r0”); printf (“Program may have crashed”); Above code will corrupt program counter, so use inline assembly carefully Also, it may lead to non portable code Copyright (c) 2006 by Ajay Dudani 59 May not be reproduced or redistributed for commercial use.
Inline assembly (2) • Developer can force use of certain registers using extended assembly asm ( assembler template : output operands /* optional */ : input operands /* optional */ : list of clobbered registers /* optional */ ); • Example: int a = 10, b; __asm__ (“mov %0, %1” : “=r”(b) : “=r”(a)); Copyright (c) 2006 by Ajay Dudani 60 May not be reproduced or redistributed for commercial use.
Inline assembly (3) • Developer can request variable to be assigned to specific register register int regVar __asm__(“%r4”); • Can be used with local and global variables • Need –ffixed-<reg> compiler option for global variables • Refer to GCC Inline Assembly reference for more examples Copyright (c) 2006 by Ajay Dudani 61 May not be reproduced or redistributed for commercial use.
GNU Toolchain • Reference: – www.gnuarm.org – www.sourceware.org/binutils/ – www.gnu.org/software/gdb/ – www.sourceware.org/insight/ – www.uclibc.org – GCC improvements for ARM • www.inf.u-szeged.hu/gcc-arm/ Copyright (c) 2006 by Ajay Dudani 62 May not be reproduced or redistributed for commercial use.
ARM Toolchain • ADS: ARM Developer Suite is older version of compiler, assembler and linker tools from ARM • RCVT: Latest ARM compiler, assembler and linker Copyright (c) 2006 by Ajay Dudani 63 May not be reproduced or redistributed for commercial use.
ARM Toolchain • ARM also provides support for RealView tools it acquired as part of Keil acquisition • JTAG Support: ARM provides debugging tools to be used with JTAG supported hardware • ETM Support: Embedded Trace Module is hardware debug unit that extends on-target debugging capabilities by providing extra memory and registers for debugging purpose • Refer to www.arm.com and www.keil.com/arm/ for details on ARM tools Copyright (c) 2006 by Ajay Dudani 64 May not be reproduced or redistributed for commercial use.
Other Toolchains • GNU X-Tools – www.microcross.com • IAR ARM Kit – www.iar.com • Intel Development Suite for XScale – www.intel.com Copyright (c) 2006 by Ajay Dudani 65 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 66 May not be reproduced or redistributed for commercial use.
ARM Instruction Set • Overview Copyright (c) 2006 by Ajay Dudani 67 May not be reproduced or redistributed for commercial use.
ARM Instruction Set (2) • Condition fields Copyright (c) 2006 by Ajay Dudani 68 May not be reproduced or redistributed for commercial use.
ARM Instruction Set (3) • Add • Subract • Multiply Copyright (c) 2006 by Ajay Dudani 69 May not be reproduced or redistributed for commercial use.
ARM Instruction Set (4) • Bit shifting Copyright (c) 2006 by Ajay Dudani 70 May not be reproduced or redistributed for commercial use.
ARM Instruction Set (5) • Status register operation Copyright (c) 2006 by Ajay Dudani 71 May not be reproduced or redistributed for commercial use.
ARM Instruction Set (6) • Semaphore instruction Copyright (c) 2006 by Ajay Dudani 72 May not be reproduced or redistributed for commercial use.
ARM Instruction Set (7) • Placeholder page Copyright (c) 2006 by Ajay Dudani 73 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 74 May not be reproduced or redistributed for commercial use.
Thumb Instruction Set • Overview of 16 bit mode Copyright (c) 2006 by Ajay Dudani 75 May not be reproduced or redistributed for commercial use.
Thumb Instruction Set (2) • Thumb Instruction set details Copyright (c) 2006 by Ajay Dudani 76 May not be reproduced or redistributed for commercial use.
Thumb Instruction Set (3) • Switching between ARM and Thumb mode Copyright (c) 2006 by Ajay Dudani 77 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 78 May not be reproduced or redistributed for commercial use.
Exceptions • Exception handling is a programming language or hardware mechanism to catch runtime errors • C++ and Java support exception handling in software 1. void func() 2. { 3. try 4. { 5. int a = 100/0; 6. } 7. catch(...) 8. { 9. cout << "Caught exception" << endl; 10. return; 11. } 12. cout << "No exception detected!" << endl; 13. return; 14. } Copyright (c) 2006 by Ajay Dudani 79 May not be reproduced or redistributed for commercial use.
Exceptions (2) • ARM support 7 exception modes • Developers can write custom exception handlers to deal with exception conditions • For example: – Consider a system that crashes if PC is corrupted. This will cause an exception. In corresponding exception handler, programmer can save state of all registers to file system for debugging and reset Copyright (c) 2006 by Ajay Dudani 80 May not be reproduced or redistributed for commercial use.
Exceptions (3) • ARM Exceptions in order of priority – Reset – Data abort – FIQ – IRQ – Prefetch abort – Undefined instruction – Software interrupt Copyright (c) 2006 by Ajay Dudani 81 May not be reproduced or redistributed for commercial use.
Reset exception • Highest priority exception • The reset handler runs in supervisor mode • Handler is generally located at 0x00000000 • In Reset handler, FIQ and IRQ are disabled • Other exceptions are not likely to occur when in reset handler Copyright (c) 2006 by Ajay Dudani 82 May not be reproduced or redistributed for commercial use.
Reset exception (2) • Actions performed when reset is de-asserted – R14_svc is set to unpredictable value – SPSR_svc is set to unpredictable value – CPSR[4:0] is 0b10011 – supervisor mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is 1 – disable fast interrupts – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000000 Copyright (c) 2006 by Ajay Dudani 83 May not be reproduced or redistributed for commercial use.
Data abort exception • Data abort exception mean software is trying to read/write an illegal memory location • Data abort has higher priority than FIQ • While handling this more, IRQ is disabled • The abort handler should not cause further aborts – Consider case of prefetch abort in abort handler – This will cause abort handler to be reentered • Abort handler is generally located at 0x00000010 Copyright (c) 2006 by Ajay Dudani 84 May not be reproduced or redistributed for commercial use.
Data abort exception (2) • Actions performed on data abort – R14_abt = address of abort instruction + 8 – SPSR_svc = CPSR – CPSR[4:0] is 0b10111 – abort mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000010 Copyright (c) 2006 by Ajay Dudani 85 May not be reproduced or redistributed for commercial use.
Fast interrupt • FIQ exception mode exists if developer wants to handle certain interrupts faster • Additional banked registers in FIQ mode make execution fast • Higher priority in IRQ • Disabled IRQ and FIQ • Default ARM cores do not handle nested interrupts • FIQ handler is generally located at 0x0000001C Copyright (c) 2006 by Ajay Dudani 86 May not be reproduced or redistributed for commercial use.
Fast interrupt (2) • Actions performed on fast interrupt – R14_fiq = address of next instruction to execute + 4 – SPSR_fiq = CPSR – CPSR[4:0] is 0b10111 – FIQ mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is 1 – disable fast interrupts – CPSR[7] is 1 – disable normal interrupts – PC = 0x0000001C Copyright (c) 2006 by Ajay Dudani 87 May not be reproduced or redistributed for commercial use.
Normal interrupt • Normal interrupt is lower priority than fast interrupts • Disabled IRQ when handling normal interrupts • Default ARM cores do not handle nested interrupts • IRQ handler is generally located at 0x00000018 Copyright (c) 2006 by Ajay Dudani 88 May not be reproduced or redistributed for commercial use.
Normal interrupt (2) • Actions performed on normal interrupt – R14_irq = address of next instruction to execute + 4 – SPSR_irq = CPSR – CPSR[4:0] is 0b10010 – IRQ mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000018 Copyright (c) 2006 by Ajay Dudani 89 May not be reproduced or redistributed for commercial use.
Prefetch abort • If processor reads instruction from undefined memory, it causes a prefetch abort exception • Prefetch abort occurs when instruction reaches execution stage of pipeline • Disabled normal interrupts when handling prefetch abort • Prefetch abort handler is generally located at 0x0000000C Copyright (c) 2006 by Ajay Dudani 90 May not be reproduced or redistributed for commercial use.
Prefetch abort (2) • Actions performed on prefetch abort – R14_abt = address of next instruction to execute + 4 – SPSR_irq = CPSR – CPSR[4:0] is 0b10111 – abort mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x0000000C Copyright (c) 2006 by Ajay Dudani 91 May not be reproduced or redistributed for commercial use.
Undefined instruction • When executing coprocessor instructions, ARM waits for coprocessor to acknowledge that it can execute the instruction • If no coprocessor can handle given instruction, undefined instruction exception is raised • In simulators, this can be used to simulate coprocessor in software • Undefined instruction handler can parse instructions and process them in software simulator • Undefined instruction handler is generally located at 0x00000004 Copyright (c) 2006 by Ajay Dudani 92 May not be reproduced or redistributed for commercial use.
Undefined instruction (2) • Actions performed on undefined instruction – R14_und = address of next instruction to execute – SPSR_und = CPSR – CPSR[4:0] is 0b11011 – undefined mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000004 Copyright (c) 2006 by Ajay Dudani 93 May not be reproduced or redistributed for commercial use.
Software interrupt • Software interrupt exception is used to enter supervisor mode to execute a privileged OS function • Typically applications run in user mode and kernel in supervisor mode • Execution of any system call will cause SWI software interrupt to change mode to supervisor mode • Software interrupt handler is generally located at 0x00000008 Copyright (c) 2006 by Ajay Dudani 94 May not be reproduced or redistributed for commercial use.
Software interrupt (2) • Actions performed on software interrupt – R14_svc = address of next instruction to execute after SWI – SPSR_irq = CPSR – CPSR[4:0] is 0b10011 – supervisor mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000008 Copyright (c) 2006 by Ajay Dudani 95 May not be reproduced or redistributed for commercial use.
Exception table • Memory layout 0x00000000 – reset exception handler 0x00000004 – undefined instruction handler 0x00000008 – software interrupt handler 0x0000000C – prefetch abort handler 0x00000010 – data abort handler 0x00000018 – normal interrupt handler 0x0000001C – fast interrupt handler • High vectors – Some implementation keep this table in 0xFFFF0000 to 0xFFFF001C range which is known as high vector location Copyright (c) 2006 by Ajay Dudani 96 May not be reproduced or redistributed for commercial use.
Exception handling 1. Exception is raised 2. Lookup to exception table to find exception handler 3. Exception handler is executed 4. Return from exception handler Exception Vector Table SWI Handler Application 0x00 Reset_Handler MOV r0, r1 0x04 Undef_Handler SWI 0x1D 0x08 SWI_Handler ... ADD r0,r2,r0 0x0c PAbt_Handler ... DAbt_Handler ... 0x10 0x14 ... IRQ_Handler MOV PC, R14_svc 0x18 FIQ_Handler 0x1c Copyright (c) 2006 by Ajay Dudani 97 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 98 May not be reproduced or redistributed for commercial use.
ARM Firmware • “Now the earth was formless and empty. Darkness was on the surface of the deep. God's Spirit was hovering over the surface of the waters.” “God said, “Let there be light”, and there was light.” • For the processor, someone needs to read application and copy it into RAM to start execution – What address to copy it to RAM – Setup stack and heap – Transfer control to application Copyright (c) 2006 by Ajay Dudani 99 May not be reproduced or redistributed for commercial use.
System initialization • Two stages of initialization: 1. Initialize stack, vectors and I/O system 2. Initialize application and associated libraries – The system set up could be – With an RTOS, in which case it does initialization of system environment (stack, vectors etc.). User application then starts with main() or RTOS specific entry point – Without an RTOS, ROM code handles transferring control to user application. User application need additional code to setup system environment Copyright (c) 2006 by Ajay Dudani 100 May not be reproduced or redistributed for commercial use.
Initialization • Execution environment: 1. At reset • Processor is in SVC mode • Interrupts are disabled • Running in ARM mode 2. Entry point on powerup • Use assember directive ENTRY to specify entry point • ROM code usually has entry point 0x00 Copyright (c) 2006 by Ajay Dudani 101 May not be reproduced or redistributed for commercial use.
Initialization (2) • Execution environment: 3. Setup exception vector table • If ROM is mapped to address 0x00, it contains hard coded exception vector table • If ROM is mapped elsewhere, exception table is copied to RAM address 0x00 4. Initialize memory system • Initialize memory management and memory protection before running any application code • Setup stack pointers, sp_SYS, sp_IRQ etc. • Initialize I/O devices. Note interrupts are still disabled • Change processor mode to user mode. At this stage we are ready to initialize application Copyright (c) 2006 by Ajay Dudani 102 May not be reproduced or redistributed for commercial use.
Initialization (3) • Application environment: 1. Initialize ZI writable region with zeroes 2. Initialize non zero data by copying initialization values 3. Pass on control to main function Copyright (c) 2006 by Ajay Dudani 103 May not be reproduced or redistributed for commercial use.
Initialization Example • Consider user code: 1. int main (void) 2. { 3. printf (“Hello ARM World”); 4. return 0; 5. } Copyright (c) 2006 by Ajay Dudani 104 May not be reproduced or redistributed for commercial use.
Initialization Example (2) • Consider ROM mapped at address 0x24000 RW Data Application Code 0x24000000 Vector table & Init Code • Above image shows setup before application has been loaded Copyright (c) 2006 by Ajay Dudani 105 May not be reproduced or redistributed for commercial use.
Initialization Example (3) • At initialization, ROM code at 0x24000000 is in flash. Flash is mapped at 0x24000000 address • On Reset, Flash will be remapped by hardware to address 0x00 – ROM init code performs certain initialization – Initialized vector tables and data regions to RAM – Copies application code from ROM to RAM – Sets REMAP bit to map RAM to address 0x00 Copyright (c) 2006 by Ajay Dudani 106 May not be reproduced or redistributed for commercial use.
Initialization Example (4) Code (RO+RW) Code (RO+RW) Flash 0x24000000 I/O Addresses UART Stack Heap RAM ZI data Initialized RW data Code aliased from Code (RO+RW) 0x24000000 Vector table Copyright (c) 2006 by Ajay Dudani 107 May not be reproduced or redistributed for commercial use.
Firmware • Typically the ROM code is bootloader – Developers configure the bootloader as per their requirements to specify memory map, bootup address, policy to copy code to RAM • Application code can – Either be single binary with RTOS in which case RTOS provides basic OS services – For simple applications there may be no RTOS, just application compiled with simplified C library Copyright (c) 2006 by Ajay Dudani 108 May not be reproduced or redistributed for commercial use.
Firmware (2) • Some examples of bootloaders – Grub – Lilo – RedBoot • Some examples of RTOS – Linux – eCos – vxWorks • Some examples of embedded libraries – Busybox – ucLib Copyright (c) 2006 by Ajay Dudani 109 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 110 May not be reproduced or redistributed for commercial use.
Memory hierarchy Registers Caches RAM Memory Hard disk External & network storage Copyright (c) 2006 by Ajay Dudani 111 May not be reproduced or redistributed for commercial use.
Caches • A cache is high speed memory location generally used to reduce latency in memory access for data and instructions • Whenever CPU reads data from (slower) RAM, a copy is stored in (faster) cache • If CPU access the same data again, it can be served from cache. This is a hit • A write buffer speeds up writing to main memory Copyright (c) 2006 by Ajay Dudani 112 May not be reproduced or redistributed for commercial use.
Cache properties • Set associativity – Fully associative – Direct mapped • Cache size • Unified or separate – Caches for data and instruction • Write through or write back – Property associated with mechanism to write data back to main memory • Read allocate or write allocate – Property associated dealing with cache miss • Replacement strategy – Property associated with replacing cache data with newer ones Copyright (c) 2006 by Ajay Dudani 113 May not be reproduced or redistributed for commercial use.
Cache issues • Address mapping changes – Virtual or physical address can get remapped • Cache coherence and invalidation • Direct Memory Access (DMA) operation can update main memory without going through cache Copyright (c) 2006 by Ajay Dudani 114 May not be reproduced or redistributed for commercial use.
ARM and caches • Cache and write buffers are controlled with coprocessor registers • Register 1: – C bit: Cache enable/disable – W bit: Enable/disable write buffer – I bit: Enable/disable instruction cache – RR bit: Cache replacement strategy Copyright (c) 2006 by Ajay Dudani 115 May not be reproduced or redistributed for commercial use.
ARM and caches (2) • Register 7: – Controls cache and write buffers – Different opcodes written to this register result in different behavior. Some examples: • Invalidate entire instruction/data cache • Flush prefetch buffer • Writeback outstanding cache data to main memory Copyright (c) 2006 by Ajay Dudani 116 May not be reproduced or redistributed for commercial use.
ARM and caches (3) • Register 9: – Controls cache lockdown – Caches can slow down worst case execution time of code and be undeterministic because • It needs to handle cache misses • Write back of data to main memory can take time • Cache mechanism can load more data than request by process – Cache lockdown helps control these parameters to remove undeterministic behavior in critical code Copyright (c) 2006 by Ajay Dudani 117 May not be reproduced or redistributed for commercial use.
Caches • Caches can provide huge performance improvements to the system • As a developer, one should do profiling by changing various caching options when developing board support package Copyright (c) 2006 by Ajay Dudani 118 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 119 May not be reproduced or redistributed for commercial use.
Memory Management • We saw earlier that during initialization, code from ROM is copied to RAM • But what is code size is larger than RAM available? Options: – Do not allow program to be loaded – Load only part of program and swap parts of program as requested – Or allow program to see large virtual memory Copyright (c) 2006 by Ajay Dudani 120 May not be reproduced or redistributed for commercial use.
Virtual Memory • Program is loaded into RAM until full • Application starts running with partial program loaded in memory • When program wants to access virtual memory address that is not in physical memory it generated a page fault • Page fault handler is responsible to get new page of memory into RAM Copyright (c) 2006 by Ajay Dudani 121 May not be reproduced or redistributed for commercial use.
ARM MMU • MMU handles translation from virtual to physical memory • Presents 4 GB address space • Supports 3 options for memory granularity: – 1 MB sections – 64 KB pages – 4 KB pages • Page fault is indicate by abort • Abort handler is responsible for fetching pages Copyright (c) 2006 by Ajay Dudani 122 May not be reproduced or redistributed for commercial use.
ARM Memory Protection • Memory protection is required to prevent one application from overwriting other application’s code • This facility can be enabled by using MMU • Using MMU, system goes to abort mode when application accesses memory to which it does not have permissions Copyright (c) 2006 by Ajay Dudani 123 May not be reproduced or redistributed for commercial use.
ARM Memory Protection (2) • ARM MPU allows memory protection without using MMU facilities • ARM defines up to 8 protection regions which can be configured through MPU registers • MPU offers good memory protection option for cases – Where 8 protection regions are enough – Virtual memory is not required Copyright (c) 2006 by Ajay Dudani 124 May not be reproduced or redistributed for commercial use.
MPU Registers • CP15 – M bit: enable/disable memory protection – Cache bits: control if cache buffer is enabled/disabled – Buffer bits: control if write buffer is enabled/disabled – Access control bits: control access rights of 8 regions – Mechanism to define 8 memory regions Copyright (c) 2006 by Ajay Dudani 125 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 126 May not be reproduced or redistributed for commercial use.
ARM Future Development • ARMv7 based processors – ARM Cortex-M3 – TI OMAP – Qualcomm Scorpion • In embedded systems its not just speed, its about speed/watt • Approximately 2 billion ARM based devices selling each year… and growing! Copyright (c) 2006 by Ajay Dudani 127 May not be reproduced or redistributed for commercial use.
ARM Future Development (2) • Qualcomm’s SnapDragon based on Scorpion: – 1 GHz microprocessor – CDMA and UMTS network support – Upto 12 mega pixels camera support – Enhanced multimedia support – DVD quality display support – GPS support – Support for various peripherals like hard disk, monitor, USB devices, bluetooth etc. Copyright (c) 2006 by Ajay Dudani 128 May not be reproduced or redistributed for commercial use.
ARM Future Development (3) • Its ARM v/s x86 for UMPC and mobile devices market Copyright (c) 2006 by Ajay Dudani 129 May not be reproduced or redistributed for commercial use.
Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 130 May not be reproduced or redistributed for commercial use.
Questions & Comments Copyright (c) 2006 by Ajay Dudani 131 May not be reproduced or redistributed for commercial use.
Ad

Recommended

Arm Processor
Arm ProcessorArm Processor
Arm Processor
Dangling Sid
 
ARM7-ARCHITECTURE
ARM7-ARCHITECTURE ARM7-ARCHITECTURE
ARM7-ARCHITECTURE
Dr.YNM
 
ARM Processor
ARM ProcessorARM Processor
ARM Processor
Aniket Thakur
 
ARM Processor Tutorial
ARM Processor Tutorial ARM Processor Tutorial
ARM Processor Tutorial
Embeddedcraft Craft
 
Arm corrected ppt
Arm corrected pptArm corrected ppt
Arm corrected ppt
anish jagan
 
Arm processor architecture awareness session pi technologies
Arm processor architecture awareness session pi technologiesArm processor architecture awareness session pi technologies
Arm processor architecture awareness session pi technologies
PiTechnologies
 
Arm architecture overview
Arm architecture overviewArm architecture overview
Arm architecture overview
Sunil Thorat
 
ARM7TDM
ARM7TDMARM7TDM
ARM7TDM
Ramasubbu .P
 
ARM
ARMARM
ARM
Pune University
 
Ppt
PptPpt
Ppt
Bala Ji
 
Arm Lecture
Arm LectureArm Lecture
Arm Lecture
anishgoel
 
Introduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM ProcessorIntroduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM Processor
Darling Jemima
 
Unit vi (2)
Unit vi (2)Unit vi (2)
Unit vi (2)
Siva Nageswararao
 
Arm
ArmArm
Arm
anishgoel
 
ARM architcture
ARM architcture ARM architcture
ARM architcture
Hossam Adel
 
2 introduction to arm architecture
2 introduction to arm architecture2 introduction to arm architecture
2 introduction to arm architecture
satish1jisatishji
 
Arm arc-2016
Arm arc-2016Arm arc-2016
Arm arc-2016
Mohammed Gomaa
 
ARM - Advance RISC Machine
ARM - Advance RISC MachineARM - Advance RISC Machine
ARM - Advance RISC Machine
EdutechLearners
 
Introduction to arm architecture
Introduction to arm architectureIntroduction to arm architecture
Introduction to arm architecture
Zakaria Gomaa
 
Unit vi (1)
Unit vi (1)Unit vi (1)
Unit vi (1)
Siva Nageswararao
 
Arm cortex-m3 by-joe_bungo_arm
Arm cortex-m3 by-joe_bungo_armArm cortex-m3 by-joe_bungo_arm
Arm cortex-m3 by-joe_bungo_arm
Prashant Ahire
 
EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj...
EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj... EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj...
EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj...
D Y PATIL COLLEGE OF ENGINEERING PUNE
 
ARM Architecture
ARM ArchitectureARM Architecture
ARM Architecture
Kshitij Gorde
 
ARM 7 Detailed instruction set
ARM 7 Detailed instruction setARM 7 Detailed instruction set
ARM 7 Detailed instruction set
P.r. Dinesh
 
Unitii armarchitecture-130305014346-phpapp01
Unitii armarchitecture-130305014346-phpapp01Unitii armarchitecture-130305014346-phpapp01
Unitii armarchitecture-130305014346-phpapp01
mannepalli Srinivasulu
 
ARM Processor architecture
ARM Processor architectureARM Processor architecture
ARM Processor architecture
rajkciitr
 
ARM CORTEX M3 PPT
ARM CORTEX M3 PPTARM CORTEX M3 PPT
ARM CORTEX M3 PPT
Gaurav Verma
 
Arm architecture
Arm architectureArm architecture
Arm architecture
MinYeop Na
 
ARM- Programmer's Model
ARM- Programmer's ModelARM- Programmer's Model
ARM- Programmer's Model
Ravikumar Tiwari
 
Arm architecture
Arm architectureArm architecture
Arm architecture
Pantech ProLabs India Pvt Ltd
 

More Related Content

What's hot (20)

ARM
ARMARM
ARM
Pune University
 
Ppt
PptPpt
Ppt
Bala Ji
 
Arm Lecture
Arm LectureArm Lecture
Arm Lecture
anishgoel
 
Introduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM ProcessorIntroduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM Processor
Darling Jemima
 
Unit vi (2)
Unit vi (2)Unit vi (2)
Unit vi (2)
Siva Nageswararao
 
Arm
ArmArm
Arm
anishgoel
 
ARM architcture
ARM architcture ARM architcture
ARM architcture
Hossam Adel
 
2 introduction to arm architecture
2 introduction to arm architecture2 introduction to arm architecture
2 introduction to arm architecture
satish1jisatishji
 
Arm arc-2016
Arm arc-2016Arm arc-2016
Arm arc-2016
Mohammed Gomaa
 
ARM - Advance RISC Machine
ARM - Advance RISC MachineARM - Advance RISC Machine
ARM - Advance RISC Machine
EdutechLearners
 
Introduction to arm architecture
Introduction to arm architectureIntroduction to arm architecture
Introduction to arm architecture
Zakaria Gomaa
 
Unit vi (1)
Unit vi (1)Unit vi (1)
Unit vi (1)
Siva Nageswararao
 
Arm cortex-m3 by-joe_bungo_arm
Arm cortex-m3 by-joe_bungo_armArm cortex-m3 by-joe_bungo_arm
Arm cortex-m3 by-joe_bungo_arm
Prashant Ahire
 
EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj...
EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj... EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj...
EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj...
D Y PATIL COLLEGE OF ENGINEERING PUNE
 
ARM Architecture
ARM ArchitectureARM Architecture
ARM Architecture
Kshitij Gorde
 
ARM 7 Detailed instruction set
ARM 7 Detailed instruction setARM 7 Detailed instruction set
ARM 7 Detailed instruction set
P.r. Dinesh
 
Unitii armarchitecture-130305014346-phpapp01
Unitii armarchitecture-130305014346-phpapp01Unitii armarchitecture-130305014346-phpapp01
Unitii armarchitecture-130305014346-phpapp01
mannepalli Srinivasulu
 
ARM Processor architecture
ARM Processor architectureARM Processor architecture
ARM Processor architecture
rajkciitr
 
ARM CORTEX M3 PPT
ARM CORTEX M3 PPTARM CORTEX M3 PPT
ARM CORTEX M3 PPT
Gaurav Verma
 
Arm architecture
Arm architectureArm architecture
Arm architecture
MinYeop Na
 
ARM
ARMARM
ARM
Pune University
 
Ppt
PptPpt
Ppt
Bala Ji
 
Arm Lecture
Arm LectureArm Lecture
Arm Lecture
anishgoel
 
Introduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM ProcessorIntroduction to Processor Design and ARM Processor
Introduction to Processor Design and ARM Processor
Darling Jemima
 
Unit vi (2)
Unit vi (2)Unit vi (2)
Unit vi (2)
Siva Nageswararao
 
Arm
ArmArm
Arm
anishgoel
 
ARM architcture
ARM architcture ARM architcture
ARM architcture
Hossam Adel
 
2 introduction to arm architecture
2 introduction to arm architecture2 introduction to arm architecture
2 introduction to arm architecture
satish1jisatishji
 
Arm arc-2016
Arm arc-2016Arm arc-2016
Arm arc-2016
Mohammed Gomaa
 
ARM - Advance RISC Machine
ARM - Advance RISC MachineARM - Advance RISC Machine
ARM - Advance RISC Machine
EdutechLearners
 
Introduction to arm architecture
Introduction to arm architectureIntroduction to arm architecture
Introduction to arm architecture
Zakaria Gomaa
 
Unit vi (1)
Unit vi (1)Unit vi (1)
Unit vi (1)
Siva Nageswararao
 
Arm cortex-m3 by-joe_bungo_arm
Arm cortex-m3 by-joe_bungo_armArm cortex-m3 by-joe_bungo_arm
Arm cortex-m3 by-joe_bungo_arm
Prashant Ahire
 
EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj...
EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj... EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj...
EMBEDDED SYSTEM DESIGN ARM architecture support for operating system by sanj...
D Y PATIL COLLEGE OF ENGINEERING PUNE
 
ARM Architecture
ARM ArchitectureARM Architecture
ARM Architecture
Kshitij Gorde
 
ARM 7 Detailed instruction set
ARM 7 Detailed instruction setARM 7 Detailed instruction set
ARM 7 Detailed instruction set
P.r. Dinesh
 
Unitii armarchitecture-130305014346-phpapp01
Unitii armarchitecture-130305014346-phpapp01Unitii armarchitecture-130305014346-phpapp01
Unitii armarchitecture-130305014346-phpapp01
mannepalli Srinivasulu
 
ARM Processor architecture
ARM Processor architectureARM Processor architecture
ARM Processor architecture
rajkciitr
 
ARM CORTEX M3 PPT
ARM CORTEX M3 PPTARM CORTEX M3 PPT
ARM CORTEX M3 PPT
Gaurav Verma
 
Arm architecture
Arm architectureArm architecture
Arm architecture
MinYeop Na
 

Viewers also liked (8)

ARM- Programmer's Model
ARM- Programmer's ModelARM- Programmer's Model
ARM- Programmer's Model
Ravikumar Tiwari
 
Arm architecture
Arm architectureArm architecture
Arm architecture
Pantech ProLabs India Pvt Ltd
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
Kamal Acharya
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
Dilum Bandara
 
Memory organization
Memory organizationMemory organization
Memory organization
Dr. Abhineet Anand
 
Arm modes
Arm modesArm modes
Arm modes
abhi165
 
04 cache memory
04 cache memory04 cache memory
04 cache memory
Sher Shah Merkhel
 
Memory organisation
Memory organisationMemory organisation
Memory organisation
ankush_kumar
 
ARM- Programmer's Model
ARM- Programmer's ModelARM- Programmer's Model
ARM- Programmer's Model
Ravikumar Tiwari
 
Arm architecture
Arm architectureArm architecture
Arm architecture
Pantech ProLabs India Pvt Ltd
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
Kamal Acharya
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
Dilum Bandara
 
Memory organization
Memory organizationMemory organization
Memory organization
Dr. Abhineet Anand
 
Arm modes
Arm modesArm modes
Arm modes
abhi165
 
04 cache memory
04 cache memory04 cache memory
04 cache memory
Sher Shah Merkhel
 
Memory organisation
Memory organisationMemory organisation
Memory organisation
ankush_kumar
 
Ad

Similar to Programming The Arm Microprocessor For Embedded Systems (20)

Programming The Arm Microprocessor For Embedded Systems
Programming The Arm Microprocessor For Embedded SystemsProgramming The Arm Microprocessor For Embedded Systems
Programming The Arm Microprocessor For Embedded Systems
ajaydudani
 
ARM Introduction.pptx
ARM Introduction.pptxARM Introduction.pptx
ARM Introduction.pptx
Pratik Gohel
 
Porting linux on ARM
Porting linux on ARMPorting linux on ARM
Porting linux on ARM
Satpal Parmar
 
Introduction to arm processor
Introduction to arm processorIntroduction to arm processor
Introduction to arm processor
RAMPRAKASHT1
 
Arm architecture chapter2_steve_furber
Arm architecture chapter2_steve_furberArm architecture chapter2_steve_furber
Arm architecture chapter2_steve_furber
asodariyabhavesh
 
Android Optimization: Myth and Reality
Android Optimization: Myth and RealityAndroid Optimization: Myth and Reality
Android Optimization: Myth and Reality
National Cheng Kung University
 
ARM
ARMARM
ARM
Ramasubbu .P
 
Mod 3.pptx
Mod 3.pptxMod 3.pptx
Mod 3.pptx
lekha349785
 
ARM Architecture
ARM ArchitectureARM Architecture
ARM Architecture
Dwight Sabio
 
Introduction To SPOT
Introduction To SPOTIntroduction To SPOT
Introduction To SPOT
pauldeng
 
1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC
1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC 1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC
1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC
IEEE SSCS AlexSC
 
ARM_System_Developers_Guide-Designing_and_Optimizing_System_Software.pdf
ARM_System_Developers_Guide-Designing_and_Optimizing_System_Software.pdfARM_System_Developers_Guide-Designing_and_Optimizing_System_Software.pdf
ARM_System_Developers_Guide-Designing_and_Optimizing_System_Software.pdf
KNaveenKumarECE
 
Simulation Directed Co-Design from Smartphones to Supercomputers
Simulation Directed Co-Design from Smartphones to SupercomputersSimulation Directed Co-Design from Smartphones to Supercomputers
Simulation Directed Co-Design from Smartphones to Supercomputers
Eric Van Hensbergen
 
Arm
ArmArm
Arm
ruchinkumar2003
 
Arm processors' architecture
Arm processors' architectureArm processors' architecture
Arm processors' architecture
Dr.YNM
 
Embedded Os [Linux & Co.]
Embedded Os [Linux & Co.]Embedded Os [Linux & Co.]
Embedded Os [Linux & Co.]
Ionela
 
Operating System Windows CE 7.0 and Processor ARM Advantages and Disadvantages
Operating System Windows CE 7.0 and Processor ARM Advantages and DisadvantagesOperating System Windows CE 7.0 and Processor ARM Advantages and Disadvantages
Operating System Windows CE 7.0 and Processor ARM Advantages and Disadvantages
Fatih Özlü
 
Bil2010 Millicomputing - The Future In Your Pocket
Bil2010 Millicomputing - The Future In Your PocketBil2010 Millicomputing - The Future In Your Pocket
Bil2010 Millicomputing - The Future In Your Pocket
Adrian Cockcroft
 
migrating from pic to m3
migrating from pic to m3migrating from pic to m3
migrating from pic to m3
Wassim Smati
 
Dai0234 a migrating_from_pic_to_m3
Dai0234 a migrating_from_pic_to_m3Dai0234 a migrating_from_pic_to_m3
Dai0234 a migrating_from_pic_to_m3
Wassim Smati
 
Programming The Arm Microprocessor For Embedded Systems
Programming The Arm Microprocessor For Embedded SystemsProgramming The Arm Microprocessor For Embedded Systems
Programming The Arm Microprocessor For Embedded Systems
ajaydudani
 
ARM Introduction.pptx
ARM Introduction.pptxARM Introduction.pptx
ARM Introduction.pptx
Pratik Gohel
 
Porting linux on ARM
Porting linux on ARMPorting linux on ARM
Porting linux on ARM
Satpal Parmar
 
Introduction to arm processor
Introduction to arm processorIntroduction to arm processor
Introduction to arm processor
RAMPRAKASHT1
 
Arm architecture chapter2_steve_furber
Arm architecture chapter2_steve_furberArm architecture chapter2_steve_furber
Arm architecture chapter2_steve_furber
asodariyabhavesh
 
Android Optimization: Myth and Reality
Android Optimization: Myth and RealityAndroid Optimization: Myth and Reality
Android Optimization: Myth and Reality
National Cheng Kung University
 
ARM
ARMARM
ARM
Ramasubbu .P
 
Mod 3.pptx
Mod 3.pptxMod 3.pptx
Mod 3.pptx
lekha349785
 
ARM Architecture
ARM ArchitectureARM Architecture
ARM Architecture
Dwight Sabio
 
Introduction To SPOT
Introduction To SPOTIntroduction To SPOT
Introduction To SPOT
pauldeng
 
1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC
1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC 1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC
1: Interfacing using ARM Cortex M4 || IEEE SSCS AlexSC
IEEE SSCS AlexSC
 
ARM_System_Developers_Guide-Designing_and_Optimizing_System_Software.pdf
ARM_System_Developers_Guide-Designing_and_Optimizing_System_Software.pdfARM_System_Developers_Guide-Designing_and_Optimizing_System_Software.pdf
ARM_System_Developers_Guide-Designing_and_Optimizing_System_Software.pdf
KNaveenKumarECE
 
Simulation Directed Co-Design from Smartphones to Supercomputers
Simulation Directed Co-Design from Smartphones to SupercomputersSimulation Directed Co-Design from Smartphones to Supercomputers
Simulation Directed Co-Design from Smartphones to Supercomputers
Eric Van Hensbergen
 
Arm
ArmArm
Arm
ruchinkumar2003
 
Arm processors' architecture
Arm processors' architectureArm processors' architecture
Arm processors' architecture
Dr.YNM
 
Embedded Os [Linux & Co.]
Embedded Os [Linux & Co.]Embedded Os [Linux & Co.]
Embedded Os [Linux & Co.]
Ionela
 
Operating System Windows CE 7.0 and Processor ARM Advantages and Disadvantages
Operating System Windows CE 7.0 and Processor ARM Advantages and DisadvantagesOperating System Windows CE 7.0 and Processor ARM Advantages and Disadvantages
Operating System Windows CE 7.0 and Processor ARM Advantages and Disadvantages
Fatih Özlü
 
Bil2010 Millicomputing - The Future In Your Pocket
Bil2010 Millicomputing - The Future In Your PocketBil2010 Millicomputing - The Future In Your Pocket
Bil2010 Millicomputing - The Future In Your Pocket
Adrian Cockcroft
 
migrating from pic to m3
migrating from pic to m3migrating from pic to m3
migrating from pic to m3
Wassim Smati
 
Dai0234 a migrating_from_pic_to_m3
Dai0234 a migrating_from_pic_to_m3Dai0234 a migrating_from_pic_to_m3
Dai0234 a migrating_from_pic_to_m3
Wassim Smati
 
Ad

Recently uploaded (20)

Scaling GenAI Inference From Prototype to Production: Real-World Lessons in S...
Scaling GenAI Inference From Prototype to Production: Real-World Lessons in S...Scaling GenAI Inference From Prototype to Production: Real-World Lessons in S...
Scaling GenAI Inference From Prototype to Production: Real-World Lessons in S...
Anish Kumar
 
Crypto Super 500 - 14th Report - June2025.pdf
Crypto Super 500 - 14th Report - June2025.pdfCrypto Super 500 - 14th Report - June2025.pdf
Crypto Super 500 - 14th Report - June2025.pdf
Stephen Perrenod
 
Artificial Intelligence in the Nonprofit Boardroom.pdf
Artificial Intelligence in the Nonprofit Boardroom.pdfArtificial Intelligence in the Nonprofit Boardroom.pdf
Artificial Intelligence in the Nonprofit Boardroom.pdf
OnBoard
 
Developing Schemas with FME and Excel - Peak of Data & AI 2025
Developing Schemas with FME and Excel - Peak of Data & AI 2025Developing Schemas with FME and Excel - Peak of Data & AI 2025
Developing Schemas with FME and Excel - Peak of Data & AI 2025
Safe Software
 
Oracle Cloud Infrastructure AI Foundations
Oracle Cloud Infrastructure AI FoundationsOracle Cloud Infrastructure AI Foundations
Oracle Cloud Infrastructure AI Foundations
VICTOR MAESTRE RAMIREZ
 
Your startup on AWS - How to architect and maintain a Lean and Mean account
Your startup on AWS - How to architect and maintain a Lean and Mean accountYour startup on AWS - How to architect and maintain a Lean and Mean account
Your startup on AWS - How to architect and maintain a Lean and Mean account
angelo60207
 
Cisco ISE Performance, Scalability and Best Practices.pdf
Cisco ISE Performance, Scalability and Best Practices.pdfCisco ISE Performance, Scalability and Best Practices.pdf
Cisco ISE Performance, Scalability and Best Practices.pdf
superdpz
 
Viral>Wondershare Filmora 14.5.18.12900 Crack Free Download
Viral>Wondershare Filmora 14.5.18.12900 Crack Free DownloadViral>Wondershare Filmora 14.5.18.12900 Crack Free Download
Viral>Wondershare Filmora 14.5.18.12900 Crack Free Download
Puppy jhon
 
Domino IQ – What to Expect, First Steps and Use Cases
Domino IQ – What to Expect, First Steps and Use CasesDomino IQ – What to Expect, First Steps and Use Cases
Domino IQ – What to Expect, First Steps and Use Cases
panagenda
 
“Solving Tomorrow’s AI Problems Today with Cadence’s Newest Processor,” a Pre...
“Solving Tomorrow’s AI Problems Today with Cadence’s Newest Processor,” a Pre...“Solving Tomorrow’s AI Problems Today with Cadence’s Newest Processor,” a Pre...
“Solving Tomorrow’s AI Problems Today with Cadence’s Newest Processor,” a Pre...
Edge AI and Vision Alliance
 
Oracle Cloud Infrastructure Generative AI Professional
Oracle Cloud Infrastructure Generative AI ProfessionalOracle Cloud Infrastructure Generative AI Professional
Oracle Cloud Infrastructure Generative AI Professional
VICTOR MAESTRE RAMIREZ
 
Mastering AI Workflows with FME - Peak of Data & AI 2025
Mastering AI Workflows with FME - Peak of Data & AI 2025Mastering AI Workflows with FME - Peak of Data & AI 2025
Mastering AI Workflows with FME - Peak of Data & AI 2025
Safe Software
 
Providing an OGC API Processes REST Interface for FME Flow
Providing an OGC API Processes REST Interface for FME FlowProviding an OGC API Processes REST Interface for FME Flow
Providing an OGC API Processes REST Interface for FME Flow
Safe Software
 
TimeSeries Machine Learning - PyData London 2025
TimeSeries Machine Learning - PyData London 2025TimeSeries Machine Learning - PyData London 2025
TimeSeries Machine Learning - PyData London 2025
Suyash Joshi
 
Down the Rabbit Hole – Solving 5 Training Roadblocks
Down the Rabbit Hole – Solving 5 Training RoadblocksDown the Rabbit Hole – Solving 5 Training Roadblocks
Down the Rabbit Hole – Solving 5 Training Roadblocks
Rustici Software
 
Your startup on AWS - How to architect and maintain a Lean and Mean account J...
Your startup on AWS - How to architect and maintain a Lean and Mean account J...Your startup on AWS - How to architect and maintain a Lean and Mean account J...
Your startup on AWS - How to architect and maintain a Lean and Mean account J...
angelo60207
 
Floods in Valencia: Two FME-Powered Stories of Data Resilience
Floods in Valencia: Two FME-Powered Stories of Data ResilienceFloods in Valencia: Two FME-Powered Stories of Data Resilience
Floods in Valencia: Two FME-Powered Stories of Data Resilience
Safe Software
 
Trends Artificial Intelligence - Mary Meeker
Trends Artificial Intelligence - Mary MeekerTrends Artificial Intelligence - Mary Meeker
Trends Artificial Intelligence - Mary Meeker
Clive Dickens
 
How Advanced Environmental Detection Is Revolutionizing Oil & Gas Safety.pdf
How Advanced Environmental Detection Is Revolutionizing Oil & Gas Safety.pdfHow Advanced Environmental Detection Is Revolutionizing Oil & Gas Safety.pdf
How Advanced Environmental Detection Is Revolutionizing Oil & Gas Safety.pdf
Rejig Digital
 
Enabling BIM / GIS integrations with Other Systems with FME
Enabling BIM / GIS integrations with Other Systems with FMEEnabling BIM / GIS integrations with Other Systems with FME
Enabling BIM / GIS integrations with Other Systems with FME
Safe Software
 
Scaling GenAI Inference From Prototype to Production: Real-World Lessons in S...
Scaling GenAI Inference From Prototype to Production: Real-World Lessons in S...Scaling GenAI Inference From Prototype to Production: Real-World Lessons in S...
Scaling GenAI Inference From Prototype to Production: Real-World Lessons in S...
Anish Kumar
 
Crypto Super 500 - 14th Report - June2025.pdf
Crypto Super 500 - 14th Report - June2025.pdfCrypto Super 500 - 14th Report - June2025.pdf
Crypto Super 500 - 14th Report - June2025.pdf
Stephen Perrenod
 
Artificial Intelligence in the Nonprofit Boardroom.pdf
Artificial Intelligence in the Nonprofit Boardroom.pdfArtificial Intelligence in the Nonprofit Boardroom.pdf
Artificial Intelligence in the Nonprofit Boardroom.pdf
OnBoard
 
Developing Schemas with FME and Excel - Peak of Data & AI 2025
Developing Schemas with FME and Excel - Peak of Data & AI 2025Developing Schemas with FME and Excel - Peak of Data & AI 2025
Developing Schemas with FME and Excel - Peak of Data & AI 2025
Safe Software
 
Oracle Cloud Infrastructure AI Foundations
Oracle Cloud Infrastructure AI FoundationsOracle Cloud Infrastructure AI Foundations
Oracle Cloud Infrastructure AI Foundations
VICTOR MAESTRE RAMIREZ
 
Your startup on AWS - How to architect and maintain a Lean and Mean account
Your startup on AWS - How to architect and maintain a Lean and Mean accountYour startup on AWS - How to architect and maintain a Lean and Mean account
Your startup on AWS - How to architect and maintain a Lean and Mean account
angelo60207
 
Cisco ISE Performance, Scalability and Best Practices.pdf
Cisco ISE Performance, Scalability and Best Practices.pdfCisco ISE Performance, Scalability and Best Practices.pdf
Cisco ISE Performance, Scalability and Best Practices.pdf
superdpz
 
Viral>Wondershare Filmora 14.5.18.12900 Crack Free Download
Viral>Wondershare Filmora 14.5.18.12900 Crack Free DownloadViral>Wondershare Filmora 14.5.18.12900 Crack Free Download
Viral>Wondershare Filmora 14.5.18.12900 Crack Free Download
Puppy jhon
 
Domino IQ – What to Expect, First Steps and Use Cases
Domino IQ – What to Expect, First Steps and Use CasesDomino IQ – What to Expect, First Steps and Use Cases
Domino IQ – What to Expect, First Steps and Use Cases
panagenda
 
“Solving Tomorrow’s AI Problems Today with Cadence’s Newest Processor,” a Pre...
“Solving Tomorrow’s AI Problems Today with Cadence’s Newest Processor,” a Pre...“Solving Tomorrow’s AI Problems Today with Cadence’s Newest Processor,” a Pre...
“Solving Tomorrow’s AI Problems Today with Cadence’s Newest Processor,” a Pre...
Edge AI and Vision Alliance
 
Oracle Cloud Infrastructure Generative AI Professional
Oracle Cloud Infrastructure Generative AI ProfessionalOracle Cloud Infrastructure Generative AI Professional
Oracle Cloud Infrastructure Generative AI Professional
VICTOR MAESTRE RAMIREZ
 
Mastering AI Workflows with FME - Peak of Data & AI 2025
Mastering AI Workflows with FME - Peak of Data & AI 2025Mastering AI Workflows with FME - Peak of Data & AI 2025
Mastering AI Workflows with FME - Peak of Data & AI 2025
Safe Software
 
Providing an OGC API Processes REST Interface for FME Flow
Providing an OGC API Processes REST Interface for FME FlowProviding an OGC API Processes REST Interface for FME Flow
Providing an OGC API Processes REST Interface for FME Flow
Safe Software
 
TimeSeries Machine Learning - PyData London 2025
TimeSeries Machine Learning - PyData London 2025TimeSeries Machine Learning - PyData London 2025
TimeSeries Machine Learning - PyData London 2025
Suyash Joshi
 
Down the Rabbit Hole – Solving 5 Training Roadblocks
Down the Rabbit Hole – Solving 5 Training RoadblocksDown the Rabbit Hole – Solving 5 Training Roadblocks
Down the Rabbit Hole – Solving 5 Training Roadblocks
Rustici Software
 
Your startup on AWS - How to architect and maintain a Lean and Mean account J...
Your startup on AWS - How to architect and maintain a Lean and Mean account J...Your startup on AWS - How to architect and maintain a Lean and Mean account J...
Your startup on AWS - How to architect and maintain a Lean and Mean account J...
angelo60207
 
Floods in Valencia: Two FME-Powered Stories of Data Resilience
Floods in Valencia: Two FME-Powered Stories of Data ResilienceFloods in Valencia: Two FME-Powered Stories of Data Resilience
Floods in Valencia: Two FME-Powered Stories of Data Resilience
Safe Software
 
Trends Artificial Intelligence - Mary Meeker
Trends Artificial Intelligence - Mary MeekerTrends Artificial Intelligence - Mary Meeker
Trends Artificial Intelligence - Mary Meeker
Clive Dickens
 
How Advanced Environmental Detection Is Revolutionizing Oil & Gas Safety.pdf
How Advanced Environmental Detection Is Revolutionizing Oil & Gas Safety.pdfHow Advanced Environmental Detection Is Revolutionizing Oil & Gas Safety.pdf
How Advanced Environmental Detection Is Revolutionizing Oil & Gas Safety.pdf
Rejig Digital
 
Enabling BIM / GIS integrations with Other Systems with FME
Enabling BIM / GIS integrations with Other Systems with FMEEnabling BIM / GIS integrations with Other Systems with FME
Enabling BIM / GIS integrations with Other Systems with FME
Safe Software
 

Programming The Arm Microprocessor For Embedded Systems

  • 1. Programming the ARM Microprocessor for Embedded Systems Ajay Dudani [email protected] Version 0.1
  • 2. Copyrights • This document is available under the terms of Creative Commons Attribution- NonCommercial-NoDerivs 2.5 License • In simpler terms, you may – Reproduce and redistribute this document as- is for non-commercial use Copyright (c) 2006 by Ajay Dudani 2 May not be reproduced or redistributed for commercial use.
  • 3. Goals • Develop a good understanding of execution of ARM processor required to develop and debug embedded software with or without an operating system • Students should have prior knowledge about programming, operating system concepts and understanding of embedded systems Copyright (c) 2006 by Ajay Dudani 3 May not be reproduced or redistributed for commercial use.
  • 4. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • Embedded operating system • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 4 May not be reproduced or redistributed for commercial use.
  • 5. Why ARM? • Low power consumption • Fast execution per Watt • Good backward compatibility • Inexpensive • Variety of core offerings • … and other advantages we will see in upcoming slides Copyright (c) 2006 by Ajay Dudani 5 May not be reproduced or redistributed for commercial use.
  • 6. Why ARM? • And … Marketing ☺ Copyright (c) 2006 by Ajay Dudani 6 May not be reproduced or redistributed for commercial use.
  • 7. Detailed Outline • ARM Technology – History – The competition Copyright (c) 2006 by Ajay Dudani 7 May not be reproduced or redistributed for commercial use.
  • 8. Detailed Outline • ARM Tools and products – Microprocessors – Compilers and debuggers – Single board computers – Documents and reference text Copyright (c) 2006 by Ajay Dudani 8 May not be reproduced or redistributed for commercial use.
  • 9. Detailed Outline • ARM Processor – Programming model – General purpose registers – Program control registers – Pipelining – Memory protection Copyright (c) 2006 by Ajay Dudani 9 May not be reproduced or redistributed for commercial use.
  • 10. Detailed Outline • Toolchain – ARM Toolchain – GNU Toolchain – Others Copyright (c) 2006 by Ajay Dudani 10 May not be reproduced or redistributed for commercial use.
  • 11. Detailed Outline • ARM Instruction Set – Instruction set encoding – Conditional field – Data processing instructions – Branch instructions – Load-store instructions – Software interrupt instruction – Program status register instructions – Semaphore instructions – Coprocessor instructions – Extending instructions Copyright (c) 2006 by Ajay Dudani 11 May not be reproduced or redistributed for commercial use.
  • 12. Detailed Outline • ARM Thumb Mode – Why Thumb? – Instruction set encoding – Branch instructions – Data processing instructions – Load and store instructions – Switching between ARM and Thumb mode Copyright (c) 2006 by Ajay Dudani 12 May not be reproduced or redistributed for commercial use.
  • 13. Detailed Outline • ARM Exceptions and Interrupts – Exception vector table – Exception modes – Exception and interrupt handling Copyright (c) 2006 by Ajay Dudani 13 May not be reproduced or redistributed for commercial use.
  • 14. Detailed Outline • ARM Firmware – Bootloader – Standalone code – Example of initialization Copyright (c) 2006 by Ajay Dudani 14 May not be reproduced or redistributed for commercial use.
  • 15. Detailed Outline • ARM Caches – Memory hierarchy – Cache policy – Flushing policy – Software performance Copyright (c) 2006 by Ajay Dudani 15 May not be reproduced or redistributed for commercial use.
  • 16. Detailed Outline • ARM MMU and MPU – Protected memory – Example of memory protection – Virtual memory concepts – Example of virtual memory system Copyright (c) 2006 by Ajay Dudani 16 May not be reproduced or redistributed for commercial use.
  • 17. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 17 May not be reproduced or redistributed for commercial use.
  • 18. ARM Technology Overview • ARM: “The Architecture For The Digital World” • ARM is a physical hardware design and intellectual property company • ARM licenses its cores out and other companies make processors based on its cores • ARM also provides toolchain and debugging tools for its cores Copyright (c) 2006 by Ajay Dudani 18 May not be reproduced or redistributed for commercial use.
  • 19. ARM Technology Overview (2) Companies licensing ARM IP: 3Com Motorola Agilent Technologies Panasonic Altera Qualcomm Epson Sharp Freescale Sanyo Fijitsu Sun Microsystems NEC Sony Nokia Symbian Intel Texas Instruments IBM Toshiba Microsoft Wipro Source: ARM Website … and many more Copyright (c) 2006 by Ajay Dudani 19 May not be reproduced or redistributed for commercial use.
  • 20. ARM History • Acorn Computer Group developed world’s first RISC processor in 1985 • Roger Wilson and Steve Furber were the principle developers • ARM (Advanced RISC Machines) was a spin out from Acorn in 1990 with goal of defining a new microprocessor standard Copyright (c) 2006 by Ajay Dudani 20 May not be reproduced or redistributed for commercial use.
  • 21. ARM History (2) • Acorn Computer Group Source: Wikipedia Copyright (c) 2006 by Ajay Dudani 21 May not be reproduced or redistributed for commercial use.
  • 22. ARM History (3) • ARM delivered ARM6 in 1991 – Introduced 32 bit addressing support – New instruction for program status registers – Variant used in Apple Newton PDA • By 1996 ARM7 was being widely used – Microsoft started port of WinCE to ARM – Added multimedia extensions • Exponential growth from then on… Copyright (c) 2006 by Ajay Dudani 22 May not be reproduced or redistributed for commercial use.
  • 23. ARM and StrongARM • Intel gained certain IP from ARM as part of lawsuit settlement and modified ARM architecture branding it as StrongARM • StrongARM name was changed to XScale – Processor SA1000 , SA1100 • XScale is close to ARMv5 instruction set • XScale division of Intel was sold to Marvel Inc. in 2006 Copyright (c) 2006 by Ajay Dudani 23 May not be reproduced or redistributed for commercial use.
  • 24. ARM Today • ARM7xxx – 3 stage pipeline – Integer processor – MMU support for WinCE, Linux and Symbian – Used in entry level mobiles, mp3 players, pagers • ARM9xxx – 5 stage pipeline – Separate data and instruction cache – Higher end mobile and communication devices – Telematic and infotainment systems – ARM and Thumb instruction set Copyright (c) 2006 by Ajay Dudani 24 May not be reproduced or redistributed for commercial use.
  • 25. ARM Today (2) • ARM11xxx – 7 stage pipeline – Trustzone security related extensions – Reduced power consumption – Speed improvements – More DSP and SIMD extensions – Used in PDA, smartphones, industrial controllers, mobile gaming Copyright (c) 2006 by Ajay Dudani 25 May not be reproduced or redistributed for commercial use.
  • 26. ARM Processor Family • ARM has devised a naming convention for its processors • Revisions: ARMv1, v2 … v6, v7 • Core implementation: – ARM1, ARM2, ARM7, StrongARM, ARM926EJ, ARM11, Cortex • ARM11 is based on ARMv6 • Cortex is based on ARMv7 Copyright (c) 2006 by Ajay Dudani 26 May not be reproduced or redistributed for commercial use.
  • 27. ARM Processor Family (2) • Differences between cores – Processor modes – Pipeline – Architecture – Memory protection unit – Memory management unit – Cache – Hardware accelerated Java – … and others Copyright (c) 2006 by Ajay Dudani 27 May not be reproduced or redistributed for commercial use.
  • 28. ARM Processor Family (3) • Examples: – ARM7TDMI • No MMU, No MPU, No cache, No Java, Thumb mode – ARM922T • MMU, No MPU, 8K+8K data and instruction cache, No Java, Thumb mode – ARM1136J-S • MMU, No MPU, configurable caches, with accelerated Java and Thumb mode Copyright (c) 2006 by Ajay Dudani 28 May not be reproduced or redistributed for commercial use.
  • 29. ARM Processor Family (4) • Naming convention • ARM [x][y][z][T][D][M][I][E][J][F][S] – x – Family – y – memory management/protection – z – cache – T – Thumb mode – D – JTAG debugging – M – fast multiplier – I – Embedded ICE macrocell – E – Enhanced instruction (implies TDMI) – J – Jazelle, hardware accelerated Java – F – Floating point unit – S – Synthesizable version Copyright (c) 2006 by Ajay Dudani 29 May not be reproduced or redistributed for commercial use.
  • 30. Outline • ARM Technology • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 30 May not be reproduced or redistributed for commercial use.
  • 31. ARM Tools & Products Disclaimer: All owners own their respective trademarks Copyright (c) 2006 by Ajay Dudani 31 May not be reproduced or redistributed for commercial use.
  • 32. ARM Chips • ARM Ltd – Provides ARM cores – Intellectual property • Analog Devices – ADuC7019, ADuC7020, ADuC7021, ADuC7022, ADuC7024, ADuC7025, ADuC7026, ADuC7027, ADuC7128, ADuC7129 • Atmel – AT91C140, AT91F40416, AT91F40816, AT91FR40162 • Freescale – MAC7101, MAC7104, MAC7105, MAC7106 • Samsung – S3C44B0X, S3C4510B • Sharp – LH75400, LH75401, LH75410, LH75411 • Texas Instruments – TMS470R1A128, TMS470R1A256, TMS470R1A288 • And others… Copyright (c) 2006 by Ajay Dudani 32 May not be reproduced or redistributed for commercial use.
  • 33. ARM Development Tools • Compilers: – GNU Compiler – ADS from ARM (older version) – RVCT Real View compiler tools from ARM – 3rd Party • Debugging – GNU gdb – Lauterbach JTAG/Trace32 tools – ETM hardware debugging & profilingmodules – Windriver tools Copyright (c) 2006 by Ajay Dudani 33 May not be reproduced or redistributed for commercial use.
  • 34. ARM Single Board Computers • TS-7200 ARM Single board computer – 200 MHz ARM9 processor with MMU – 32 MB RAM – 8 MB Flash – Compact flash – 10/100 Ethernet Copyright (c) 2006 by Ajay Dudani 34 May not be reproduced or redistributed for commercial use.
  • 35. ARM Single Board Computers (2) • Cirrus Logic ARM CS98712 – 16 MB RAM – 1MB Flash – 1 Serial port – LED lights Copyright (c) 2006 by Ajay Dudani 35 May not be reproduced or redistributed for commercial use.
  • 36. ARM Single Board Computers (3) • LN24x0/LP64 – 200 Mhz ARM9 processor – LCD controller – Touchscreen – USB, IrDA ports – HDD and CD-ROM support – Speaker – JTAG ports Copyright (c) 2006 by Ajay Dudani 36 May not be reproduced or redistributed for commercial use.
  • 37. Recommended Text • “ARM System Developer’s Guide” – Sloss, et. al. – ISBN 1-55860-874-5 • “ARM Architecture Reference Manual” – David Seal – ISBN 0-201-737191 – Softcopy available at www.arm.com • “ARM system-on-chip architecture” – Steve Fuber – ISBN 0-201-67519-6 Copyright (c) 2006 by Ajay Dudani 37 May not be reproduced or redistributed for commercial use.
  • 38. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 38 May not be reproduced or redistributed for commercial use.
  • 39. ARM Design Philosophy • ARM core uses RISC architecture – Reduced instruction set – Load store architecture – Large number of general purpose registers – Parallel executions with pipelines • But some differences from RISC – Enhanced instructions for • Thumb mode • DSP instructions • Conditional execution instruction • 32 bit barrel shifter Copyright (c) 2006 by Ajay Dudani 39 May not be reproduced or redistributed for commercial use.
  • 40. ARM Programming Model • A=B+C • To evaluate the above expression – Load A to a general purpose register R1 – Load B to a general purpose register R2 – Load C to a general purpose register R3 – ADD R1, R2, R3 – Store R1 to A Copyright (c) 2006 by Ajay Dudani 40 May not be reproduced or redistributed for commercial use.
  • 41. Registers • ARM has a load store architecture • General purpose registers can hold data or address • Total of 37 registers each 32 bit wide • There are 18 active registers – 16 data registers – 2 status registers Copyright (c) 2006 by Ajay Dudani 41 May not be reproduced or redistributed for commercial use.
  • 42. Registers (2) • Registers R0 thru R12 are general R0 R1 purpose registers R2 R3 • R13 is used as stack pointer (sp) R4 R5 R6 • R14 is used as link register (lr) R7 R8 • R15 is used a program counter (pc) R9 R10 • CPSR – Current program status R11 R12 register R13 (sp) R14 (lr) R15 (pc) • SPSR – Stored program status register CPSR SPSR Copyright (c) 2006 by Ajay Dudani 42 May not be reproduced or redistributed for commercial use.
  • 43. Registers (3) • Program status register – CPSR is used to control and store CPU states – CPSR is divided in four 8 bit fields • Flags • Status • Extension • Control Copyright (c) 2006 by Ajay Dudani 43 May not be reproduced or redistributed for commercial use.
  • 44. Registers (4) • Program status register flags – N:1 – Negative result – Z:1 – Result is zero – C:1 – Carry in addition operation – C:0 – Borrow in subtraction operation – V:1 – Overflow or underflow Copyright (c) 2006 by Ajay Dudani 44 May not be reproduced or redistributed for commercial use.
  • 45. Registers (5) • Program status register controls – I:1 – IRQ interrupts disabled – F:1 – FIQ interrupts disabled – T:0 – ARM Mode – T:1 – Thumb Mode Copyright (c) 2006 by Ajay Dudani 45 May not be reproduced or redistributed for commercial use.
  • 46. Registers (6) • Program status register control modes – 0b10000 – User mode – 0b10001 – FIQ mode – 0b10010 – IRQ mode – 0b10011 – Supervisor mode – 0b10111 – Abort mode – 0b11011 – Undefined mode – 0b11111 – System mode Copyright (c) 2006 by Ajay Dudani 46 May not be reproduced or redistributed for commercial use.
  • 47. Processor Modes • Processor modes are execution modes which determines active registers and privileges • List of modes – Abort mode – Fast interrupt mode – Interrupt mode – Supervisor mode – System mode – Undefined mode – User mode • All except User mode are privileged modes – User mode is used for normal execution of programs and applications – Privileged modes allow full read/write to CPSR Copyright (c) 2006 by Ajay Dudani 47 May not be reproduced or redistributed for commercial use.
  • 48. Banked Registers • Of total 37 registers only 18 are active in a given register mode User/System Supervisor Abort FIQ IRQ Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R8_fiq R9 R9_fiq R10 R10_fiq R11 R11_fiq R12 R12_fiq R13 (sp) R13_svc (sp) R13_abt (sp) R13_fiq (sp) R13_irq (sp) R13_und (sp) R14 (lr) R14_svc (lr) R14_abt (lr) R14_fiq (lr) R14_irq (lr) R14_und (lr) R15 (pc) CPSR SPSR SPSR_svc SPSR_abt SPSR_fiq SPSR_irq SPSR_und Copyright (c) 2006 by Ajay Dudani 48 May not be reproduced or redistributed for commercial use.
  • 49. Pipeline • Pipelining is breaking down execution into multiple steps, and executing each step in parallel • Basic 3 stage pipeline – Fetch – Load from memory – Decode – Identify instruction to execute – Execute – Process instruction and write back result Copyright (c) 2006 by Ajay Dudani 49 May not be reproduced or redistributed for commercial use.
  • 50. Pipeline (2) • Fetch Decode Execute Cycle 1 ADD Cycle 2 SUB ADD Time Cycle 3 CMP SUB ADD Copyright (c) 2006 by Ajay Dudani 50 May not be reproduced or redistributed for commercial use.
  • 51. Pipeline (3) • ARM7 has a 3 stage pipeline – Fetch, Decode, Execute • ARM9 has a 5 stage pipeline – Fetch, Decode, Execute, Memory, Write • ARM10 has a 6 stage pipeline – Fetch, Issue, Decode, Execute, Memory, Write Copyright (c) 2006 by Ajay Dudani 51 May not be reproduced or redistributed for commercial use.
  • 52. Pipeline (4) • In theory, each instruction is one instruction cycle • In practice, there is interdependency between instructions – Solution: instruction scheduling Copyright (c) 2006 by Ajay Dudani 52 May not be reproduced or redistributed for commercial use.
  • 53. Memory Protection • Two modes for ARM memory protection – Unprotected mode • No hardware protection, software does protection of data between tasks – Protected mode • Hardware protects areas of memory and raises exceptions when policy is voilated • ARM divides memory to regions and programmer can set attributes on regions • ARM provides mechanisms to define and set attributes of regions programmatically Copyright (c) 2006 by Ajay Dudani 53 May not be reproduced or redistributed for commercial use.
  • 54. Memory Management • ARM supports memory management and virtual memory • Programmatically access translation look- aside buffers • ARM memory management unit also supports Fast Context Switching Extensions that optimizes use of caches in multitasking environments • Details in later section Copyright (c) 2006 by Ajay Dudani 54 May not be reproduced or redistributed for commercial use.
  • 55. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 55 May not be reproduced or redistributed for commercial use.
  • 56. Toolchain • GNU Tools – gcc – Front end to GNU compiler – binutils – Binary tools • ld – GNU Linker • as – GNU assembler • And others – gdb – GNU Debugger – uClib – Small footprint C Library Copyright (c) 2006 by Ajay Dudani 56 May not be reproduced or redistributed for commercial use.
  • 57. Toolchain (2) • GCC – Invoked language specific modules – Invoked assembler and linker – arm-elf-gcc command • arm-elf-gcc test.c –o test • arm-elf-gcc test.S –o test Copyright (c) 2006 by Ajay Dudani 57 May not be reproduced or redistributed for commercial use.
  • 58. Toolchain (3) • GCC ARM specific options – mapcs-frame: Generate ARM procedure call compliant stack frame – mbig-endian: Generate big endian code – mno-alignment-traps: Generate code that assumes that MMU does not trap on handling misaligned data – mcpu=name : Specify CPU name; gcc can determine what instructions it can use to generate output accordingly – mthumb: Generate code for ARM Thumb mode – msoft-float: Generate code assuming floating point hardware is not present. Do floating point operation optimization in software – Refer to GCC manual page for more on compiler options Copyright (c) 2006 by Ajay Dudani 58 May not be reproduced or redistributed for commercial use.
  • 59. Inline assembly • Developer can insert ARM assembly code in C code – for example printf (“Hello ARM GCC”); __asm__ (“ldr r15, r0”); printf (“Program may have crashed”); Above code will corrupt program counter, so use inline assembly carefully Also, it may lead to non portable code Copyright (c) 2006 by Ajay Dudani 59 May not be reproduced or redistributed for commercial use.
  • 60. Inline assembly (2) • Developer can force use of certain registers using extended assembly asm ( assembler template : output operands /* optional */ : input operands /* optional */ : list of clobbered registers /* optional */ ); • Example: int a = 10, b; __asm__ (“mov %0, %1” : “=r”(b) : “=r”(a)); Copyright (c) 2006 by Ajay Dudani 60 May not be reproduced or redistributed for commercial use.
  • 61. Inline assembly (3) • Developer can request variable to be assigned to specific register register int regVar __asm__(“%r4”); • Can be used with local and global variables • Need –ffixed-<reg> compiler option for global variables • Refer to GCC Inline Assembly reference for more examples Copyright (c) 2006 by Ajay Dudani 61 May not be reproduced or redistributed for commercial use.
  • 62. GNU Toolchain • Reference: – www.gnuarm.org – www.sourceware.org/binutils/ – www.gnu.org/software/gdb/ – www.sourceware.org/insight/ – www.uclibc.org – GCC improvements for ARM • www.inf.u-szeged.hu/gcc-arm/ Copyright (c) 2006 by Ajay Dudani 62 May not be reproduced or redistributed for commercial use.
  • 63. ARM Toolchain • ADS: ARM Developer Suite is older version of compiler, assembler and linker tools from ARM • RCVT: Latest ARM compiler, assembler and linker Copyright (c) 2006 by Ajay Dudani 63 May not be reproduced or redistributed for commercial use.
  • 64. ARM Toolchain • ARM also provides support for RealView tools it acquired as part of Keil acquisition • JTAG Support: ARM provides debugging tools to be used with JTAG supported hardware • ETM Support: Embedded Trace Module is hardware debug unit that extends on-target debugging capabilities by providing extra memory and registers for debugging purpose • Refer to www.arm.com and www.keil.com/arm/ for details on ARM tools Copyright (c) 2006 by Ajay Dudani 64 May not be reproduced or redistributed for commercial use.
  • 65. Other Toolchains • GNU X-Tools – www.microcross.com • IAR ARM Kit – www.iar.com • Intel Development Suite for XScale – www.intel.com Copyright (c) 2006 by Ajay Dudani 65 May not be reproduced or redistributed for commercial use.
  • 66. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 66 May not be reproduced or redistributed for commercial use.
  • 67. ARM Instruction Set • Overview Copyright (c) 2006 by Ajay Dudani 67 May not be reproduced or redistributed for commercial use.
  • 68. ARM Instruction Set (2) • Condition fields Copyright (c) 2006 by Ajay Dudani 68 May not be reproduced or redistributed for commercial use.
  • 69. ARM Instruction Set (3) • Add • Subract • Multiply Copyright (c) 2006 by Ajay Dudani 69 May not be reproduced or redistributed for commercial use.
  • 70. ARM Instruction Set (4) • Bit shifting Copyright (c) 2006 by Ajay Dudani 70 May not be reproduced or redistributed for commercial use.
  • 71. ARM Instruction Set (5) • Status register operation Copyright (c) 2006 by Ajay Dudani 71 May not be reproduced or redistributed for commercial use.
  • 72. ARM Instruction Set (6) • Semaphore instruction Copyright (c) 2006 by Ajay Dudani 72 May not be reproduced or redistributed for commercial use.
  • 73. ARM Instruction Set (7) • Placeholder page Copyright (c) 2006 by Ajay Dudani 73 May not be reproduced or redistributed for commercial use.
  • 74. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 74 May not be reproduced or redistributed for commercial use.
  • 75. Thumb Instruction Set • Overview of 16 bit mode Copyright (c) 2006 by Ajay Dudani 75 May not be reproduced or redistributed for commercial use.
  • 76. Thumb Instruction Set (2) • Thumb Instruction set details Copyright (c) 2006 by Ajay Dudani 76 May not be reproduced or redistributed for commercial use.
  • 77. Thumb Instruction Set (3) • Switching between ARM and Thumb mode Copyright (c) 2006 by Ajay Dudani 77 May not be reproduced or redistributed for commercial use.
  • 78. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 78 May not be reproduced or redistributed for commercial use.
  • 79. Exceptions • Exception handling is a programming language or hardware mechanism to catch runtime errors • C++ and Java support exception handling in software 1. void func() 2. { 3. try 4. { 5. int a = 100/0; 6. } 7. catch(...) 8. { 9. cout << "Caught exception" << endl; 10. return; 11. } 12. cout << "No exception detected!" << endl; 13. return; 14. } Copyright (c) 2006 by Ajay Dudani 79 May not be reproduced or redistributed for commercial use.
  • 80. Exceptions (2) • ARM support 7 exception modes • Developers can write custom exception handlers to deal with exception conditions • For example: – Consider a system that crashes if PC is corrupted. This will cause an exception. In corresponding exception handler, programmer can save state of all registers to file system for debugging and reset Copyright (c) 2006 by Ajay Dudani 80 May not be reproduced or redistributed for commercial use.
  • 81. Exceptions (3) • ARM Exceptions in order of priority – Reset – Data abort – FIQ – IRQ – Prefetch abort – Undefined instruction – Software interrupt Copyright (c) 2006 by Ajay Dudani 81 May not be reproduced or redistributed for commercial use.
  • 82. Reset exception • Highest priority exception • The reset handler runs in supervisor mode • Handler is generally located at 0x00000000 • In Reset handler, FIQ and IRQ are disabled • Other exceptions are not likely to occur when in reset handler Copyright (c) 2006 by Ajay Dudani 82 May not be reproduced or redistributed for commercial use.
  • 83. Reset exception (2) • Actions performed when reset is de-asserted – R14_svc is set to unpredictable value – SPSR_svc is set to unpredictable value – CPSR[4:0] is 0b10011 – supervisor mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is 1 – disable fast interrupts – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000000 Copyright (c) 2006 by Ajay Dudani 83 May not be reproduced or redistributed for commercial use.
  • 84. Data abort exception • Data abort exception mean software is trying to read/write an illegal memory location • Data abort has higher priority than FIQ • While handling this more, IRQ is disabled • The abort handler should not cause further aborts – Consider case of prefetch abort in abort handler – This will cause abort handler to be reentered • Abort handler is generally located at 0x00000010 Copyright (c) 2006 by Ajay Dudani 84 May not be reproduced or redistributed for commercial use.
  • 85. Data abort exception (2) • Actions performed on data abort – R14_abt = address of abort instruction + 8 – SPSR_svc = CPSR – CPSR[4:0] is 0b10111 – abort mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000010 Copyright (c) 2006 by Ajay Dudani 85 May not be reproduced or redistributed for commercial use.
  • 86. Fast interrupt • FIQ exception mode exists if developer wants to handle certain interrupts faster • Additional banked registers in FIQ mode make execution fast • Higher priority in IRQ • Disabled IRQ and FIQ • Default ARM cores do not handle nested interrupts • FIQ handler is generally located at 0x0000001C Copyright (c) 2006 by Ajay Dudani 86 May not be reproduced or redistributed for commercial use.
  • 87. Fast interrupt (2) • Actions performed on fast interrupt – R14_fiq = address of next instruction to execute + 4 – SPSR_fiq = CPSR – CPSR[4:0] is 0b10111 – FIQ mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is 1 – disable fast interrupts – CPSR[7] is 1 – disable normal interrupts – PC = 0x0000001C Copyright (c) 2006 by Ajay Dudani 87 May not be reproduced or redistributed for commercial use.
  • 88. Normal interrupt • Normal interrupt is lower priority than fast interrupts • Disabled IRQ when handling normal interrupts • Default ARM cores do not handle nested interrupts • IRQ handler is generally located at 0x00000018 Copyright (c) 2006 by Ajay Dudani 88 May not be reproduced or redistributed for commercial use.
  • 89. Normal interrupt (2) • Actions performed on normal interrupt – R14_irq = address of next instruction to execute + 4 – SPSR_irq = CPSR – CPSR[4:0] is 0b10010 – IRQ mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000018 Copyright (c) 2006 by Ajay Dudani 89 May not be reproduced or redistributed for commercial use.
  • 90. Prefetch abort • If processor reads instruction from undefined memory, it causes a prefetch abort exception • Prefetch abort occurs when instruction reaches execution stage of pipeline • Disabled normal interrupts when handling prefetch abort • Prefetch abort handler is generally located at 0x0000000C Copyright (c) 2006 by Ajay Dudani 90 May not be reproduced or redistributed for commercial use.
  • 91. Prefetch abort (2) • Actions performed on prefetch abort – R14_abt = address of next instruction to execute + 4 – SPSR_irq = CPSR – CPSR[4:0] is 0b10111 – abort mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x0000000C Copyright (c) 2006 by Ajay Dudani 91 May not be reproduced or redistributed for commercial use.
  • 92. Undefined instruction • When executing coprocessor instructions, ARM waits for coprocessor to acknowledge that it can execute the instruction • If no coprocessor can handle given instruction, undefined instruction exception is raised • In simulators, this can be used to simulate coprocessor in software • Undefined instruction handler can parse instructions and process them in software simulator • Undefined instruction handler is generally located at 0x00000004 Copyright (c) 2006 by Ajay Dudani 92 May not be reproduced or redistributed for commercial use.
  • 93. Undefined instruction (2) • Actions performed on undefined instruction – R14_und = address of next instruction to execute – SPSR_und = CPSR – CPSR[4:0] is 0b11011 – undefined mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000004 Copyright (c) 2006 by Ajay Dudani 93 May not be reproduced or redistributed for commercial use.
  • 94. Software interrupt • Software interrupt exception is used to enter supervisor mode to execute a privileged OS function • Typically applications run in user mode and kernel in supervisor mode • Execution of any system call will cause SWI software interrupt to change mode to supervisor mode • Software interrupt handler is generally located at 0x00000008 Copyright (c) 2006 by Ajay Dudani 94 May not be reproduced or redistributed for commercial use.
  • 95. Software interrupt (2) • Actions performed on software interrupt – R14_svc = address of next instruction to execute after SWI – SPSR_irq = CPSR – CPSR[4:0] is 0b10011 – supervisor mode – CPSR[5] is 0 – execute in ARM mode – CPSR[6] is unchanged – CPSR[7] is 1 – disable normal interrupts – PC = 0x00000008 Copyright (c) 2006 by Ajay Dudani 95 May not be reproduced or redistributed for commercial use.
  • 96. Exception table • Memory layout 0x00000000 – reset exception handler 0x00000004 – undefined instruction handler 0x00000008 – software interrupt handler 0x0000000C – prefetch abort handler 0x00000010 – data abort handler 0x00000018 – normal interrupt handler 0x0000001C – fast interrupt handler • High vectors – Some implementation keep this table in 0xFFFF0000 to 0xFFFF001C range which is known as high vector location Copyright (c) 2006 by Ajay Dudani 96 May not be reproduced or redistributed for commercial use.
  • 97. Exception handling 1. Exception is raised 2. Lookup to exception table to find exception handler 3. Exception handler is executed 4. Return from exception handler Exception Vector Table SWI Handler Application 0x00 Reset_Handler MOV r0, r1 0x04 Undef_Handler SWI 0x1D 0x08 SWI_Handler ... ADD r0,r2,r0 0x0c PAbt_Handler ... DAbt_Handler ... 0x10 0x14 ... IRQ_Handler MOV PC, R14_svc 0x18 FIQ_Handler 0x1c Copyright (c) 2006 by Ajay Dudani 97 May not be reproduced or redistributed for commercial use.
  • 98. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 98 May not be reproduced or redistributed for commercial use.
  • 99. ARM Firmware • “Now the earth was formless and empty. Darkness was on the surface of the deep. God's Spirit was hovering over the surface of the waters.” “God said, “Let there be light”, and there was light.” • For the processor, someone needs to read application and copy it into RAM to start execution – What address to copy it to RAM – Setup stack and heap – Transfer control to application Copyright (c) 2006 by Ajay Dudani 99 May not be reproduced or redistributed for commercial use.
  • 100. System initialization • Two stages of initialization: 1. Initialize stack, vectors and I/O system 2. Initialize application and associated libraries – The system set up could be – With an RTOS, in which case it does initialization of system environment (stack, vectors etc.). User application then starts with main() or RTOS specific entry point – Without an RTOS, ROM code handles transferring control to user application. User application need additional code to setup system environment Copyright (c) 2006 by Ajay Dudani 100 May not be reproduced or redistributed for commercial use.
  • 101. Initialization • Execution environment: 1. At reset • Processor is in SVC mode • Interrupts are disabled • Running in ARM mode 2. Entry point on powerup • Use assember directive ENTRY to specify entry point • ROM code usually has entry point 0x00 Copyright (c) 2006 by Ajay Dudani 101 May not be reproduced or redistributed for commercial use.
  • 102. Initialization (2) • Execution environment: 3. Setup exception vector table • If ROM is mapped to address 0x00, it contains hard coded exception vector table • If ROM is mapped elsewhere, exception table is copied to RAM address 0x00 4. Initialize memory system • Initialize memory management and memory protection before running any application code • Setup stack pointers, sp_SYS, sp_IRQ etc. • Initialize I/O devices. Note interrupts are still disabled • Change processor mode to user mode. At this stage we are ready to initialize application Copyright (c) 2006 by Ajay Dudani 102 May not be reproduced or redistributed for commercial use.
  • 103. Initialization (3) • Application environment: 1. Initialize ZI writable region with zeroes 2. Initialize non zero data by copying initialization values 3. Pass on control to main function Copyright (c) 2006 by Ajay Dudani 103 May not be reproduced or redistributed for commercial use.
  • 104. Initialization Example • Consider user code: 1. int main (void) 2. { 3. printf (“Hello ARM World”); 4. return 0; 5. } Copyright (c) 2006 by Ajay Dudani 104 May not be reproduced or redistributed for commercial use.
  • 105. Initialization Example (2) • Consider ROM mapped at address 0x24000 RW Data Application Code 0x24000000 Vector table & Init Code • Above image shows setup before application has been loaded Copyright (c) 2006 by Ajay Dudani 105 May not be reproduced or redistributed for commercial use.
  • 106. Initialization Example (3) • At initialization, ROM code at 0x24000000 is in flash. Flash is mapped at 0x24000000 address • On Reset, Flash will be remapped by hardware to address 0x00 – ROM init code performs certain initialization – Initialized vector tables and data regions to RAM – Copies application code from ROM to RAM – Sets REMAP bit to map RAM to address 0x00 Copyright (c) 2006 by Ajay Dudani 106 May not be reproduced or redistributed for commercial use.
  • 107. Initialization Example (4) Code (RO+RW) Code (RO+RW) Flash 0x24000000 I/O Addresses UART Stack Heap RAM ZI data Initialized RW data Code aliased from Code (RO+RW) 0x24000000 Vector table Copyright (c) 2006 by Ajay Dudani 107 May not be reproduced or redistributed for commercial use.
  • 108. Firmware • Typically the ROM code is bootloader – Developers configure the bootloader as per their requirements to specify memory map, bootup address, policy to copy code to RAM • Application code can – Either be single binary with RTOS in which case RTOS provides basic OS services – For simple applications there may be no RTOS, just application compiled with simplified C library Copyright (c) 2006 by Ajay Dudani 108 May not be reproduced or redistributed for commercial use.
  • 109. Firmware (2) • Some examples of bootloaders – Grub – Lilo – RedBoot • Some examples of RTOS – Linux – eCos – vxWorks • Some examples of embedded libraries – Busybox – ucLib Copyright (c) 2006 by Ajay Dudani 109 May not be reproduced or redistributed for commercial use.
  • 110. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 110 May not be reproduced or redistributed for commercial use.
  • 111. Memory hierarchy Registers Caches RAM Memory Hard disk External & network storage Copyright (c) 2006 by Ajay Dudani 111 May not be reproduced or redistributed for commercial use.
  • 112. Caches • A cache is high speed memory location generally used to reduce latency in memory access for data and instructions • Whenever CPU reads data from (slower) RAM, a copy is stored in (faster) cache • If CPU access the same data again, it can be served from cache. This is a hit • A write buffer speeds up writing to main memory Copyright (c) 2006 by Ajay Dudani 112 May not be reproduced or redistributed for commercial use.
  • 113. Cache properties • Set associativity – Fully associative – Direct mapped • Cache size • Unified or separate – Caches for data and instruction • Write through or write back – Property associated with mechanism to write data back to main memory • Read allocate or write allocate – Property associated dealing with cache miss • Replacement strategy – Property associated with replacing cache data with newer ones Copyright (c) 2006 by Ajay Dudani 113 May not be reproduced or redistributed for commercial use.
  • 114. Cache issues • Address mapping changes – Virtual or physical address can get remapped • Cache coherence and invalidation • Direct Memory Access (DMA) operation can update main memory without going through cache Copyright (c) 2006 by Ajay Dudani 114 May not be reproduced or redistributed for commercial use.
  • 115. ARM and caches • Cache and write buffers are controlled with coprocessor registers • Register 1: – C bit: Cache enable/disable – W bit: Enable/disable write buffer – I bit: Enable/disable instruction cache – RR bit: Cache replacement strategy Copyright (c) 2006 by Ajay Dudani 115 May not be reproduced or redistributed for commercial use.
  • 116. ARM and caches (2) • Register 7: – Controls cache and write buffers – Different opcodes written to this register result in different behavior. Some examples: • Invalidate entire instruction/data cache • Flush prefetch buffer • Writeback outstanding cache data to main memory Copyright (c) 2006 by Ajay Dudani 116 May not be reproduced or redistributed for commercial use.
  • 117. ARM and caches (3) • Register 9: – Controls cache lockdown – Caches can slow down worst case execution time of code and be undeterministic because • It needs to handle cache misses • Write back of data to main memory can take time • Cache mechanism can load more data than request by process – Cache lockdown helps control these parameters to remove undeterministic behavior in critical code Copyright (c) 2006 by Ajay Dudani 117 May not be reproduced or redistributed for commercial use.
  • 118. Caches • Caches can provide huge performance improvements to the system • As a developer, one should do profiling by changing various caching options when developing board support package Copyright (c) 2006 by Ajay Dudani 118 May not be reproduced or redistributed for commercial use.
  • 119. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 119 May not be reproduced or redistributed for commercial use.
  • 120. Memory Management • We saw earlier that during initialization, code from ROM is copied to RAM • But what is code size is larger than RAM available? Options: – Do not allow program to be loaded – Load only part of program and swap parts of program as requested – Or allow program to see large virtual memory Copyright (c) 2006 by Ajay Dudani 120 May not be reproduced or redistributed for commercial use.
  • 121. Virtual Memory • Program is loaded into RAM until full • Application starts running with partial program loaded in memory • When program wants to access virtual memory address that is not in physical memory it generated a page fault • Page fault handler is responsible to get new page of memory into RAM Copyright (c) 2006 by Ajay Dudani 121 May not be reproduced or redistributed for commercial use.
  • 122. ARM MMU • MMU handles translation from virtual to physical memory • Presents 4 GB address space • Supports 3 options for memory granularity: – 1 MB sections – 64 KB pages – 4 KB pages • Page fault is indicate by abort • Abort handler is responsible for fetching pages Copyright (c) 2006 by Ajay Dudani 122 May not be reproduced or redistributed for commercial use.
  • 123. ARM Memory Protection • Memory protection is required to prevent one application from overwriting other application’s code • This facility can be enabled by using MMU • Using MMU, system goes to abort mode when application accesses memory to which it does not have permissions Copyright (c) 2006 by Ajay Dudani 123 May not be reproduced or redistributed for commercial use.
  • 124. ARM Memory Protection (2) • ARM MPU allows memory protection without using MMU facilities • ARM defines up to 8 protection regions which can be configured through MPU registers • MPU offers good memory protection option for cases – Where 8 protection regions are enough – Virtual memory is not required Copyright (c) 2006 by Ajay Dudani 124 May not be reproduced or redistributed for commercial use.
  • 125. MPU Registers • CP15 – M bit: enable/disable memory protection – Cache bits: control if cache buffer is enabled/disabled – Buffer bits: control if write buffer is enabled/disabled – Access control bits: control access rights of 8 regions – Mechanism to define 8 memory regions Copyright (c) 2006 by Ajay Dudani 125 May not be reproduced or redistributed for commercial use.
  • 126. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 126 May not be reproduced or redistributed for commercial use.
  • 127. ARM Future Development • ARMv7 based processors – ARM Cortex-M3 – TI OMAP – Qualcomm Scorpion • In embedded systems its not just speed, its about speed/watt • Approximately 2 billion ARM based devices selling each year… and growing! Copyright (c) 2006 by Ajay Dudani 127 May not be reproduced or redistributed for commercial use.
  • 128. ARM Future Development (2) • Qualcomm’s SnapDragon based on Scorpion: – 1 GHz microprocessor – CDMA and UMTS network support – Upto 12 mega pixels camera support – Enhanced multimedia support – DVD quality display support – GPS support – Support for various peripherals like hard disk, monitor, USB devices, bluetooth etc. Copyright (c) 2006 by Ajay Dudani 128 May not be reproduced or redistributed for commercial use.
  • 129. ARM Future Development (3) • Its ARM v/s x86 for UMPC and mobile devices market Copyright (c) 2006 by Ajay Dudani 129 May not be reproduced or redistributed for commercial use.
  • 130. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani 130 May not be reproduced or redistributed for commercial use.
  • 131. Questions & Comments Copyright (c) 2006 by Ajay Dudani 131 May not be reproduced or redistributed for commercial use.