Recent articles published in VLSI design & Communication Systems

Recent articles published in
VLSI design &
Communication Systems
International journal of VLSI design &
Communication Systems (VLSICS)
ISSN : 0976 - 1357 (Online); 0976 - 1527(print)
http://airccse.org/journal/vlsi/vlsics.html

A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR
ELECTRONIC APPLICATIONS
1
Angila Rose Daniel and 2
B. Deepa
1
M.Tech in VLSI and embedded systems, Kerala technical university, India
2
Assistant professor, EC Department, Kerala technical university, India
ABSTRACT
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach
is to around the operands to the closest exponent of 2. This way the machine intensive a part of the
multiplication is omitted up speed and energy consumption. The potency of the planned multiplier
factor is evaluated by comparing its performance with those of some approximate and correct
multipliers using different design parameters. In this proposed approach combined the conventional
RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases,
the newly designed RoBA multiplier architectures outperformed the corresponding approximate
(exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice
or image smoothing applications in the DSP.
KEYWORDS
Accuracy, approximate computing, efficient, error analysis, high speed multiplier, RoBa architecture,
kogge stone adder, DSP processing
Full Text : https://aircconline.com/vlsics/V10N1/10119vlsi01.pdf
International Journal of VLSI design & Communication Systems (VLSICS)
http://airccse.org/journal/vlsi/vol10.html

REFERENCES
[1] Zendegani, Reza, Mehdi Kamal, Milad Bahadori, Ali Afzali-Kusha and Massoud Pedram. “RoBA
Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital
Signal Processing.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2017):
393-401.
[2] M. Alioto, “Ultra-low power VLSI circuit design demystified and explained: A tutorial,” IEEE
Trans. Cir-cuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 3–29, Jan. 2016.
[3] V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, “Low-power digital signal processing
using approx-imate adders,” IEEE Trans. Comput.-Aided Design In-tegr. Circuits Syst., vol. 32, no. 1,
pp. 124–137, Jan. 2013.
[4] H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas, “Bio-inspired imprecise computational
blocks for efficient VLSI implementation of soft-computing appli-cations,” IEEE Trans. Circuits
Syst. I, Reg. Papers, vol. 57, no. 4, pp. 850–862, Apr. 2010.
[5] R. Venkatesan, A. Agarwal, K. Roy, and A. Raghu-nathan, “MACACO: Modeling and analysis of
circuits for approximate computing,” in Proc. Int. Conf. Com-put.-Aided Design, Nov. 2011, pp. 667–
673.
[6] F. Farshchi, M. S. Abrishami, and S. M. Fakhraie, “New approximate multiplier for low power
digital signal processing,” in Proc. 17th Int. Symp. Comput. Archit. Digit. Syst. (CADS), Oct. 2013,
pp. 25–30.
[7] D. R. Kelly, B. J. Phillips, and S. Al-Sarawi, “Ap-proximate signed binary integer multipliers for
arithmetic data value speculation,” in Proc. Conf.Design Archit. Signal Image Process., 2009, pp. 97–
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[8] K. Y. Kyaw, W. L. Goh, and K. S. Yeo, “Low-power high-speed multiplier for error-tolerant
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1–4.
[9] A. Momeni, J. Han, P. Montuschi, and F. Lombardi, “Design and analysis of approximate
compressors for multiplication,” IEEE Trans.Comput., vol. 64, no. 4, pp. 984–994, Apr. 2015.
[10] K. Bhardwaj and P. S. Mane, “ACMA: Accuracy-configurable multiplier architecture for
errorresilient system-on-chip,” in Proc. 8th Int.Workshop Reconfigur-able Commun.-Centric Syst.-
Chip, 2013, pp. 1–6.
[11] K. Bhardwaj, P. S. Mane, and J. Henkel, “Power- and area-efficient approximate wallace tree
multiplier for error-resilient systems,” in Proc.15th Int. Symp. Quality Electron. Design (ISQED),
2014, pp. 263–269.
[12] J. N. Mitchell, “Computer multiplication and divi-sion using binary logarithms,” IRE Trans.
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[15] H. R. Myler and A. R. Weeks, The Pocket Hand-book of Image Processing Algorithms in C.
Englewood Cliffs, NJ, USA: Prentice-Hall, 2009.
[16] S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. S. Kim, “Energy-efficient
approximate mul-tiplication for digital signal processing and classification applications,” IEEE Trans.
Very Large ScaleIntegr. (VLSI) Syst., vol. 23, no. 6, pp. 1180–1184, Jun. 2015.
[17] S. Hashemi, R. I. Bahar, and S. Reda, “DRUM: A dynamic range unbiased multiplier for
approximate ap-plications,” in Proc. IEEE/ACMInt. Conf. Comput.-Aided Design (ICCAD), Austin,
TX, USA, 2015, pp. 418–425.
[18] C.-H. Lin and I.-C. Lin, “High accuracy approx-imate multiplier with error correction,” in Proc.
31st Int. Conf. Comput. Design (ICCD), 2013, pp. 33–38.
[19] A. B. Kahng and S. Kang, “Accuracy-configurable adder for approximate arithmetic designs,” in
Proc. 49th Design Autom. Conf. (DAC), Jun. 2012, pp. 820–825.
[20] J. Liang, J. Han, and F. Lombardi, “New metrics for the reliability of approximate and
probabilistic adders,” IEEE Trans. Comput., vol. 62, no. 9, pp. 1760–1771, Sep. 2013.

EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON
FPGA
Jaya Koshta, Kavita Khare and M.K Gupta Maulana Azad
National Institute of Technology, Bhopal
ABSTRACT
Video Compression is very essential to meet the technological demands such as low power, less
memory and fast transfer rate for different range of devices and for various multimedia applications.
Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder
which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as
distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed
which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle
and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15%
and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and
synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA.
KEYWORDS
HEVC, motion estimation, sum of absolute difference, parallel prefix adders, Brent Kung Adder.
Full Text : https://aircconline.com/vlsics/V10N2/10219vlsi01.pdf

REFERENCES
[1] G. J. Sullivan, J.-R. Ohm, W.-J. Han, and T. Wiegand, “Overview of the high efficiency video
coding (HEVC)standard,” IEEE Trans. Circuits Syst. Video Technol., vol.22, no. 12, pp. 1649-1668,
December 2012.
[2] I. Richardson, “HEVC: An introduction to high efficiency video coding,” 2001,
https://www.vcodex.com/h265.html
[3] N. Purnachand, L. N. Alves, and A. Navarro, “Fast Motion Estimation Algorithm for HEVC”,
IEEE International Conference on Consumer Electronics-Berlin (ICCE-Berlin), September 2012.
[4] S.Wong, B. Stougie, and S. Cotofana, “Alternatives in FPGA-based SAD Implementations,” in
IEEE International Conference on Field-Programmable Technology (FPT),IEEE, 2002, pp. 449–452.
[5] S. Vassiliadis, E. A. Hakkennes, J. S. S. M. Wong, and G.G.Pechanek, “The Sum-
AbsoluteDifference Motion Estimation Accelerator,” in Euromicro Conference, 1998. Proceedings,
24th. IEEE, 1998, pp. 559–566.
[6] Ahmed Medhat, Ahmed Shalaby, Mohammed S. Sayed, Maha Elsabrouty and Farhad Mehdipour.
“A Highly Parallel SAD Architecture for Motion Estimation in HEVC Encoder”, Circuits and
Systems (APCCAS), IEEE Asia Pacific Conference, 280 - 283, 2014.
[7] Stefania Perri , Paolo Zicari , Pasquale Corsonello, “Efficient Absolute Difference Circuits in
Virtex5 FPGAs”, IEEE, 2010.
[8] Martin Kumm, Marco Kleinlein and Peter Zipf, “Efficient Sum of Absolute Difference
Computation on FPGAs”,26thInternational Conference on Field Programmable Logic and
Applications.
[9] Joaquin Olivares, Ignacio Benavides and et.al., “Minimum Sum of Absolute Differences
implementation in a single FPGA device”, Dept. of Electro-technics and Electronics, University of
Cordoba, Spain.
[10] P.Jayakrishnan and Harish. M. Kittur, “Pipelined Arch.for Motion Estimation in HEVC Video
Coding”, Indian Journal of Science and Tech,August 2016.
[11] D. V Manjunatha, Pradeep Kumar and R. Karthik, “FPGA Implementation of Sum of Absolute
Difference (SAD) for video applications”, ARPN Journal of Engineering and Applied Sciences, Vol.
12, No. 24, December 2017
[12] Geeta Rani and Sachin Kumar, “Delay analysis of parallel-prefix adders”, International Journal
of Science and Research (IJSR), 3(6):2339-2342, 2014.
[13] Nurdiani Zamhari, Peter Voon, Kuryati Kipli, Kho Lee Chin, Maimun Huja Husin,“Comparison
of Parallel Prefix Adder (PPA)”, Proceedings of the World Congress on Engineering 2012,Vol II.
[14] R. P Brent & H. T. Kung, “A Regular Layout for Parallel Adders”, IEEE Trans. Computers, Vol.
C31, pp 260-264, 1982.
[15] Shun-Wen Cheng, “A High-Speed Magnitude Comparator with Small Transistor Count”, in
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[16] J.Sklansky, “Conditional-Sum Addition Logic,” IRE Transactions on Electronic Computers, Vol.

EC9, No. 2, pp. 226-231, June,1960
[17] S. Rehman; R. Young;C. Chatwin;P. Birch, “An FPGA Based Generic Framework for High
Speed Sum of Absolute Difference Implementation”, Europ. Jour Scient. Res., vol.33, no.1, 2009.
[18] Manjunatha, D. V., and G. Sainarayanan. “Low-Power Sum of Absolute Difference Architecture
for Video Coding”, Emerging Research in Electronics, Computer Science and Technology. Springer
India, 2014. 335-341.
[19] LiYufei，Feng Xiubo and Wang Q in, “A High-Performance Low Cost SAD Architecture for
Video Coding”, IEEE Transactions on Consumer Electronics, pp. 535-541, Vol. 53, No. 2, May 2007.
[20] Jarno, Vanne, Eero Aho, Timo D. Hamalainen and Kimmo Kuusilinna, “A High-Performance
Sum of Absolute Difference Implementation Motion Estimation”, IEEE Transactions on Circuits and
Systems for Video Technology, pp. 876-883, Vol. 16, No. 7, 2006.
[21] Elhamzi W., Dubois J., Miteran J “An efficient low-cost FPGA implementation of a
configurable motion estimation for H.264 video coding”, Springer Journal of Real-Time
Processing,Vol:9, No:1, pp. 19–30,2014.
[22] Moorthy T., Ye A, “A scalable architecture for variable block size motion estimation on
fieldprogrammable gate arrays” , IEEE Canadian Conference of Electrical and Computer Engineering
(CCECE),Niagara Falls, May, pp.1303–1308,2008.
[23] Davis P., Sangeetha M. ,“Implementation of Motion Estimation Algorithm for H.265/HEVC”,
International Journal of Advanced Research in Electrical, Electronics and Instrumentation
Engineering. Vol:3,No:3, pp. 122–126,2014.

DUTY CYCLE CORRECTOR USING PULSE WIDTH MODULATION
Meghana Patil1
, Dr. Kiran Bailey2
and Rajanikanth Anuvanahally3
1
Department of Electronics and Communication, BMSCE, Bengaluru, Karnataka, India
2
Department of Electronics and Communication, BMSCE, Bengaluru, Karnataka, India
3
Senior Member IEEE, Bengaluru, Karnataka, India
ABSTRACT
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done
with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very
much necessary to see to it that the clock signals are properly received specially in receiver circuits
where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter,
skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle
correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog
feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector
operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy.
The design is simple and the power consumption is 1.01mW.
KEYWORDS
DCC, Integrator, Control voltage generator, frequency range
Full Text - https://aircconline.com/vlsics/V10N3/10319vlsi01.pdf

REFERENCES
[1] Jayaprakash SR, Sujatha S. Hiremath,(2017) “Dual loop clock duty cycle corrector for high speed
serial interface”, IEEE, pp 935-939.
[2] Immanuel Raja, Gaurab Banerjee, Jacob A Abraham, (2016) “ A 0/1-3.5Ghz duty cycle
measurement and correction technique in 130nm CMOS”, IEEE transaction on VLSI, Vol. 24, No.5,
pp 1975-1983.
[3] Feng Lin, (2011) “All digital duty-cycle correction circuit design and its applications in high
performance DRAM”, IEEE.
[4] Yusong Qiu, Yun Zeng and Feng Zhang, (2014) “1-5Ghz duty-cycle corrector circuit with wide
correction range and high precision”, Electronics letters, Vol. 50, No.11, pp 792-794.
[5] Young Jae Min, Chan Hui Jeong, et.al.,(2012) “A 0.31-1 Ghz Fast corrected duty cycle corrector
withsuccessive approximation register for DDR DRAM applications”, IEEE transaction on VLSI,
Vol. 20, No. 8, pp 1524-1528.
[6] Chan hui Jeong, Ammar Abdullah, (2016) “All digital duty cycle corrector with a wide duty
correction range for DRAM applications”, IEEE transaction on VLSI, Vol. 24, No.1, pp 363-367.
[7] Poki Chen, Shi Wei Chen, Juan-shan Lai, (2007) “Low power wide range duty cycle corrector
based on pulse shrinking/stretching mechanism”, IEEE, pp 935-939.
[8] Behzad Razavi, :Design of analog CMOS integrated circuits”, McGraw Hill International Edition.
[9] Ravi Mehta, Sumanthra set, et.al., (2012) “A programmable, Multi GHz, Wide range duty cycle
correction circuit in 45nm process”, IEEE, pp 257-260.
[10] Sotirios Tambouris, Texas Instruments Deutschland, (2009) “CMOS integrated circuit for
correction of duty cycle of clock signal”, US Patent 7586349.
[11] Chin – Wei Tsai, Yu – Lung Lo, Chia – Chen Chang, et.al., (2017) “ All digital duty cycle
corrector with synchronous and high accuracy output for double data rate synchronous dynamic
random access memory applications”, The Japan Society of Applied Physics, pp 04CF02-1 – 04CF02-
6.
[12] Sharath Patil, S. B. Rudraswamy, (2009) “Duty cycle correction using negative feedback loop”,
MIXDES 16th International Conference on Mixed design of integrated circuits systems, Poland, pp
424-426.
[13] Ji - Hoon Lim, Jun – Hyun Bae, et.al., (2016) “ A Delay- locked loop with a feedback edge
combiner of duty cycle corrector with 20-80% input duty cycle for SDRAMs”, IEEE transcation on
circuits and systems – II: express briefs, Vol. 63. No/ 2, pp 141-145.
[14] Kanak Agarwal, Robert Montoye, (2006) “ A duty cycle correction circuit for high frequency
clocks”, IEEE : Symposium on VLSI circuit digest of technical papers.

AUTHORS
Meghana Patil is a MTech student in VLSI and embedded systems at BMS college of
engineering, Bengaluru, Karnataka. She has done one year of internship in Analog
domain.
Dr Kiran Bailey is working in the Dept. of ECE, BMSCE, for the past 21 years and
has completed her doctorate in the field of VLSI devices. Her areas of interest include
novel device structures such as FinFETs, vertical MOSFETs and Tunnel FETs.
Mr. Rajanikanth Anuvanahally is a IEEE Senior member. He has over 11 years of
experience in Analog and Mixed signal design with specialisation in Data converters
and clock circuits. In addition. he carries 4+ years of experience in Learning and
Development, built and deployed many E learning courses in the Semiconductor
domain.

FPGA IMPLEMENTATION OF HUANG HILBERT TRANSFORM FOR
CLASSIFICATION OF EPILEPTIC SEIZURES USING ARTIFICIAL NEURAL
NETWORK
G.Deepika1
and K.S.Rao2
1
Research scholar at JNTU,Hyderabad , Asso.Prof at RRS college of Engg,
2
Director & Professor in ECE Dept,Anurag group of Institutions, Hyderabad
ABSTRACT
The most common brain disorders due to abnormal burst of electrical discharges are termed as
Epileptic seizures. This work proposes an efficient approach to extract the features of epileptic
seizures by decomposing EEG into band limited signals termed as IMF’s by empirical decomposition
EMD. Huang Hilbert Transform is applied on these IMF’s for calculating Instantaneous frequencies
and are classified using artificial neural network trained by Back propagation algorithm. The results
indicate an accuracy of 97.87%. The algorithm is implemented using Verilog HDL on Zynq 7000
family FPGA evaluation board using Xilinx vivado 2015.2 version.
KEYWORDS
EEG, IMF,EMD

REFERENCES
[1] J. Gotman., “Automatic recognition of epileptic seizures in the EEG,” Clinical Neurophysiology,
vol. 54, pp. 530–540, 1982
[2] J.Gotman., “Automatic seizure detection: improvements and evaluation,” Clinical
Neurophysiology, vol. 76, pp. 317–324, 1990
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cerebral”, Clinical Neurophysiology, vol. 114, pp. 899-908, 2003
[5] Güler NF, Übeyli ED, Güler.”Recurrent neural networks employing Lyapunov xponents for EEG
signal classification”,Expert Syst Appl. 2005; 29(3):506-14
[6] Varun Bajaj, Ram Bilas Pachori “Epileptic Seizure Detection Based on the Instantaneous Area of
Analytic Intrinsic Mode Functions of EEG Signals,” Biomed Eng Lett, vol. 3, pp. 17-21, 2013
[7] EEG time time series (epilepticdata)(2005,Nov.) [Online],
http://www.meb.unibonn.de/epileptologie/science/physik/eegdata.html
[8] Hedi Khammari , Ashraf Anwar, “A Spectral Based Forecasting Tool of Epileptic Seizures ”
IJCSI International.Journal of Computer Science Issues, Vol. 9, Issue 3, No 3, May 2012
[9] Rami J Oweis and Enas W Abdulhay., “Seizure classification in EEG signals utilizing Hilbert-
Huang transform” BioMedical Engineering OnLine 2011, 10:38
[10] lajos losonczi, lászló bakó, sándor-tihamér ,Brassai and lászló-ferenc Márton., “Hilbert-huang
transform used for eeg signal analysis ,” The 6th edition of the Interdisciplinarity in Engineering
International Conference , “Petru Maior” University of Tîrgu Mure, Romania, 2012
AUTHORS PROFILE
G. Deepika obtained her B.E., M.Tech degree in ECE in the year of 2002, 2005 from
CBIT, Osmania University and JNT University, Hyderabad respectively. She had 10
years of teaching experience. Presently she is an Associate Professor in RRS College
of Engineering & Technology, Medak District and pursuing Ph.D in JNT University,
Hyderabad.
Dr. K. S. Rao obtained his B. Tech, M. Tech and Ph.D. in Electronics and
Instrumentation Engineering in the years 1986, 89 and 97 from KITS, REC Warangal
and VRCE Nagpur respectively. He had 25 years of teaching and research experience
and worked in all academic positions, presently he is the Director, Anu rag Group of
Institutions (Autonomous) Hyderabad. His fields of interests are Signal Processing,
Neural Networks and VLSI system design.

DESIGN AND IMPLEMENTATION OF COMBINED PIPELINING AND PARALLEL
PROCESSING ARCHITECTURE FOR FIR AND IIR FILTERS USING VHDL
Jacinta Potsangbam1
and Manoj Kumar2
1
M. Tech VLSI Design, Dept. of ECE, National Institute of Technology, Manipur, India
2
Assistant Professor, Dept. of ECE, National Institute of Technology, Manipur, India
ABSTRACT
Along with the advancement in VLSI (Very Large Scale Integration) technology, the implementation
of Finite impulse response (FIR) filters and Infinite impulse response (IIR) filters with enhanced
speed has become more demanding. This paper aims at designing and implementing a combined
pipelining and parallel processing architecture for FIR and IIR filter using VHDL (Very High Speed
Integrated Circuit Hardware Descriptive Language) to reduce the power consumption and delay of the
filter. The proposed architecture is compared with the original FIR and IIR filter respectively in terms
of speed, area, and power. Also, the proposed architecture is compared with existing architectures in
terms of delay. The implementation is done by using VHDL codes. FIR and IIR filters structures are
implemented at 1200 KHz clock frequency. Synthesis and simulation have been accomplished on
Artix-7 series FPGA, target device (xc7a200tfbg676) (speed grade -1) using VIVADO 2016.3.
KEYWORDS
DSP, FIR, FPGA, IIR, MIMO.

REFERENCES
[1]. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York:
Wiley, 1999.
[2]. S. M. Rabiul Islam, R. Sarker, S. Saha and A. F. M. Nokib Uddin, “Design of a Programmable
digital IIR filter based on FPGA” 2012 International Conference on Informatics, Electronics & Vision
(ICIEV), Dhaka, pp. 716-72, 2012.
[3]. Suresh Gawande and SnehaBhujbal “High Speed IIR Notch Filter Using Pipelined Technique”
International Journal of Advanced Research in Electrical, Electronics and Instrumentation
Engineering Vol. 6, Issue 2, February 2017.
[4]. Yu-Chi Tsao and Ken Choi“Area-Efficient VLSI Implementation for Parallel Linear- Phase FIR
Digital Filters of Odd Length Based on Fast FIR Algorithm” IEEE Transactions On Circuits And
Systems—ii: Express Briefs, Vol. 59, No. 6, June 2012.
[5]. Ravinder Kaur and Ashish Raman “Design and Implementation of High Speed IIR and FIR Filter
using Pipelining” International Journal of Computer Theory and Engineering, Vol. 3, No. 2, April
2011.
[6]. B. K. Mohanty and P. K. Meher, "A High-Performance FIR Filter Architecture for Fixed and
Reconfigurable Applications," IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 24, no. 2, pp. 444-452, Feb. 2016.
[7]. https://en.wikipedia.org/wiki/Infinite_impulse_responsepage was last edited on 17 January 2019,
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[8]. Aarti Sharma and Sanjay Kumar “VLSI Implementation of Pipelined FIR Filter” International
Journal of Innovative Research In Electrical, Electronics, InstrumentationAnd Control Engineering
Vol. 1, Issue 5, August 2013.
[9]. S. Khorbotly, J. E. Carletta and R. J. Veillette, “A methodology for implementing pipelined
fixedpoint infinite impulse response filters,” 41st Southeastern Symposium on System Theory,
Tullahoma, TN, 2009, pp. 280-284, 2009.
[10]. Keshab K. Parhi and David G. Messerschmitt, “Pipeline Interleaving and Parallelism in
Recursive Digital Filters-Part I: Pipelining Using Scattered Look-Ahead and Decomposition” IEEE
Transactions on Acoustics, Speech, and Signal Processing, Vol. 31. No. 7, July 1989.
[11]. David A. Parker and Keshab K. Parhi, “Low-Area/Power Parallel FIR Digital Filter
Implementations,” Journal of VLSI Signal Processing 17, 75–92 (1997).
[12]. Shaila Khan and Uma Sharma, “Implementation of Low Power Area Efficient Parallel FIR
Digital Filter Structures of Odd Length Based on Common Sub expression Algorithm” International
Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 5,
Issue 1, January 2016.
[13]. S. Balasubramaniam and R. Bharathi, “Performance Analysis of Parallel FIR Digital Filter using
VHDL” International Journal of Computer Applications Volume 39– No.9, February 2012.
[14]. Keshab K. Parhi and David G. Messerschmitt, “Pipeline Interleaving and Parallelism in

Recursive Digital Filters-Part II: Pipelined Incremental Block Filtering” IEEE Transactions on
Acoustics, Speech, and Signal Processing. Vol 37. No.7. July1989.
[15]. KanuPriya and Rajesh Mehra “Area Efficient Design of Fir Filter using Symmetric Structure”
International Journal of Advanced Research in Computer and Communication Engineering Vol. 1,
Issue 10, December 2012.
[16]. L KholeePhimu and Manojkumar“VLSI Implementation of Area Efficient 2-parallel FIR Digital
Filter” International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6,
December 2016.
[17]. Saranya R, Pradeep C, Neena Baby and R Radhakrishnan “FPGA Synthesis of Reconfigurable
Modules for FIR Filter” International Journal of Reconfigurable and Embedded Systems (IJRES) Vol.
4, No. 2, pp. 63-70, 2015.
[18]. Mahesh Kadam, KishorSawarkar and SudhakarMande “Comparative Analysis and Efficient
VLSI Implementation of FIR Filter” International Journal of Advanced Research in Electrical,
Electronics and Instrumentation Engineering, Vol. 3, Issue 7, July 2014.
[19]. TamliDhanrajSawarkar, Prof.LokeshChawle and Prof. N.G. Narole, “Implementation of 4-Tap
Sequential and Parallel Micro-programmed Based Digital FIR Filter Architecture using VHDL”
International Journal of Innovative Research in Computer and Communication Engineering Vol. 4,
Issue 4, April 2016.
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Implementation of FIR Filters in FPGA Platform," 2007 International Symposium on Signals, Circuits
and Systems, Iasi, 2007, pp. 1-4.
[21]. Manoj Kumar, “Design of IIR systolic array architecture by using linear mapping technique”,
International Journal of Computer Applications, vol.182, no.39, pp.14-19, 2019.

DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR
P. Indira1
, M. Kamaraju2
and Ved Vyas Dwivedi3
1,3
Department of Electronics and Communication Engineering, CU Shah University, Wadhwan,
Gujarat, India
2
Department of Electronics and Communication Engineering,Gudlavalleru Engineering College, JNT
University, Kakinada, Andhra Pradesh, India
ABSTRACT
Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction
stream to get increased throughput, and it lessens the total time to complete the work. . The major
objective of this architecture is to design a low power high performance structure which fulfils all the
requirements of the design. The critical factors like power, frequency, area, propagation delay are
analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC
processor is used in 6-stage pipelining to optimize the critical performance factors. The fundamental
functional blocks of the processor include Input/Output blocks, configurable logic blocks, Block
RAM, and Digital clock Manager and each block permits to connect to multiple sources for the
routing. The Auxiliary units enhance the performance of the processor. The comparative study
elevates the designed model in terms of Area, Power and Frequency. MATLAB2D/3D graphs
represents the relationship among various parameters of this pipelining. In this pipeline model, it
consumes very less power (0.129 W),path delay (11.180 ns) and low LUT utilization (421). Similarly,
the proposed model achieves better frequency increase (285.583 Mhz.), which obtained better results
compared to other models.
KEYWORDS
MATLAB, SPARTAN3E, MIPS RISC processor, Xilinx, Digital Clock Manager.

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AUTHORS
PONUGUMATLA INDIRA,
M. Tech., MBA, M.Sc. (Psych), (Ph.D.).
Assistant Professor, GITAM University, Hyderabad
DR. M. KAMARAJU,
M. Tech., Ph.D.
Professor, ECE Dept.,
Gudlavalleru Engineering College, JNTUK,
Krishna District, Andhra Pradesh, India
DR. VED VYAS DWIVEDI,
M. Tech., Ph.D.
Professor, ECE Dept.
Pro-Vice Chancellor, CU Shah University,
Wadhwan – Gujarat, India

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