RISC-V LLVM State of the Union

Nov 11, 20240 likes21 views

The success of the RISC-V instruction set architecture depends on the ability for software to exploit the hardware effectively, both for the baseline (and now defined ISA profiles) and for new instruction set extensions. The LLVM compiler infrastructure (including Clang) is key for this, and has been a major success story for RISC-V software ecosystem enablement through cross-party collaboration. This talk provides an update on the current status, with up to date benchmarks for code size and generated code performance vs GCC. We'll explore how recent work in CI and tracking of these metrics has been helping to accelerate progress and ensure quality, and look ahead to future challenges. (c) RISC-V Summit North America 2024 October 22-23, 2024 Santa Clara, California (US) https://riscv.org/event/risc-v-summit-north-america-2024/ https://www.youtube.com/watch?v=8SSNZwvRhqU

RISC-V LLVM State of the Union
Alex Bradbury asb@igalia.com
RISC-V Summit North America, 2024-10-23

What is LLVM?
● A collection of modular compiler and toolchain technologies
● Modern C++ implementation
● Library-based design
● Permissively licensed
● C/C++ toolchain (Clang) and equivalents to various binutils tools
● Primary backend for e.g. Rust
● Used by many downstream vendor toolchains

RISC-V LLVM status today
● Full support for all mandatory extensions in RVA20, RVA22, RVA23 proﬁles.
○ Some optional RVA23 features like CFI via Zicﬁlp and Zicﬁss supported
but marked experimental.
○ Equivalent support for 32-bit, with all proposed RVM23 extensions
supported.
● All standard ABIs supported.
● Range of vendor speciﬁc extensions supported.
● See: https://llvm.org/docs/RISCVUsage.html and clang
-print-supported-extensions to dump extension support in your build.

RISC-V LLVM development
● Contributors from across the RISC-V ecosystem (mixture of vendors, and
adopters).
● Policies for upstreaming of not-yet-ratiﬁed extensions (supporting
incremental development) and vendor extensions.
● Biweekly community sync-up calls
● LLVM release cadence: 2 major releases a year
● ~7500 commits, ~80KLoC (llvm/lib/Target/RISCV) and many more in tests!

Testing
● Buildbot infrastructure and development supported by RISE
● Cluster of buildbots providing post-commit checks
○ rva20, rva23, rva23 -mrvv-vector-bits, rva23 evl tail folding
○ QEMU based
● QEMU-supported performance investigation
○ Custom plugins + processing for identifying and analysing hot blocks.
● LNT

By the numbers: performance
TO UPDATE (Tests still running)

By the numbers: code size
TO UPDATE (Tests still running)

Recent improvements
● Superword-level parallelism (SLP) vectorizer enabled in LVLM 17.
● Growth in scheduling models for different microarchitectures.
● Complete CFI implementation using Zicﬁlp/Zicﬁss
● Rework of vsetvli insertion pass ordering
● Non-power-of-two vectorisation

Recent improvements
● Atomics: Zacas, Ztso no longer experimental
● Major improvements to Z[v]fh/Z[v]fhmin/Z[v]fbfmin codegen.
● Ongoing tuning and addressing performance gaps (e.g. LoopStrengthReduce
term folding).
● Full LLVM libc support for RV32 and RV64
● Large code model support.

Getting involved
● Documentation/tutorials on internals such as
○ LLVM Docs: RISC-V Vector extension
○ RISC-V Summit Europe tutorial: Supporting custom RISC-V extensions
in LLVM
● RISC-V on LLVM’s Discourse
https://discourse.llvm.org/c/code-generation/riscv/57
○ Has details on bi-weekly sync-up calls.

A sampling of future work
● Completion of function multiversioning support.
● VLOptimizer pass
● Further SPEC codegen improvements (supported by RISE)
● Machine outliner gap analysis and improvements.
● Epilogue vectorization and tail folding in the loop vectorizer.
● Register allocator / constant rematerialisation improvements.
● Teaching the loop vectorizer to dynamically select LMUL
● … and much more

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1. RISC-V LLVM State of the Union Alex Bradbury [email protected] RISC-V Summit North America, 2024-10-23

2. What is LLVM? ● A collection of modular compiler and toolchain technologies ● Modern C++ implementation ● Library-based design ● Permissively licensed ● C/C++ toolchain (Clang) and equivalents to various binutils tools ● Primary backend for e.g. Rust ● Used by many downstream vendor toolchains

3. RISC-V LLVM status today ● Full support for all mandatory extensions in RVA20, RVA22, RVA23 profiles. ○ Some optional RVA23 features like CFI via Zicfilp and Zicfiss supported but marked experimental. ○ Equivalent support for 32-bit, with all proposed RVM23 extensions supported. ● All standard ABIs supported. ● Range of vendor specific extensions supported. ● See: https://llvm.org/docs/RISCVUsage.html and clang -print-supported-extensions to dump extension support in your build.

4. RISC-V LLVM development ● Contributors from across the RISC-V ecosystem (mixture of vendors, and adopters). ● Policies for upstreaming of not-yet-ratiﬁed extensions (supporting incremental development) and vendor extensions. ● Biweekly community sync-up calls ● LLVM release cadence: 2 major releases a year ● ~7500 commits, ~80KLoC (llvm/lib/Target/RISCV) and many more in tests!

5. Testing ● Buildbot infrastructure and development supported by RISE ● Cluster of buildbots providing post-commit checks ○ rva20, rva23, rva23 -mrvv-vector-bits, rva23 evl tail folding ○ QEMU based ● QEMU-supported performance investigation ○ Custom plugins + processing for identifying and analysing hot blocks. ● LNT

6. Performance and code size comparisons

7. By the numbers: performance TO UPDATE (Tests still running)

8. By the numbers: performance TO UPDATE (Tests still running)

9. By the numbers: code size TO UPDATE (Tests still running)

10. Recent improvements ● Superword-level parallelism (SLP) vectorizer enabled in LVLM 17. ● Growth in scheduling models for different microarchitectures. ● Complete CFI implementation using Zicﬁlp/Zicﬁss ● Rework of vsetvli insertion pass ordering ● Non-power-of-two vectorisation

11. Recent improvements ● Atomics: Zacas, Ztso no longer experimental ● Major improvements to Z[v]fh/Z[v]fhmin/Z[v]fbfmin codegen. ● Ongoing tuning and addressing performance gaps (e.g. LoopStrengthReduce term folding). ● Full LLVM libc support for RV32 and RV64 ● Large code model support.

12. Getting involved ● Documentation/tutorials on internals such as ○ LLVM Docs: RISC-V Vector extension ○ RISC-V Summit Europe tutorial: Supporting custom RISC-V extensions in LLVM ● RISC-V on LLVM’s Discourse https://discourse.llvm.org/c/code-generation/riscv/57 ○ Has details on bi-weekly sync-up calls.

13. A sampling of future work ● Completion of function multiversioning support. ● VLOptimizer pass ● Further SPEC codegen improvements (supported by RISE) ● Machine outliner gap analysis and improvements. ● Epilogue vectorization and tail folding in the loop vectorizer. ● Register allocator / constant rematerialisation improvements. ● Teaching the loop vectorizer to dynamically select LMUL ● … and much more

14. Questions? Contact: [email protected]

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