RISC-V and open source chip design
0 likes176 views
The document discusses RISC-V as a free and open instruction set architecture that is revolutionizing chip design, moving from academia to industry with support from numerous organizations and companies. It highlights the growth of open source FPGA tools, enabling makers to create hardware more easily and efficiently. Additionally, the document covers various projects and initiatives surrounding RISC-V technology, showcasing its potential in fostering innovation and independence in chip technology globally.
RISC-V and open source chip design
- 1. RISC-V and open source chip design Drew Fustini OSH Park [email protected] @oshpark / @pdp7 Slides: https://github.com/pdp7/talks/blob/master/nerp-riscv.pdf NERP meetup at PS1 hackerspace (2020-01-27)
- 2. ● Open Source Hardware designer at OSH Park ● PCB manufacturing service in the USA ● [email protected] / Twitter: @oshpark ● Volunteer Member of Board of Directors of BeagleBoard.org Foundation ● [email protected] ● Volunteer Member of the Board of Directors of the Open Source Hardware Association (OSHWA) ● [email protected]
- 4. Section: RISC-V the instruction set for everything? Slides: https://github.com/pdp7/talks/blob/master/nerp-riscv.pdf
- 5. ● My column in the latest Hackspace Magazine is an introduction to RISC-V and how it is enabling open source chip design: – hackspace.raspberrypi.org/issues/27/
- 6. ● When you write a program in the Arduino IDE, it is compiled into instructions for the microcontroller to execute. ● How does the compiler know what instructions the chip understands? – defined by the Instruction Set Architecture – The ISA is a standard, a set of rules that define the tasks the processor can perform. – Examples: x86 (Intel/AMD) and ARM ● Both are proprietary and need commercial licensing
- 7. ● RISC-V: Free and Open RISC Instruction Set Arch – “new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry”
- 8. ● RISC-V: Free and Open RISC Instruction Set Arch ● Instruction Sets Want To Be Free: A Case for RISC-V – David Patterson, UC Berekely – co-creator of the original RISC! – https://www.youtube.com/watch?v=mD-njD2QKN0 ● RISC-V Summit 2019: State of the Union – Krste Asanovic, UC Berkeley – https://www.youtube.com/watch?v=jdkFi9_Hw-c
- 17. RISC-V and Industry ● Created at UC Berkeley but useful beyond academia ● Designed to be extensible – Microcontroller to supercomputer ● RISC-V Foundation now controls standard: riscv.org – Over 400 members: companies, universities and more – YouTube channel has hundreds of talks! ● https://www.youtube.com/channel/UC5gLmcFuvdGbajs4VL-WU3g ● Nvidia and Western Digital are now shipping millions of devices with RISC-V processors – freedom to leverage open source implementations ● BOOM, Rocket, PULP, SweRV, and many more – avoiding ARM licensing fees
- 20. RISC-V and the world ● RISC-V Foundation moving from US to Switzerland ● Nations such as India have RISC-V initiatives – Desire for sovereign technology and avoid backdoors from other nations ● Strong interest from chipmakers in China – U.S. companies have been banned from doing business with Huawei… who’s next? – ARM deemed UK-origin tech so ok to do business with Huawei, but what will brexit-govt bring?
- 21. ● OnChip Open-V “completely free (as in freedom) and open source 32-bit microcontroller based on the RISC-V architecture”
- 22. OnChip Open-V
- 23. ● lowRISC: “creating a fully open-sourced, Linux- capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design” ● Video: Rob Mullins talking about lowRISC – (RISC-V & Open Source Silicon Event in Munich on March 23, 2017 ● OpenTitan project with Google: – Announcing OpenTitan, the First Transparent Silicon Root of Trust
- 24. ● The Future of Operating Systems on RISC-V – Alex Bradbury gives an overview of the status and development of RISC-V as it relates to modern operating systems, highlighting major research strands, controversies, and opportunities to get involved. – https://www.youtube.com/watch?v=emnN9p4vhzk
- 25. ● FOSSi Foundation – The Free and Open Source Silicon Foundation – “non-profit foundation with the mission to promote and assist free and open digital hardware designs” – Events: ORConf, Latch-up, Week of OSHW – Open Source Silicon Design Ecosystem ● Talk by FOSSi co-founder Julius Baxter
- 26. ● LibreCores – Project of the FOSSi Foundation – “gateway to free and open source digital designs and other components that you can use and re-use in your digital designs” – “advances the idea of OpenCores.org”
- 27. SiFive ● “founded by the creators of the free and open RISC-V architecture as a reaction to the end of conventional transistor scaling and escalating chip design costs”
- 28. ● RISC-V Keynote at Embedded Linux Conf – March 12th, 2018 – Yunsup Lee, Co-Founder and CTO, SiFive – Designing the Next Billion Chips: How RISC-V is Revolutionizing Hardware
- 29. ● HiFive1: Arduino-Compatible RISC-V Dev Kit SiFive FE310 microcontroller
- 30. ● FOSDEM 2018 talk – YouTube: “Igniting the Open Hardware Ecosystem with RISC-V: SiFive's Freedom U500 is the World's First Linux-capable Open Source SoC Platform” – Interview with Palmer Dabbelt of SiFive SiFive: Linux on RISC-V
- 31. ● HiFive Unleashed on Crowd Supply SiFive: Linux on RISC-V
- 34. ● Experiment to get Linux on the low cost Kendryte K210 RISC-V microcontroller ● PDF: RISC-V NOMMU and M-mode Linux ● https://www.youtube.com/watch?v=ycG592N9EMA &t=10394 ● jump to 2h 53m ● Many RISC-V Improvements Ready For Linux 5.5: M-Mode, SECCOMP, Other Features
- 35. ● Great talk with overview of bootloader, Linux kernel, distro support – HOT CHIPS 2019: Linux RISC-V tutorial – https://youtu.be/nPXdbm9lc3A?t=6139 – 1 hour 42 minutes – “Overview of RISC-V SW Ecosystem” ● Bunnaroath Sou, SiFive
- 39. ● Andes 27-series CPU – “32-bit A27 and 64-bit AX27 and NX27V cores, which will enter production in Q1 2020.” – Andes’ RISC-V SoC debuts with AI-ready VPU as Microchip opens access to its PolarFire SoC ● Microchip PolarFire SoC FPGA – Hard RISC-V with FPGA fabric… like the Xilinx Zync for ARM ● NXP iMX with RISC-V instead of ARM! – “OpenHW Group Unveils CORE-V Chassis SoC Project, Buil ding on PULP Project IP” Coming in 2020?
- 41. Coming in 2020?
- 42. ● Goal: Sub-$100 Open Source Hardware board that can run Linux on RISC-V ● Possible by 2021? ● Interested in working together? – [email protected] / Twitter: @pdp7 – create a mailing list? OSHW RISC-V Linux board for less than $100?
- 43. Section: Open Source FPGA tools Slides: https://github.com/pdp7/talks/blob/master/nerp-riscv.pdf
- 44. ● Hackspace Magazine column about how about open source FPGA tools developed by Claire Wolf (oe1cxw), David Shah and others have made FPGAs more accessible than ever before to makers and hackers: – hackspace.raspberrypi.org/issues/26/ Open Source and FPGAs
- 45. ● Keynote at Hackday Supercon 2019 by Dr. Megan Wachs of SiFive ● “RISC-V and FPGAs: Open Source Hardware Hacking” – https://www.youtube.com/watch?v=vCG5_nxm2G4
- 47. ● Open Source toolchains for FPGAs! – Project IceStorm for Lattice iCE40 ● “A Free and Open Source Verilog-to-Bitstream Flow for iC E40 FPGAs” by Claire Wolf (oe1cxw) at 32c3 Open Source and FPGAs
- 48. ● Open Source toolchains for FPGAs! – Project Trellis for Lattice ECP5 – “Project Trellis and nextpnr FOSS FPGA flow for the Lattice ECP5” - David Shah (@fpga_dave) ● youtube.com/watch?v=0se7kNes3EU Open Source and FPGAs
- 49. ● Open Source toolchains for FPGAs! – Project X-Ray and SymbiFlow for Xilinix Series 7 – Timothy ‘mithro’ Ansell: “Xilinx Series 7 FPGAs Now Have a Fully Open Source Toolchain!” (almost) ● youtube.com/watch?v=EHePto95qoE Open Source and FPGAs
- 50. ● Open Source Hardware boards with Lattice ECP5 FPGA with open RISC-V “soft” CPU: – Orange Crab by Greg Davill ● https://github.com/gregdavill/OrangeCrab Open Source and FPGAs
- 52. ● Radiona.org ULX3S ● https://www.crowdsupply.com/radiona/ulx3s Open Source and FPGAs
- 53. ● Open Source Hardware boards with Lattice ECP5 FPGA with open RISC-V “soft” CPU: – David Shah's Trellis board (Ultimate ECP5 Board) – https://github.com/daveshah1/TrellisBoard Open Source and FPGAs
- 54. Hackaday 2019 Supercon badge ● RISC-V “soft” core on ECP5 FPGA ● Gigantic FPGA In A Game Boy Form Factor
- 56. ● LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs. ● LiteX is based on Migen and provides specific building/ debugging tools for a higher level of abstraction and compatibily with the LiteX core ecosystem. ● Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a SoC builder to create/develop/debug FPGA SoCs in Python ● https://github.com/enjoy-digital/litex
- 57. ● Bunnie: LiteX vs. Vivado: First Impressions https://www.bunniestudios.com/blog/?p=5018
- 59. Linux on LiteX-VexRiscv ● Linux with VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU written in Spinal HDL ● SoC around the VexRiscv CPU is created using LiteX as the SoC builder and LiteX's cores written in Migen Python DSL (LiteDRAM, LiteEth, LiteSDCard) ● github.com/litex-hub/linux-on-litex-vexriscv
- 61. Section: Linux on the Hackaday Badge Slides: https://github.com/pdp7/talks/blob/master/nerp-riscv.pdf
- 62. Hackaday 2019 Supercon badge ● RISC-V “soft” core on ECP5 FPGA ● Gigantic FPGA In A Game Boy Form Factor
- 63. “Team Linux on Badge”
- 64. “Team Linux on Badge” ● Blog post: Hackaday Supercon badge boots Linux using SDRAM cartridge – https://blog.oshpark.com/2019/12/20/boot-linux-on-this- hackaday-supercon-badge-with-this-sdram-cartridge/ ● Michael Welling (@QwertyEmedded), Tim Ansell (@mithro), Sean Cross (@xobs), Jacob Creedon (@jacobcreedon) ● First attempt: use the built-in 16MB SRAM… no luck :( – (though xobs now might have a way to do it)
- 65. “Team Linux on Badge” ● Second attempt: – Jacob Creedon designed an a cartridge board that adds 32MB of SDRAM to the Hackaday Supercon badge… before the event!
- 66. “Team Linux on Badge” ● Second attempt: – Jacob Creedon designed an a cartridge board that adds 32MB of SDRAM to the Hackaday Supercon badge… before the event!
- 68. “Team Linux on Badge” ● https://youtu.be/3se_L0tRZeg?t=1055
- 69. Linux on LiteX-VexRiscv ● Linux with VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU written in Spinal HDL – github.com/litex-hub/linux-on-litex-vexriscv ● NOW with upstream support for the Hackaday Supercon badge! – https://github.com/litex-hub/litex-boards/pull/31
- 71. ● Opened GitHub issue: – optimize performance on Hackaday Badge #35 ● https://github.com/litex-hub/litex-boards/issues/35 ● Now 10x faster! – https://asciinema.org/a/Pcm3vd1BEdEKY9srYX6Ms NfCE – Thanks to enjoy-digital
- 73. Slides: github.com/pdp7/talks/blob/master/lug-riscv.pdf Drew Fustini [email protected] @pdp7 / @oshpark This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.
- 74. bonus section: Open Source Hardware laptop from Berlin Slides: https://github.com/pdp7/talks/blob/master/lug-riscv.pdf