SystemVerilog Assertions verification with SVAUnit - DVCon US 2016 Tutorial

Tutorial
SystemVerilog Assertions
Verification with SVAUnit
Andra Radu Ionu Ciocîrlanț

SVAUnit tutorial topics
• Introduction to SystemVerilog Assertions (SVAs)
• Planning SVA development
• Implementation
• SVA verification using SVAUnit
• SVA test patterns
2/29/2016 Andra Radu - AMIQ Consulting Ionu Ciocîrlan - AMIQ Consultingț 2

Introduction to SystemVerilog
Assertions
(SVAs)

Assertions and properties
• What is an assertion?
• What is a property?
assert (a |-> b)
else $error("Assertion failed!")
property p_example;
a |-> b
endproperty

Simple assertion example
property req_to_rise_p;
@(posedge clk)
$rose(req) |-> ##[1:3] $rose(ack);
endproperty
ASSERT_LABEL: assert property (req_to_rise_p)
else `uvm_error(“ERR", "Assertion failed")

Types of SystemVerilog
Assertions
• Immediate
• Concurrent
assert (expression) pass_statement
[else fail_statement]

Assertions are used
• In a verification component
• In a formal proof kit
• In RTL generation
“Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to
Hardware” (Fatemeh (Negin) Javaheri, Katell Morin-Allory, Dominique
Borrione)
• For test patterns generation
“Towards a Toolchain for Assertion-Driven Test Sequence Generation” (Laurence
PIERRE)

SVAs advantages
•Fast
•Non-instrusive
•Flexible
•Coverable

Planning SVA development

Identify design characteristics
• Defined in a document (design specification)
• Known or specified by the designer
• The most common format is of the form cause and
effect: antecedent |-> consequent
• Antecedent:
• Consequent:
$rose(req)
##[1:3] $rose(ack)

Keep it simple. Partition!
• Complex assertions are typically constructed from
complex sequences and properties.
a ##1 b[*1:2] |=> c ##1 d[*1:2] |=> $fell(a)
sequence seq(arg1, arg2);
arg1 ##1 arg2[*1:2];
endsequence
seq(a, b) |=> seq(c, d) |=> $fell(a)

Implementation

Coding guidelines
• Avoid duplicating design logic in assertions
• Avoid infinite assertions
• Reset considerations
• Mind the sampling clock

Coding guidelines (contd.)
• Always check for unknown condition (‘X’)
• Assertion naming
• Detailed assertion messages
• Assertion encapsulation

Best practices
• Review the SVA with the designer to avoid DS
misinterpretation
• Use strong in assertions that may never complete:
• Properties should not hold under certain conditions
(reset, enable switch)
assert property ( req |-> strong(##[1:$] ack));
assert property (
@(posedge clk) disable iff (!setup || !rst_n)
req |-> strong(##[1:$] ack)
);

Best practices (contd.)
• Avoid overlapping assertions that contradict each
other
CPU_0:
CPU_1:
assert property (WRITE |=> ERROR);
assert property (WRITE |=> !ERROR);
assert property (WRITE and CPU==0 |=> ERROR);
assert property (WRITE and CPU==1 |=> !ERROR);

Best practices (contd.)
• Use the $sampled() function in action blocks
Active
Inactive
NBA
Observed
Re-active
Re-inactive
Postponed
Preponed
Previous timeslot
Next timeslot
assert property ( @(posedge clk) ack == 0 )
else
`uvm_error("ERROR", $sformatf("Assertion
failed. ack is %d", $sampled(ack)));

Assertion example
• AMBA APB protocol specification:
The bus only remains in the SETUP state for one clock
cycle and always moves to the ACCESS state on the
next rising edge of the clock.

Assertion example (contd.)
• Antecedent (the SETUP phase)
• Consequent (the ACCESS phase)
sequence setup_phase_s;
$rose(psel) and $rose(pwrite)
and (!penable) and (!pready);
endsequence
sequence access_phase_s;
$rose(penable) and $rose(pready) and
$stable(pwrite) and $stable(pwdata)and
$stable(paddr) and $stable(psel);
endsequence

Assertion example (contd.)
• The property can be expressed as:
• The assertion will look like:
property access_to_setup_p;
@(posedge clk) disable iff (reset)
setup_phase_s |=> access_phase_s;
endproperty
assert property (access_to_setup_p)
else `uvm_error("ERR", "Assertion failed")

Does it work as intended?

SVA Verification with SVAUnit

SVA Verification Challenges
Clear separation between
validation and SVA
definition code
Easy to:
-Update
-Enhance
-Disable
Results should be:
- Deterministic
-Repeatable
Self-contained
Adaptable
Predictable

Introducing SVAUnit
• Structured framework for Unit Testing for SVAs
• Allows the user to decouple the SVA definition from its
validation code
• UVM compliant package written in SystemVerilog
• Encapsulate each SVA testing scenario inside an unit
test
• Easily controlled and supervised using a simple API

SVAUnit Infrastructure
SVAUnit Testbench
SVAUnit Test Suite
SVAUnit Unit Test
SVAUnit Test
test()
SVA interface handle
Interface
containing
SVA
Interface
containing
SVA
SVAUnit Test
SVAUnit Test Suite
Reports
Reports
Reports
Reports
• SVAUnit Testbench
- Enables SVAUnit
- Instantiates SVA
interface
- Starts test
• SVAUnit Test
- Contains the SVA scenario
• SVAUnit Test Suite
- Test and test suite
container

Example specification
• AMBA APB protocol specification:
The bus only remains in the SETUP state for one clock
cycle and always moves to the ACCESS state on the
next rising edge of the clock.

Example APB interface
interface apb_if (input pclk);
logic psel;
logic pwrite;
logic penable;
logic pready;
logic [`ADDR_WIDTH-1 :0] paddr;
logic [`WDATA_WIDTH-1:0] pwdata;
endinterface
APB sequences definitions
APB property definition
APB assertion definition

APB sequences definitions
• Antecedent (the SETUP phase)
• Consequent (the ACCESS phase)
sequence setup_phase_s;
$rose(psel) and $rose(pwrite)
and (!penable) and (!pready);
endsequence
sequence access_phase_s;
$rose(penable) and $rose(pready) and
$stable(pwrite) and $stable(pwdata)and
$stable(paddr) and $stable(psel);
endsequence

APB property & assertion
definitions
• The property can be expressed as:
• The assertion will look like:
property access_to_setup_p;
@(posedge clk) disable iff (reset)
setup_phase_s |=> access_phase_s;
endproperty
assert property (access_to_setup_p)
else `uvm_error("ERR", "Assertion failed")

Example of SVAUnit
Testbench
module top;
// Instantiate the SVAUnit framework
`SVAUNIT_UTILS
...
// APB interface with the SVA we want to test
apb_if an_apb_if(.clk(clock));
initial begin
// Register interface with the uvm_config_db
uvm_config_db#(virtual an_if)::
set(uvm_root::get(), "*", “VIF", an_apb_if);
// Start the scenarios
run_test();
end
...
endmodule

Example of SVAUnit Test
class ut1 extends svaunit_test;
// The virtual interface used to drive the signals
virtual apb_if apb_vif;
function void build_phase(input uvm_phase phase);
// Retrieve the interface handle from the uvm_config_db
if (!uvm_config_db#(virtual an_if)::get(this, "", “VIF", apb_vif))
`uvm_fatal(“UT1_NO_VIF_ERR", "SVA interface is not set!")
// Test will run by default;
disable_test();
endfunction
task test();
// Initialize signals
// Create scenarios for SVA verification
endtask
endclass

APB – SVAUnit test steps
Enable the APB SVA
Initialize the interface signals
Generate setup phase stimuli
Generate access phase stimuli
SVA checks based on generated stimuli

Enable SVA and initialize
signals
...
// Enable the APB SVA
vpiw.disable_all_assertions();
vpiw.enable_assertion("APB_PHASES");
// Initialize signals
task initialize_signals();
apb_vif.paddr <= 32'b0;
apb_vif.pwdata <= 32'b0;
apb_vif.pwrite <= 1'b0;
apb_vif.penable <= 1'b0;
apb_vif.psel <= 1'b0;
endtask
...

Generate setup phase stimuli
...
task generate_setup_phase_stimuli(bit valid);
...
// Stimuli for valid SVA scenario
valid == 1 ->
pwrite == 1 && psel == 1 && penable == 0 && pready ==
0;
// Stimuli for invalid SVA scenario
valid == 0 ->
pwrite != 1 || psel != 1 || penable != 0 || pready !=
0;
...
endtask
...

Generate access phase
stimuli
...
task generate_access_phase_stimuli(bit valid);
...
// Constrained stimuli for valid SVA scenario
valid == 1 ->
pwdata == apb_vif.pwdata && paddr == apb_vif.paddr &&
pwrite == 1 && psel == 1 && penable == 1 && pready == 1;
// Constrained stimuli for invalid SVA scenario
valid == 0 ->
pwdata != apb_vif.pwdata || paddr != apb_vif.paddr ||
pwrite != 1 || psel != 1 || penable != 1 || pready != 1;
...
endtask
...

SVA state checking
...
if (valid_setup_phase)
if (valid_access_phase)
vpiw.fail_if_sva_not_succeeded("APB_PHASES",
"The assertion should have succeeded!");
else
vpiw.fail_if_sva_succeeded("APB_PHASES",
"The assertion should have failed!");
else
vpiw.pass_if_sva_not_started("APB_PHASES",
"The assertion should not have started!");
...

Example of SVAUnit Test
Suite
class uts extends svaunit_test_suite;
// Instantiate the SVAUnit tests
ut1 ut1;
...
ut10 ut10;
function void build_phase(input uvm_phase phase);
// Create the tests using UVM factory
ut1 = ut1::type_id::create("ut1", this);
...
ut10 = ut10::type_id::create("ut10", this);
// Register tests in suite
`add_test(ut1);
...
`add_test(ut10);
endfunction
endclass

SVAUnit Test API

SVAUnit Flow
Instantiate test in Test Suite
Create an SVAUnit Test Suite
Register tests in test suite
Scan report
Simulate
Create SVAUnit Testbench
Create an SVAUnit Test
Implement test() task

Error reporting
Name of SVAUnit
check
Custom error
message
Name of SVA under
test
SVAUnit test path

Hierarchy report

Test scenarios exercised

SVAs and checks exercised

SVA test patterns

Simple implication test
• a and b |=> c
repeat (test_loop_count) begin
randomize(stimuli_for_a, stimuli_for_b, stimuli_for_c);
interface.a <= stimuli_for_a;
interface.b <= stimuli_for_b;
@(posedge an_vif.clk);
interface.c <= stimuli_for_c;
@(posedge interface.clk);
if (stimuli_for_a == 1 && stimuli_for_b == 1)
if (stimuli_for_c == 1)
vpiw.fail_if_sva_not_succeeded("IMPLICATION_ASSERT",
else
vpiw.fail_if_sva_succeeded("IMPLICATION_ASSERT",
else
vpiw.pass_if_sva_not_started("IMPLICATION_ASSERT",
"The assertion should not have started!");
end

Multi-thread
antecedent/consequent
• $rose(a) ##[1:4] b |-> ##[1:3] c
// Generate valid delays for asserting b and c signals
randomize(delay_for_b inside {[1:4]}, delay_for_c inside {[1:3]});
interface.a <= 1;
repeat (delay_for_b)
interface.b <= 1;
vpiw.pass_if_sva_started_but_not_finished("MULTITHREAD_ASSERT",
"The assertion should have started but not finished!");
repeat (delay_for_c)
interface.c <= 1;
vpiw.pass_if_sva_succeeded("MULTITHREAD_ASSERT",
end

Multi-thread
antecedent/consequent (contd.)
• $rose(a) ##[1:4] b |-> ##[1:3] c
// Generate invalid delays for asserting b and c signals
randomize(delay_for_b inside {[0:10]}, delay_for_c inside {0,[4:10]});
interface.a <= 1;
repeat (delay_for_b)
interface.b <= 1;
vpiw.pass_if_sva_not_succeeded("MULTITHREAD_ASSERT",
repeat (delay_for_c)
interface.c <= 1;
if (delay_for_b < 5)
vpiw.fail_if_sva_succeeded("MULTITHREAD_ASSERT",
end

Consecutive repetition
• a |-> b[*1:2] ##1 c
randomize(stimuli_for_a, stimuli_for_c, number_of_b_cycles <= 2);
repeat (number_of_b_cycles) begin
randomize(stimuli_for_b)
if (stimuli_for_b == 1) number_of_b_assertions += 1;
end
if (stimuli_for_a == 1 && number_of_b_assertions == number_of_b_cycles &&
number_of_b_assertions > 0)
vpiw.pass_if_sva_started_but_not_finished("IMPLICATION_ASSERT",
"The assertion should have started but not finished!");
... // (continued on the next slide)

Consecutive repetition
(contd.)
• a |-> b[*1:2] ##1 c
...
// (continued from previous slide)
if (stimuli_for_a == 1)
if (number_of_b_assertions != number_of_b_cycles ||
number_of_b_assertions == 0 ||
stimuli_for_c == 0)
vpiw.fail_if_sva_succeeded("IMPLICATION_ASSERT",
else
vpiw.fail_if_sva_not_succeeded("IMPLICATION_ASSERT",
end // end of test repeat loop

Repetition range with zero
• a |-> b[*0:2] ##1 c

Repetition range with zero
(contd.)
• a |-> b[*0:2] ##1 c

Sequence disjunction
• a |=> (b ##1 c) or (d ##1 e)
randomize(stimuli_for_a, stimuli_for_b, stimuli_for_c, stimuli_for_d, stimuli_for_e);
fork
begin
end
begin
end
join
end
Stimuli for branch: (b ##1 c)
SVA state check based on branch stimuli
Stimuli for branch: (c ##1 d)
SVA state check based on branch stimuli

(contd.)
• a |=> (b ##1 c) or (d ##1 e)
...
// Stimuli for branch (b ##1 c)
fork
begin
// SVA state check based on branch stimuli
sva_check_phase(interface.a, interface.b, interface.c);
end
join

(contd.)
• a |=> (b ##1 c) or (d ##1 e)
...
// Stimuli for branch (d ##1 e)
fork
begin
interface.b <= stimuli_for_d;
interface.c <= stimuli_for_e;
// SVA state check based on branch stimuli
sva_check_phase(interface.a, interface.d, interface.e);
end
join

(contd.)
• a |=> (b ##1 c) or (d ##1 e)
// SVA state checking task used in each fork branch
task sva_check_phase(bit stimuli_a, bit stimuli_b, bit stimuli_c);
if (stimuli_a)
if (stimuli_b && stimuli_c)
vpiw.pass_if_sva_succeeded("DISJUNCTION_ASSERT",
"The assertion should have succeeded");
else
vpiw.fail_if_sva_succeeded("DISJUNCTION_ASSERT",
"The assertion should have failed");
endtask

Tools integration
Simulator independent!

Availability
• SVAUnit is an open-source package released by
AMIQ Consulting
• We provide:
- SystemVerilog and simulator integration codes
- AMBA-APB assertion package
- Code templates and examples
- HTML documentation for API
https://github.com/amiq-consulting/svaunit

Conclusions
• SVAUnit decouples the checking logic from SVA
definition code
• Safety net for eventual code refactoring
• Can also be used as self-checking documentation on
how SVAs work
• Quick learning curve
• Easy-to-use and flexible API
• Speed up verification closure
• Boost verification quality

Q & A
?

Thank you!

SystemVerilog Assertions verification with SVAUnit - DVCon US 2016 Tutorial

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