Vhdl identifiers,data types

VLSI Design
Asst.Prof.Ms M B Mulik

VHDL IDENTIFIERS
Identifier (naming) rules:
•Can consist of alphabet characters, numbers, and underscore.
•First character must be a letter (alphabet)
•Last character cannot be an underscore
•Consecutive underscores are not allowed
•Upper and lower case are equivalent (case insensitive)
•VHDL keywords cannot be used as identifiers
e.g- Valid identifiers- x10,x_10,my_gate1
Invalid identifies- _x10, mygate@input

Literals
• A literal is a written value of a type. They are in total five different kinds of
literals.
1) Numerical literals-
Universal literal- Do not include a point
Universal real- Include a point
Physical type- include a point and unit
All numerical literals may include :-
- ‘_’ to increase readability, e.g:- 1_100
- ‘E’ or ‘e’ to include the exponent, e.g:- 5E3(i.e.5000)
- ‘#’ to describe a base
A physical type must include a space between it’s value and it’s unit, e.g:- 1ns

Literals
2) Enumeration literals
[e.g. BIT,BOOLEAN,CHARACTER]
Enumeration literals are graphical characters or identifiers
e.g:- reset ,start, ‘a’, ‘A’
3) String Literals
[e.g. STRING]
String literals are one dimensional arrays including character literals. They always begin and
end with a “ (the “ character may be included in the literal, but must then be doubled, e.g. “A”
“character”)
4) Bit string literals:-
[e.g. BIT_VETCTOR], STD_LOGIC_VECTOR]
Bit string literals are one dimensional arrays including extended digits. They always begin
and end with a “. It is possible to include a base for a bit string literals. There are three bases:-
B - Binary (Possible values:0-1)
O – Octal (Possible values:0-7) Each value is replaced by three values (0 or 1)
X – Hexadecimal (Possible values:0-9, A-F, a-f) Each value is replaced by Four values (0 or
1)
5) The Null literlas
[NULL]- it is only used for access types i.e. pointers and imply that the pointer is empty, i.e.
not pointing anywhere

Operators
- VHDL supports different classes of operators on signals, variables and
constants.
1) Logical operators -
and , or, nand, nor, xor ,xnor. They are used to define Boolean logic
expression or to perform bit-per-bit operations on arrays of bits.
2) Relational operators –
= Equality
| = Inequality
< Smaller than
<= Smaller than or equal
> Greater than
>= Greater than or equal
The relational operators test the relative values of two scalar types and give us
result a Boolean output of ‘TRUE’ or ‘FALSE’

Operators
3) Shift operators-
These operators perform a bit-wise shift or rotate operation on a one-
dimensional array of elements of the type bit (or std_logic) or boolean.
-sll –shift left logical (fill right vacant bits with the 0)
-srl – shift right logical (fill left vacant bits with the 0)
-sla – shift left arithmetic (fill right vacant bits with rightmost bit)
-sra – shift right arithmetic (fill left vacant bits with leftmost bit)
-rol – rotate left (circular)
-ror – rotate right (circular)
4) Addition operators-
The addition operators are used to perform arithmetic operation (addition
and subtraction) on operands of any numeric type. The concatenation (&)
operator is used to concatenate two vectors together to make a longer one.
+ addition
- substraction
& concatenation

Operators
5) Unary operators
Unary operators ‘+’ & ‘-’ are used to specify the sign of a numeric type.
+ identity
- Negation
6) Multiplying operators
The multiplying operators are used to perform mathematical functions on numeric
types (integer or floating input)
* Multiplication
/ Division
mod Modulus
rem Remainder
7) Miscellaneous operators
These are the absolute value and exponentiation operators that can be applied to
numeric types. The logical negation (not) results in the inverse polarity but the
same type.
** Exponentiation
abs absolute value
not logical negation

Data Types
• Each data object has a type associated with it. The type defines the set of
values that the object can have and the set of operations that are allowed on
it. The notation of types is key to VHDL since it is a strongly typed
language that requires each object to be of a certain type. In general one is
not allowed to assign a value of one type to an object another data type.
There four classes of data types: scalar, composite, access and file types.
- Data types defined in the standard package-
To use this package one has to include the following clause-
Library std.work;
use std.standard.all;
Type defined in the package standard of the std library- bit,
bit_vector_boolean, character, file_open_kind*, file_open_status*, integer,
natual, positive, real*.
-User defined types
1) Integer types
e.g type small_int is range 0 to 1024;

Data Types
2) Floating types
-Point types
type cmos_level is range 0.0 to 3.3;
-Physical types
type conductance is range 0 to 2E_9 units
mho;
mmho = 1E_3 mho;
umho = 1E_6 mho;
nmho = 1E_9 mho;
pmho = 1E_12 mho;
end units conductance;
3) Enumerated types
type type_name is (identifier list or character literal)
e.g. type my_3values is (‘0’ ,‘1’ ,‘Z’);
guest

Data Types
4) composite types
- Array type
type array_name is array(indexing scheme) of element_type;
e.g. type my_word is array(15vdownto 0) of std_logic;
-Record type
type name is record
identifier: subtype_indication;
:
:
identifier: subtype_indication;
end record;

IEEE_1164 specified 9 valued logic system used in VHDL
coding
- The IEEE_1164 standard defines a package design unit that contains
declarations that supports a uniform representation of a logic value in a
VHDL h/w description.
- It was sponsored by the design Automation Standards Committee of the
Institute of Electrical and

Vhdl identifiers,data types

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