2. Control unit generates timing and control signals for the
operations of the computer.
(groups of bits that select the paths in multiplexers, decoders, and
arithmetic logic units)
It’s the part of the CPU that initiates sequences of
microoperations.
It tells the computer’s memory, arithmetic & logic unit and
input/output devices how to respond to a program’s
instructions.
CONTROL UNIT
3. METHODS TO IMPLEMENT
CONTROL UNIT
HARDWIRED CONTROL UNIT
uses fixes instructions,
combinational logic
units of AND/OR (logic
gates), encoders,
decoders, etc.
MICROPROGRAMMED CONTROL
UNIT
the logic of the control unit
is specified by
microprograms (consists of
a sequence of instructions
that specify
microoperations)
5. IMPORTANT
TERMS
CONTROL WORD
• The control variables at any
time are represented by 1’s and
0’s, known as Control Word.
• Control words can be
programmed to perform various
operations.
L
ns
6. IMPORTANT
TERMS
CONTROL WORD
• The control variables at any
time are represented by 1’s and
0’s, known as Control Word.
• Control words can be
programmed to perform various
operations.
MICROPROGRAMMED
CONTROL UNIT
• A control unit whose binary control
variables are stored in the memory is
called MICROPROGRAMMED CONTROL
UNIT.
ns
7. IMPORTANT
TERMS
CONTROL WORD
• The control variables at any
time are represented by 1’s and
0’s, known as Control Word.
• Control words can be
programmed to perform various
operations.
MICROPROGRAMMED
CONTROL UNIT
• A control unit whose binary control
variables are stored in the memory is
called MICROPROGRAMMED CONTROL
UNIT.
MICROINSTRUCTIONS
• Each word in the control memory
contains microinstructions.
• It specifies one or more microoperations
for the system.
8. IMPORTANT
TERMS
CONTROL WORD
• The control variables at any
time are represented by 1’s and
0’s, known as Control Word.
• Control words can be
programmed to perform various
operations.
MICROPROGRAMMED
CONTROL UNIT
• A control unit whose binary control
variables are stored in the memory is
called MICROPROGRAMMED CONTROL
UNIT.
MICROINSTRUCTIONS
• Each word in the control memory
contains microinstructions.
• It specifies one or more microoperations
for the system.
MICROPROGRAM
• Sequence of microinstructions
constitutes a microprogram.
Dynamic microprogramming : Control Memory =>RAM
• RAM can be used for writing (to change a
writable control memory)
• Microprogram is loaded initially from an
auxiliary memory such as a magnetic disk
• Control words in ROM are made permanent
during the hardware production.
Static microprogramming : Control Memory =>ROM
10. 1. Incrementing the control register 2. Loading an address from control memory to
CAR. 3. Loading an initial address
Sequencer
• Determine the address sequence that is read from control
memory.
• Next address of the next microinstruction can be specified several
way depending on the sequencer input.
1. Incrementing the control register
2. Loading an address from control memory to CAR.
3. Loading an initial address
Functions:
12. Control memory
(ROM)
• A memory is part of a control unit :
• Computer Memory (employs a microprogrammed control unit)
• Main Memory : for storing user program (Machine instruction/data)
• Control Memory : for storing microprogram (Microinstruction)
13. 1. Incrementing the control register 2. Loading an address from control memory to
CAR. 3. Loading an initial address
Control data register
• Hold the present microinstruction while the next address is
computed & read from control memory.
• Allows the execution of the microoperations specified by the
control word simultaneously with the generation of the next
microinstruction. This requires two phase clock, with one clock
applied to add. Register and other to data register.
16. CONTROL
ADDRESS
REGISTER
CAR Receive The Address
from 4 Different Paths
Incrementer
Branch address from
control memory
Mapping Logic
SBR : Subroutine Register
18. CONDITIONAL
BRANCHING
If Condition is true,
then Branch (address from the next address field of the
current microinstruction)
else
Fall through
Conditions to test: O(overflow), N(negative), Z(zero),
C(carry) etc.
Fixing the value of one status bit at the input of the multiplexer
to 1.
UNCONDITIONAL BRANCH
19. MAPPING OF
INSTRUCTION
4 bit opcode = specify up to 16 distinct
instruction
Mapping from the OP-code of an
instruction to the address of the
Microinstruction which is the
starting microinstruction of its
execution microprogram
0 1 0 1 1 0 0
1 0 1 1 Address
0 x x x x 0 0
OP-code
Machine
Instruction
Mapping bits
Microinstruction
address
Mapping process : converts the 4-bit opcode
to a 7-bit control memory address
1) Place a “0” in the most significant bit of the
address.
2) Transfer 4-bit Operation code bits
3) Clear the two least significant bits of the CAR
20. DIRECT MAPPING
ADD Routine
AND Routine
LDA Routine
STA Routine
BUN Routine
Control
Storage
Address
0000
0001
0010
0011
0100
0000
0001
0010
0011
0100
ADD
AND
LDA
STA
BUN
OP-codes of
Instructions
.
.
.
Mapping Function :
Implemented by Mapping ROM or PLD.
A PLD is similar to ROM except that it uses AND and OR gates with
internal electronic fuses.
The interconnection between AND, OR and outputs can be
programmed as in ROM
21. MICROPROGRAM
EXAMPLE
COMPUTER CONFIGURATION
Two memory units:
Main memory, control memory.
CONTROL MEMORY :
• 4 registers are associated with
processor unit (PC,AR,DR,AC)
• 2 registers are associated with the
control unit (CAR,SBR)
25. SYMBOLIC
MICRO-
INSTRUCTIONS
Each line of the assembly language
microprogram defines a symbolic
microinstruction.
Each symbolic microinstruction is divided
into five fields:
Labels
• The label field may be
empty or it may specify
a symbolic address.
• A label is terminated
with a colon (:).
26. SYMBOLIC
MICRO-
INSTRUCTIONS
Labels
Each line of the assembly language
microprogram defines a symbolic
microinstruction.
Each symbolic microinstruction is divided
into five fields:
Micro-ops • Consists of one, two or
three symbols separated
by comas
27. SYMBOLIC
MICRO-
INSTRUCTIONS
Labels
Each line of the assembly language
microprogram defines a symbolic
microinstruction.
Each symbolic microinstruction is divided
into five fields:
Micro-ops
• Consists of one of the letters
U, I, S, Z
Where U: Unconditional Branch
I : Indirect address bit
S: Sign of AC
Z: Zero value in AC
CD
28. SYMBOLIC
MICRO-
INSTRUCTIONS
Labels
Each line of the assembly language
microprogram defines a symbolic
microinstruction.
Each symbolic microinstruction is divided
into five fields:
Micro-ops
CD
BR • One of JMP, CALL, RET, MAP
29. Micro-ops
SYMBOLIC
MICRO-
INSTRUCTIONS
Labels
Each line of the assembly language
microprogram defines a symbolic
microinstruction.
Each symbolic microinstruction is divided
into five fields:
CD
BR
• One of Symbolic address,
NEXT,
empty
AD
30. The Fetch Routine
During FETCH, read an instruction from memory and decode the instruction and
update PC.
Microinstructions needed for the fetch routine:
AR <- PC
DR <-M[AR], PC <- PC + 1
AR <- DR(0-10), CAR(2-5) <- DR(l l-14), CAR(0, 1,6) <-0
Symbolic Microprogram for fetch routine:
ORG 64
PCTAR U JMP NEXT
READ,INCPC U JMP NEXT
DRTAR U MAP
Binary Equivalents
Translated by an
Assembler
34. DESIGN OF
CONTROL UNIT
The bits of microinstruction are
usually divided into fields, with each
field defining a distinct, separate
function.
The various fields available in the
instruction format provide control
bits to initiate the microoperation.
Decoding of Microinstruction Fields :
• F1, F2, and F3 of Microinstruction are decoded with a 3
x 8 decoder
• Output of decoder must be connected to the proper
circuit to initiate the corresponding microoperation
35. F1 = 101 (5) : DRTAR (The next clock pulse transition transfer the content
of DR(0 -10) to AR)
F1 = 110 (6) : PCTAR
• Output 5 and 6 of decoder F1 are connected to the load input of AR (two input of
OR gate)
• Multiplexer select the data from DR when output 5 is active
• Multiplexer select the data from AC when output 5 is inactive
Arithmetic Logic Shift Unit:
Instead of using the gates to generate the control signal marked by
AND, ADD, and DR Control signal will be now come from the output
of the decoders associated with the AND, ADD, and DRTAC
respectively.
36. PROGRAM
SEQUENCER
Microprogram sequencer select the
next address for control memory
MUX 1 :
Selects an address from one of the four sources
and route to CAR
CAR + 1
JMP/CALL
Mapping
Subroutine Return
MUX 2:
• Test a status bit and the result of the test is
applied to an input logic circuit
• One of 4 Status bit is selected by Condition bit
(CD)
37. Input Logic
» Select one of the source address (S0 , S1) for CAR
» Enable the load input(L) in SBR
Input Logic Truth Table:
Input :
> I0 , I 1 from Branch bit (BR )
> T from MUX 2 ( T)
Output :
>MUX 1 Select signal ( S 0 , S 1 )
S1 = I 1 I0 ’ + I 1 I0
= I 1 (I0 ’ + I0)
= I 1
S0 = I 1 ’ I0’T + I 1 ’ I0 T + I 1 I0
= I 1’T (I0 ’ + I0 ) + I 1 I0
= I 1 ’T + I 1 I0
>SBR Load signal ( L)
L = I 1’ I0 T
BR
FIELD Input MUX 1
Load
SBR
I1 I0 T S1 S0 L
0 0 0 0 0 0 0 0
0 0 0 0 1 0 1 0
0 1 0 1 0 0 0 0
0 1 0 1 1 0 1 1
1 0 1 0 X 1 0 0
1 1 1 1 X 1 1 0
CALL
![The Fetch Routine
During FETCH, read an instruction from memory and decode the instruction and
update PC.
Microinstructions needed for the fetch routine:
AR <- PC
DR <-M[AR], PC <- PC + 1
AR <- DR(0-10), CAR(2-5) <- DR(l l-14), CAR(0, 1,6) <-0
Symbolic Microprogram for fetch routine:
ORG 64
PCTAR U JMP NEXT
READ,INCPC U JMP NEXT
DRTAR U MAP
Binary Equivalents
Translated by an
Assembler](https://image.slidesharecdn.com/whitepaperproposalpresentation-250406141450-89daeb3a/85/Whitepaper-proposal-presentation-_pre-pptx-30-320.jpg)
