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Nico Weber6d46ebe2019-08-01 14:36:381//===-- checksum.cpp --------------------------------------------*- C++ -*-===//
Kostya Kortchinsky1f066a72019-03-12 14:46:312//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "checksum.h"
10#include "atomic_helpers.h"
11
12#if defined(__x86_64__) || defined(__i386__)
13#include <cpuid.h>
14#elif defined(__arm__) || defined(__aarch64__)
15#if SCUDO_FUCHSIA
16#include <zircon/features.h>
17#include <zircon/syscalls.h>
18#else
19#include <sys/auxv.h>
20#endif
21#endif
22
23namespace scudo {
24
Kostya Kortchinsky6a856312019-05-08 21:54:0225Checksum HashAlgorithm = {Checksum::BSD};
Kostya Kortchinsky1f066a72019-03-12 14:46:3126
27#if defined(__x86_64__) || defined(__i386__)
28// i386 and x86_64 specific code to detect CRC32 hardware support via CPUID.
29// CRC32 requires the SSE 4.2 instruction set.
30#ifndef bit_SSE4_2
31#define bit_SSE4_2 bit_SSE42 // clang and gcc have different defines.
32#endif
33
Kostya Kortchinsky9959eb92020-05-11 16:16:5434#ifndef signature_HYGON_ebx // They are not defined in gcc.
35// HYGON: "HygonGenuine".
36#define signature_HYGON_ebx 0x6f677948
37#define signature_HYGON_edx 0x6e65476e
38#define signature_HYGON_ecx 0x656e6975
39#endif
40
Kostya Kortchinsky1f066a72019-03-12 14:46:3141bool hasHardwareCRC32() {
42 u32 Eax, Ebx = 0, Ecx = 0, Edx = 0;
43 __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx);
44 const bool IsIntel = (Ebx == signature_INTEL_ebx) &&
45 (Edx == signature_INTEL_edx) &&
46 (Ecx == signature_INTEL_ecx);
47 const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) &&
48 (Ecx == signature_AMD_ecx);
Kostya Kortchinsky9959eb92020-05-11 16:16:5449 const bool IsHygon = (Ebx == signature_HYGON_ebx) &&
50 (Edx == signature_HYGON_edx) &&
51 (Ecx == signature_HYGON_ecx);
52 if (!IsIntel && !IsAMD && !IsHygon)
Kostya Kortchinsky1f066a72019-03-12 14:46:3153 return false;
54 __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
55 return !!(Ecx & bit_SSE4_2);
56}
Kostya Kortchinsky1f066a72019-03-12 14:46:3157#elif defined(__arm__) || defined(__aarch64__)
58#ifndef AT_HWCAP
59#define AT_HWCAP 16
60#endif
61#ifndef HWCAP_CRC32
62#define HWCAP_CRC32 (1U << 7) // HWCAP_CRC32 is missing on older platforms.
63#endif
64
65bool hasHardwareCRC32() {
66#if SCUDO_FUCHSIA
67 u32 HWCap;
68 const zx_status_t Status =
69 zx_system_get_features(ZX_FEATURE_KIND_CPU, &HWCap);
70 if (Status != ZX_OK)
71 return false;
72 return !!(HWCap & ZX_ARM64_FEATURE_ISA_CRC32);
73#else
74 return !!(getauxval(AT_HWCAP) & HWCAP_CRC32);
75#endif // SCUDO_FUCHSIA
76}
Kostya Kortchinskyb36b1632019-12-09 21:06:3477#else
78// No hardware CRC32 implemented in Scudo for other architectures.
79bool hasHardwareCRC32() { return false; }
Kostya Kortchinsky1f066a72019-03-12 14:46:3180#endif // defined(__x86_64__) || defined(__i386__)
81
82} // namespace scudo