A-PDF Merger DEMO : Purchase from www.A-PDF.com to remove the watermark Roll No. ...................... Total No.

of Questions : 13]

[Total No. of Pages : 02

Paper ID [A0210]
(Please fill this Paper ID in OMR Sheet)

BCA (205) (S05) (O) (Sem. - 2nd) DIGITAL CIRCUITS AND LOGIC DESIGN

Time : 03 Hours Instruction to Candidates: 1) Section - A is Compulsory. 2) Attempt any Nine questions from Section - B. Section - A

Maximum Marks : 75

Q1)

a) b) c) d) e) f) g)

(15 2 = 30) Convert (i) 11011.11(binary number )to decimal number. (ii) 7825.6875 decimal number to octal. Convert (i) 125.89 binary number to BCD number. (ii) A4F to Octal number. Simplify

(a + b ) + (a + b ) Prove using truth table

A + AB = A + B Draw the logic diagram & truth table of Full adder. Define the term propagation Delay. Simply the following logic function using k-map and find the minterms & maxterms. F(X,Y,Z) = X Z + XYZ + YZ h) Write the truth table of 3:8 Decoder. i) State & prove the De-Margin theorems. j) What do you mean by race around condition? k) Explain the term LOCKOUT with the help of a suitable example? l) What is the difference between Latch and a Flip-Flop? m) What is a shift register? What are the various configurations of shift register? n) Differentiate between synchronous & asynchronous logical circuits. o) Explain the operation of master-Slave Flip-flop?
P.T.O.

D-434

(9 5 = 45) Q2) What do you mean by error detecting and correcting codes? Explain both with the help of suitable examples. Q3) Obtain the truth table of the following & implement it by using NAND Gates?

Section - B

F(A, B, C) = (A B + B C) A C + B C

Q4) Minimize the following Using K-Map and Realize it with NAND Gates? F(A,B,C, D) = m(2,3,4,5,13 ,15)+ d(8,9,10,11) Q5) Implement BCD to Excess-3 Code converter? Q6) Explain the following terms with help of suitable examples: (a) HAZARDS. (b) RACES. Q7) Implement following using 4X16 Decoder. F=XY+Z Q8) What do you mean by Multiplexer. Draw the block diagram and logical diagram of 4:1 Multiplexer. Q9) Design a synchronous counter using JK flip-flop for the following sequence? 000,101,110,111,011,010,000 Q10)Explain the term universal shift register. Q11)Classify the counters and Discuss the BCD Counters. Also explain Ring counters. Q12)Explain the various rules of k-map reduction technique. Q13)Give any five differences between combinational & sequential logical circuits.

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D-434 2

Roll No. ...................... Total No. of Questions : 13]

[Total No. of Pages : 02

Paper ID [A0210]
(Please fill this Paper ID in OMR Sheet)

BCA (205) (S05) (O) (Sem. - 2nd ) DIGITAL CIRCUITS & LOGIC DESIGN
Time : 03 Hours Instruction to Candidates: 1) 2) Q1) a) b) c) d) e) f) g) h) i) j) k) l) (i) 3FFE (ii) 2180 Section - A is Compulsory. Attempt any Nine questions from Section - B. Section - A (15 2 = 30) Convert the following hexadecimal numbers into decimal (10101) convert to Decimal Number system. What do you understand from propagation delay time? What is the use of karnaugh maps? What is the use of gray codes for number representation? Differentiate between combinational and sequential circuits. Give the advantages of edge triggered flip-flops. What is a race around condition? Explain NOR gate with truth table. Write the working of 4: 1 multiplexer. What is Encoder? Give advantages and disadvantages of synchronous over asynchronous counters. Give four possible modes of operation for registers. What is a ring counter? Maximum Marks : 75

m) Give applications of shift registers. n) o)

A-67

P.T.O.

Section - B (9 5 = 45) Q2) Draw the minimized logic circuit for the Boolean equation Y=ABCD+ABCD+ABCD+ABCD. Q3) How are AND, OR and NOT operations realized with NAND gates? Q4) Convert decimal no. 100.55 into binary, octal codes. Q5) State and discuss the De-Morgans Theorems. Q6) Draw the circuit of a 3 to 8 decoder and explain its operation. Q7) Explain code converters with example. Q8) Draw and explain full adder using two multiplexers. Q9) Discuss the working of JK master slave flip-flop. Q10) Write short note on error detecting and correcting codes. Q11) Discuss the working of synchronous counter. Q12) Explain working of asynchronous counter. Q13) Draw and explain 4 bit bi-directional shift registers.

A-67

Roll No. ...................... Total No. of Questions : 13]

Paper ID [A0210]
(Please fill this Paper ID in OMR Sheet)

[Total No. of Pages : 02

BCA-205 (OLD/S05) (Sem. - 2nd) DIGITAL CIRCUITS & LOGIC DESIGN Time : 03 Hours Instruction to Candidates: 1) Section - A is Compulsory. 2) Attempt any Nine questions from Section - B. Section - A (15 2 = 30) Q1) a) b) c) d) e) f) g) h) i) j) k) l) n) o) Convert 40 from decimal to octal number. Convert DF from hex to decimal number. What are Minterms and Maxterms? What is a combinational circuit? What is a half-adder? What is a flip-flop? What is an asynchronous input? What is a shift register? Subtract 101 from 1011 using 2s complement. Subtract 1101 from 1111 using 1s complement. What is an error correcting code? What is an encoder? What is a T flip-flop? What is positive logic?
P.T.O.

Maximum Marks : 75

m) What are universal gate?

J-8799[S-9700796]

Section - B Q2) Enumerate the features of Hamming code. Q3) Explain SOP and POS functions with examples.

(9 5 =45)

Q4) Using De- Morgans Laws, convert the NAND function Y =(AB) into NOR function. Q5) Explain the essential features of the Karnaugh map. What are their advantages and disadvantages? Q6) Discuss the features of the Quine-McCluskey method. Q7) What is a multiplexer? Construct a 64-to-1 multiplexer using 4*1 MUX. Q8) Draw an S-R flip-flop using NOR gates and develop its truth table. Q9) Compare between synchronous and asynchronous counters. Q10)What is the race-around problem, and how is it rectified? Q11)Discuss the various types of shift registers and their applications. Q12)Discuss the Master Slave J-K flip flop with the help of suitable block diagram. Q13)What is an updown counter? Design an updown counter which counts from 0 to 9.

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J-8799[S-9700796]