ECE 128 – VerilogA Lab: Creating & simulating an 8-bit A-D Converter (ADC)

Adapted for GWU by: Thomas Farmer

Objectives:
• To create a sample 8-bit ADC in VerilogA for use with 8-bit CPU Project
• Familiarize student with Cadence VerilogA code generator known as the ModelWriter
• Simulate an 8-bit ADC using Spectre

Assumptions:
• Student has working knowledge of A/D converter
• Student understand verilog-A

Note:
• This tutorial was created using Cadence 5.41, but it has been tested and works properly
in Cadence 6.1. There are some basic menu differences, but if a student is familiar with
Cadence 6.1, this should be no problem for the student.

SECTION I: Creating the ADC

1. Log into a Sun Workstation.

2. Start Cadence by typing these commands:

$ cd cadence
$ virtuoso &

3. Create a new library entitled: ece128_lab_8 (Attach to .6 AMI)

4. Create a new “verilogA” cell entitled: adc_8bit
5. When the editor opens, delete the existing lines of text and copy & paste this code for an 8-bit
ADC converter below:

// FUNCTION: Analog to Digital Converter

// VERSION: $Revision: 2.12 $
// AUTHOR: Cadence Design Systems, Inc.
//
// GENERATED BY: Cadence Modelwriter 2.31
// ON: Fri Mar 07 09:37:38 EST 2008
//
// Description: Ideal Analog to Digital Converter
// Generates an N bit ADC.
// - selectable logic output levels
// - model valid for negative values of vmin
// - adjustable conversion time, and rise/fall time
// This model is an example, provided "as is" without express or
// implied warranty and with no claim as to its suitability for
// any purpose.
//
// PARAMETERS:
// slack = The smallest time interval considered negligible for
// cross event on clock [S]
// tconv = Delay from threshold crossing to output change [S]
// trise = Rise time for digital output signals [S]
// trise = Rise time for digital output signals [S]
// vmax = ADC Full scale output voltage [V]
// vmin = ADC Zero scale output voltage [V]
// vone = The voltage of a logical 1 on digital outputs [V]
// vth = Threshold value of clock signal [V]
// vzero = The voltage of a logical 0 on digital outputs [V]
//

`include "discipline.h"
`include "constants.h"
`define NUM_ADC_BITS 8

module adc_8bit (vin, clk, data);

input vin, clk;
electrical vin, clk;

output [`NUM_ADC_BITS-1:0] data;

electrical [`NUM_ADC_BITS-1:0] data;

parameter real vmax = 5;

parameter real vmin = 0;
parameter real one = 5.0;
parameter real zero = 0.0;
parameter real vth = 2.5;
parameter real slack = 0.5p from (0:inf);
parameter real trise = 1.0p from (0:inf);
parameter real tfall = 1.0p from (0:inf);
parameter real tconv = 0.5p from [0:inf);
parameter integer traceflag = 1;

real sample, vref, lsb, voffset;

real vd[0:`NUM_ADC_BITS-1];
integer ii, binvalue;

analog begin
@(initial_step or initial_step("dc", "ac", "tran", "xf")) begin
vref = (vmax - vmin) / 2.0;
lsb = (vmax - vmin) / (1 << `NUM_ADC_BITS) ;
voffset = vmin;

if (traceflag)
$display("%M ADC range ( %g v ) / %d bits = lsb %g volts.\n",
vmax - vmin, `NUM_ADC_BITS, lsb );

generate i ( `NUM_ADC_BITS-1, 0) begin

vd[i] = 0 ;
end
end
 @(cross ( V(clk)-vth, 1, slack, clk.potential.abstol)) begin
binvalue = 0;
sample = V(vin) - voffset;
for ( ii = `NUM_ADC_BITS -1 ; ii>=0 ; ii = ii -1 ) begin
vd[ii] = 0;
if (sample > vref ) begin
vd[ii] = one;
sample = sample - vref;
binvalue = binvalue + ( 1 << ii );
end
else begin
vd[ii] = zero;
end
sample = sample * 2.0;
end
if (traceflag)
$strobe("%M at %g sec. digital out: %d vin: %g (d2a: %g)\n",
$abstime, binvalue, V(vin), (binvalue*lsb)+voffset);
end

generate i ( `NUM_ADC_BITS-1, 0) begin

V(data[i]) <+ transition ( vd[i] , tconv, trise, tfall );
end
end
endmodule

`undef NUM_ADC_BITS

6. After the above code has been entered, save and close the editor window. Cadence will
syntax check the verilogA code that has been entered. Fix any errors that may have
occurred due to syntax. Note: Any time a change is made, cadence will automatically syntax
check the code.

7. You will be prompted to create a symbol for this device, answer yes and save the symbol.
SECTION II: The Cadence VerilogA code generator: ModelWriter

The code for the 8-bit ADC above was generated automatically by using the Cadence Model
Writer. This is a feature that can normally be accessed by creating a new cell using the
“ModelWriter” Tool as show here.

At the time of this tutorials authoring, GWU had the model writer installed (it is part of the base
cadence package) but did not have a license to support this feature. However, the student is
encouraged to look at the Model Writer Guide, under the ECE 128 references page.

The Model Writer can generate veriloga code for many common analog parts, and it is a good
idea for students to familiarize themselves with the parts is can create. The model writer’s main
menu show the choices:

For this example, an ADC was chosen from the above list, and all the user is required to do is set
the # of bits to use and various other threshold parameters, then cadence generates the verilogA
code automatically to fulfill the user’s requirements. This very powerful feature will be activated in
the near future at GWU.
SECTION III: Creating the ADC Test Bench

Creating the test bench shown below has 2 or 3 tricky steps, please read through this section
before simply implementing the schematic.

1. Create a new cell entitled: adc_8bit_tb

2. Begin creating the following schematic,
DO NOT jump ahead and add the wire names or output pins as of yet:

CLK Pulse Settings Piece Wise Linear Function Source Settings

Source Type vpulse Source Type vpwl
Voltage 1 0 V Number of Pairs of Points 2
Voltage 2 5 V Time 1 0 s
Delay 0 s Voltage 1 0 V
Rise Time 50n s Time 2 100m s
Fall Time 50n s Voltage 2 5 V
Pulse Width 500u s
Period 1m s

3. Creating the BUS style Output Pins:

Bring up the “add pin” dialog box: type in the name: data<7:0>

Turn ON Bus expansion

Change Placement to X multiple
Make sure Direction is set to Output

Click on the schematic window to place the first pin, then click again to place the last 7 pins.
Be sure to give yourself a lot of room from the ADC to route wires
4. Creating the BUS wires
a. From the menu, choose: Add->Wire (WIDE)
b. From the output pin of the ADC, draw a wire extending to the right
BUT, do not connect it to output pin 7, make this wire VERY long (see step 6d as to
why this is necessary)

c. Now use the NARROW wire to connect from the bus to output pin data<7>

d. Repeat this NARROW wire procedure for each output pin, but make sure to connect
each narrow wire from the output pin, directly to the bus. DO NOT connect any
narrow wire to another narrow wire

5. Be sure to leave a lot of space on the bus for wire naming later on.
6. Naming the Bus and the wires
Note: This is a crucial step that must be done to properly separate out the bus

a. From the menu choose: Add-Wire Name, fill in the dialog box as follows:

Make sure to turn ON bus expansion

Make sure to set placement to
multiple

b. Click first on wire #7, then click each NARROW wire until the bus tapped wires are all
named:

c. Lastly, name the bus itself. Choose Add->Wire Name from the menu:

Call the bus: data<7:0>

Turn OFF bus expansion

Placement to
single

d. Place the label on the WIDE bus wire (do NOT accidentally name the narrow wire, if
you do not have space to access your WIDE bus wire with the label, delete the bus
and start from step 5):

Be sure to
label clk
and vin
wires as
well
7. Save the schematic ONLY after the wiring and labeling are complete.
8. You MUST check the CIW window to ensure there are NO errors. If there are any errors
repeat the steps above as it is very difficult to debug. Simulation will not work with errors.
SECTION IV: Simulating the ADC

1. Set the simulator to “SPECTRE”

2. Setup a transient simulation to last for 100m seconds.
3. Plot the outputs: clk, vin, and each data output pin
4. Run the simulation, and when the results are displayed, drop a vertical marker

5. With using a ramp, the output of the ADC can be checked to see if it corresponds to the
correct input voltage. Pick a few points on vin and verify that the 8-bit ADC is accurate
(determine the 8-bit binary value at this point by viewing the data pins to see if they are high
or low). Verify that the output is changing on the rising edge of the clock. To change the
ADC so the output changes on the falling edge, go to the Library Manager window and select
the veriloga cell view of the adc_8bit. Find the following line of code:

@(cross ( V(clk)-vth, 1, slack, clk.potential.abstol)) begin

6. Change the '1' to a '-1'. This argument determines whether or not the ADC will change on the
rising or falling edge of the clock. Save your file and then rerun the simulation from the
Cadence Analog Design Environment window. In the Waveform Window, verify that the
output is different from the previous simulation, with the output changing on the falling edge of
the clock. Also, verify that the digital output is consistent with the analog input.

7. HW:
a. For both cases, hand in a picture of your simulation write down the “8-bit binary”
equivalent code at 1V, 2.5V, 3V, 4.5, & 5V.
b. Also, find the fastest clock speed that this ADC can be run at (shrinking the clock
pulse, see if proper data output is still on the data line)
c. Could the speed of your ADC influence your CPU clock speed?

SECTION IV: Observations

You will notice that the expansion to output pins is not necessary. But this painstaking procedure
was put into the lab to prepare the student for wiring the ADC up to the CPU final project. In
some cases it will be necessary to separate the data bus wires.
SECTION IV: References

This tutorial was adapted from the “Analog Tutorial 5: Verilog-A” from the electrical engineering
department of Brigham Young University. Originally found at the following URL:

http://www.ee.byu.edu/help/computing/software/cadence-help/tutA5.html