TMS320F28P55x Real-Time

Microcontrollers

Technical Reference Manual

Literature Number: SPRUJ53B

APRIL 2024 – REVISED SEPTEMBER 2024
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Table of Contents

Read This First.........................................................................................................................................................................89

About This Manual................................................................................................................................................................. 89
Notational Conventions.......................................................................................................................................................... 89
Glossary................................................................................................................................................................................. 89
Related Documentation From Texas Instruments.................................................................................................................. 89
Support Resources................................................................................................................................................................ 89
Trademarks............................................................................................................................................................................ 90
1 C2000™ Microcontrollers Software Support......................................................................................................................91
1.1 Introduction...................................................................................................................................................................... 92
1.2 C2000Ware Structure.......................................................................................................................................................92
1.3 Documentation................................................................................................................................................................. 92
1.4 Devices............................................................................................................................................................................ 92
1.5 Libraries........................................................................................................................................................................... 92
1.6 Code Composer Studio™ Integrated Development Environment (IDE).......................................................................... 92
1.7 SysConfig and PinMUX Tool............................................................................................................................................ 93
2 C28x Processor.....................................................................................................................................................................94
2.1 Introduction...................................................................................................................................................................... 95
2.2 C28X Related Collateral...................................................................................................................................................95
2.3 Features........................................................................................................................................................................... 95
2.4 Floating-Point Unit (FPU)................................................................................................................................................. 96
2.5 Trigonometric Math Unit (TMU)........................................................................................................................................96
2.6 VCRC Unit........................................................................................................................................................................97
3 System Control and Interrupts............................................................................................................................................ 98
3.1 Introduction...................................................................................................................................................................... 99
3.1.1 SYSCTL Related Collateral....................................................................................................................................... 99
3.1.2 LOCK Protection on System Configuration Registers............................................................................................... 99
3.1.3 EALLOW Protection.................................................................................................................................................. 99
3.2 Power Management....................................................................................................................................................... 100
3.3 Device Identification and Configuration Registers......................................................................................................... 100
3.4 Resets............................................................................................................................................................................ 100
3.4.1 Reset Sources......................................................................................................................................................... 100
3.4.2 External Reset (XRS).............................................................................................................................................. 101
3.4.3 Simulate External Reset (SIMRESET.XRS)............................................................................................................ 101
3.4.4 Power-On Reset (POR)...........................................................................................................................................101
3.4.5 Brown-Out Reset (BOR)..........................................................................................................................................102
3.4.6 Debugger Reset (SYSRS).......................................................................................................................................102
3.4.7 Simulate CPU Reset (SIMRESET)..........................................................................................................................102
3.4.8 Watchdog Reset (WDRS)........................................................................................................................................102
3.4.9 NMI Watchdog Reset (NMIWDRS)..........................................................................................................................102
3.4.10 DCSM Safe Code Copy Reset (SCCRESET)....................................................................................................... 102
3.5 Peripheral Interrupts.......................................................................................................................................................103
3.5.1 Interrupt Concepts................................................................................................................................................... 103
3.5.2 Interrupt Architecture............................................................................................................................................... 103
3.5.3 Interrupt Entry Sequence.........................................................................................................................................105
3.5.4 Configuring and Using Interrupts.............................................................................................................................106
3.5.5 PIE Channel Mapping..............................................................................................................................................108
3.5.6 PIE Interrupt Priority................................................................................................................................................ 109
3.5.7 System Error............................................................................................................................................................ 110
3.5.8 Vector Tables............................................................................................................................................................111

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3.6 Exceptions and Non-Maskable Interrupts.......................................................................................................................117

3.6.1 Configuring and Using NMIs.................................................................................................................................... 117
3.6.2 Emulation Considerations........................................................................................................................................ 117
3.6.3 NMI Sources............................................................................................................................................................ 117
3.6.4 Illegal Instruction Trap (ITRAP)................................................................................................................................118
3.6.5 ERRORSTS Pin.......................................................................................................................................................118
3.7 Clocking..........................................................................................................................................................................118
3.7.1 Clock Sources......................................................................................................................................................... 120
3.7.2 Derived Clocks........................................................................................................................................................ 124
3.7.3 Device Clock Domains............................................................................................................................................ 124
3.7.4 XCLKOUT................................................................................................................................................................125
3.7.5 Clock Connectivity................................................................................................................................................... 125
3.7.6 Clock Source and PLL Setup.................................................................................................................................. 128
3.7.7 Using an External Crystal or Resonator.................................................................................................................. 128
3.7.8 Using an External Oscillator.................................................................................................................................... 129
3.7.9 Choosing PLL Settings............................................................................................................................................ 129
3.7.10 System Clock Setup.............................................................................................................................................. 130
3.7.11 SYS PLL Bypass....................................................................................................................................................130
3.7.12 Clock (OSCCLK) Failure Detection....................................................................................................................... 131
3.8 32-Bit CPU Timers 0/1/2................................................................................................................................................ 133
3.9 Watchdog Timer............................................................................................................................................................. 134
3.9.1 Servicing the Watchdog Timer.................................................................................................................................135
3.9.2 Minimum Window Check......................................................................................................................................... 135
3.9.3 Watchdog Reset or Watchdog Interrupt Mode.........................................................................................................136
3.9.4 Watchdog Operation in Low-Power Modes............................................................................................................. 136
3.9.5 Emulation Considerations........................................................................................................................................136
3.10 Low-Power Modes....................................................................................................................................................... 137
3.10.1 Clock-Gating Low-Power Modes........................................................................................................................... 137
3.10.2 IDLE.......................................................................................................................................................................137
3.10.3 STANDBY.............................................................................................................................................................. 138
3.10.4 HALT......................................................................................................................................................................139
3.11 Memory Controller Module........................................................................................................................................... 140
3.11.1 Functional Description........................................................................................................................................... 140
3.12 JTAG............................................................................................................................................................................ 148
3.12.1 JTAG Noise and TAP_STATUS............................................................................................................................. 148
3.13 Live Firmware Update.................................................................................................................................................. 148
3.13.1 LFU Background....................................................................................................................................................148
3.13.2 LFU Switchover Steps........................................................................................................................................... 149
3.13.3 Device Features Supporting LFU.......................................................................................................................... 149
3.13.4 LFU Switchover..................................................................................................................................................... 153
3.13.5 LFU Resources......................................................................................................................................................153
3.14 System Control Register Configuration Restrictions.................................................................................................... 153
3.15 Software....................................................................................................................................................................... 154
3.15.1 SYSCTL Registers to Driverlib Functions..............................................................................................................154
3.15.2 CPUTIMER Registers to Driverlib Functions.........................................................................................................163
3.15.3 MEMCFG Registers to Driverlib Functions............................................................................................................164
3.15.4 PIE Registers to Driverlib Functions......................................................................................................................168
3.15.5 NMI Registers to Driverlib Functions..................................................................................................................... 169
3.15.6 XINT Registers to Driverlib Functions................................................................................................................... 170
3.15.7 WWD Registers to Driverlib Functions.................................................................................................................. 171
3.15.8 SYSCTL Examples................................................................................................................................................171
3.15.9 TIMER Examples...................................................................................................................................................172
3.15.10 MEMCFG Examples............................................................................................................................................172
3.15.11 INTERRUPT Examples........................................................................................................................................173
3.15.12 LPM Examples.................................................................................................................................................... 175
3.15.13 WATCHDOG Examples.......................................................................................................................................177
3.16 SYSCTRL Registers.................................................................................................................................................... 178
3.16.1 SYSCTRL Base Address Table............................................................................................................................. 178
3.16.2 CPUTIMER_REGS Registers............................................................................................................................... 179
3.16.3 PIE_CTRL_REGS Registers................................................................................................................................. 186
3.16.4 NMI_INTRUPT_REGS Registers.......................................................................................................................... 238

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3.16.5 XINT_REGS Registers.......................................................................................................................................... 254

3.16.6 SYNC_SOC_REGS Registers.............................................................................................................................. 263
3.16.7 DMA_CLA_SRC_SEL_REGS Registers...............................................................................................................270
3.16.8 LFU_REGS Registers........................................................................................................................................... 277
3.16.9 DEV_CFG_REGS Registers................................................................................................................................. 283
3.16.10 CLK_CFG_REGS Registers................................................................................................................................341
3.16.11 CPU_SYS_REGS Registers................................................................................................................................364
3.16.12 SYS_STATUS_REGS Registers......................................................................................................................... 424
3.16.13 PERIPH_AC_REGS Registers............................................................................................................................433
3.16.14 MEM_CFG_REGS Registers.............................................................................................................................. 484
3.16.15 ACCESS_PROTECTION_REGS Registers........................................................................................................539
3.16.16 MEMORY_ERROR_REGS Registers................................................................................................................. 566
3.16.17 TEST_ERROR_REGS Registers........................................................................................................................ 590
3.16.18 UID_REGS Registers.......................................................................................................................................... 594
4 ROM Code and Peripheral Booting...................................................................................................................................603
4.1 Introduction.................................................................................................................................................................... 604
4.1.1 ROM Related Collateral...........................................................................................................................................604
4.2 Device Boot Sequence...................................................................................................................................................605
4.3 Device Boot Modes........................................................................................................................................................ 605
4.3.1 Default Boot Modes................................................................................................................................................. 605
4.3.2 Custom Boot Modes................................................................................................................................................ 606
4.4 Device Boot Configurations............................................................................................................................................606
4.4.1 Configuring Boot Mode Pins....................................................................................................................................607
4.4.2 Configuring Boot Mode Table Options.....................................................................................................................609
4.4.3 Boot Mode Example Use Cases..............................................................................................................................610
4.5 Device Boot Flow Diagrams........................................................................................................................................... 611
4.5.1 Boot Flow................................................................................................................................................................. 611
4.5.2 Emulation Boot Flow................................................................................................................................................613
4.5.3 Standalone Boot Flow ............................................................................................................................................ 614
4.6 Device Reset and Exception Handling...........................................................................................................................615
4.6.1 Reset Causes and Handling....................................................................................................................................615
4.6.2 Exceptions and Interrupts Handling.........................................................................................................................616
4.7 Boot ROM Description................................................................................................................................................... 617
4.7.1 Boot ROM Configuration Registers......................................................................................................................... 617
4.7.2 Entry Points............................................................................................................................................................. 619
4.7.3 Wait Points...............................................................................................................................................................620
4.7.4 Secure Flash Boot................................................................................................................................................... 620
4.7.5 Firmware Update (FWU) Flash Boot....................................................................................................................... 623
4.7.6 Memory Maps..........................................................................................................................................................624
4.7.7 ROM Tables.............................................................................................................................................................625
4.7.8 Boot Modes and Loaders........................................................................................................................................ 625
4.7.9 GPIO Assignments.................................................................................................................................................. 643
4.7.10 Secure ROM Function APIs.................................................................................................................................. 645
4.7.11 Clock Initializations................................................................................................................................................ 646
4.7.12 Boot Status Information......................................................................................................................................... 646
4.7.13 ROM Version......................................................................................................................................................... 648
4.8 Application Notes for Using the Bootloaders..................................................................................................................648
4.8.1 Bootloader Data Stream Structure.......................................................................................................................... 648
4.8.2 The C2000 Hex Utility..............................................................................................................................................650
4.9 Software......................................................................................................................................................................... 651
4.9.1 BOOT Examples......................................................................................................................................................651
5 Dual Code Security Module (DCSM)................................................................................................................................. 652
5.1 Introduction.................................................................................................................................................................... 653
5.1.1 DCSM Related Collateral........................................................................................................................................ 653
5.2 Functional Description....................................................................................................................................................653
5.2.1 CSM Passwords...................................................................................................................................................... 654
5.2.2 Emulation Code Security Logic (ECSL)...................................................................................................................656
5.2.3 CPU Secure Logic................................................................................................................................................... 656
5.2.4 Execute-Only Protection..........................................................................................................................................656
5.2.5 Password Lock........................................................................................................................................................ 656
5.2.6 JTAGLOCK.............................................................................................................................................................. 657

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5.2.7 Link Pointer and Zone Select.................................................................................................................................. 657

5.2.8 C Code Example to Get Zone Select Block Addr for Zone1....................................................................................660
5.3 Flash and OTP Erase/Program......................................................................................................................................660
5.4 Secure Copy Code.........................................................................................................................................................660
5.5 SecureCRC.................................................................................................................................................................... 661
5.6 CSM Impact on Other On-Chip Resources....................................................................................................................662
5.7 Incorporating Code Security in User Applications..........................................................................................................663
5.7.1 Environments That Require Security Unlocking...................................................................................................... 663
5.7.2 CSM Password Match Flow.................................................................................................................................... 663
5.7.3 C Code Example to Unsecure C28x Zone1............................................................................................................ 665
5.7.4 C Code Example to Resecure C28x Zone1............................................................................................................ 665
5.7.5 Environments That Require ECSL Unlocking..........................................................................................................665
5.7.6 ECSL Password Match Flow................................................................................................................................... 665
5.7.7 ECSL Disable Considerations for any Zone............................................................................................................ 667
5.7.8 Device Unique ID.....................................................................................................................................................667
5.8 Software......................................................................................................................................................................... 667
5.8.1 DCSM Registers to Driverlib Functions................................................................................................................... 667
5.8.2 DCSM Examples..................................................................................................................................................... 671
5.9 DCSM Registers............................................................................................................................................................ 672
5.9.1 DCSM Base Address Table..................................................................................................................................... 672
5.9.2 DCSM_Z1_REGS Registers................................................................................................................................... 673
5.9.3 DCSM_Z2_REGS Registers................................................................................................................................... 721
5.9.4 DCSM_COMMON_REGS Registers.......................................................................................................................758
5.9.5 DCSM_Z1_OTP Registers...................................................................................................................................... 780
5.9.6 DCSM_Z2_OTP Registers...................................................................................................................................... 797
6 Flash Module.......................................................................................................................................................................807
6.1 Introduction to Flash and OTP Memory......................................................................................................................... 808
6.1.1 FLASH Related Collateral....................................................................................................................................... 808
6.1.2 Features.................................................................................................................................................................. 808
6.1.3 Flash Tools.............................................................................................................................................................. 809
6.1.4 Default Flash Configuration..................................................................................................................................... 809
6.2 Flash Bank, OTP, and Pump.......................................................................................................................................... 809
6.3 Flash Wrapper ...............................................................................................................................................................810
6.4 Flash and OTP Memory Performance............................................................................................................................811
6.5 Flash Read Interface...................................................................................................................................................... 811
6.5.1 C28x-Flash Read Interface...................................................................................................................................... 811
6.6 Flash Erase and Program.............................................................................................................................................. 814
6.6.1 Erase....................................................................................................................................................................... 814
6.6.2 Program...................................................................................................................................................................814
6.6.3 Verify........................................................................................................................................................................814
6.7 Error Correction Code (ECC) Protection........................................................................................................................815
6.7.1 Single-Bit Data Error................................................................................................................................................816
6.7.2 Uncorrectable Error................................................................................................................................................. 817
6.7.3 Mechanism to Check the Correctness of ECC Logic.............................................................................................. 817
6.8 Reserved Locations Within Flash and OTP................................................................................................................... 819
6.9 Migrating an Application from RAM to Flash..................................................................................................................819
6.10 Procedure to Change the Flash Control Registers...................................................................................................... 820
6.11 Software....................................................................................................................................................................... 820
6.11.1 FLASH Registers to Driverlib Functions................................................................................................................ 820
6.11.2 FLASH Examples...................................................................................................................................................820
6.12 FLASH Registers......................................................................................................................................................... 821
6.12.1 FLASH Base Address Table.................................................................................................................................. 821
6.12.2 FLASH_CTRL_REGS Registers........................................................................................................................... 822
6.12.3 FLASH_ECC_REGS Registers............................................................................................................................. 826
7 Control Law Accelerator (CLA)..........................................................................................................................................829
7.1 Introduction.................................................................................................................................................................... 830
7.1.1 Features.................................................................................................................................................................. 830
7.1.2 CLA Related Collateral............................................................................................................................................ 830
7.1.3 Block Diagram......................................................................................................................................................... 831
7.2 CLA Interface................................................................................................................................................................. 832
7.2.1 CLA Memory............................................................................................................................................................832

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7.2.2 CLA Memory Bus.................................................................................................................................................... 833

7.2.3 Shared Peripherals and EALLOW Protection..........................................................................................................833
7.2.4 CLA Tasks and Interrupt Vectors............................................................................................................................. 834
7.3 CLA, DMA, and CPU Arbitration.................................................................................................................................... 838
7.3.1 CLA Message RAM................................................................................................................................................. 838
7.3.2 CLA Program Memory.............................................................................................................................................839
7.3.3 CLA Data Memory................................................................................................................................................... 840
7.3.4 Peripheral Registers (ePWM, HRPWM, Comparator).............................................................................................840
7.4 CLA Configuration and Debug....................................................................................................................................... 841
7.4.1 Building a CLA Application...................................................................................................................................... 841
7.4.2 Typical CLA Initialization Sequence........................................................................................................................ 841
7.4.3 Debugging CLA Code..............................................................................................................................................842
7.4.4 CLA Illegal Opcode Behavior.................................................................................................................................. 843
7.4.5 Resetting the CLA................................................................................................................................................... 844
7.5 Pipeline.......................................................................................................................................................................... 844
7.5.1 Pipeline Overview....................................................................................................................................................844
7.5.2 CLA Pipeline Alignment...........................................................................................................................................845
7.5.3 Parallel Instructions................................................................................................................................................. 849
7.5.4 CLA Task Execution Latency...................................................................................................................................849
7.6 Software......................................................................................................................................................................... 850
7.6.1 CLA Registers to Driverlib Functions.......................................................................................................................850
7.6.2 CLA Examples.........................................................................................................................................................852
7.7 Instruction Set................................................................................................................................................................ 857
7.7.1 Instruction Descriptions........................................................................................................................................... 857
7.7.2 Addressing Modes and Encoding............................................................................................................................858
7.7.3 Instructions.............................................................................................................................................................. 861
7.8 CLA Registers................................................................................................................................................................ 988
7.8.1 CLA Base Address Table.........................................................................................................................................988
7.8.2 CLA_ONLY_REGS Registers..................................................................................................................................989
7.8.3 CLA_SOFTINT_REGS Registers............................................................................................................................998
7.8.4 CLA_REGS Registers........................................................................................................................................... 1002
8 Neural-network Processing Unit (NPU).......................................................................................................................... 1051
8.1 Introduction.................................................................................................................................................................. 1052
8.1.1 NPU Related Collateral......................................................................................................................................... 1052
9 Dual-Clock Comparator (DCC).........................................................................................................................................1053
9.1 Introduction.................................................................................................................................................................. 1054
9.1.1 Features................................................................................................................................................................ 1054
9.1.2 Block Diagram....................................................................................................................................................... 1054
9.2 Module Operation.........................................................................................................................................................1055
9.2.1 Configuring DCC Counters....................................................................................................................................1056
9.2.2 Single-Shot Measurement Mode........................................................................................................................... 1057
9.2.3 Continuous Monitoring Mode.................................................................................................................................1058
9.2.4 Error Conditions.....................................................................................................................................................1059
9.3 Interrupts...................................................................................................................................................................... 1061
9.4 Software....................................................................................................................................................................... 1062
9.4.1 DCC Registers to Driverlib Functions....................................................................................................................1062
9.4.2 DCC Examples...................................................................................................................................................... 1062
9.5 DCC Registers............................................................................................................................................................. 1064
9.5.1 DCC Base Address Table......................................................................................................................................1064
9.5.2 DCC_REGS Registers.......................................................................................................................................... 1065
10 General-Purpose Input/Output (GPIO)..........................................................................................................................1076
10.1 Introduction................................................................................................................................................................ 1077
10.1.1 GPIO Related Collateral...................................................................................................................................... 1078
10.2 Configuration Overview..............................................................................................................................................1079
10.3 Digital Inputs on ADC Pins (AIOs)............................................................................................................................. 1080
10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)....................................................................................................1080
10.5 Digital General-Purpose I/O Control.......................................................................................................................... 1082
10.6 Input Qualification...................................................................................................................................................... 1083
10.6.1 No Synchronization (Asynchronous Input).......................................................................................................... 1083
10.6.2 Synchronization to SYSCLKOUT Only................................................................................................................1083
10.6.3 Qualification Using a Sampling Window..............................................................................................................1084

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10.7 USB Signals............................................................................................................................................................... 1088

10.8 PMBUS and I2C Signals............................................................................................................................................ 1088
10.9 GPIO and Peripheral Muxing..................................................................................................................................... 1089
10.9.1 GPIO Muxing....................................................................................................................................................... 1089
10.9.2 Peripheral Muxing................................................................................................................................................1094
10.10 Internal Pullup Configuration Requirements............................................................................................................ 1096
10.11 Software................................................................................................................................................................... 1096
10.11.1 GPIO Registers to Driverlib Functions............................................................................................................... 1096
10.11.2 GPIO Examples................................................................................................................................................. 1101
10.11.3 LED Examples................................................................................................................................................... 1102
10.12 GPIO Registers........................................................................................................................................................ 1102
10.12.1 GPIO Base Address Table................................................................................................................................. 1102
10.12.2 GPIO_CTRL_REGS Registers.......................................................................................................................... 1103
10.12.3 GPIO_DATA_REGS Registers.......................................................................................................................... 1264
10.12.4 GPIO_DATA_READ_REGS Registers.............................................................................................................. 1311
11 Crossbar (X-BAR)........................................................................................................................................................... 1317
11.1 Input X-BAR and CLB Input X-BAR ...........................................................................................................................1318
11.1.1 CLB Input X-BAR................................................................................................................................................. 1321
11.2 ePWM , CLB, and GPIO Output X-BAR..................................................................................................................... 1322
11.2.1 ePWM X-BAR...................................................................................................................................................... 1322
11.2.2 CLB X-BAR.......................................................................................................................................................... 1324
11.2.3 GPIO Output X-BAR............................................................................................................................................ 1327
11.2.4 X-BAR Flags........................................................................................................................................................ 1329
11.3 Software..................................................................................................................................................................... 1331
11.3.1 INPUTXBAR Registers to Driverlib Functions..................................................................................................... 1331
11.3.2 EPWMXBAR Registers to Driverlib Functions..................................................................................................... 1331
11.3.3 CLBXBAR Registers to Driverlib Functions......................................................................................................... 1333
11.3.4 OUTPUTXBAR Registers to Driverlib Functions................................................................................................. 1334
11.3.5 XBAR Registers to Driverlib Functions................................................................................................................ 1335
11.4 XBAR Registers..........................................................................................................................................................1336
11.4.1 XBAR Base Address Table.................................................................................................................................. 1336
11.4.2 INPUT_XBAR_REGS Registers.......................................................................................................................... 1337
11.4.3 XBAR_REGS Registers.......................................................................................................................................1356
11.4.4 EPWM_XBAR_REGS Registers..........................................................................................................................1380
11.4.5 CLB_XBAR_REGS Registers..............................................................................................................................1473
11.4.6 OUTPUT_XBAR_REGS Registers...................................................................................................................... 1566
11.4.7 OUTPUT_XBAR_REGS Registers...................................................................................................................... 1667
12 Direct Memory Access (DMA)........................................................................................................................................1768
12.1 Introduction................................................................................................................................................................ 1769
12.1.1 Features.............................................................................................................................................................. 1769
12.1.2 Block Diagram..................................................................................................................................................... 1770
12.2 Architecture................................................................................................................................................................ 1771
12.2.1 Peripheral Interrupt Event Trigger Sources......................................................................................................... 1771
12.2.2 DMA Bus............................................................................................................................................................. 1775
12.3 Address Pointer and Transfer Control........................................................................................................................1776
12.4 Pipeline Timing and Throughput................................................................................................................................ 1782
12.5 CPU and CLA Arbitration........................................................................................................................................... 1783
12.6 Channel Priority..........................................................................................................................................................1784
12.6.1 Round-Robin Mode............................................................................................................................................. 1784
12.6.2 Channel 1 High-Priority Mode............................................................................................................................. 1785
12.7 Overrun Detection Feature.........................................................................................................................................1785
12.8 Software..................................................................................................................................................................... 1786
12.8.1 DMA Registers to Driverlib Functions..................................................................................................................1786
12.8.2 DMA Examples....................................................................................................................................................1787
12.9 DMA Registers........................................................................................................................................................... 1788
12.9.1 DMA Base Address Table....................................................................................................................................1788
12.9.2 DMA_REGS Registers........................................................................................................................................ 1789
12.9.3 DMA_CH_REGS Registers................................................................................................................................. 1794
13 Embedded Real-time Analysis and Diagnostic (ERAD).............................................................................................. 1821
13.1 Introduction................................................................................................................................................................ 1822
13.1.1 ERAD Related Collateral..................................................................................................................................... 1822

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13.2 Enhanced Bus Comparator Unit................................................................................................................................ 1823

13.2.1 Enhanced Bus Comparator Unit Operations....................................................................................................... 1823
13.2.2 Event Masking and Exporting..............................................................................................................................1824
13.3 System Event Counter Unit........................................................................................................................................1825
13.3.1 System Event Counter Modes.............................................................................................................................1825
13.3.2 Reset on Event.................................................................................................................................................... 1830
13.3.3 Operation Conditions...........................................................................................................................................1830
13.4 ERAD Ownership, Initialization and Reset.................................................................................................................1831
13.5 ERAD Programming Sequence................................................................................................................................. 1832
13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence....................................................... 1832
13.5.2 Timer and Counter Programming Sequence....................................................................................................... 1833
13.6 Cyclic Redundancy Check Unit..................................................................................................................................1833
13.6.1 CRC Unit Qualifier............................................................................................................................................... 1834
13.6.2 CRC Unit Programming Sequence......................................................................................................................1835
13.7 Program Counter Trace..............................................................................................................................................1836
13.7.1 Functional Block Diagram....................................................................................................................................1837
13.7.2 Trace Qualification Modes................................................................................................................................... 1838
13.7.3 Trace Memory......................................................................................................................................................1842
13.7.4 Trace Input Signal Conditioning...........................................................................................................................1843
13.7.5 PC Trace Software Operation..............................................................................................................................1844
13.7.6 Trace Operation in Debug Mode......................................................................................................................... 1844
13.8 Software..................................................................................................................................................................... 1845
13.8.1 ERAD Registers to Driverlib Functions................................................................................................................1845
13.8.2 ERAD Examples..................................................................................................................................................1847
13.9 ERAD Registers......................................................................................................................................................... 1855
13.9.1 ERAD Base Address Table..................................................................................................................................1855
13.9.2 ERAD_GLOBAL_REGS Registers......................................................................................................................1856
13.9.3 ERAD_HWBP_REGS Registers......................................................................................................................... 1879
13.9.4 ERAD_COUNTER_REGS Registers.................................................................................................................. 1886
13.9.5 ERAD_CRC_GLOBAL_REGS Registers............................................................................................................ 1897
13.9.6 ERAD_CRC_REGS Registers............................................................................................................................ 1900
13.9.7 PCTRACE_REGS Registers............................................................................................................................... 1904
13.9.8 PCTRACE_BUFFER_REGS Registers............................................................................................................... 1911
14 Analog Subsystem......................................................................................................................................................... 1913
14.1 Introduction................................................................................................................................................................ 1914
14.1.1 Features.............................................................................................................................................................. 1914
14.1.2 Block Diagram..................................................................................................................................................... 1914
14.2 Optimizing Power-Up Time........................................................................................................................................ 1919
14.3 Digital Inputs on ADC Pins (AIOs)............................................................................................................................. 1919
14.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)....................................................................................................1919
14.5 Analog Pins and Internal Connections....................................................................................................................... 1922
14.6 Software..................................................................................................................................................................... 1926
14.6.1 ASYSCTL Registers to Driverlib Functions......................................................................................................... 1926
14.7 ASBSYS Registers.....................................................................................................................................................1928
14.7.1 ASBSYS Base Address Table............................................................................................................................. 1928
14.7.2 ANALOG_SUBSYS_REGS Registers.................................................................................................................1929
15 Analog-to-Digital Converter (ADC)................................................................................................................................1966
15.1 Introduction................................................................................................................................................................ 1967
15.1.1 ADC Related Collateral....................................................................................................................................... 1967
15.1.2 Features.............................................................................................................................................................. 1968
15.1.3 Block Diagram..................................................................................................................................................... 1969
15.2 ADC Configurability....................................................................................................................................................1970
15.2.1 Clock Configuration............................................................................................................................................. 1970
15.2.2 Resolution............................................................................................................................................................1970
15.2.3 Voltage Reference............................................................................................................................................... 1971
15.2.4 Signal Mode.........................................................................................................................................................1972
15.2.5 Expected Conversion Results............................................................................................................................. 1972
15.2.6 Interpreting Conversion Results.......................................................................................................................... 1972
15.3 SOC Principle of Operation........................................................................................................................................1973
15.3.1 SOC Configuration.............................................................................................................................................. 1974
15.3.2 Trigger Operation.................................................................................................................................................1974

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15.3.3 ADC Acquisition (Sample and Hold) Window......................................................................................................1982

15.3.4 Sample Capacitor Reset......................................................................................................................................1983
15.3.5 ADC Input Models............................................................................................................................................... 1983
15.3.6 Channel Selection............................................................................................................................................... 1984
15.4 SOC Configuration Examples.................................................................................................................................... 1991
15.4.1 Single Conversion from ePWM Trigger............................................................................................................... 1991
15.4.2 Oversampled Conversion from ePWM Trigger....................................................................................................1991
15.4.3 Multiple Conversions from CPU Timer Trigger.................................................................................................... 1992
15.4.4 Software Triggering of SOCs...............................................................................................................................1993
15.5 ADC Conversion Priority............................................................................................................................................ 1993
15.6 Burst Mode.................................................................................................................................................................1996
15.6.1 Burst Mode Example........................................................................................................................................... 1996
15.6.2 Burst Mode Priority Example............................................................................................................................... 1997
15.7 EOC and Interrupt Operation..................................................................................................................................... 1998
15.7.1 Interrupt Overflow................................................................................................................................................ 1999
15.7.2 Continue to Interrupt Mode..................................................................................................................................1999
15.7.3 Early Interrupt Configuration Mode......................................................................................................................2000
15.8 Post-Processing Blocks............................................................................................................................................. 2001
15.8.1 PPB Offset Correction......................................................................................................................................... 2002
15.8.2 PPB Error Calculation..........................................................................................................................................2002
15.8.3 PPB Result Delta Calculation.............................................................................................................................. 2002
15.8.4 PPB Limit Detection and Zero-Crossing Detection..............................................................................................2003
15.8.5 PPB Sample Delay Capture................................................................................................................................ 2006
15.8.6 PPB Oversampling.............................................................................................................................................. 2006
15.9 Opens/Shorts Detection Circuit (OSDETECT)...........................................................................................................2008
15.9.1 Implementation.................................................................................................................................................... 2009
15.9.2 Detecting an Open Input Pin............................................................................................................................... 2009
15.9.3 Detecting a Shorted Input Pin..............................................................................................................................2009
15.10 Power-Up Sequence................................................................................................................................................ 2010
15.11 ADC Calibration........................................................................................................................................................2010
15.11.1 ADC Zero Offset Calibration.............................................................................................................................. 2010
15.12 ADC Timings............................................................................................................................................................ 2011
15.12.1 ADC Timing Diagrams....................................................................................................................................... 2011
15.12.2 Post-Processing Block Timings......................................................................................................................... 2015
15.13 Additional Information.............................................................................................................................................. 2017
15.13.1 Ensuring Synchronous Operation......................................................................................................................2017
15.13.2 Choosing an Acquisition Window Duration........................................................................................................2020
15.13.3 Achieving Simultaneous Sampling.................................................................................................................... 2022
15.13.4 Result Register Mapping................................................................................................................................... 2022
15.13.5 Internal Temperature Sensor............................................................................................................................. 2022
15.13.6 Designing an External Reference Circuit...........................................................................................................2023
15.13.7 ADC-DAC Loopback Testing............................................................................................................................. 2023
15.13.8 Internal Test Mode............................................................................................................................................. 2025
15.13.9 ADC Gain and Offset Calibration.......................................................................................................................2025
15.14 Software................................................................................................................................................................... 2026
15.14.1 ADC Registers to Driverlib Functions................................................................................................................ 2026
15.14.2 ADC Examples.................................................................................................................................................. 2034
15.15 ADC Registers......................................................................................................................................................... 2039
15.15.1 ADC Base Address Table.................................................................................................................................. 2039
15.15.2 ADC_RESULT_REGS Registers.......................................................................................................................2040
15.15.3 ADC_REGS Registers.......................................................................................................................................2086
16 Buffered Digital-to-Analog Converter (DAC)................................................................................................................2284
16.1 Introduction................................................................................................................................................................ 2285
16.1.1 DAC Related Collateral....................................................................................................................................... 2285
16.1.2 Features.............................................................................................................................................................. 2285
16.1.3 Block Diagram..................................................................................................................................................... 2285
16.2 Using the DAC........................................................................................................................................................... 2286
16.2.1 Initialization Sequence.........................................................................................................................................2286
16.2.2 DAC Offset Adjustment........................................................................................................................................2287
16.2.3 EPWMSYNCPER Signal..................................................................................................................................... 2287
16.3 Lock Registers........................................................................................................................................................... 2287

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16.4 Software..................................................................................................................................................................... 2288

16.4.1 DAC Registers to Driverlib Functions.................................................................................................................. 2288
16.4.2 DAC Examples.................................................................................................................................................... 2288
16.5 DAC Registers........................................................................................................................................................... 2289
16.5.1 DAC Base Address Table.................................................................................................................................... 2289
16.5.2 DAC_REGS Registers.........................................................................................................................................2290
17 Comparator Subsystem (CMPSS)................................................................................................................................. 2298
17.1 Introduction................................................................................................................................................................ 2299
17.1.1 CMPSS Related Collateral.................................................................................................................................. 2299
17.1.2 Features.............................................................................................................................................................. 2299
17.1.3 Block Diagram..................................................................................................................................................... 2300
17.2 Comparator................................................................................................................................................................ 2300
17.3 Reference DAC.......................................................................................................................................................... 2301
17.4 Ramp Generator........................................................................................................................................................ 2302
17.4.1 Ramp Generator Overview..................................................................................................................................2302
17.4.2 Ramp Generator Behavior...................................................................................................................................2303
17.4.3 Ramp Generator Behavior at Corner Cases....................................................................................................... 2304
17.5 Digital Filter................................................................................................................................................................ 2306
17.5.1 Filter Initialization Sequence................................................................................................................................2307
17.6 Using the CMPSS...................................................................................................................................................... 2307
17.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals ..............................................................................2307
17.6.2 Synchronizer, Digital Filter, and Latch Delays..................................................................................................... 2307
17.6.3 Calibrating the CMPSS .......................................................................................................................................2308
17.6.4 Enabling and Disabling the CMPSS Clock.......................................................................................................... 2308
17.7 CMPSS DAC Output.................................................................................................................................................. 2309
17.8 Software..................................................................................................................................................................... 2309
17.8.1 CMPSS Registers to Driverlib Functions.............................................................................................................2309
17.8.2 CMPSS Examples............................................................................................................................................... 2312
17.9 CMPSS Registers...................................................................................................................................................... 2313
17.9.1 CMPSS Base Address Table...............................................................................................................................2313
17.9.2 CMPSS_REGS Registers................................................................................................................................... 2314
18 Programmable Gain Amplifier (PGA)............................................................................................................................2356
18.1 Programmable Gain Amplifier (PGA) Overview......................................................................................................... 2357
18.1.1 Features.............................................................................................................................................................. 2357
18.1.2 Block Diagram..................................................................................................................................................... 2357
18.2 Linear Output Range..................................................................................................................................................2358
18.3 Gain Values................................................................................................................................................................2358
18.4 Modes of Operation....................................................................................................................................................2359
18.4.1 Buffer Mode......................................................................................................................................................... 2359
18.4.2 Standalone Mode................................................................................................................................................ 2360
18.4.3 Non-inverting Mode............................................................................................................................................. 2361
18.4.4 Subtractor Mode.................................................................................................................................................. 2362
18.5 External Filtering........................................................................................................................................................ 2363
18.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor................................................................2363
18.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor............................................. 2364
18.6 Error Calibration......................................................................................................................................................... 2365
18.6.1 Offset Error.......................................................................................................................................................... 2365
18.6.2 Gain Error............................................................................................................................................................ 2365
18.7 Chopping Feature...................................................................................................................................................... 2366
18.8 Enabling and Disabling the PGA Clock......................................................................................................................2367
18.9 Lock Register............................................................................................................................................................. 2367
18.10 Analog Front-End Integration................................................................................................................................... 2368
18.10.1 Buffered DAC.....................................................................................................................................................2368
18.10.2 Analog-to-Digital Converter (ADC) ................................................................................................................... 2369
18.10.3 Comparator Subsystem (CMPSS).....................................................................................................................2369
18.10.4 PGA_NEG_SHARED Feature...........................................................................................................................2369
18.10.5 Alternate Functions............................................................................................................................................2371
18.11 Examples..................................................................................................................................................................2372
18.11.1 Non-Inverting Amplifier Using Non-Inverting Mode............................................................................................2372
18.11.2 Buffer Mode....................................................................................................................................................... 2372
18.11.3 Low-Side Current Sensing................................................................................................................................. 2373

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18.11.4 Bidirectional Current Sensing............................................................................................................................ 2374

18.12 Software................................................................................................................................................................... 2375
18.12.1 PGA Registers to Driverlib Functions................................................................................................................ 2375
18.12.2 PGA Examples.................................................................................................................................................. 2375
18.13 PGA Registers......................................................................................................................................................... 2376
18.13.1 PGA Base Address Table.................................................................................................................................. 2376
18.13.2 PGA_REGS Registers.......................................................................................................................................2377
19 Enhanced Pulse Width Modulator (ePWM)...................................................................................................................2383
19.1 Introduction................................................................................................................................................................ 2384
19.1.1 EPWM Related Collateral....................................................................................................................................2385
19.1.2 Submodule Overview.......................................................................................................................................... 2386
19.2 Configuring Device Pins.............................................................................................................................................2391
19.3 ePWM Modules Overview..........................................................................................................................................2391
19.4 Time-Base (TB) Submodule.......................................................................................................................................2393
19.4.1 Purpose of the Time-Base Submodule................................................................................................................2393
19.4.2 Controlling and Monitoring the Time-Base Submodule....................................................................................... 2394
19.4.3 Calculating PWM Period and Frequency.............................................................................................................2396
19.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules..................................................................... 2400
19.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules............................................... 2401
19.4.6 Time-Base Counter Modes and Timing Waveforms............................................................................................ 2401
19.4.7 Global Load......................................................................................................................................................... 2406
19.5 Counter-Compare (CC) Submodule...........................................................................................................................2408
19.5.1 Purpose of the Counter-Compare Submodule.................................................................................................... 2408
19.5.2 Controlling and Monitoring the Counter-Compare Submodule............................................................................2409
19.5.3 Operational Highlights for the Counter-Compare Submodule............................................................................. 2410
19.5.4 Count Mode Timing Waveforms...........................................................................................................................2411
19.6 Action-Qualifier (AQ) Submodule...............................................................................................................................2414
19.6.1 Purpose of the Action-Qualifier Submodule........................................................................................................ 2414
19.6.2 Action-Qualifier Submodule Control and Status Register Definitions..................................................................2415
19.6.3 Action-Qualifier Event Priority..............................................................................................................................2417
19.6.4 AQCTLA and AQCTLB Shadow Mode Operations............................................................................................. 2418
19.6.5 Configuration Requirements for Common Waveforms........................................................................................ 2420
19.7 Dead-Band Generator (DB) Submodule.................................................................................................................... 2427
19.7.1 Purpose of the Dead-Band Submodule...............................................................................................................2427
19.7.2 Dead-band Submodule Additional Operating Modes.......................................................................................... 2428
19.7.3 Operational Highlights for the Dead-Band Submodule........................................................................................2430
19.8 PWM Chopper (PC) Submodule................................................................................................................................ 2434
19.8.1 Purpose of the PWM Chopper Submodule......................................................................................................... 2434
19.8.2 Operational Highlights for the PWM Chopper Submodule.................................................................................. 2434
19.8.3 Waveforms...........................................................................................................................................................2435
19.9 Trip-Zone (TZ) Submodule.........................................................................................................................................2438
19.9.1 Purpose of the Trip-Zone Submodule..................................................................................................................2438
19.9.2 Operational Highlights for the Trip-Zone Submodule.......................................................................................... 2439
19.9.3 Generating Trip Event Interrupts......................................................................................................................... 2441
19.10 Event-Trigger (ET) Submodule................................................................................................................................ 2444
19.10.1 Operational Overview of the ePWM Event-Trigger Submodule........................................................................ 2445
19.11 Digital Compare (DC) Submodule............................................................................................................................ 2449
19.11.1 Purpose of the Digital Compare Submodule......................................................................................................2451
19.11.2 Enhanced Trip Action Using CMPSS.................................................................................................................2451
19.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis............................................................................ 2451
19.11.4 Operation Highlights of the Digital Compare Submodule.................................................................................. 2452
19.12 ePWM Crossbar (X-BAR)........................................................................................................................................ 2459
19.13 Applications to Power Topologies............................................................................................................................ 2460
19.13.1 Overview of Multiple Modules............................................................................................................................2460
19.13.2 Key Configuration Capabilities.......................................................................................................................... 2461
19.13.3 Controlling Multiple Buck Converters With Independent Frequencies.............................................................. 2462
19.13.4 Controlling Multiple Buck Converters With Same Frequencies......................................................................... 2464
19.13.5 Controlling Multiple Half H-Bridge (HHB) Converters........................................................................................2466
19.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)...................................................................... 2468
19.13.7 Practical Applications Using Phase Control Between PWM Modules............................................................... 2470
19.13.8 Controlling a 3-Phase Interleaved DC/DC Converter........................................................................................ 2471

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19.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter.................................................................. 2474
19.13.10 Controlling a Peak Current Mode Controlled Buck Module............................................................................. 2476
19.13.11 Controlling H-Bridge LLC Resonant Converter................................................................................................2477
19.14 Register Lock Protection.......................................................................................................................................... 2478
19.15 High-Resolution Pulse Width Modulator (HRPWM)................................................................................................. 2479
19.15.1 Operational Description of HRPWM.................................................................................................................. 2481
19.15.2 SFO Library Software - SFO_TI_Build_V8.lib................................................................................................... 2502
19.16 Software................................................................................................................................................................... 2505
19.16.1 EPWM Registers to Driverlib Functions............................................................................................................ 2505
19.16.2 HRPWM Registers to Driverlib Functions..........................................................................................................2512
19.16.3 EPWM Examples...............................................................................................................................................2516
19.16.4 HRPWM Examples............................................................................................................................................2521
19.17 EPWM Registers......................................................................................................................................................2524
19.17.1 EPWM Base Address Table.............................................................................................................................. 2524
19.17.2 EPWM_REGS Registers................................................................................................................................... 2525
20 Enhanced Capture (eCAP)............................................................................................................................................. 2655
20.1 Introduction................................................................................................................................................................ 2656
20.1.1 Features.............................................................................................................................................................. 2656
20.1.2 ECAP Related Collateral..................................................................................................................................... 2656
20.2 Description................................................................................................................................................................. 2657
20.3 Configuring Device Pins for the eCAP....................................................................................................................... 2658
20.4 Capture and APWM Operating Mode........................................................................................................................ 2661
20.5 Capture Mode Description......................................................................................................................................... 2663
20.5.1 Event Prescaler................................................................................................................................................... 2664
20.5.2 Edge Polarity Select and Qualifier.......................................................................................................................2664
20.5.3 Continuous/One-Shot Control............................................................................................................................. 2665
20.5.4 32-Bit Counter and Phase Control.......................................................................................................................2666
20.5.5 CAP1-CAP4 Registers........................................................................................................................................ 2666
20.5.6 eCAP Synchronization.........................................................................................................................................2666
20.5.7 Interrupt Control...................................................................................................................................................2667
20.5.8 DMA Interrupt...................................................................................................................................................... 2669
20.5.9 Shadow Load and Lockout Control..................................................................................................................... 2669
20.5.10 APWM Mode Operation.....................................................................................................................................2669
20.6 Application of the eCAP Module................................................................................................................................ 2671
20.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger.................................................................... 2671
20.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger.................................................2672
20.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger..................................................................2673
20.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger.............................................. 2674
20.7 Application of the APWM Mode................................................................................................................................. 2675
20.7.1 Example 1 - Simple PWM Generation (Independent Channels)......................................................................... 2675
20.8 Software..................................................................................................................................................................... 2676
20.8.1 ECAP Registers to Driverlib Functions................................................................................................................2676
20.8.2 ECAP Examples.................................................................................................................................................. 2677
20.9 ECAP Registers......................................................................................................................................................... 2678
20.9.1 ECAP Base Address Table..................................................................................................................................2678
20.9.2 ECAP_REGS Registers...................................................................................................................................... 2679
21 Enhanced Quadrature Encoder Pulse (eQEP)............................................................................................................. 2698
21.1 Introduction................................................................................................................................................................ 2699
21.1.1 EQEP Related Collateral..................................................................................................................................... 2701
21.2 Configuring Device Pins.............................................................................................................................................2701
21.3 Description................................................................................................................................................................. 2702
21.3.1 EQEP Inputs........................................................................................................................................................2702
21.3.2 Functional Description......................................................................................................................................... 2705
21.3.3 eQEP Memory Map............................................................................................................................................. 2706
21.4 Quadrature Decoder Unit (QDU)................................................................................................................................2707
21.4.1 Position Counter Input Modes............................................................................................................................. 2707
21.4.2 eQEP Input Polarity Selection............................................................................................................................. 2710
21.4.3 Position-Compare Sync Output........................................................................................................................... 2710
21.5 Position Counter and Control Unit (PCCU)................................................................................................................ 2710
21.5.1 Position Counter Operating Modes..................................................................................................................... 2710
21.5.2 Position Counter Latch........................................................................................................................................ 2713

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21.5.3 Position Counter Initialization.............................................................................................................................. 2715

21.5.4 eQEP Position-compare Unit...............................................................................................................................2716
21.6 eQEP Edge Capture Unit........................................................................................................................................... 2718
21.7 eQEP Watchdog.........................................................................................................................................................2722
21.8 eQEP Unit Timer Base............................................................................................................................................... 2722
21.9 QMA Module.............................................................................................................................................................. 2723
21.9.1 Modes of Operation............................................................................................................................................. 2724
21.9.2 Interrupt and Error Generation............................................................................................................................ 2725
21.10 eQEP Interrupt Structure..........................................................................................................................................2726
21.11 Software................................................................................................................................................................... 2727
21.11.1 EQEP Registers to Driverlib Functions.............................................................................................................. 2727
21.11.2 EQEP Examples................................................................................................................................................ 2728
21.12 EQEP Registers....................................................................................................................................................... 2731
21.12.1 EQEP Base Address Table................................................................................................................................2731
21.12.2 EQEP_REGS Registers.................................................................................................................................... 2732
22 Serial Peripheral Interface (SPI).................................................................................................................................... 2770
22.1 Introduction................................................................................................................................................................ 2771
22.1.1 Features.............................................................................................................................................................. 2771
22.1.2 SPI Related Collateral......................................................................................................................................... 2771
22.1.3 Block Diagram..................................................................................................................................................... 2772
22.2 System-Level Integration........................................................................................................................................... 2773
22.2.1 SPI Module Signals............................................................................................................................................. 2773
22.2.2 Configuring Device Pins...................................................................................................................................... 2774
22.2.3 SPI Interrupts.......................................................................................................................................................2774
22.2.4 DMA Support....................................................................................................................................................... 2776
22.3 SPI Operation.............................................................................................................................................................2777
22.3.1 Introduction to Operation..................................................................................................................................... 2777
22.3.2 Controller Mode................................................................................................................................................... 2778
22.3.3 Peripheral Mode.................................................................................................................................................. 2779
22.3.4 Data Format.........................................................................................................................................................2781
22.3.5 Baud Rate Selection............................................................................................................................................2782
22.3.6 SPI Clocking Schemes........................................................................................................................................ 2783
22.3.7 SPI FIFO Description...........................................................................................................................................2784
22.3.8 SPI DMA Transfers..............................................................................................................................................2785
22.3.9 SPI High-Speed Mode.........................................................................................................................................2786
22.3.10 SPI 3-Wire Mode Description............................................................................................................................ 2786
22.4 Programming Procedure............................................................................................................................................ 2788
22.4.1 Initialization Upon Reset......................................................................................................................................2788
22.4.2 Configuring the SPI............................................................................................................................................. 2788
22.4.3 Configuring the SPI for High-Speed Mode.......................................................................................................... 2789
22.4.4 Data Transfer Example........................................................................................................................................2790
22.4.5 SPI 3-Wire Mode Code Examples.......................................................................................................................2791
22.4.6 SPI STEINV Bit in Digital Audio Transfers...........................................................................................................2793
22.5 Software..................................................................................................................................................................... 2794
22.5.1 SPI Registers to Driverlib Functions....................................................................................................................2794
22.5.2 SPI Examples...................................................................................................................................................... 2795
22.6 SPI Registers............................................................................................................................................................. 2798
22.6.1 SPI Base Address Table......................................................................................................................................2798
22.6.2 SPI_REGS Registers.......................................................................................................................................... 2799
23 Serial Communications Interface (SCI)........................................................................................................................ 2818
23.1 Introduction................................................................................................................................................................ 2819
23.1.1 Features.............................................................................................................................................................. 2819
23.1.2 SCI Related Collateral......................................................................................................................................... 2820
23.1.3 Block Diagram..................................................................................................................................................... 2820
23.2 Architecture................................................................................................................................................................ 2820
23.3 SCI Module Signal Summary..................................................................................................................................... 2820
23.4 Configuring Device Pins.............................................................................................................................................2822
23.5 Multiprocessor and Asynchronous Communication Modes....................................................................................... 2822
23.6 SCI Programmable Data Format................................................................................................................................2823
23.7 SCI Multiprocessor Communication...........................................................................................................................2824
23.7.1 Recognizing the Address Byte............................................................................................................................ 2824

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23.7.2 Controlling the SCI TX and RX Features.............................................................................................................2824

23.7.3 Receipt Sequence............................................................................................................................................... 2824
23.8 Idle-Line Multiprocessor Mode................................................................................................................................... 2825
23.8.1 Idle-Line Mode Steps...........................................................................................................................................2825
23.8.2 Block Start Signal................................................................................................................................................ 2826
23.8.3 Wake-Up Temporary (WUT) Flag........................................................................................................................ 2826
23.8.4 Receiver Operation..............................................................................................................................................2826
23.9 Address-Bit Multiprocessor Mode.............................................................................................................................. 2827
23.9.1 Sending an Address............................................................................................................................................ 2827
23.10 SCI Communication Format.....................................................................................................................................2828
23.10.1 Receiver Signals in Communication Modes...................................................................................................... 2829
23.10.2 Transmitter Signals in Communication Modes.................................................................................................. 2830
23.11 SCI Port Interrupts....................................................................................................................................................2831
23.11.1 Break Detect...................................................................................................................................................... 2832
23.12 SCI Baud Rate Calculations.....................................................................................................................................2832
23.13 SCI Enhanced Features...........................................................................................................................................2833
23.13.1 SCI FIFO Description........................................................................................................................................ 2833
23.13.2 SCI Auto-Baud...................................................................................................................................................2835
23.13.3 Autobaud-Detect Sequence.............................................................................................................................. 2835
23.14 Software................................................................................................................................................................... 2836
23.14.1 SCI Registers to Driverlib Functions..................................................................................................................2836
23.14.2 SCI Examples....................................................................................................................................................2838
23.15 SCI Registers........................................................................................................................................................... 2840
23.15.1 SCI Base Address Table....................................................................................................................................2840
23.15.2 SCI_REGS Registers........................................................................................................................................ 2841
24 Universal Serial Bus (USB) Controller..........................................................................................................................2863
24.1 Introduction................................................................................................................................................................ 2864
24.1.1 Features.............................................................................................................................................................. 2864
24.1.2 USB Related Collateral........................................................................................................................................2864
24.1.3 Block Diagram..................................................................................................................................................... 2865
24.2 Functional Description................................................................................................................................................2867
24.2.1 Operation as a Device......................................................................................................................................... 2867
24.2.2 Operation as a Host.............................................................................................................................................2872
24.2.3 DMA Operation....................................................................................................................................................2876
24.2.4 Address/Data Bus Bridge.................................................................................................................................... 2876
24.3 Initialization and Configuration................................................................................................................................... 2878
24.3.1 Pin Configuration................................................................................................................................................. 2878
24.3.2 Endpoint Configuration........................................................................................................................................ 2879
24.4 USB Global Interrupts................................................................................................................................................ 2879
24.5 Software..................................................................................................................................................................... 2880
24.5.1 USB Registers to Driverlib Functions.................................................................................................................. 2880
24.5.2 USB Examples.................................................................................................................................................... 2897
24.6 USB Registers............................................................................................................................................................2899
24.6.1 USB Base Address Table.................................................................................................................................... 2899
24.6.2 USB_REGS Registers.........................................................................................................................................2900
25 Fast Serial Interface (FSI)...............................................................................................................................................3047
25.1 Introduction................................................................................................................................................................ 3048
25.1.1 FSI Related Collateral......................................................................................................................................... 3048
25.1.2 FSI Features........................................................................................................................................................3048
25.2 System-level Integration.............................................................................................................................................3049
25.2.1 CPU Interface...................................................................................................................................................... 3049
25.2.2 Signal Description................................................................................................................................................3051
25.2.3 FSI Interrupts.......................................................................................................................................................3052
25.2.4 CLA Task Triggering............................................................................................................................................ 3054
25.2.5 DMA Interface......................................................................................................................................................3054
25.2.6 External Frame Trigger Mux................................................................................................................................ 3055
25.3 FSI Functional Description......................................................................................................................................... 3056
25.3.1 Introduction to Operation .................................................................................................................................... 3056
25.3.2 FSI Transmitter Module....................................................................................................................................... 3057
25.3.3 FSI Receiver Module........................................................................................................................................... 3063
25.3.4 Frame Format......................................................................................................................................................3069

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25.3.5 Flush Sequence...................................................................................................................................................3073

25.3.6 Internal Loopback................................................................................................................................................ 3074
25.3.7 CRC Generation.................................................................................................................................................. 3074
25.3.8 ECC Module........................................................................................................................................................ 3075
25.3.9 Tag Matching....................................................................................................................................................... 3076
25.3.10 User Data Filtering (UDATA Matching).............................................................................................................. 3076
25.3.11 TDM Configurations........................................................................................................................................... 3076
25.3.12 FSI Trigger Generation...................................................................................................................................... 3078
25.3.13 FSI-SPI Compatibility Mode.............................................................................................................................. 3080
25.4 FSI Programing Guide............................................................................................................................................... 3084
25.4.1 Establishing the Communication Link..................................................................................................................3084
25.4.2 Register Protection.............................................................................................................................................. 3086
25.4.3 Emulation Mode...................................................................................................................................................3086
25.5 Software..................................................................................................................................................................... 3087
25.5.1 FSI Registers to Driverlib Functions.................................................................................................................... 3087
25.5.2 FSI Examples...................................................................................................................................................... 3091
25.6 FSI Registers............................................................................................................................................................. 3097
25.6.1 FSI Base Address Table...................................................................................................................................... 3097
25.6.2 FSI_TX_REGS Registers.................................................................................................................................... 3098
25.6.3 FSI_RX_REGS Registers....................................................................................................................................3125
26 Inter-Integrated Circuit Module (I2C).............................................................................................................................3174
26.1 Introduction................................................................................................................................................................ 3175
26.1.1 I2C Related Collateral......................................................................................................................................... 3175
26.1.2 Features.............................................................................................................................................................. 3176
26.1.3 Features Not Supported...................................................................................................................................... 3176
26.1.4 Functional Overview............................................................................................................................................ 3177
26.1.5 Clock Generation.................................................................................................................................................3178
26.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)....................................................................................... 3179
26.2 Configuring Device Pins.............................................................................................................................................3180
26.3 I2C Module Operational Details................................................................................................................................. 3180
26.3.1 Input and Output Voltage Levels......................................................................................................................... 3180
26.3.2 Selecting Pullup Resistors...................................................................................................................................3180
26.3.3 Data Validity.........................................................................................................................................................3180
26.3.4 Operating Modes................................................................................................................................................. 3181
26.3.5 I2C Module START and STOP Conditions.......................................................................................................... 3185
26.3.6 Non-repeat Mode versus Repeat Mode.............................................................................................................. 3186
26.3.7 Serial Data Formats.............................................................................................................................................3186
26.3.8 Clock Synchronization......................................................................................................................................... 3189
26.3.9 Clock Stretching.................................................................................................................................................. 3190
26.3.10 Arbitration.......................................................................................................................................................... 3192
26.3.11 Digital Loopback Mode...................................................................................................................................... 3193
26.3.12 NACK Bit Generation.........................................................................................................................................3194
26.4 Interrupt Requests Generated by the I2C Module..................................................................................................... 3194
26.4.1 Basic I2C Interrupt Requests...............................................................................................................................3195
26.4.2 I2C FIFO Interrupts..............................................................................................................................................3197
26.5 Resetting or Disabling the I2C Module.......................................................................................................................3197
26.6 Software..................................................................................................................................................................... 3198
26.6.1 I2C Registers to Driverlib Functions.................................................................................................................... 3198
26.6.2 I2C Examples...................................................................................................................................................... 3199
26.7 I2C Registers............................................................................................................................................................. 3202
26.7.1 I2C Base Address Table...................................................................................................................................... 3202
26.7.2 I2C_REGS Registers...........................................................................................................................................3203
27 Power Management Bus Module (PMBus)................................................................................................................... 3227
27.1 Introduction................................................................................................................................................................ 3228
27.1.1 PMBUS Related Collateral.................................................................................................................................. 3228
27.1.2 Features.............................................................................................................................................................. 3228
27.1.3 Block Diagram..................................................................................................................................................... 3229
27.2 Configuring Device Pins.............................................................................................................................................3230
27.3 Target Mode Operation.............................................................................................................................................. 3230
27.3.1 Configuration....................................................................................................................................................... 3230
27.3.2 Message Handling...............................................................................................................................................3231

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27.4 Controller Mode Operation.........................................................................................................................................3241

27.4.1 Configuration....................................................................................................................................................... 3241
27.4.2 Message Handling...............................................................................................................................................3241
27.5 Software..................................................................................................................................................................... 3252
27.5.1 PMBUS Registers to Driverlib Functions.............................................................................................................3252
27.6 PMBUS Registers...................................................................................................................................................... 3253
27.6.1 PMBUS Base Address Table...............................................................................................................................3253
27.6.2 PMBUS_REGS Registers................................................................................................................................... 3254
28 Modular Controller Area Network (MCAN)................................................................................................................... 3275
28.1 MCAN Introduction.....................................................................................................................................................3276
28.1.1 MCAN Related Collateral.................................................................................................................................... 3276
28.1.2 MCAN Features...................................................................................................................................................3277
28.2 MCAN Environment................................................................................................................................................... 3277
28.3 CAN Network Basics..................................................................................................................................................3278
28.4 MCAN Integration.......................................................................................................................................................3279
28.5 MCAN Functional Description.................................................................................................................................... 3281
28.5.1 Module Clocking Requirements...........................................................................................................................3282
28.5.2 Interrupt Requests............................................................................................................................................... 3282
28.5.3 Operating Modes................................................................................................................................................. 3283
28.5.4 Transmitter Delay Compensation........................................................................................................................ 3286
28.5.5 Restricted Operation Mode..................................................................................................................................3288
28.5.6 Bus Monitoring Mode...........................................................................................................................................3288
28.5.7 Disabled Automatic Retransmission (DAR) Mode...............................................................................................3289
28.5.8 Clock Stop Mode................................................................................................................................................. 3289
28.5.9 Test Modes.......................................................................................................................................................... 3292
28.5.10 Timestamp Generation...................................................................................................................................... 3293
28.5.11 Timeout Counter................................................................................................................................................ 3295
28.5.12 Safety................................................................................................................................................................ 3295
28.5.13 Rx Handling....................................................................................................................................................... 3297
28.5.14 Tx Handling....................................................................................................................................................... 3303
28.5.15 FIFO Acknowledge Handling.............................................................................................................................3307
28.5.16 Message RAM................................................................................................................................................... 3307
28.6 Software..................................................................................................................................................................... 3318
28.6.1 MCAN Registers to Driverlib Functions............................................................................................................... 3318
28.6.2 MCAN Examples................................................................................................................................................. 3321
28.7 MCAN Registers........................................................................................................................................................ 3325
28.7.1 MCAN Base Address Table................................................................................................................................. 3325
28.7.2 MCANSS_REGS Registers.................................................................................................................................3326
28.7.3 MCAN_REGS Registers......................................................................................................................................3338
28.7.4 MCAN_ERROR_REGS Registers.......................................................................................................................3416
29 Local Interconnect Network (LIN)..................................................................................................................................3442
29.1 LIN Overview..............................................................................................................................................................3443
29.1.1 SCI Features....................................................................................................................................................... 3443
29.1.2 LIN Features........................................................................................................................................................3444
29.1.3 LIN Related Collateral......................................................................................................................................... 3444
29.1.4 Block Diagram..................................................................................................................................................... 3445
29.2 Serial Communications Interface Module.................................................................................................................. 3448
29.2.1 SCI Communication Formats.............................................................................................................................. 3448
29.2.2 SCI Interrupts...................................................................................................................................................... 3458
29.2.3 SCI DMA Interface...............................................................................................................................................3462
29.2.4 SCI Configurations.............................................................................................................................................. 3463
29.2.5 SCI Low-Power Mode..........................................................................................................................................3465
29.3 Local Interconnect Network Module...........................................................................................................................3466
29.3.1 LIN Communication Formats...............................................................................................................................3466
29.3.2 LIN Interrupts.......................................................................................................................................................3485
29.3.3 Servicing LIN Interrupts....................................................................................................................................... 3485
29.3.4 LIN DMA Interface............................................................................................................................................... 3486
29.3.5 LIN Configurations...............................................................................................................................................3486
29.4 Low-Power Mode....................................................................................................................................................... 3488
29.4.1 Entering Sleep Mode........................................................................................................................................... 3489
29.4.2 Wakeup................................................................................................................................................................3489

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29.4.3 Wakeup Timeouts................................................................................................................................................ 3490

29.5 Emulation Mode......................................................................................................................................................... 3490
29.6 Software..................................................................................................................................................................... 3491
29.6.1 LIN Registers to Driverlib Functions.................................................................................................................... 3491
29.6.2 LIN Examples...................................................................................................................................................... 3494
29.7 LIN Registers............................................................................................................................................................. 3496
29.7.1 LIN Base Address Table...................................................................................................................................... 3496
29.7.2 LIN_REGS Registers...........................................................................................................................................3497
30 Configurable Logic Block (CLB)....................................................................................................................................3552
30.1 Introduction................................................................................................................................................................ 3553
30.1.1 CLB Related Collateral........................................................................................................................................ 3553
30.2 Description................................................................................................................................................................. 3553
30.2.1 CLB Clock............................................................................................................................................................3555
30.3 CLB Input/Output Connection.................................................................................................................................... 3557
30.3.1 Overview..............................................................................................................................................................3557
30.3.2 CLB Input Selection.............................................................................................................................................3557
30.3.3 CLB Output Selection.......................................................................................................................................... 3565
30.3.4 CLB Output Signal Multiplexer............................................................................................................................ 3567
30.4 CLB Tile......................................................................................................................................................................3570
30.4.1 Static Switch Block.............................................................................................................................................. 3571
30.4.2 Counter Block...................................................................................................................................................... 3573
30.4.3 FSM Block........................................................................................................................................................... 3577
30.4.4 LUT4 Block.......................................................................................................................................................... 3579
30.4.5 Output LUT Block................................................................................................................................................ 3579
30.4.6 Asynchronous Output Conditioning (AOC) Block................................................................................................ 3580
30.4.7 High Level Controller (HLC)................................................................................................................................ 3583
30.5 CPU Interface.............................................................................................................................................................3588
30.5.1 Register Description............................................................................................................................................ 3588
30.5.2 Non-Memory Mapped Registers..........................................................................................................................3589
30.6 DMA Access...............................................................................................................................................................3589
30.7 CLB Data Export Through SPI RX Buffer...................................................................................................................3590
30.8 Software..................................................................................................................................................................... 3591
30.8.1 CLB Registers to Driverlib Functions...................................................................................................................3591
30.8.2 CLB Examples.....................................................................................................................................................3594
30.9 CLB Registers............................................................................................................................................................ 3600
30.9.1 CLB Base Address Table.....................................................................................................................................3600
30.9.2 CLB_LOGIC_CONFIG_REGS Registers............................................................................................................ 3601
30.9.3 CLB_LOGIC_CONTROL_REGS Registers........................................................................................................ 3653
30.9.4 CLB_DATA_EXCHANGE_REGS Registers........................................................................................................ 3686
31 Advanced Encryption Standard (AES) Accelerator.....................................................................................................3689
31.1 Introduction................................................................................................................................................................ 3690
31.1.1 AES Block Diagram............................................................................................................................................. 3690
31.1.2 AES Algorithm..................................................................................................................................................... 3693
31.2 AES Operating Modes............................................................................................................................................... 3694
31.2.1 GCM Operation................................................................................................................................................... 3694
31.2.2 CCM Operation....................................................................................................................................................3695
31.2.3 XTS Operation.....................................................................................................................................................3696
31.2.4 ECB Feedback Mode.......................................................................................................................................... 3697
31.2.5 CBC Feedback Mode.......................................................................................................................................... 3698
31.2.6 CTR and ICM Feedback Modes.......................................................................................................................... 3699
31.2.7 CFB Mode........................................................................................................................................................... 3700
31.2.8 F8 Mode.............................................................................................................................................................. 3701
31.2.9 F9 Operation........................................................................................................................................................3702
31.2.10 CBC-MAC Operation......................................................................................................................................... 3703
31.3 Extended and Combined Modes of Operations......................................................................................................... 3704
31.3.1 GCM Protocol Operation..................................................................................................................................... 3704
31.3.2 CCM Protocol Operation..................................................................................................................................... 3704
31.3.3 Hardware Requests.............................................................................................................................................3704
31.4 AES Module Programming Guide.............................................................................................................................. 3705
31.4.1 AES Low-Level Programming Models.................................................................................................................3705
31.5 Software..................................................................................................................................................................... 3710

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31.5.1 AES Registers to Driverlib Functions.................................................................................................................. 3710

31.5.2 AES_SS Registers to Driverlib Functions............................................................................................................3712
31.5.3 AES Examples.....................................................................................................................................................3712
31.6 AES Registers............................................................................................................................................................3714
31.6.1 AES Base Address Table.................................................................................................................................... 3714
31.6.2 AES_REGS Registers......................................................................................................................................... 3715
31.6.3 AES_SS_REGS Registers.................................................................................................................................. 3759
32 Embedded Pattern Generator (EPG).............................................................................................................................3762
32.1 Introduction................................................................................................................................................................ 3763
32.1.1 Features.............................................................................................................................................................. 3763
32.1.2 EPG Block Diagram.............................................................................................................................................3763
32.1.3 EPG Related Collateral....................................................................................................................................... 3764
32.2 Clock Generator Modules.......................................................................................................................................... 3765
32.2.1 DCLK (50% duty cycle clock).............................................................................................................................. 3765
32.2.2 Clock Stop........................................................................................................................................................... 3766
32.3 Signal Generator Module........................................................................................................................................... 3767
32.4 EPG Peripheral Signal Mux Selection........................................................................................................................3770
32.5 Application Software Notes........................................................................................................................................ 3772
32.6 EPG Example Use Cases.......................................................................................................................................... 3773
32.6.1 EPG Example: Synchronous Clocks with Offset................................................................................................. 3773
32.6.2 EPG Example: Serial Data Bit Stream (LSB first)............................................................................................... 3774
32.6.3 EPG Example: Serial Data Bit Stream (MSB first).............................................................................................. 3775
32.7 EPG Interrupt............................................................................................................................................................. 3776
32.8 Software..................................................................................................................................................................... 3777
32.8.1 EPG Registers to Driverlib Functions.................................................................................................................. 3777
32.8.2 EPG Examples.................................................................................................................................................... 3778
32.9 EPG Registers........................................................................................................................................................... 3779
32.9.1 EPG Base Address Table.................................................................................................................................... 3779
32.9.2 EPG_REGS Registers.........................................................................................................................................3780
32.9.3 EPG_MUX_REGS Registers...............................................................................................................................3809
33 Revision History............................................................................................................................................................. 3815

List of Figures
Figure 3-1. Device Interrupt Architecture.................................................................................................................................103
Figure 3-2. Interrupt Propagation Path.................................................................................................................................... 105
Figure 3-3. System Error..........................................................................................................................................................110
Figure 3-4. ERRORSTS Pin Diagram...................................................................................................................................... 118
Figure 3-5. Clocking System.................................................................................................................................................... 119
Figure 3-6. System PLL........................................................................................................................................................... 120
Figure 3-7. AUXCLKIN............................................................................................................................................................ 121
Figure 3-8. Single-ended 3.3V External Clock.........................................................................................................................122
Figure 3-9. External Crystal..................................................................................................................................................... 122
Figure 3-10. External Resonator..............................................................................................................................................123
Figure 3-11. Missing Clock Detection Logic.............................................................................................................................132
Figure 3-12. CPU Timers......................................................................................................................................................... 133
Figure 3-13. CPU Timer Interrupt Signals and Output Signal..................................................................................................133
Figure 3-14. Watchdog Timer Module......................................................................................................................................134
Figure 3-15. Memory Architecture........................................................................................................................................... 140
Figure 3-16. Arbitration Scheme on Local Shared Memories..................................................................................................143
Figure 3-17. Arbitration Scheme on Global Shared Memories................................................................................................ 143
Figure 3-18. Simplified LFU Representation............................................................................................................................149
Figure 3-19. PIE Vector Table Swap........................................................................................................................................150
Figure 3-20. LS0/LS1 RAM Memory Swap..............................................................................................................................151
Figure 3-21. TIM Register........................................................................................................................................................180
Figure 3-22. PRD Register...................................................................................................................................................... 181
Figure 3-23. TCR Register.......................................................................................................................................................182
Figure 3-24. TPR Register.......................................................................................................................................................184
Figure 3-25. TPRH Register.................................................................................................................................................... 185
Figure 3-26. PIECTRL Register...............................................................................................................................................188
Figure 3-27. PIEACK Register.................................................................................................................................................189

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Figure 3-28. PIEIER1 Register................................................................................................................................................ 190

Figure 3-29. PIEIFR1 Register................................................................................................................................................ 192
Figure 3-30. PIEIER2 Register................................................................................................................................................ 194
Figure 3-31. PIEIFR2 Register................................................................................................................................................ 196
Figure 3-32. PIEIER3 Register................................................................................................................................................ 198
Figure 3-33. PIEIFR3 Register................................................................................................................................................ 200
Figure 3-34. PIEIER4 Register................................................................................................................................................ 202
Figure 3-35. PIEIFR4 Register................................................................................................................................................ 204
Figure 3-36. PIEIER5 Register................................................................................................................................................ 206
Figure 3-37. PIEIFR5 Register................................................................................................................................................ 208
Figure 3-38. PIEIER6 Register................................................................................................................................................ 210
Figure 3-39. PIEIFR6 Register................................................................................................................................................ 212
Figure 3-40. PIEIER7 Register................................................................................................................................................ 214
Figure 3-41. PIEIFR7 Register................................................................................................................................................ 216
Figure 3-42. PIEIER8 Register................................................................................................................................................ 218
Figure 3-43. PIEIFR8 Register................................................................................................................................................ 220
Figure 3-44. PIEIER9 Register................................................................................................................................................ 222
Figure 3-45. PIEIFR9 Register................................................................................................................................................ 224
Figure 3-46. PIEIER10 Register.............................................................................................................................................. 226
Figure 3-47. PIEIFR10 Register.............................................................................................................................................. 228
Figure 3-48. PIEIER11 Register...............................................................................................................................................230
Figure 3-49. PIEIFR11 Register...............................................................................................................................................232
Figure 3-50. PIEIER12 Register.............................................................................................................................................. 234
Figure 3-51. PIEIFR12 Register.............................................................................................................................................. 236
Figure 3-52. NMICFG Register................................................................................................................................................239
Figure 3-53. NMIFLG Register................................................................................................................................................ 240
Figure 3-54. NMIFLGCLR Register......................................................................................................................................... 242
Figure 3-55. NMIFLGFRC Register......................................................................................................................................... 244
Figure 3-56. NMIWDCNT Register.......................................................................................................................................... 245
Figure 3-57. NMIWDPRD Register..........................................................................................................................................246
Figure 3-58. NMISHDFLG Register.........................................................................................................................................247
Figure 3-59. ERRORSTS Register.......................................................................................................................................... 249
Figure 3-60. ERRORSTSCLR Register...................................................................................................................................250
Figure 3-61. ERRORSTSFRC Register...................................................................................................................................251
Figure 3-62. ERRORCTL Register.......................................................................................................................................... 252
Figure 3-63. ERRORLOCK Register....................................................................................................................................... 253
Figure 3-64. XINT1CR Register...............................................................................................................................................255
Figure 3-65. XINT2CR Register...............................................................................................................................................256
Figure 3-66. XINT3CR Register...............................................................................................................................................257
Figure 3-67. XINT4CR Register...............................................................................................................................................258
Figure 3-68. XINT5CR Register...............................................................................................................................................259
Figure 3-69. XINT1CTR Register............................................................................................................................................ 260
Figure 3-70. XINT2CTR Register............................................................................................................................................ 261
Figure 3-71. XINT3CTR Register............................................................................................................................................ 262
Figure 3-72. SYNCSELECT Register...................................................................................................................................... 264
Figure 3-73. ADCSOCOUTSELECT Register......................................................................................................................... 266
Figure 3-74. SYNCSOCLOCK Register.................................................................................................................................. 269
Figure 3-75. CLA1TASKSRCSELLOCK Register....................................................................................................................271
Figure 3-76. DMACHSRCSELLOCK Register.........................................................................................................................272
Figure 3-77. CLA1TASKSRCSEL1 Register............................................................................................................................273
Figure 3-78. CLA1TASKSRCSEL2 Register............................................................................................................................274
Figure 3-79. DMACHSRCSEL1 Register................................................................................................................................ 275
Figure 3-80. DMACHSRCSEL2 Register................................................................................................................................ 276
Figure 3-81. LFUConfig Register.............................................................................................................................................278
Figure 3-82. LFUStatus Register............................................................................................................................................. 279
Figure 3-83. LFU_LOCK Register........................................................................................................................................... 280
Figure 3-84. LFU_COMMIT Register.......................................................................................................................................281
Figure 3-85. PARTIDL Register............................................................................................................................................... 285
Figure 3-86. PARTIDH Register...............................................................................................................................................287
Figure 3-87. REVID Register................................................................................................................................................... 288
Figure 3-88. TRIMERRSTS Register.......................................................................................................................................289

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Figure 3-89. SOFTPRES0 Register.........................................................................................................................................290

Figure 3-90. SOFTPRES2 Register.........................................................................................................................................291
Figure 3-91. SOFTPRES3 Register.........................................................................................................................................293
Figure 3-92. SOFTPRES4 Register.........................................................................................................................................294
Figure 3-93. SOFTPRES7 Register.........................................................................................................................................295
Figure 3-94. SOFTPRES8 Register.........................................................................................................................................296
Figure 3-95. SOFTPRES9 Register.........................................................................................................................................297
Figure 3-96. SOFTPRES10 Register.......................................................................................................................................298
Figure 3-97. SOFTPRES11 Register....................................................................................................................................... 299
Figure 3-98. SOFTPRES13 Register.......................................................................................................................................300
Figure 3-99. SOFTPRES14 Register.......................................................................................................................................301
Figure 3-100. SOFTPRES15 Register.....................................................................................................................................302
Figure 3-101. SOFTPRES16 Register.....................................................................................................................................303
Figure 3-102. SOFTPRES17 Register.....................................................................................................................................304
Figure 3-103. SOFTPRES18 Register.....................................................................................................................................305
Figure 3-104. SOFTPRES19 Register.....................................................................................................................................306
Figure 3-105. SOFTPRES20 Register.....................................................................................................................................307
Figure 3-106. SOFTPRES21 Register.....................................................................................................................................308
Figure 3-107. SOFTPRES26 Register.....................................................................................................................................309
Figure 3-108. SOFTPRES27 Register.....................................................................................................................................310
Figure 3-109. SOFTPRES28 Register..................................................................................................................................... 311
Figure 3-110. SOFTPRES30 Register..................................................................................................................................... 312
Figure 3-111. SOFTPRES40 Register..................................................................................................................................... 313
Figure 3-112. TAP_STATUS Register...................................................................................................................................... 314
Figure 3-113. TAP_CONTROL Register.................................................................................................................................. 315
Figure 3-114. USBTYPE Register............................................................................................................................................316
Figure 3-115. ECAPTYPE Register......................................................................................................................................... 317
Figure 3-116. MCUCNF3 Register...........................................................................................................................................318
Figure 3-117. MCUCNF8 Register...........................................................................................................................................320
Figure 3-118. MCUCNF11 Register......................................................................................................................................... 321
Figure 3-119. MCUCNF12 Register.........................................................................................................................................322
Figure 3-120. MCUCNF14 Register........................................................................................................................................ 323
Figure 3-121. MCUCNF16 Register........................................................................................................................................ 324
Figure 3-122. MCUCNF18 Register........................................................................................................................................ 325
Figure 3-123. MCUCNF20 Register........................................................................................................................................ 327
Figure 3-124. MCUCNF21 Register........................................................................................................................................ 329
Figure 3-125. MCUCNF23 Register........................................................................................................................................ 330
Figure 3-126. MCUCNF31 Register........................................................................................................................................ 331
Figure 3-127. MCUCNF32 Register........................................................................................................................................ 333
Figure 3-128. MCUCNF33 Register........................................................................................................................................ 335
Figure 3-129. MCUCNF34 Register........................................................................................................................................ 337
Figure 3-130. MCUCNF35 Register........................................................................................................................................ 339
Figure 3-131. MCUCNFLOCK Register...................................................................................................................................340
Figure 3-132. CLKCFGLOCK1 Register..................................................................................................................................343
Figure 3-133. CLKSRCCTL1 Register.....................................................................................................................................345
Figure 3-134. CLKSRCCTL2 Register.....................................................................................................................................347
Figure 3-135. CLKSRCCTL3 Register.....................................................................................................................................348
Figure 3-136. SYSPLLCTL1 Register......................................................................................................................................349
Figure 3-137. SYSPLLMULT Register..................................................................................................................................... 350
Figure 3-138. SYSPLLSTS Register....................................................................................................................................... 351
Figure 3-139. SYSCLKDIVSEL Register................................................................................................................................. 352
Figure 3-140. AUXCLKDIVSEL Register.................................................................................................................................353
Figure 3-141. PERCLKDIVSEL Register.................................................................................................................................354
Figure 3-142. XCLKOUTDIVSEL Register.............................................................................................................................. 355
Figure 3-143. CLBCLKCTL Register....................................................................................................................................... 356
Figure 3-144. LOSPCP Register............................................................................................................................................. 357
Figure 3-145. MCDCR Register...............................................................................................................................................358
Figure 3-146. X1CNT Register................................................................................................................................................ 360
Figure 3-147. XTALCR Register.............................................................................................................................................. 361
Figure 3-148. XTALCR2 Register............................................................................................................................................ 362
Figure 3-149. CLKFAILCFG Register...................................................................................................................................... 363

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Figure 3-150. CPUSYSLOCK1 Register................................................................................................................................. 366

Figure 3-151. CPUSYSLOCK2 Register................................................................................................................................. 369
Figure 3-152. PIEVERRADDR Register.................................................................................................................................. 371
Figure 3-153. PCLKCR0 Register........................................................................................................................................... 372
Figure 3-154. PCLKCR2 Register........................................................................................................................................... 374
Figure 3-155. PCLKCR3 Register........................................................................................................................................... 376
Figure 3-156. PCLKCR4 Register........................................................................................................................................... 377
Figure 3-157. PCLKCR7 Register........................................................................................................................................... 378
Figure 3-158. PCLKCR8 Register........................................................................................................................................... 379
Figure 3-159. PCLKCR9 Register........................................................................................................................................... 380
Figure 3-160. PCLKCR10 Register......................................................................................................................................... 381
Figure 3-161. PCLKCR11 Register..........................................................................................................................................382
Figure 3-162. PCLKCR12 Register......................................................................................................................................... 383
Figure 3-163. PCLKCR13 Register......................................................................................................................................... 384
Figure 3-164. PCLKCR14 Register......................................................................................................................................... 385
Figure 3-165. PCLKCR15 Register......................................................................................................................................... 386
Figure 3-166. PCLKCR16 Register......................................................................................................................................... 387
Figure 3-167. PCLKCR17 Register......................................................................................................................................... 388
Figure 3-168. PCLKCR18 Register......................................................................................................................................... 389
Figure 3-169. PCLKCR19 Register......................................................................................................................................... 390
Figure 3-170. PCLKCR20 Register......................................................................................................................................... 391
Figure 3-171. PCLKCR21 Register......................................................................................................................................... 392
Figure 3-172. PCLKCR26 Register......................................................................................................................................... 393
Figure 3-173. PCLKCR27 Register......................................................................................................................................... 394
Figure 3-174. SIMRESET Register..........................................................................................................................................395
Figure 3-175. LPMCR Register............................................................................................................................................... 396
Figure 3-176. GPIOLPMSEL0 Register...................................................................................................................................397
Figure 3-177. GPIOLPMSEL1 Register...................................................................................................................................400
Figure 3-178. TMR2CLKCTL Register.................................................................................................................................... 403
Figure 3-179. RESCCLR Register...........................................................................................................................................404
Figure 3-180. RESC Register.................................................................................................................................................. 406
Figure 3-181. CMPSSLPMSEL Register................................................................................................................................. 408
Figure 3-182. MCANRAMACC Register..................................................................................................................................410
Figure 3-183. MCANWAKESTATUS Register..........................................................................................................................411
Figure 3-184. MCANWAKESTATUSCLR Register.................................................................................................................. 412
Figure 3-185. CLKSTOPREQ Register....................................................................................................................................413
Figure 3-186. CLKSTOPACK Register.................................................................................................................................... 414
Figure 3-187. USER_REG1_SYSRSn Register...................................................................................................................... 415
Figure 3-188. USER_REG2_SYSRSn Register...................................................................................................................... 416
Figure 3-189. USER_REG1_XRSn Register...........................................................................................................................417
Figure 3-190. USER_REG2_XRSn Register...........................................................................................................................418
Figure 3-191. USER_REG1_PORESETn Register................................................................................................................. 419
Figure 3-192. USER_REG2_PORESETn Register................................................................................................................. 420
Figure 3-193. USER_REG3_PORESETn Register................................................................................................................. 421
Figure 3-194. USER_REG4_PORESETn Register................................................................................................................. 422
Figure 3-195. JTAG_MMR_REG Register...............................................................................................................................423
Figure 3-196. SYS_ERR_INT_FLG Register.......................................................................................................................... 425
Figure 3-197. SYS_ERR_INT_CLR Register.......................................................................................................................... 427
Figure 3-198. SYS_ERR_INT_SET Register.......................................................................................................................... 429
Figure 3-199. SYS_ERR_MASK Register............................................................................................................................... 431
Figure 3-200. ADCA_AC Register........................................................................................................................................... 435
Figure 3-201. ADCB_AC Register........................................................................................................................................... 436
Figure 3-202. ADCC_AC Register...........................................................................................................................................437
Figure 3-203. ADCD_AC Register...........................................................................................................................................438
Figure 3-204. ADCE_AC Register........................................................................................................................................... 439
Figure 3-205. CMPSS1_AC Register...................................................................................................................................... 440
Figure 3-206. CMPSS2_AC Register...................................................................................................................................... 441
Figure 3-207. CMPSS3_AC Register...................................................................................................................................... 442
Figure 3-208. CMPSS4_AC Register...................................................................................................................................... 443
Figure 3-209. DACA_AC Register........................................................................................................................................... 444
Figure 3-210. PGA1_AC Register........................................................................................................................................... 445

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Figure 3-211. PGA2_AC Register............................................................................................................................................446

Figure 3-212. PGA3_AC Register........................................................................................................................................... 447
Figure 3-213. EPWM1_AC Register........................................................................................................................................448
Figure 3-214. EPWM2_AC Register........................................................................................................................................449
Figure 3-215. EPWM3_AC Register........................................................................................................................................450
Figure 3-216. EPWM4_AC Register........................................................................................................................................451
Figure 3-217. EPWM5_AC Register........................................................................................................................................452
Figure 3-218. EPWM6_AC Register........................................................................................................................................453
Figure 3-219. EPWM7_AC Register........................................................................................................................................454
Figure 3-220. EPWM8_AC Register........................................................................................................................................455
Figure 3-221. EPWM9_AC Register........................................................................................................................................456
Figure 3-222. EPWM10_AC Register......................................................................................................................................457
Figure 3-223. EPWM11_AC Register...................................................................................................................................... 458
Figure 3-224. EPWM12_AC Register......................................................................................................................................459
Figure 3-225. EQEP1_AC Register......................................................................................................................................... 460
Figure 3-226. EQEP2_AC Register......................................................................................................................................... 461
Figure 3-227. EQEP3_AC Register......................................................................................................................................... 462
Figure 3-228. ECAP1_AC Register......................................................................................................................................... 463
Figure 3-229. ECAP2_AC Register......................................................................................................................................... 464
Figure 3-230. CLB1_AC Register............................................................................................................................................ 465
Figure 3-231. CLB2_AC Register............................................................................................................................................ 466
Figure 3-232. SCIA_AC Register.............................................................................................................................................467
Figure 3-233. SCIB_AC Register.............................................................................................................................................468
Figure 3-234. SCIC_AC Register............................................................................................................................................ 469
Figure 3-235. SPIA_AC Register.............................................................................................................................................470
Figure 3-236. SPIB_AC Register.............................................................................................................................................471
Figure 3-237. I2CA_AC Register............................................................................................................................................. 472
Figure 3-238. I2CB_AC Register............................................................................................................................................. 473
Figure 3-239. PMBUS_A_AC Register....................................................................................................................................474
Figure 3-240. LIN_A_AC Register........................................................................................................................................... 475
Figure 3-241. MCANA_AC Register........................................................................................................................................ 476
Figure 3-242. MCANB_AC Register........................................................................................................................................ 477
Figure 3-243. FSIATX_AC Register.........................................................................................................................................478
Figure 3-244. FSIARX_AC Register........................................................................................................................................ 479
Figure 3-245. USBA_AC Register........................................................................................................................................... 480
Figure 3-246. HRPWM_A_AC Register...................................................................................................................................481
Figure 3-247. AESA_AC Register........................................................................................................................................... 482
Figure 3-248. PERIPH_AC_LOCK Register............................................................................................................................483
Figure 3-249. DxLOCK Register..............................................................................................................................................486
Figure 3-250. DxCOMMIT Register......................................................................................................................................... 487
Figure 3-251. DxACCPROT0 Register.................................................................................................................................... 488
Figure 3-252. DxACCPROT1 Register.................................................................................................................................... 489
Figure 3-253. DxTEST Register.............................................................................................................................................. 490
Figure 3-254. DxINIT Register.................................................................................................................................................491
Figure 3-255. DxINITDONE Register...................................................................................................................................... 492
Figure 3-256. DxRAMTEST_LOCK Register...........................................................................................................................493
Figure 3-257. LSxLOCK Register............................................................................................................................................ 494
Figure 3-258. LSxCOMMIT Register....................................................................................................................................... 496
Figure 3-259. LSxMSEL Register............................................................................................................................................ 498
Figure 3-260. LSxCLAPGM Register.......................................................................................................................................500
Figure 3-261. LSxACCPROT0 Register.................................................................................................................................. 502
Figure 3-262. LSxACCPROT1 Register.................................................................................................................................. 504
Figure 3-263. LSxACCPROT2_y Register.............................................................................................................................. 506
Figure 3-264. LSxTEST Register.............................................................................................................................................507
Figure 3-265. LSxINIT Register............................................................................................................................................... 510
Figure 3-266. LSxINITDONE Register.....................................................................................................................................512
Figure 3-267. LSxRAMTEST_LOCK Register.........................................................................................................................513
Figure 3-268. GSxLOCK Register........................................................................................................................................... 514
Figure 3-269. GSxCOMMIT Register...................................................................................................................................... 516
Figure 3-270. GSxACCPROT0 Register................................................................................................................................. 518
Figure 3-271. GSxTEST Register............................................................................................................................................520

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 23

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Figure 3-272. GSxINIT Register.............................................................................................................................................. 522

Figure 3-273. GSxINITDONE Register....................................................................................................................................524
Figure 3-274. GSxRAMTEST_LOCK Register........................................................................................................................ 526
Figure 3-275. MSGxLOCK Register........................................................................................................................................ 527
Figure 3-276. MSGxCOMMIT Register................................................................................................................................... 529
Figure 3-277. MSGxTEST Register.........................................................................................................................................531
Figure 3-278. MSGxINIT Register........................................................................................................................................... 533
Figure 3-279. MSGxINITDONE Register.................................................................................................................................534
Figure 3-280. MSGxRAMTEST_LOCK Register..................................................................................................................... 535
Figure 3-281. ROM_LOCK Register........................................................................................................................................536
Figure 3-282. ROM_TEST Register........................................................................................................................................ 537
Figure 3-283. ROM_FORCE_ERROR Register...................................................................................................................... 538
Figure 3-284. NMAVFLG Register........................................................................................................................................... 541
Figure 3-285. NMAVSET Register........................................................................................................................................... 543
Figure 3-286. NMAVCLR Register...........................................................................................................................................545
Figure 3-287. NMAVINTEN Register....................................................................................................................................... 547
Figure 3-288. NMCPURDAVADDR Register........................................................................................................................... 549
Figure 3-289. NMCPUWRAVADDR Register.......................................................................................................................... 550
Figure 3-290. NMCPUFAVADDR Register.............................................................................................................................. 551
Figure 3-291. NMDMAWRAVADDR Register.......................................................................................................................... 552
Figure 3-292. NMCLA1RDAVADDR Register..........................................................................................................................553
Figure 3-293. NMCLA1WRAVADDR Register......................................................................................................................... 554
Figure 3-294. NMCLA1FAVADDR Register............................................................................................................................. 555
Figure 3-295. NMDMARDAVADDR Register...........................................................................................................................556
Figure 3-296. MAVFLG Register..............................................................................................................................................557
Figure 3-297. MAVSET Register..............................................................................................................................................558
Figure 3-298. MAVCLR Register............................................................................................................................................. 559
Figure 3-299. MAVINTEN Register..........................................................................................................................................560
Figure 3-300. MCPUFAVADDR Register................................................................................................................................. 561
Figure 3-301. MCPUWRAVADDR Register............................................................................................................................. 562
Figure 3-302. MDMAWRAVADDR Register.............................................................................................................................563
Figure 3-303. NMNPURDAVADDR Register........................................................................................................................... 564
Figure 3-304. NMNPUWRAVADDR Register.......................................................................................................................... 565
Figure 3-305. UCERRFLG Register........................................................................................................................................ 568
Figure 3-306. UCERRSET Register........................................................................................................................................ 569
Figure 3-307. UCERRCLR Register........................................................................................................................................ 570
Figure 3-308. UCCPUREADDR Register................................................................................................................................ 571
Figure 3-309. UCDMAREADDR Register................................................................................................................................572
Figure 3-310. UCCLA1READDR Register...............................................................................................................................573
Figure 3-311. UCNPUREADDR Register................................................................................................................................ 574
Figure 3-312. FLUCERRSTATUS Register............................................................................................................................. 575
Figure 3-313. FLCERRSTATUS Register................................................................................................................................ 576
Figure 3-314. CERRFLG Register...........................................................................................................................................578
Figure 3-315. CERRSET Register...........................................................................................................................................579
Figure 3-316. CERRCLR Register...........................................................................................................................................580
Figure 3-317. CCPUREADDR Register...................................................................................................................................581
Figure 3-318. CDMAREADDR Register.................................................................................................................................. 582
Figure 3-319. CCLA1READDR Register................................................................................................................................. 583
Figure 3-320. CERRCNT Register.......................................................................................................................................... 584
Figure 3-321. CERRTHRES Register......................................................................................................................................585
Figure 3-322. CEINTFLG Register.......................................................................................................................................... 586
Figure 3-323. CEINTCLR Register.......................................................................................................................................... 587
Figure 3-324. CEINTSET Register.......................................................................................................................................... 588
Figure 3-325. CEINTEN Register............................................................................................................................................ 589
Figure 3-326. CPU_RAM_TEST_ERROR_STS Register....................................................................................................... 591
Figure 3-327. CPU_RAM_TEST_ERROR_STS_CLR Register.............................................................................................. 592
Figure 3-328. CPU_RAM_TEST_ERROR_ADDR Register.................................................................................................... 593
Figure 3-329. UID_PSRAND0 Register...................................................................................................................................595
Figure 3-330. UID_PSRAND1 Register...................................................................................................................................596
Figure 3-331. UID_PSRAND2 Register...................................................................................................................................597
Figure 3-332. UID_PSRAND3 Register...................................................................................................................................598

24 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 3-333. UID_PSRAND4 Register...................................................................................................................................599

Figure 3-334. UID_UNIQUE0 Register....................................................................................................................................600
Figure 3-335. UID_UNIQUE1 Register....................................................................................................................................601
Figure 3-336. UID_CHECKSUM Register............................................................................................................................... 602
Figure 4-1. Device Boot Flow.................................................................................................................................................. 612
Figure 4-2. Emulation Boot Flow............................................................................................................................................. 613
Figure 4-3. CPU Standalone Boot Flow...................................................................................................................................614
Figure 4-4. Overview of SCI Bootloader Operation................................................................................................................. 626
Figure 4-5. Overview of SCI Boot Function............................................................................................................................. 627
Figure 4-6. Overview of SPI Bootloader Operation................................................................................................................. 628
Figure 4-7. Data Transfer from EEPROM Flow....................................................................................................................... 630
Figure 4-8. EEPROM Device at Address 0x50........................................................................................................................631
Figure 4-9. Overview of I2C Boot Function..............................................................................................................................632
Figure 4-10. Random Read..................................................................................................................................................... 633
Figure 4-11. Sequential Read.................................................................................................................................................. 633
Figure 4-12. Overview of Parallel GPIO Bootloader Operation............................................................................................... 634
Figure 4-13. Parallel GPIO Bootloader Handshake Protocol...................................................................................................635
Figure 4-14. Overview of Parallel GPIO Boot Function........................................................................................................... 635
Figure 4-15. Parallel GPIO Mode - Host Transfer Flow........................................................................................................... 636
Figure 4-16. 8-Bit Parallel GetWord Function.......................................................................................................................... 637
Figure 4-17. Overview of CAN-A Bootloader Operation.......................................................................................................... 638
Figure 4-18. USB Boot Flow.................................................................................................................................................... 641
Figure 5-1. Storage of Zone-Select Bits in OTP...................................................................................................................... 658
Figure 5-2. Location of Zone-Select Block Based on Link-Pointer.......................................................................................... 659
Figure 5-3. CSM Password Match Flow (PMF)....................................................................................................................... 664
Figure 5-4. ECSL Password Match Flow (PMF)......................................................................................................................666
Figure 5-5. Z1_LINKPOINTER Register..................................................................................................................................675
Figure 5-6. Z1_OTPSECLOCK Register................................................................................................................................. 676
Figure 5-7. Z1_JLM_ENABLE Register...................................................................................................................................677
Figure 5-8. Z1_LINKPOINTERERR Register.......................................................................................................................... 678
Figure 5-9. Z1_GPREG1 Register...........................................................................................................................................679
Figure 5-10. Z1_GPREG2 Register.........................................................................................................................................680
Figure 5-11. Z1_GPREG3 Register......................................................................................................................................... 681
Figure 5-12. Z1_GPREG4 Register.........................................................................................................................................682
Figure 5-13. Z1_CSMKEY0 Register.......................................................................................................................................683
Figure 5-14. Z1_CSMKEY1 Register.......................................................................................................................................684
Figure 5-15. Z1_CSMKEY2 Register.......................................................................................................................................685
Figure 5-16. Z1_CSMKEY3 Register.......................................................................................................................................686
Figure 5-17. Z1_CR Register...................................................................................................................................................687
Figure 5-18. Z1_GRABSECT1R Register............................................................................................................................... 689
Figure 5-19. Z1_GRABSECT2R Register............................................................................................................................... 693
Figure 5-20. Z1_GRABSECT3R Register............................................................................................................................... 697
Figure 5-21. Z1_GRABRAM1R Register................................................................................................................................. 699
Figure 5-22. Z1_EXEONLYSECT1R Register......................................................................................................................... 702
Figure 5-23. Z1_EXEONLYSECT2R Register......................................................................................................................... 708
Figure 5-24. Z1_EXEONLYRAM1R Register...........................................................................................................................710
Figure 5-25. Z1_JTAGKEY0 Register......................................................................................................................................712
Figure 5-26. Z1_JTAGKEY1 Register......................................................................................................................................713
Figure 5-27. Z1_JTAGKEY2 Register......................................................................................................................................714
Figure 5-28. Z1_JTAGKEY3 Register......................................................................................................................................715
Figure 5-29. Z1_CMACKEY0 Register.................................................................................................................................... 716
Figure 5-30. Z1_CMACKEY1 Register.................................................................................................................................... 717
Figure 5-31. Z1_CMACKEY2 Register.................................................................................................................................... 718
Figure 5-32. Z1_CMACKEY3 Register.................................................................................................................................... 719
Figure 5-33. Z1_DIAG Register............................................................................................................................................... 720
Figure 5-34. Z2_LINKPOINTER Register................................................................................................................................722
Figure 5-35. Z2_OTPSECLOCK Register............................................................................................................................... 723
Figure 5-36. Z2_LINKPOINTERERR Register........................................................................................................................ 724
Figure 5-37. Z2_GPREG1 Register.........................................................................................................................................725
Figure 5-38. Z2_GPREG2 Register.........................................................................................................................................726
Figure 5-39. Z2_GPREG3 Register.........................................................................................................................................727

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 25

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Figure 5-40. Z2_GPREG4 Register.........................................................................................................................................728

Figure 5-41. Z2_CSMKEY0 Register.......................................................................................................................................729
Figure 5-42. Z2_CSMKEY1 Register.......................................................................................................................................730
Figure 5-43. Z2_CSMKEY2 Register.......................................................................................................................................731
Figure 5-44. Z2_CSMKEY3 Register.......................................................................................................................................732
Figure 5-45. Z2_CR Register...................................................................................................................................................733
Figure 5-46. Z2_GRABSECT1R Register............................................................................................................................... 735
Figure 5-47. Z2_GRABSECT2R Register............................................................................................................................... 739
Figure 5-48. Z2_GRABSECT3R Register............................................................................................................................... 743
Figure 5-49. Z2_GRABRAM1R Register................................................................................................................................. 745
Figure 5-50. Z2_EXEONLYSECT1R Register......................................................................................................................... 748
Figure 5-51. Z2_EXEONLYSECT2R Register......................................................................................................................... 754
Figure 5-52. Z2_EXEONLYRAM1R Register...........................................................................................................................756
Figure 5-53. FLSEM Register.................................................................................................................................................. 759
Figure 5-54. SECTSTAT1 Register..........................................................................................................................................760
Figure 5-55. SECTSTAT2 Register..........................................................................................................................................763
Figure 5-56. SECTSTAT3 Register..........................................................................................................................................766
Figure 5-57. RAMSTAT1 Register........................................................................................................................................... 768
Figure 5-58. SECERRSTAT Register...................................................................................................................................... 770
Figure 5-59. SECERRCLR Register........................................................................................................................................771
Figure 5-60. SECERRFRC Register........................................................................................................................................772
Figure 5-61. DENYCODE Register..........................................................................................................................................773
Figure 5-62. UID_UNIQUE_31_0 Register..............................................................................................................................775
Figure 5-63. UID_UNIQUE_63_32 Register............................................................................................................................776
Figure 5-64. PARTIDH Register...............................................................................................................................................777
Figure 5-65. PERSEM1 Register.............................................................................................................................................778
Figure 5-66. Z1OTP_LINKPOINTER1 Register...................................................................................................................... 781
Figure 5-67. Z1OTP_LINKPOINTER2 Register...................................................................................................................... 782
Figure 5-68. Z1OTP_LINKPOINTER3 Register...................................................................................................................... 783
Figure 5-69. Z1OTP_JLM_ENABLE Register......................................................................................................................... 784
Figure 5-70. Z1OTP_GPREG1 Register................................................................................................................................. 785
Figure 5-71. Z1OTP_GPREG2 Register................................................................................................................................. 786
Figure 5-72. Z1OTP_GPREG3 Register................................................................................................................................. 787
Figure 5-73. Z1OTP_GPREG4 Register................................................................................................................................. 788
Figure 5-74. Z1OTP_PSWDLOCK Register............................................................................................................................789
Figure 5-75. Z1OTP_CRCLOCK Register...............................................................................................................................790
Figure 5-76. Z1OTP_JTAGPSWDH0 Register........................................................................................................................ 791
Figure 5-77. Z1OTP_JTAGPSWDH1 Register........................................................................................................................ 792
Figure 5-78. Z1OTP_CMACKEY0 Register.............................................................................................................................793
Figure 5-79. Z1OTP_CMACKEY1 Register.............................................................................................................................794
Figure 5-80. Z1OTP_CMACKEY2 Register.............................................................................................................................795
Figure 5-81. Z1OTP_CMACKEY3 Register.............................................................................................................................796
Figure 5-82. Z2OTP_LINKPOINTER1 Register...................................................................................................................... 798
Figure 5-83. Z2OTP_LINKPOINTER2 Register...................................................................................................................... 799
Figure 5-84. Z2OTP_LINKPOINTER3 Register...................................................................................................................... 800
Figure 5-85. Z2OTP_GPREG1 Register................................................................................................................................. 801
Figure 5-86. Z2OTP_GPREG2 Register................................................................................................................................. 802
Figure 5-87. Z2OTP_GPREG3 Register................................................................................................................................. 803
Figure 5-88. Z2OTP_GPREG4 Register................................................................................................................................. 804
Figure 5-89. Z2OTP_PSWDLOCK Register............................................................................................................................805
Figure 5-90. Z2OTP_CRCLOCK Register...............................................................................................................................806
Figure 6-1. Flash Interface Block Diagram.............................................................................................................................. 810
Figure 6-2. Flash Prefetch Mode............................................................................................................................................. 812
Figure 6-3. ECC Logic Inputs and Outputs..............................................................................................................................815
Figure 6-4. Testing ECC Logic.................................................................................................................................................818
Figure 6-5. FRDCNTL Register............................................................................................................................................... 823
Figure 6-6. FLPROT Register..................................................................................................................................................824
Figure 6-7. FRD_INTF_CTRL Register................................................................................................................................... 825
Figure 6-8. ECC_ENABLE Register........................................................................................................................................ 827
Figure 6-9. FECC_CTRL Register...........................................................................................................................................828
Figure 7-1. CLA Block Diagram............................................................................................................................................... 831

26 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 7-2. _MVECTBGRNDACTIVE Register....................................................................................................................... 990

Figure 7-3. _MPSACTL Register............................................................................................................................................. 991
Figure 7-4. _MPSA1 Register..................................................................................................................................................993
Figure 7-5. _MPSA2 Register..................................................................................................................................................994
Figure 7-6. SOFTINTEN Register............................................................................................................................................995
Figure 7-7. SOFTINTFRC Register......................................................................................................................................... 997
Figure 7-8. SOFTINTEN Register............................................................................................................................................999
Figure 7-9. SOFTINTFRC Register....................................................................................................................................... 1001
Figure 7-10. MVECT1 Register............................................................................................................................................. 1004
Figure 7-11. MVECT2 Register..............................................................................................................................................1005
Figure 7-12. MVECT3 Register............................................................................................................................................. 1006
Figure 7-13. MVECT4 Register............................................................................................................................................. 1007
Figure 7-14. MVECT5 Register............................................................................................................................................. 1008
Figure 7-15. MVECT6 Register............................................................................................................................................. 1009
Figure 7-16. MVECT7 Register............................................................................................................................................. 1010
Figure 7-17. MVECT8 Register..............................................................................................................................................1011
Figure 7-18. MCTL Register.................................................................................................................................................. 1012
Figure 7-19. _MVECTBGRNDACTIVE Register................................................................................................................... 1013
Figure 7-20. SOFTINTEN Register........................................................................................................................................1014
Figure 7-21. _MSTSBGRND Register................................................................................................................................... 1016
Figure 7-22. _MCTLBGRND Register................................................................................................................................... 1017
Figure 7-23. _MVECTBGRND Register................................................................................................................................ 1018
Figure 7-24. MIFR Register................................................................................................................................................... 1019
Figure 7-25. MIOVF Register.................................................................................................................................................1023
Figure 7-26. MIFRC Register.................................................................................................................................................1026
Figure 7-27. MICLR Register.................................................................................................................................................1028
Figure 7-28. MICLROVF Register......................................................................................................................................... 1030
Figure 7-29. MIER Register................................................................................................................................................... 1032
Figure 7-30. MIRUN Register................................................................................................................................................ 1035
Figure 7-31. _MPC Register.................................................................................................................................................. 1037
Figure 7-32. _MAR0 Register................................................................................................................................................ 1038
Figure 7-33. _MAR1 Register................................................................................................................................................ 1039
Figure 7-34. _MSTF Register................................................................................................................................................ 1040
Figure 7-35. _MR0 Register.................................................................................................................................................. 1043
Figure 7-36. _MR1 Register.................................................................................................................................................. 1044
Figure 7-37. _MR2 Register.................................................................................................................................................. 1045
Figure 7-38. _MR3 Register.................................................................................................................................................. 1046
Figure 7-39. _MPSACTL Register......................................................................................................................................... 1047
Figure 7-40. _MPSA1 Register..............................................................................................................................................1049
Figure 7-41. _MPSA2 Register..............................................................................................................................................1050
Figure 8-1. NPU Development Flow ..................................................................................................................................... 1052
Figure 9-1. DCC Module Overview........................................................................................................................................1054
Figure 9-2. DCC Operation....................................................................................................................................................1055
Figure 9-3. Counter Relationship...........................................................................................................................................1059
Figure 9-4. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting...............................................................1059
Figure 9-5. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting............................................................... 1060
Figure 9-6. Clock1 Not Present - Results in an Error and Stops Counting............................................................................1060
Figure 9-7. Clock0 Not Present - Results in an Error and Stops Counting............................................................................1061
Figure 9-8. DCCGCTRL Register.......................................................................................................................................... 1066
Figure 9-9. DCCCNTSEED0 Register................................................................................................................................... 1067
Figure 9-10. DCCVALIDSEED0 Register.............................................................................................................................. 1068
Figure 9-11. DCCCNTSEED1 Register................................................................................................................................. 1069
Figure 9-12. DCCSTATUS Register.......................................................................................................................................1070
Figure 9-13. DCCCNT0 Register...........................................................................................................................................1071
Figure 9-14. DCCVALID0 Register........................................................................................................................................ 1072
Figure 9-15. DCCCNT1 Register...........................................................................................................................................1073
Figure 9-16. DCCCLKSRC1 Register....................................................................................................................................1074
Figure 9-17. DCCCLKSRC0 Register....................................................................................................................................1075
Figure 10-1. GPIO Logic for a Single Pin.............................................................................................................................. 1078
Figure 10-2. Analog Subsystem Block Diagram with AGPIO Implementation.......................................................................1081
Figure 10-3. Input Qualification Using a Sampling Window...................................................................................................1084

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Figure 10-4. Input Qualifier Clock Cycles.............................................................................................................................. 1086

Figure 10-5. GPACTRL Register............................................................................................................................................1106
Figure 10-6. GPAQSEL1 Register......................................................................................................................................... 1107
Figure 10-7. GPAQSEL2 Register..........................................................................................................................................1110
Figure 10-8. GPAMUX1 Register........................................................................................................................................... 1113
Figure 10-9. GPAMUX2 Register........................................................................................................................................... 1115
Figure 10-10. GPADIR Register............................................................................................................................................. 1117
Figure 10-11. GPAPUD Register............................................................................................................................................ 1119
Figure 10-12. GPAINV Register............................................................................................................................................. 1121
Figure 10-13. GPAODR Register........................................................................................................................................... 1123
Figure 10-14. GPAAMSEL Register.......................................................................................................................................1125
Figure 10-15. GPAGMUX1 Register...................................................................................................................................... 1127
Figure 10-16. GPAGMUX2 Register...................................................................................................................................... 1129
Figure 10-17. GPACSEL1 Register........................................................................................................................................1131
Figure 10-18. GPACSEL2 Register........................................................................................................................................1132
Figure 10-19. GPACSEL3 Register........................................................................................................................................1133
Figure 10-20. GPACSEL4 Register........................................................................................................................................1134
Figure 10-21. GPALOCK Register......................................................................................................................................... 1135
Figure 10-22. GPACR Register..............................................................................................................................................1137
Figure 10-23. GPBCTRL Register......................................................................................................................................... 1139
Figure 10-24. GPBQSEL1 Register....................................................................................................................................... 1140
Figure 10-25. GPBQSEL2 Register....................................................................................................................................... 1142
Figure 10-26. GPBMUX1 Register.........................................................................................................................................1145
Figure 10-27. GPBMUX2 Register.........................................................................................................................................1146
Figure 10-28. GPBDIR Register.............................................................................................................................................1148
Figure 10-29. GPBPUD Register........................................................................................................................................... 1150
Figure 10-30. GPBINV Register.............................................................................................................................................1152
Figure 10-31. GPBODR Register...........................................................................................................................................1154
Figure 10-32. GPBAMSEL Register.......................................................................................................................................1156
Figure 10-33. GPBGMUX1 Register...................................................................................................................................... 1158
Figure 10-34. GPBGMUX2 Register...................................................................................................................................... 1159
Figure 10-35. GPBCSEL1 Register....................................................................................................................................... 1161
Figure 10-36. GPBCSEL2 Register....................................................................................................................................... 1162
Figure 10-37. GPBCSEL3 Register....................................................................................................................................... 1163
Figure 10-38. GPBCSEL4 Register....................................................................................................................................... 1164
Figure 10-39. GPBLOCK Register......................................................................................................................................... 1165
Figure 10-40. GPBCR Register..............................................................................................................................................1167
Figure 10-41. GPCCTRL Register......................................................................................................................................... 1169
Figure 10-42. GPCQSEL1 Register....................................................................................................................................... 1170
Figure 10-43. GPCQSEL2 Register....................................................................................................................................... 1173
Figure 10-44. GPCMUX1 Register.........................................................................................................................................1174
Figure 10-45. GPCMUX2 Register.........................................................................................................................................1176
Figure 10-46. GPCDIR Register............................................................................................................................................ 1177
Figure 10-47. GPCPUD Register........................................................................................................................................... 1179
Figure 10-48. GPCINV Register.............................................................................................................................................1181
Figure 10-49. GPCODR Register...........................................................................................................................................1183
Figure 10-50. GPCAMSEL Register...................................................................................................................................... 1185
Figure 10-51. GPCGMUX1 Register......................................................................................................................................1187
Figure 10-52. GPCGMUX2 Register......................................................................................................................................1189
Figure 10-53. GPCCSEL1 Register....................................................................................................................................... 1190
Figure 10-54. GPCCSEL2 Register....................................................................................................................................... 1191
Figure 10-55. GPCCSEL3 Register....................................................................................................................................... 1192
Figure 10-56. GPCLOCK Register.........................................................................................................................................1193
Figure 10-57. GPCCR Register............................................................................................................................................. 1195
Figure 10-58. GPGCTRL Register......................................................................................................................................... 1197
Figure 10-59. GPGQSEL2 Register.......................................................................................................................................1198
Figure 10-60. GPGMUX2 Register........................................................................................................................................ 1200
Figure 10-61. GPGDIR Register............................................................................................................................................1202
Figure 10-62. GPGPUD Register.......................................................................................................................................... 1204
Figure 10-63. GPGINV Register............................................................................................................................................ 1206
Figure 10-64. GPGODR Register.......................................................................................................................................... 1208

28 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 10-65. GPGAMSEL Register......................................................................................................................................1210

Figure 10-66. GPGGMUX2 Register..................................................................................................................................... 1213
Figure 10-67. GPGCSEL3 Register.......................................................................................................................................1215
Figure 10-68. GPGLOCK Register........................................................................................................................................ 1216
Figure 10-69. GPGCR Register.............................................................................................................................................1218
Figure 10-70. GPHCTRL Register.........................................................................................................................................1220
Figure 10-71. GPHQSEL1 Register.......................................................................................................................................1221
Figure 10-72. GPHQSEL2 Register.......................................................................................................................................1223
Figure 10-73. GPHMUX1 Register........................................................................................................................................ 1225
Figure 10-74. GPHMUX2 Register........................................................................................................................................ 1227
Figure 10-75. GPHDIR Register............................................................................................................................................ 1229
Figure 10-76. GPHPUD Register...........................................................................................................................................1231
Figure 10-77. GPHINV Register............................................................................................................................................ 1237
Figure 10-78. GPHODR Register.......................................................................................................................................... 1241
Figure 10-79. GPHAMSEL Register...................................................................................................................................... 1243
Figure 10-80. GPHGMUX1 Register..................................................................................................................................... 1249
Figure 10-81. GPHGMUX2 Register..................................................................................................................................... 1251
Figure 10-82. GPHCSEL1 Register.......................................................................................................................................1253
Figure 10-83. GPHCSEL2 Register.......................................................................................................................................1254
Figure 10-84. GPHCSEL3 Register.......................................................................................................................................1255
Figure 10-85. GPHCSEL4 Register.......................................................................................................................................1256
Figure 10-86. GPHLOCK Register........................................................................................................................................ 1257
Figure 10-87. GPHCR Register............................................................................................................................................. 1261
Figure 10-88. GPADAT Register............................................................................................................................................1266
Figure 10-89. GPASET Register............................................................................................................................................1268
Figure 10-90. GPACLEAR Register.......................................................................................................................................1270
Figure 10-91. GPATOGGLE Register.................................................................................................................................... 1272
Figure 10-92. GPBDAT Register............................................................................................................................................1274
Figure 10-93. GPBSET Register........................................................................................................................................... 1276
Figure 10-94. GPBCLEAR Register...................................................................................................................................... 1278
Figure 10-95. GPBTOGGLE Register....................................................................................................................................1280
Figure 10-96. GPCDAT Register........................................................................................................................................... 1282
Figure 10-97. GPCSET Register........................................................................................................................................... 1284
Figure 10-98. GPCCLEAR Register...................................................................................................................................... 1286
Figure 10-99. GPCTOGGLE Register................................................................................................................................... 1288
Figure 10-100. GPGDAT Register......................................................................................................................................... 1290
Figure 10-101. GPGSET Register......................................................................................................................................... 1292
Figure 10-102. GPGCLEAR Register.................................................................................................................................... 1294
Figure 10-103. GPGTOGGLE Register................................................................................................................................. 1296
Figure 10-104. GPHDAT Register......................................................................................................................................... 1298
Figure 10-105. GPHSET Register......................................................................................................................................... 1305
Figure 10-106. GPHCLEAR Register.................................................................................................................................... 1307
Figure 10-107. GPHTOGGLE Register................................................................................................................................. 1309
Figure 10-108. GPADAT_R Register..................................................................................................................................... 1312
Figure 10-109. GPBDAT_R Register..................................................................................................................................... 1313
Figure 10-110. GPCDAT_R Register..................................................................................................................................... 1314
Figure 10-111. GPGDAT_R Register..................................................................................................................................... 1315
Figure 10-112. GPHDAT_R Register..................................................................................................................................... 1316
Figure 11-1. Input X-BAR.......................................................................................................................................................1319
Figure 11-2. ePWM X-BAR Architecture - Single Output.......................................................................................................1322
Figure 11-3. CLB X-BAR Architecture - Single Output...........................................................................................................1324
Figure 11-4. GPIO to CLB Tile Connections.......................................................................................................................... 1325
Figure 11-5. GPIO Output X-BAR Architecture......................................................................................................................1327
Figure 11-6. X-BAR Input Sources.........................................................................................................................................1329
Figure 11-7. INPUT1SELECT Register..................................................................................................................................1338
Figure 11-8. INPUT2SELECT Register..................................................................................................................................1339
Figure 11-9. INPUT3SELECT Register..................................................................................................................................1340
Figure 11-10. INPUT4SELECT Register................................................................................................................................1341
Figure 11-11. INPUT5SELECT Register................................................................................................................................1342
Figure 11-12. INPUT6SELECT Register................................................................................................................................1343
Figure 11-13. INPUT7SELECT Register................................................................................................................................1344

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Figure 11-14. INPUT8SELECT Register................................................................................................................................1345

Figure 11-15. INPUT9SELECT Register................................................................................................................................1346
Figure 11-16. INPUT10SELECT Register..............................................................................................................................1347
Figure 11-17. INPUT11SELECT Register..............................................................................................................................1348
Figure 11-18. INPUT12SELECT Register..............................................................................................................................1349
Figure 11-19. INPUT13SELECT Register..............................................................................................................................1350
Figure 11-20. INPUT14SELECT Register..............................................................................................................................1351
Figure 11-21. INPUT15SELECT Register..............................................................................................................................1352
Figure 11-22. INPUT16SELECT Register..............................................................................................................................1353
Figure 11-23. INPUTSELECTLOCK Register........................................................................................................................1354
Figure 11-24. XBARFLG1 Register........................................................................................................................................1357
Figure 11-25. XBARFLG2 Register........................................................................................................................................1360
Figure 11-26. XBARFLG3 Register........................................................................................................................................1365
Figure 11-27. XBARFLG4 Register........................................................................................................................................1368
Figure 11-28. XBARCLR1 Register....................................................................................................................................... 1371
Figure 11-29. XBARCLR2 Register....................................................................................................................................... 1373
Figure 11-30. XBARCLR3 Register....................................................................................................................................... 1376
Figure 11-31. XBARCLR4 Register....................................................................................................................................... 1378
Figure 11-32. TRIP4MUX0TO15CFG Register......................................................................................................................1382
Figure 11-33. TRIP4MUX16TO31CFG Register....................................................................................................................1385
Figure 11-34. TRIP5MUX0TO15CFG Register......................................................................................................................1388
Figure 11-35. TRIP5MUX16TO31CFG Register....................................................................................................................1391
Figure 11-36. TRIP7MUX0TO15CFG Register......................................................................................................................1394
Figure 11-37. TRIP7MUX16TO31CFG Register....................................................................................................................1397
Figure 11-38. TRIP8MUX0TO15CFG Register......................................................................................................................1400
Figure 11-39. TRIP8MUX16TO31CFG Register....................................................................................................................1403
Figure 11-40. TRIP9MUX0TO15CFG Register......................................................................................................................1406
Figure 11-41. TRIP9MUX16TO31CFG Register....................................................................................................................1409
Figure 11-42. TRIP10MUX0TO15CFG Register....................................................................................................................1412
Figure 11-43. TRIP10MUX16TO31CFG Register..................................................................................................................1415
Figure 11-44. TRIP11MUX0TO15CFG Register....................................................................................................................1418
Figure 11-45. TRIP11MUX16TO31CFG Register..................................................................................................................1421
Figure 11-46. TRIP12MUX0TO15CFG Register....................................................................................................................1424
Figure 11-47. TRIP12MUX16TO31CFG Register..................................................................................................................1427
Figure 11-48. TRIP4MUXENABLE Register.......................................................................................................................... 1430
Figure 11-49. TRIP5MUXENABLE Register.......................................................................................................................... 1435
Figure 11-50. TRIP7MUXENABLE Register.......................................................................................................................... 1440
Figure 11-51. TRIP8MUXENABLE Register.......................................................................................................................... 1445
Figure 11-52. TRIP9MUXENABLE Register.......................................................................................................................... 1450
Figure 11-53. TRIP10MUXENABLE Register........................................................................................................................ 1455
Figure 11-54. TRIP11MUXENABLE Register........................................................................................................................ 1460
Figure 11-55. TRIP12MUXENABLE Register........................................................................................................................ 1465
Figure 11-56. TRIPOUTINV Register.....................................................................................................................................1470
Figure 11-57. TRIPLOCK Register........................................................................................................................................ 1472
Figure 11-58. AUXSIG0MUX0TO15CFG Register................................................................................................................ 1475
Figure 11-59. AUXSIG0MUX16TO31CFG Register.............................................................................................................. 1478
Figure 11-60. AUXSIG1MUX0TO15CFG Register................................................................................................................ 1481
Figure 11-61. AUXSIG1MUX16TO31CFG Register.............................................................................................................. 1484
Figure 11-62. AUXSIG2MUX0TO15CFG Register................................................................................................................ 1487
Figure 11-63. AUXSIG2MUX16TO31CFG Register.............................................................................................................. 1490
Figure 11-64. AUXSIG3MUX0TO15CFG Register................................................................................................................ 1493
Figure 11-65. AUXSIG3MUX16TO31CFG Register.............................................................................................................. 1496
Figure 11-66. AUXSIG4MUX0TO15CFG Register................................................................................................................ 1499
Figure 11-67. AUXSIG4MUX16TO31CFG Register.............................................................................................................. 1502
Figure 11-68. AUXSIG5MUX0TO15CFG Register................................................................................................................ 1505
Figure 11-69. AUXSIG5MUX16TO31CFG Register.............................................................................................................. 1508
Figure 11-70. AUXSIG6MUX0TO15CFG Register................................................................................................................ 1511
Figure 11-71. AUXSIG6MUX16TO31CFG Register.............................................................................................................. 1514
Figure 11-72. AUXSIG7MUX0TO15CFG Register................................................................................................................ 1517
Figure 11-73. AUXSIG7MUX16TO31CFG Register.............................................................................................................. 1520
Figure 11-74. AUXSIG0MUXENABLE Register.....................................................................................................................1523

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Figure 11-75. AUXSIG1MUXENABLE Register.....................................................................................................................1528

Figure 11-76. AUXSIG2MUXENABLE Register.....................................................................................................................1533
Figure 11-77. AUXSIG3MUXENABLE Register.....................................................................................................................1538
Figure 11-78. AUXSIG4MUXENABLE Register.....................................................................................................................1543
Figure 11-79. AUXSIG5MUXENABLE Register.....................................................................................................................1548
Figure 11-80. AUXSIG6MUXENABLE Register.....................................................................................................................1553
Figure 11-81. AUXSIG7MUXENABLE Register.....................................................................................................................1558
Figure 11-82. AUXSIGOUTINV Register............................................................................................................................... 1563
Figure 11-83. AUXSIGLOCK Register................................................................................................................................... 1565
Figure 11-84. OUTPUT1MUX0TO15CFG Register............................................................................................................... 1568
Figure 11-85. OUTPUT1MUX16TO31CFG Register............................................................................................................. 1571
Figure 11-86. OUTPUT2MUX0TO15CFG Register............................................................................................................... 1574
Figure 11-87. OUTPUT2MUX16TO31CFG Register............................................................................................................. 1577
Figure 11-88. OUTPUT3MUX0TO15CFG Register............................................................................................................... 1580
Figure 11-89. OUTPUT3MUX16TO31CFG Register............................................................................................................. 1583
Figure 11-90. OUTPUT4MUX0TO15CFG Register............................................................................................................... 1586
Figure 11-91. OUTPUT4MUX16TO31CFG Register............................................................................................................. 1589
Figure 11-92. OUTPUT5MUX0TO15CFG Register............................................................................................................... 1592
Figure 11-93. OUTPUT5MUX16TO31CFG Register............................................................................................................. 1595
Figure 11-94. OUTPUT6MUX0TO15CFG Register............................................................................................................... 1598
Figure 11-95. OUTPUT6MUX16TO31CFG Register............................................................................................................. 1601
Figure 11-96. OUTPUT7MUX0TO15CFG Register............................................................................................................... 1604
Figure 11-97. OUTPUT7MUX16TO31CFG Register............................................................................................................. 1607
Figure 11-98. OUTPUT8MUX0TO15CFG Register............................................................................................................... 1610
Figure 11-99. OUTPUT8MUX16TO31CFG Register............................................................................................................. 1613
Figure 11-100. OUTPUT1MUXENABLE Register................................................................................................................. 1616
Figure 11-101. OUTPUT2MUXENABLE Register................................................................................................................. 1621
Figure 11-102. OUTPUT3MUXENABLE Register................................................................................................................. 1626
Figure 11-103. OUTPUT4MUXENABLE Register................................................................................................................. 1631
Figure 11-104. OUTPUT5MUXENABLE Register................................................................................................................. 1636
Figure 11-105. OUTPUT6MUXENABLE Register................................................................................................................. 1641
Figure 11-106. OUTPUT7MUXENABLE Register................................................................................................................. 1646
Figure 11-107. OUTPUT8MUXENABLE Register................................................................................................................. 1651
Figure 11-108. OUTPUTLATCH Register.............................................................................................................................. 1656
Figure 11-109. OUTPUTLATCHCLR Register.......................................................................................................................1658
Figure 11-110. OUTPUTLATCHFRC Register.......................................................................................................................1660
Figure 11-111. OUTPUTLATCHENABLE Register................................................................................................................ 1662
Figure 11-112. OUTPUTINV Register....................................................................................................................................1664
Figure 11-113. OUTPUTLOCK Register................................................................................................................................ 1666
Figure 11-114. OUTPUT1MUX0TO15CFG Register............................................................................................................. 1669
Figure 11-115. OUTPUT1MUX16TO31CFG Register........................................................................................................... 1672
Figure 11-116. OUTPUT2MUX0TO15CFG Register............................................................................................................. 1675
Figure 11-117. OUTPUT2MUX16TO31CFG Register........................................................................................................... 1678
Figure 11-118. OUTPUT3MUX0TO15CFG Register............................................................................................................. 1681
Figure 11-119. OUTPUT3MUX16TO31CFG Register........................................................................................................... 1684
Figure 11-120. OUTPUT4MUX0TO15CFG Register............................................................................................................. 1687
Figure 11-121. OUTPUT4MUX16TO31CFG Register........................................................................................................... 1690
Figure 11-122. OUTPUT5MUX0TO15CFG Register............................................................................................................. 1693
Figure 11-123. OUTPUT5MUX16TO31CFG Register........................................................................................................... 1696
Figure 11-124. OUTPUT6MUX0TO15CFG Register............................................................................................................. 1699
Figure 11-125. OUTPUT6MUX16TO31CFG Register........................................................................................................... 1702
Figure 11-126. OUTPUT7MUX0TO15CFG Register............................................................................................................. 1705
Figure 11-127. OUTPUT7MUX16TO31CFG Register........................................................................................................... 1708
Figure 11-128. OUTPUT8MUX0TO15CFG Register............................................................................................................. 1711
Figure 11-129. OUTPUT8MUX16TO31CFG Register........................................................................................................... 1714
Figure 11-130. OUTPUT1MUXENABLE Register................................................................................................................. 1717
Figure 11-131. OUTPUT2MUXENABLE Register................................................................................................................. 1722
Figure 11-132. OUTPUT3MUXENABLE Register................................................................................................................. 1727
Figure 11-133. OUTPUT4MUXENABLE Register................................................................................................................. 1732
Figure 11-134. OUTPUT5MUXENABLE Register................................................................................................................. 1737
Figure 11-135. OUTPUT6MUXENABLE Register................................................................................................................. 1742

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Figure 11-136. OUTPUT7MUXENABLE Register................................................................................................................. 1747

Figure 11-137. OUTPUT8MUXENABLE Register................................................................................................................. 1752
Figure 11-138. OUTPUTLATCH Register.............................................................................................................................. 1757
Figure 11-139. OUTPUTLATCHCLR Register.......................................................................................................................1759
Figure 11-140. OUTPUTLATCHFRC Register.......................................................................................................................1761
Figure 11-141. OUTPUTLATCHENABLE Register................................................................................................................1763
Figure 11-142. OUTPUTINV Register....................................................................................................................................1765
Figure 11-143. OUTPUTLOCK Register................................................................................................................................1767
Figure 12-1. DMA Block Diagram.......................................................................................................................................... 1770
Figure 12-2. DMA Trigger Architecture.................................................................................................................................. 1772
Figure 12-3. Peripheral Interrupt Trigger Input Diagram........................................................................................................1773
Figure 12-4. DMA State Diagram.......................................................................................................................................... 1781
Figure 12-5. 3-Stage Pipeline DMA Transfer.........................................................................................................................1782
Figure 12-6. 3-stage Pipeline with One Read Stall................................................................................................................1782
Figure 12-7. Overrun Detection Logic....................................................................................................................................1785
Figure 12-8. DMACTRL Register...........................................................................................................................................1790
Figure 12-9. DEBUGCTRL Register......................................................................................................................................1791
Figure 12-10. PRIORITYCTRL1 Register..............................................................................................................................1792
Figure 12-11. PRIORITYSTAT Register.................................................................................................................................1793
Figure 12-12. MODE Register............................................................................................................................................... 1795
Figure 12-13. CONTROL Register........................................................................................................................................ 1797
Figure 12-14. BURST_SIZE Register....................................................................................................................................1799
Figure 12-15. BURST_COUNT Register............................................................................................................................... 1800
Figure 12-16. SRC_BURST_STEP Register.........................................................................................................................1801
Figure 12-17. DST_BURST_STEP Register......................................................................................................................... 1802
Figure 12-18. TRANSFER_SIZE Register.............................................................................................................................1803
Figure 12-19. TRANSFER_COUNT Register........................................................................................................................1804
Figure 12-20. SRC_TRANSFER_STEP Register..................................................................................................................1805
Figure 12-21. DST_TRANSFER_STEP Register.................................................................................................................. 1806
Figure 12-22. SRC_WRAP_SIZE Register............................................................................................................................1807
Figure 12-23. SRC_WRAP_COUNT Register.......................................................................................................................1808
Figure 12-24. SRC_WRAP_STEP Register.......................................................................................................................... 1809
Figure 12-25. DST_WRAP_SIZE Register............................................................................................................................ 1810
Figure 12-26. DST_WRAP_COUNT Register........................................................................................................................1811
Figure 12-27. DST_WRAP_STEP Register...........................................................................................................................1812
Figure 12-28. SRC_BEG_ADDR_SHADOW Register.......................................................................................................... 1813
Figure 12-29. SRC_ADDR_SHADOW Register.................................................................................................................... 1814
Figure 12-30. SRC_BEG_ADDR_ACTIVE Register..............................................................................................................1815
Figure 12-31. SRC_ADDR_ACTIVE Register....................................................................................................................... 1816
Figure 12-32. DST_BEG_ADDR_SHADOW Register...........................................................................................................1817
Figure 12-33. DST_ADDR_SHADOW Register.................................................................................................................... 1818
Figure 12-34. DST_BEG_ADDR_ACTIVE Register.............................................................................................................. 1819
Figure 12-35. DST_ADDR_ACTIVE Register........................................................................................................................1820
Figure 13-1. ERAD Overview................................................................................................................................................ 1822
Figure 13-2. EBC Units Event Masking................................................................................................................................. 1824
Figure 13-3. System Event Counter Inputs............................................................................................................................1826
Figure 13-4. Event Masking and Exporting for CRC Qualifiers............................................................................................. 1834
Figure 13-5. PC Trace Operation...........................................................................................................................................1836
Figure 13-6. PC Trace Block Diagram................................................................................................................................... 1837
Figure 13-7. Trace Qualifier Input Conditioning Circuit..........................................................................................................1843
Figure 13-8. GLBL_EVENT_STAT Register.......................................................................................................................... 1857
Figure 13-9. GLBL_HALT_STAT Register............................................................................................................................. 1859
Figure 13-10. GLBL_ENABLE Register.................................................................................................................................1861
Figure 13-11. GLBL_CTM_RESET Register......................................................................................................................... 1863
Figure 13-12. GLBL_NMI_CTL Register............................................................................................................................... 1864
Figure 13-13. GLBL_OWNER Register................................................................................................................................. 1866
Figure 13-14. GLBL_EVENT_AND_MASK Register............................................................................................................. 1867
Figure 13-15. GLBL_EVENT_OR_MASK Register............................................................................................................... 1872
Figure 13-16. GLBL_AND_EVENT_INT_MASK Register..................................................................................................... 1877
Figure 13-17. GLBL_OR_EVENT_INT_MASK Register....................................................................................................... 1878
Figure 13-18. HWBP_MASK Register................................................................................................................................... 1880

32 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 13-19. HWBP_REF Register...................................................................................................................................... 1881

Figure 13-20. HWBP_CLEAR Register................................................................................................................................. 1882
Figure 13-21. HWBP_CNTL Register....................................................................................................................................1883
Figure 13-22. HWBP_STATUS Register................................................................................................................................1885
Figure 13-23. CTM_CNTL Register.......................................................................................................................................1887
Figure 13-24. CTM_STATUS Register...................................................................................................................................1889
Figure 13-25. CTM_REF Register......................................................................................................................................... 1890
Figure 13-26. CTM_COUNT Register................................................................................................................................... 1891
Figure 13-27. CTM_MAX_COUNT Register..........................................................................................................................1892
Figure 13-28. CTM_INPUT_SEL Register.............................................................................................................................1893
Figure 13-29. CTM_CLEAR Register.................................................................................................................................... 1894
Figure 13-30. CTM_INPUT_SEL_2 Register.........................................................................................................................1895
Figure 13-31. CTM_INPUT_COND Register.........................................................................................................................1896
Figure 13-32. CRC_GLOBAL_CTRL Register...................................................................................................................... 1898
Figure 13-33. CRC_CURRENT Register...............................................................................................................................1901
Figure 13-34. CRC_SEED Register...................................................................................................................................... 1902
Figure 13-35. CRC_QUALIFIER Register............................................................................................................................. 1903
Figure 13-36. PCTRACE_GLOBAL Register........................................................................................................................ 1905
Figure 13-37. PCTRACE_BUFFER Register........................................................................................................................ 1906
Figure 13-38. PCTRACE_QUAL1 Register........................................................................................................................... 1907
Figure 13-39. PCTRACE_QUAL2 Register........................................................................................................................... 1908
Figure 13-40. PCTRACE_LOGPC_SOFTENABLE Register................................................................................................ 1909
Figure 13-41. PCTRACE_LOGPC_SOFTDISABLE Register............................................................................................... 1910
Figure 13-42. PCTRACE_BUFFER_BASE_y Register......................................................................................................... 1912
Figure 14-1. Analog Subsystem Block Diagram (128/80/64/56- Pins).................................................................................. 1915
Figure 14-2. Analog Subsystem Block Diagram (100-Pin QFP)............................................................................................1916
Figure 14-3. Analog Group Connections............................................................................................................................... 1917
Figure 14-4. Analog Subsystem Block Diagram with AGPIO Implementation.......................................................................1921
Figure 14-5. ADCOSDETECT Register.................................................................................................................................1931
Figure 14-6. REFCONFIGB Register.................................................................................................................................... 1932
Figure 14-7. INTERNALTESTCTL Register...........................................................................................................................1934
Figure 14-8. CONFIGLOCK Register.................................................................................................................................... 1936
Figure 14-9. TSNSCTL Register............................................................................................................................................1937
Figure 14-10. ANAREFPCTL Register.................................................................................................................................. 1938
Figure 14-11. ANAREFNCTL Register.................................................................................................................................. 1940
Figure 14-12. VMONCTL Register........................................................................................................................................ 1941
Figure 14-13. CMPHPMXSEL Register.................................................................................................................................1942
Figure 14-14. CMPLPMXSEL Register................................................................................................................................. 1943
Figure 14-15. CMPHNMXSEL Register.................................................................................................................................1944
Figure 14-16. CMPLNMXSEL Register................................................................................................................................. 1945
Figure 14-17. ADCDACLOOPBACK Register....................................................................................................................... 1946
Figure 14-18. CMPSSCTL Register...................................................................................................................................... 1948
Figure 14-19. CMPSSDACBUFCONFIG Register................................................................................................................ 1949
Figure 14-20. LOCK Register................................................................................................................................................ 1950
Figure 14-21. AGPIOCTRLA Register...................................................................................................................................1952
Figure 14-22. AGPIOCTRLB Register...................................................................................................................................1954
Figure 14-23. AGPIOCTRLG Register.................................................................................................................................. 1956
Figure 14-24. AGPIOCTRLH Register...................................................................................................................................1958
Figure 14-25. GPIOINENACTRL Register.............................................................................................................................1960
Figure 14-26. IO_DRVSEL Register...................................................................................................................................... 1961
Figure 14-27. IO_MODESEL Register...................................................................................................................................1962
Figure 14-28. ADCSOCFRCGB Register.............................................................................................................................. 1963
Figure 14-29. ADCSOCFRCGBSEL Register....................................................................................................................... 1965
Figure 15-1. ADC Module Block Diagram..............................................................................................................................1969
Figure 15-2. SOC Block Diagram.......................................................................................................................................... 1973
Figure 15-3. ADC Trigger Repeater Block Diagram.............................................................................................................. 1975
Figure 15-4. Oversampled ADC Trigger Example................................................................................................................. 1976
Figure 15-5. Undersampled ADC Trigger Example............................................................................................................... 1977
Figure 15-6. Oversampled ADC Trigger Example with Phase Delay.................................................................................... 1978
Figure 15-7. ADC Trigger Example with Phase Delay...........................................................................................................1978
Figure 15-8. ADC Interleaved Trigger Example (12 Samples Across 3 ADCs)..................................................................... 1979

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Figure 15-9. ADC Repeated Trigger Example with Sample Spread......................................................................................1980

Figure 15-10. Trigger Repeater Repeat Logic....................................................................................................................... 1982
Figure 15-11. Single-Ended Input Model............................................................................................................................... 1983
Figure 15-12. ADC with External Input Mux.......................................................................................................................... 1985
Figure 15-13. ADC with Multiple External Input Muxes and Shared Selection......................................................................1986
Figure 15-14. ADC External Channel Select Timing Example...............................................................................................1987
Figure 15-15. ADC External Channel Timing Example in Preselect Mode............................................................................1988
Figure 15-16. ADC External Channel Select Timing Example with Asynchronous Trigger................................................... 1989
Figure 15-17. ADC External Channel Timing Example in Preselect Mode with Asynchronous Trigger................................ 1990
Figure 15-18. Round Robin Priority Example........................................................................................................................ 1994
Figure 15-19. High Priority Example......................................................................................................................................1995
Figure 15-20. Burst Priority Example.....................................................................................................................................1997
Figure 15-21. ADC EOC Interrupts........................................................................................................................................1998
Figure 15-22. ADC PPB Block Diagram................................................................................................................................ 2001
Figure 15-23. ADC PPB Interrupt Event................................................................................................................................ 2004
Figure 15-24. ADC PPB Limit Compare and Zero-Crossing Logic........................................................................................2004
Figure 15-25. ADC PPB Limit Filter Logic............................................................................................................................. 2005
Figure 15-26. Opens/Shorts Detection Circuit....................................................................................................................... 2008
Figure 15-27. Input Circuit Equivalent with OSDETECT Enabled......................................................................................... 2009
Figure 15-28. ADC Timings for 12-bit Mode in Early Interrupt Mode.....................................................................................2012
Figure 15-29. ADC Timings for 12-bit Mode in Late Interrupt Mode...................................................................................... 2013
Figure 15-30. Example: Basic Synchronous Operation.........................................................................................................2017
Figure 15-31. Example: Synchronous Operation with Multiple Trigger Sources................................................................... 2018
Figure 15-32. Example: Synchronous Operation with Uneven SOC Numbers..................................................................... 2019
Figure 15-33. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow..................................... 2019
Figure 15-34. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions........................................ 2020
Figure 15-35. ADC Reference System.................................................................................................................................. 2023
Figure 15-36. CMPSS to ADC Loopback Connection........................................................................................................... 2024
Figure 15-37. ADCRESULT0 Register...................................................................................................................................2042
Figure 15-38. ADCRESULT1 Register...................................................................................................................................2043
Figure 15-39. ADCRESULT2 Register...................................................................................................................................2044
Figure 15-40. ADCRESULT3 Register...................................................................................................................................2045
Figure 15-41. ADCRESULT4 Register...................................................................................................................................2046
Figure 15-42. ADCRESULT5 Register...................................................................................................................................2047
Figure 15-43. ADCRESULT6 Register...................................................................................................................................2048
Figure 15-44. ADCRESULT7 Register...................................................................................................................................2049
Figure 15-45. ADCRESULT8 Register...................................................................................................................................2050
Figure 15-46. ADCRESULT9 Register...................................................................................................................................2051
Figure 15-47. ADCRESULT10 Register.................................................................................................................................2052
Figure 15-48. ADCRESULT11 Register.................................................................................................................................2053
Figure 15-49. ADCRESULT12 Register.................................................................................................................................2054
Figure 15-50. ADCRESULT13 Register.................................................................................................................................2055
Figure 15-51. ADCRESULT14 Register.................................................................................................................................2056
Figure 15-52. ADCRESULT15 Register.................................................................................................................................2057
Figure 15-53. ADCPPB1RESULT Register........................................................................................................................... 2058
Figure 15-54. ADCPPB2RESULT Register........................................................................................................................... 2059
Figure 15-55. ADCPPB3RESULT Register........................................................................................................................... 2060
Figure 15-56. ADCPPB4RESULT Register........................................................................................................................... 2061
Figure 15-57. ADCPPB1SUM Register................................................................................................................................. 2062
Figure 15-58. ADCPPB1COUNT Register............................................................................................................................ 2063
Figure 15-59. ADCPPB2SUM Register................................................................................................................................. 2064
Figure 15-60. ADCPPB2COUNT Register............................................................................................................................ 2065
Figure 15-61. ADCPPB3SUM Register................................................................................................................................. 2066
Figure 15-62. ADCPPB3COUNT Register............................................................................................................................ 2067
Figure 15-63. ADCPPB4SUM Register................................................................................................................................. 2068
Figure 15-64. ADCPPB4COUNT Register............................................................................................................................ 2069
Figure 15-65. ADCPPB1MAX Register................................................................................................................................. 2070
Figure 15-66. ADCPPB1MAXI Register................................................................................................................................ 2071
Figure 15-67. ADCPPB1MIN Register...................................................................................................................................2072
Figure 15-68. ADCPPB1MINI Register..................................................................................................................................2073
Figure 15-69. ADCPPB2MAX Register................................................................................................................................. 2074

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Figure 15-70. ADCPPB2MAXI Register................................................................................................................................ 2075

Figure 15-71. ADCPPB2MIN Register...................................................................................................................................2076
Figure 15-72. ADCPPB2MINI Register..................................................................................................................................2077
Figure 15-73. ADCPPB3MAX Register................................................................................................................................. 2078
Figure 15-74. ADCPPB3MAXI Register................................................................................................................................ 2079
Figure 15-75. ADCPPB3MIN Register...................................................................................................................................2080
Figure 15-76. ADCPPB3MINI Register..................................................................................................................................2081
Figure 15-77. ADCPPB4MAX Register................................................................................................................................. 2082
Figure 15-78. ADCPPB4MAXI Register................................................................................................................................ 2083
Figure 15-79. ADCPPB4MIN Register...................................................................................................................................2084
Figure 15-80. ADCPPB4MINI Register..................................................................................................................................2085
Figure 15-81. ADCCTL1 Register..........................................................................................................................................2090
Figure 15-82. ADCCTL2 Register..........................................................................................................................................2092
Figure 15-83. ADCBURSTCTL Register............................................................................................................................... 2093
Figure 15-84. ADCINTFLG Register......................................................................................................................................2095
Figure 15-85. ADCINTFLGCLR Register.............................................................................................................................. 2098
Figure 15-86. ADCINTOVF Register..................................................................................................................................... 2099
Figure 15-87. ADCINTOVFCLR Register.............................................................................................................................. 2100
Figure 15-88. ADCINTSEL1N2 Register............................................................................................................................... 2101
Figure 15-89. ADCINTSEL3N4 Register............................................................................................................................... 2103
Figure 15-90. ADCSOCPRICTL Register..............................................................................................................................2105
Figure 15-91. ADCINTSOCSEL1 Register............................................................................................................................ 2107
Figure 15-92. ADCSOCFLG1 Register.................................................................................................................................. 2110
Figure 15-93. ADCSOCFRC1 Register..................................................................................................................................2114
Figure 15-94. ADCSOCOVF1 Register..................................................................................................................................2119
Figure 15-95. ADCSOCOVFCLR1 Register.......................................................................................................................... 2122
Figure 15-96. ADCSOC0CTL Register..................................................................................................................................2125
Figure 15-97. ADCSOC1CTL Register..................................................................................................................................2128
Figure 15-98. ADCSOC2CTL Register..................................................................................................................................2131
Figure 15-99. ADCSOC3CTL Register..................................................................................................................................2134
Figure 15-100. ADCSOC4CTL Register................................................................................................................................2137
Figure 15-101. ADCSOC5CTL Register................................................................................................................................2140
Figure 15-102. ADCSOC6CTL Register................................................................................................................................2143
Figure 15-103. ADCSOC7CTL Register................................................................................................................................2146
Figure 15-104. ADCSOC8CTL Register................................................................................................................................2149
Figure 15-105. ADCSOC9CTL Register................................................................................................................................2152
Figure 15-106. ADCSOC10CTL Register..............................................................................................................................2155
Figure 15-107. ADCSOC11CTL Register.............................................................................................................................. 2158
Figure 15-108. ADCSOC12CTL Register..............................................................................................................................2161
Figure 15-109. ADCSOC13CTL Register..............................................................................................................................2164
Figure 15-110. ADCSOC14CTL Register.............................................................................................................................. 2167
Figure 15-111. ADCSOC15CTL Register.............................................................................................................................. 2170
Figure 15-112. ADCEVTSTAT Register................................................................................................................................. 2173
Figure 15-113. ADCEVTCLR Register...................................................................................................................................2176
Figure 15-114. ADCEVTSEL Register................................................................................................................................... 2178
Figure 15-115. ADCEVTINTSEL Register............................................................................................................................. 2180
Figure 15-116. ADCCOUNTER Register............................................................................................................................... 2182
Figure 15-117. ADCREV Register......................................................................................................................................... 2183
Figure 15-118. ADCOFFTRIM Register.................................................................................................................................2184
Figure 15-119. ADCCONFIG2 Register.................................................................................................................................2185
Figure 15-120. ADCPPB1CONFIG Register......................................................................................................................... 2186
Figure 15-121. ADCPPB1STAMP Register........................................................................................................................... 2188
Figure 15-122. ADCPPB1OFFCAL Register......................................................................................................................... 2189
Figure 15-123. ADCPPB1OFFREF Register.........................................................................................................................2190
Figure 15-124. ADCPPB1TRIPHI Register........................................................................................................................... 2191
Figure 15-125. ADCPPB1TRIPLO Register.......................................................................................................................... 2192
Figure 15-126. ADCPPBTRIP1FILCTL Register................................................................................................................... 2193
Figure 15-127. ADCPPBTRIP1FILCLKCTL Register............................................................................................................ 2194
Figure 15-128. ADCPPB2CONFIG Register......................................................................................................................... 2195
Figure 15-129. ADCPPB2STAMP Register........................................................................................................................... 2197
Figure 15-130. ADCPPB2OFFCAL Register......................................................................................................................... 2198

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 35

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Figure 15-131. ADCPPB2OFFREF Register.........................................................................................................................2199

Figure 15-132. ADCPPB2TRIPHI Register........................................................................................................................... 2200
Figure 15-133. ADCPPB2TRIPLO Register.......................................................................................................................... 2201
Figure 15-134. ADCPPBTRIP2FILCTL Register................................................................................................................... 2202
Figure 15-135. ADCPPBTRIP2FILCLKCTL Register............................................................................................................ 2203
Figure 15-136. ADCPPB3CONFIG Register......................................................................................................................... 2204
Figure 15-137. ADCPPB3STAMP Register........................................................................................................................... 2206
Figure 15-138. ADCPPB3OFFCAL Register......................................................................................................................... 2207
Figure 15-139. ADCPPB3OFFREF Register.........................................................................................................................2208
Figure 15-140. ADCPPB3TRIPHI Register........................................................................................................................... 2209
Figure 15-141. ADCPPB3TRIPLO Register.......................................................................................................................... 2210
Figure 15-142. ADCPPBTRIP3FILCTL Register................................................................................................................... 2211
Figure 15-143. ADCPPBTRIP3FILCLKCTL Register............................................................................................................ 2212
Figure 15-144. ADCPPB4CONFIG Register......................................................................................................................... 2213
Figure 15-145. ADCPPB4STAMP Register........................................................................................................................... 2215
Figure 15-146. ADCPPB4OFFCAL Register......................................................................................................................... 2216
Figure 15-147. ADCPPB4OFFREF Register.........................................................................................................................2217
Figure 15-148. ADCPPB4TRIPHI Register........................................................................................................................... 2218
Figure 15-149. ADCPPB4TRIPLO Register.......................................................................................................................... 2219
Figure 15-150. ADCPPBTRIP4FILCTL Register................................................................................................................... 2220
Figure 15-151. ADCPPBTRIP4FILCLKCTL Register............................................................................................................ 2221
Figure 15-152. ADCINTCYCLE Register...............................................................................................................................2222
Figure 15-153. ADCINLTRIM1 Register................................................................................................................................ 2223
Figure 15-154. ADCINLTRIM2 Register................................................................................................................................ 2224
Figure 15-155. ADCINLTRIM3 Register................................................................................................................................ 2225
Figure 15-156. ADCINLTRIM4 Register................................................................................................................................ 2226
Figure 15-157. ADCINLTRIM5 Register................................................................................................................................ 2227
Figure 15-158. ADCINLTRIM6 Register................................................................................................................................ 2228
Figure 15-159. ADCREV2 Register....................................................................................................................................... 2229
Figure 15-160. REP1CTL Register........................................................................................................................................2230
Figure 15-161. REP1N Register............................................................................................................................................ 2233
Figure 15-162. REP1PHASE Register.................................................................................................................................. 2234
Figure 15-163. REP1SPREAD Register................................................................................................................................2235
Figure 15-164. REP1FRC Register....................................................................................................................................... 2236
Figure 15-165. REP2CTL Register........................................................................................................................................2237
Figure 15-166. REP2N Register............................................................................................................................................ 2240
Figure 15-167. REP2PHASE Register.................................................................................................................................. 2241
Figure 15-168. REP2SPREAD Register................................................................................................................................2242
Figure 15-169. REP2FRC Register....................................................................................................................................... 2243
Figure 15-170. ADCPPB1LIMIT Register.............................................................................................................................. 2244
Figure 15-171. ADCPPBP1PCOUNT Register......................................................................................................................2245
Figure 15-172. ADCPPB1CONFIG2 Register....................................................................................................................... 2246
Figure 15-173. ADCPPB1PSUM Register.............................................................................................................................2248
Figure 15-174. ADCPPB1PMAX Register............................................................................................................................. 2249
Figure 15-175. ADCPPB1PMAXI Register............................................................................................................................ 2250
Figure 15-176. ADCPPB1PMIN Register.............................................................................................................................. 2251
Figure 15-177. ADCPPB1PMINI Register............................................................................................................................. 2252
Figure 15-178. ADCPPB1TRIPLO2 Register........................................................................................................................ 2253
Figure 15-179. ADCPPB2LIMIT Register.............................................................................................................................. 2254
Figure 15-180. ADCPPBP2PCOUNT Register......................................................................................................................2255
Figure 15-181. ADCPPB2CONFIG2 Register....................................................................................................................... 2256
Figure 15-182. ADCPPB2PSUM Register.............................................................................................................................2258
Figure 15-183. ADCPPB2PMAX Register............................................................................................................................. 2259
Figure 15-184. ADCPPB2PMAXI Register............................................................................................................................ 2260
Figure 15-185. ADCPPB2PMIN Register.............................................................................................................................. 2261
Figure 15-186. ADCPPB2PMINI Register............................................................................................................................. 2262
Figure 15-187. ADCPPB2TRIPLO2 Register........................................................................................................................ 2263
Figure 15-188. ADCPPB3LIMIT Register.............................................................................................................................. 2264
Figure 15-189. ADCPPBP3PCOUNT Register......................................................................................................................2265
Figure 15-190. ADCPPB3CONFIG2 Register....................................................................................................................... 2266
Figure 15-191. ADCPPB3PSUM Register.............................................................................................................................2268

36 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 15-192. ADCPPB3PMAX Register............................................................................................................................. 2269

Figure 15-193. ADCPPB3PMAXI Register............................................................................................................................ 2270
Figure 15-194. ADCPPB3PMIN Register.............................................................................................................................. 2271
Figure 15-195. ADCPPB3PMINI Register............................................................................................................................. 2272
Figure 15-196. ADCPPB3TRIPLO2 Register........................................................................................................................ 2273
Figure 15-197. ADCPPB4LIMIT Register.............................................................................................................................. 2274
Figure 15-198. ADCPPBP4PCOUNT Register......................................................................................................................2275
Figure 15-199. ADCPPB4CONFIG2 Register....................................................................................................................... 2276
Figure 15-200. ADCPPB4PSUM Register.............................................................................................................................2278
Figure 15-201. ADCPPB4PMAX Register............................................................................................................................. 2279
Figure 15-202. ADCPPB4PMAXI Register............................................................................................................................ 2280
Figure 15-203. ADCPPB4PMIN Register.............................................................................................................................. 2281
Figure 15-204. ADCPPB4PMINI Register............................................................................................................................. 2282
Figure 15-205. ADCPPB4TRIPLO2 Register........................................................................................................................ 2283
Figure 16-1. DAC Module Block Diagram..............................................................................................................................2285
Figure 16-2. DACREV Register............................................................................................................................................. 2291
Figure 16-3. DACCTL Register..............................................................................................................................................2292
Figure 16-4. DACVALA Register............................................................................................................................................2293
Figure 16-5. DACVALS Register............................................................................................................................................2294
Figure 16-6. DACOUTEN Register........................................................................................................................................2295
Figure 16-7. DACLOCK Register...........................................................................................................................................2296
Figure 16-8. DACTRIM Register............................................................................................................................................2297
Figure 17-1. CMPSS Module Block Diagram........................................................................................................................ 2300
Figure 17-2. Comparator Block Diagram............................................................................................................................... 2300
Figure 17-3. Reference DAC Block Diagram.........................................................................................................................2301
Figure 17-4. Ramp Generator Block Diagram....................................................................................................................... 2303
Figure 17-5. Ramp Generator Behavior................................................................................................................................ 2305
Figure 17-6. Digital Filter Behavior........................................................................................................................................ 2306
Figure 17-7. COMPCTL Register.......................................................................................................................................... 2316
Figure 17-8. COMPHYSCTL Register................................................................................................................................... 2318
Figure 17-9. COMPSTS Register.......................................................................................................................................... 2319
Figure 17-10. COMPSTSCLR Register................................................................................................................................. 2320
Figure 17-11. COMPDACHCTL Register...............................................................................................................................2321
Figure 17-12. COMPDACHCTL2 Register............................................................................................................................ 2323
Figure 17-13. DACHVALS Register....................................................................................................................................... 2324
Figure 17-14. DACHVALA Register....................................................................................................................................... 2325
Figure 17-15. RAMPHREFA Register....................................................................................................................................2326
Figure 17-16. RAMPHREFS Register................................................................................................................................... 2327
Figure 17-17. RAMPHSTEPVALA Register...........................................................................................................................2328
Figure 17-18. RAMPHCTLA Register....................................................................................................................................2329
Figure 17-19. RAMPHSTEPVALS Register...........................................................................................................................2330
Figure 17-20. RAMPHCTLS Register....................................................................................................................................2331
Figure 17-21. RAMPHSTS Register...................................................................................................................................... 2332
Figure 17-22. DACLVALS Register........................................................................................................................................2333
Figure 17-23. DACLVALA Register........................................................................................................................................2334
Figure 17-24. RAMPHDLYA Register.................................................................................................................................... 2335
Figure 17-25. RAMPHDLYS Register.................................................................................................................................... 2336
Figure 17-26. CTRIPLFILCTL Register................................................................................................................................. 2337
Figure 17-27. CTRIPLFILCLKCTL Register.......................................................................................................................... 2338
Figure 17-28. CTRIPHFILCTL Register.................................................................................................................................2339
Figure 17-29. CTRIPHFILCLKCTL Register..........................................................................................................................2340
Figure 17-30. COMPLOCK Register..................................................................................................................................... 2341
Figure 17-31. COMPDACLCTL Register...............................................................................................................................2342
Figure 17-32. COMPDACLCTL2 Register.............................................................................................................................2344
Figure 17-33. RAMPLREFA Register.................................................................................................................................... 2345
Figure 17-34. RAMPLREFS Register.................................................................................................................................... 2346
Figure 17-35. RAMPLSTEPVALA Register........................................................................................................................... 2347
Figure 17-36. RAMPLCTLA Register.................................................................................................................................... 2348
Figure 17-37. RAMPLSTEPVALS Register........................................................................................................................... 2349
Figure 17-38. RAMPLCTLS Register.................................................................................................................................... 2350
Figure 17-39. RAMPLSTS Register.......................................................................................................................................2351

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 37

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Figure 17-40. RAMPLDLYA Register.....................................................................................................................................2352

Figure 17-41. RAMPLDLYS Register.....................................................................................................................................2353
Figure 17-42. CTRIPLFILCLKCTL2 Register........................................................................................................................ 2354
Figure 17-43. CTRIPHFILCLKCTL2 Register........................................................................................................................2355
Figure 18-1. PGA Block Diagram.......................................................................................................................................... 2357
Figure 18-2. Buffer Mode.......................................................................................................................................................2359
Figure 18-3. Standalone Mode.............................................................................................................................................. 2360
Figure 18-4. Non-inverting Mode........................................................................................................................................... 2361
Figure 18-5. Subtractor Mode................................................................................................................................................2362
Figure 18-6. Low-Pass Filter Using External Capacitor.........................................................................................................2364
Figure 18-7. PGA Offset Trim................................................................................................................................................ 2365
Figure 18-8. PGA Gain Error................................................................................................................................................. 2365
Figure 18-9. General Chopping Technique............................................................................................................................2366
Figure 18-10. ADC-Assisted Chopping Block Diagram......................................................................................................... 2366
Figure 18-11. Level Shifting Using Internal DAC................................................................................................................... 2368
Figure 18-12. Sharing PGA_NEG Pin Between PGA Modules............................................................................................. 2370
Figure 18-13. Three-phase Current Sensing Using PGA_NEG_SHARED Feature.............................................................. 2370
Figure 18-14. PGA Pin Alternate Functions...........................................................................................................................2371
Figure 18-15. Signal Conditioning Using Non-inverting Mode...............................................................................................2372
Figure 18-16. Buffer Mode Example...................................................................................................................................... 2372
Figure 18-17. PGA Shunt Current Example.......................................................................................................................... 2373
Figure 18-18. Bidirectional Current Sensing..........................................................................................................................2374
Figure 18-19. PGACTL Register............................................................................................................................................2378
Figure 18-20. MUXSEL Register........................................................................................................................................... 2379
Figure 18-21. OFFSETTRIM Register................................................................................................................................... 2380
Figure 18-22. PGATYPE Register......................................................................................................................................... 2381
Figure 18-23. PGALOCK Register.........................................................................................................................................2382
Figure 19-1. Multiple ePWM Modules....................................................................................................................................2387
Figure 19-2. Submodules and Signal Connections for an ePWM Module.............................................................................2388
Figure 19-3. ePWM Modules and Critical Internal Signal Interconnects............................................................................... 2390
Figure 19-4. Time-Base Submodule...................................................................................................................................... 2393
Figure 19-5. Time-Base Submodule Signals and Registers.................................................................................................. 2394
Figure 19-6. Time-Base Frequency and Period.....................................................................................................................2396
Figure 19-7. Time-Base Counter Synchronization Scheme...................................................................................................2398
Figure 19-8. ePWM External SYNC Output...........................................................................................................................2399
Figure 19-9. Time-Base Up-Count Mode Waveforms............................................................................................................2402
Figure 19-10. Time-Base Down-Count Mode Waveforms..................................................................................................... 2403
Figure 19-11. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event....... 2404
Figure 19-12. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event............2405
Figure 19-13. Global Load: Signals and Registers................................................................................................................ 2406
Figure 19-14. One-Shot Sync Mode...................................................................................................................................... 2407
Figure 19-15. Counter-Compare Submodule........................................................................................................................ 2408
Figure 19-16. Detailed View of the Counter-Compare Submodule........................................................................................2409
Figure 19-17. Counter-Compare Event Waveforms in Up-Count Mode................................................................................ 2412
Figure 19-18. Counter-Compare Events in Down-Count Mode.............................................................................................2412
Figure 19-19. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event....................................................................................................................................................... 2413
Figure 19-20. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event.................................................................................................................................................................................. 2413
Figure 19-21. Action-Qualifier Submodule.............................................................................................................................2414
Figure 19-22. Action-Qualifier Submodule Inputs and Outputs............................................................................................. 2415
Figure 19-23. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs..........................................................2416
Figure 19-24. AQCTL[SHDWAQAMODE]............................................................................................................................. 2419
Figure 19-25. AQCTL[SHDWAQBMODE]............................................................................................................................. 2419
Figure 19-26. Up-Down Count Mode Symmetrical Waveform...............................................................................................2421
Figure 19-27. Up, Single Edge Asymmetric Waveform, with Independent Modulation on EPWMxA and EPWMxB—
Active High......................................................................................................................................................................... 2422
Figure 19-28. Up, Single Edge Asymmetric Waveform with Independent Modulation on EPWMxA and EPWMxB—
Active Low..........................................................................................................................................................................2423
Figure 19-29. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA..................2424

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Figure 19-30. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Active Low.....................................................................................................................................................2424
Figure 19-31. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Complementary.............................................................................................................................................2425
Figure 19-32. Up-Down Count, Dual-Edge Asymmetric Waveform, with Independent Modulation on EPWMxA—Active
Low.....................................................................................................................................................................................2425
Figure 19-33. Up-Down Count, PWM Waveform Generation Utilizing T1 and T2 Events..................................................... 2426
Figure 19-34. Dead_Band Submodule.................................................................................................................................. 2427
Figure 19-35. Configuration Options for the Dead-Band Submodule.................................................................................... 2430
Figure 19-36. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)..................................................................... 2432
Figure 19-37. PWM Chopper Submodule..............................................................................................................................2434
Figure 19-38. PWM Chopper Submodule Operational Details.............................................................................................. 2435
Figure 19-39. Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only............................................ 2435
Figure 19-40. PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses........... 2436
Figure 19-41. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses 2437
Figure 19-42. Trip-Zone Submodule......................................................................................................................................2438
Figure 19-43. Trip-Zone Submodule Mode Control Logic......................................................................................................2442
Figure 19-44. Trip-Zone Submodule Interrupt Logic..............................................................................................................2443
Figure 19-45. Event-Trigger Submodule................................................................................................................................2444
Figure 19-46. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs...................................................... 2445
Figure 19-47. Event-Trigger Interrupt Generator................................................................................................................... 2447
Figure 19-48. Event-Trigger SOCA Pulse Generator............................................................................................................ 2448
Figure 19-49. Event-Trigger SOCB Pulse Generator............................................................................................................ 2448
Figure 19-50. Digital-Compare Submodule High-Level Block Diagram.................................................................................2449
Figure 19-51. GPIO MUX-to-Trip Input Connectivity............................................................................................................. 2450
Figure 19-52. DCxEVT1 Event Triggering............................................................................................................................. 2453
Figure 19-53. DCxEVT2 Event Triggering............................................................................................................................. 2454
Figure 19-54. Event Filtering................................................................................................................................................. 2455
Figure 19-55. Blanking Window Timing Diagram...................................................................................................................2456
Figure 19-56. Valley Switching...............................................................................................................................................2458
Figure 19-57. ePWM X-BAR..................................................................................................................................................2459
Figure 19-58. Simplified ePWM Module................................................................................................................................ 2460
Figure 19-59. EPWM1 Configured as a Typical Sync Source, EPWM2 Configured as a Sync Receiver ............................ 2461
Figure 19-60. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ............................................................. 2462
Figure 19-61. Buck Waveforms for Control of Four Buck Stages (Note: Only three bucks shown here).............................. 2463
Figure 19-62. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1).............................................................................. 2464
Figure 19-63. Buck Waveforms for Control of Four Buck Stages (Note: FPWM2 = FPWM1).................................................... 2465
Figure 19-64. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1)............................................................................ 2466
Figure 19-65. Half-H Bridge Waveforms for Control of Two Half-H Bridge Stages (Note: Here FPWM2 = FPWM1)................. 2467
Figure 19-66. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control..........................................2468
Figure 19-67. 3-Phase Inverter Waveforms for Control of Dual 3-Phase Inverter Stages (Only One Inverter Shown)......... 2469
Figure 19-68. Configuring Two PWM Modules for Phase Control......................................................................................... 2470
Figure 19-69. Timing Waveforms Associated with Phase Control Between Two Modules....................................................2471
Figure 19-70. Control of 3-Phase Interleaved DC/DC Converter.......................................................................................... 2472
Figure 19-71. 3-Phase Interleaved DC/DC Converter Waveforms for Control of 3-Phase Interleaved DC/DC Converter....2473
Figure 19-72. Control of Full-H Bridge Stage (FPWM2 = FPWM1)............................................................................................ 2474
Figure 19-73. ZVS Full-H Bridge Waveforms........................................................................................................................ 2475
Figure 19-74. Peak Current Mode Control of Buck Converter...............................................................................................2476
Figure 19-75. Peak Current Mode Control Waveforms for Control of Buck Converter.......................................................... 2476
Figure 19-76. Control of Two Resonant Converter Stages....................................................................................................2477
Figure 19-77. H-Bridge LLC Resonant Converter PWM Waveforms.....................................................................................2477
Figure 19-78. HRPWM Block Diagram.................................................................................................................................. 2479
Figure 19-79. Resolution Calculations for Conventionally Generated PWM......................................................................... 2480
Figure 19-80. Operating Logic Using MEP............................................................................................................................ 2481
Figure 19-81. HRPWM Extension Registers and Memory Configuration.............................................................................. 2482
Figure 19-82. HRPWM System Interface.............................................................................................................................. 2483
Figure 19-83. HRPWM and HRCAL Source Clock................................................................................................................2484
Figure 19-84. Required PWM Waveform for a Requested Duty = 40.5%..............................................................................2487
Figure 19-85. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................ 2490
Figure 19-86. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................2491
Figure 19-87. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 1)........................................................2491

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Figure 19-88. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 1)..............................................2491
Figure 19-89. Simple Buck Controlled Converter Using a Single PWM................................................................................ 2498
Figure 19-90. PWM Waveform Generated for Simple Buck Controlled Converter................................................................ 2498
Figure 19-91. Simple Reconstruction Filter for a PWM-based DAC......................................................................................2500
Figure 19-92. PWM Waveform Generated for the PWM DAC Function................................................................................ 2500
Figure 19-93. TBCTL Register...............................................................................................................................................2528
Figure 19-94. TBCTL2 Register.............................................................................................................................................2530
Figure 19-95. EPWMSYNCINSEL Register.......................................................................................................................... 2531
Figure 19-96. TBCTR Register.............................................................................................................................................. 2532
Figure 19-97. TBSTS Register.............................................................................................................................................. 2533
Figure 19-98. EPWMSYNCOUTEN Register........................................................................................................................ 2534
Figure 19-99. TBCTL3 Register.............................................................................................................................................2536
Figure 19-100. CMPCTL Register......................................................................................................................................... 2537
Figure 19-101. CMPCTL2 Register....................................................................................................................................... 2539
Figure 19-102. DBCTL Register............................................................................................................................................ 2541
Figure 19-103. DBCTL2 Register.......................................................................................................................................... 2544
Figure 19-104. AQCTL Register............................................................................................................................................ 2545
Figure 19-105. AQTSRCSEL Register.................................................................................................................................. 2547
Figure 19-106. PCCTL Register............................................................................................................................................ 2548
Figure 19-107. VCAPCTL Register....................................................................................................................................... 2550
Figure 19-108. VCNTCFG Register.......................................................................................................................................2552
Figure 19-109. HRCNFG Register.........................................................................................................................................2554
Figure 19-110. HRPWR Register...........................................................................................................................................2556
Figure 19-111. HRMSTEP Register....................................................................................................................................... 2557
Figure 19-112. HRCNFG2 Register....................................................................................................................................... 2558
Figure 19-113. HRPCTL Register.......................................................................................................................................... 2559
Figure 19-114. TRREM Register............................................................................................................................................2561
Figure 19-115. GLDCTL Register.......................................................................................................................................... 2562
Figure 19-116. GLDCFG Register......................................................................................................................................... 2564
Figure 19-117. EPWMXLINK Register...................................................................................................................................2566
Figure 19-118. AQCTLA Register.......................................................................................................................................... 2568
Figure 19-119. AQCTLA2 Register........................................................................................................................................ 2570
Figure 19-120. AQCTLB Register..........................................................................................................................................2571
Figure 19-121. AQCTLB2 Register........................................................................................................................................2573
Figure 19-122. AQSFRC Register......................................................................................................................................... 2574
Figure 19-123. AQCSFRC Register...................................................................................................................................... 2575
Figure 19-124. DBREDHR Register...................................................................................................................................... 2576
Figure 19-125. DBRED Register........................................................................................................................................... 2577
Figure 19-126. DBFEDHR Register.......................................................................................................................................2578
Figure 19-127. DBFED Register............................................................................................................................................2579
Figure 19-128. TBPHS Register............................................................................................................................................ 2580
Figure 19-129. TBPRDHR Register.......................................................................................................................................2581
Figure 19-130. TBPRD Register............................................................................................................................................2582
Figure 19-131. CMPA Register.............................................................................................................................................. 2583
Figure 19-132. CMPB Register..............................................................................................................................................2584
Figure 19-133. CMPC Register............................................................................................................................................. 2585
Figure 19-134. CMPD Register............................................................................................................................................. 2586
Figure 19-135. GLDCTL2 Register........................................................................................................................................2587
Figure 19-136. SWVDELVAL Register...................................................................................................................................2588
Figure 19-137. TZSEL Register.............................................................................................................................................2589
Figure 19-138. TZDCSEL Register........................................................................................................................................2591
Figure 19-139. TZCTL Register.............................................................................................................................................2592
Figure 19-140. TZCTL2 Register...........................................................................................................................................2594
Figure 19-141. TZCTLDCA Register..................................................................................................................................... 2596
Figure 19-142. TZCTLDCB Register..................................................................................................................................... 2598
Figure 19-143. TZEINT Register........................................................................................................................................... 2600
Figure 19-144. TZFLG Register.............................................................................................................................................2601
Figure 19-145. TZCBCFLG Register..................................................................................................................................... 2603
Figure 19-146. TZOSTFLG Register..................................................................................................................................... 2605
Figure 19-147. TZCLR Register............................................................................................................................................ 2607
Figure 19-148. TZCBCCLR Register.....................................................................................................................................2609

40 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 19-149. TZOSTCLR Register..................................................................................................................................... 2610

Figure 19-150. TZFRC Register.............................................................................................................................................2611
Figure 19-151. ETSEL Register.............................................................................................................................................2612
Figure 19-152. ETPS Register...............................................................................................................................................2615
Figure 19-153. ETFLG Register............................................................................................................................................ 2618
Figure 19-154. ETCLR Register............................................................................................................................................ 2619
Figure 19-155. ETFRC Register............................................................................................................................................ 2620
Figure 19-156. ETINTPS Register.........................................................................................................................................2621
Figure 19-157. ETSOCPS Register.......................................................................................................................................2622
Figure 19-158. ETCNTINITCTL Register.............................................................................................................................. 2624
Figure 19-159. ETCNTINIT Register..................................................................................................................................... 2625
Figure 19-160. DCTRIPSEL Register....................................................................................................................................2626
Figure 19-161. DCACTL Register..........................................................................................................................................2628
Figure 19-162. DCBCTL Register..........................................................................................................................................2630
Figure 19-163. DCFCTL Register..........................................................................................................................................2632
Figure 19-164. DCCAPCTL Register.....................................................................................................................................2634
Figure 19-165. DCFOFFSET Register.................................................................................................................................. 2636
Figure 19-166. DCFOFFSETCNT Register........................................................................................................................... 2637
Figure 19-167. DCFWINDOW Register.................................................................................................................................2638
Figure 19-168. DCFWINDOWCNT Register..........................................................................................................................2639
Figure 19-169. BLANKPULSEMIXSEL Register................................................................................................................... 2640
Figure 19-170. DCCAP Register........................................................................................................................................... 2642
Figure 19-171. DCAHTRIPSEL Register...............................................................................................................................2643
Figure 19-172. DCALTRIPSEL Register................................................................................................................................2645
Figure 19-173. DCBHTRIPSEL Register...............................................................................................................................2647
Figure 19-174. DCBLTRIPSEL Register................................................................................................................................2649
Figure 19-175. EPWMLOCK Register................................................................................................................................... 2651
Figure 19-176. HWVDELVAL Register.................................................................................................................................. 2653
Figure 19-177. VCNTVAL Register........................................................................................................................................2654
Figure 20-1. Capture and APWM Modes of Operation..........................................................................................................2661
Figure 20-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode....................................................... 2662
Figure 20-3. eCAP Block Diagram.........................................................................................................................................2663
Figure 20-4. Event Prescale Control......................................................................................................................................2664
Figure 20-5. Prescale Function Waveforms...........................................................................................................................2664
Figure 20-6. Details of the Continuous/One-shot Block.........................................................................................................2665
Figure 20-7. Details of the Counter and Synchronization Block............................................................................................ 2666
Figure 20-8. eCAP Synchronization Scheme........................................................................................................................ 2667
Figure 20-9. Interrupts in eCAP Module................................................................................................................................ 2668
Figure 20-10. PWM Waveform Details Of APWM Mode Operation.......................................................................................2669
Figure 20-11. Time-Base Frequency and Period Calculation................................................................................................ 2670
Figure 20-12. Capture Sequence for Absolute Time-stamp and Rising-Edge Detect........................................................... 2671
Figure 20-13. Capture Sequence for Absolute Time-stamp with Rising- and Falling-Edge Detect....................................... 2672
Figure 20-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect....................................................... 2673
Figure 20-15. Capture Sequence for Delta Mode Time-stamp with Rising- and Falling-Edge Detect...................................2674
Figure 20-16. PWM Waveform Details of APWM Mode Operation....................................................................................... 2675
Figure 20-17. TSCTR Register.............................................................................................................................................. 2680
Figure 20-18. CTRPHS Register........................................................................................................................................... 2681
Figure 20-19. CAP1 Register.................................................................................................................................................2682
Figure 20-20. CAP2 Register.................................................................................................................................................2683
Figure 20-21. CAP3 Register.................................................................................................................................................2684
Figure 20-22. CAP4 Register.................................................................................................................................................2685
Figure 20-23. ECCTL0 Register............................................................................................................................................ 2686
Figure 20-24. ECCTL1 Register............................................................................................................................................ 2687
Figure 20-25. ECCTL2 Register............................................................................................................................................ 2689
Figure 20-26. ECEINT Register.............................................................................................................................................2691
Figure 20-27. ECFLG Register.............................................................................................................................................. 2693
Figure 20-28. ECCLR Register..............................................................................................................................................2695
Figure 20-29. ECFRC Register..............................................................................................................................................2696
Figure 20-30. ECAPSYNCINSEL Register............................................................................................................................2697
Figure 21-1. Optical Encoder Disk.........................................................................................................................................2699
Figure 21-2. QEP Encoder Output Signal for Forward/Reverse Movement.......................................................................... 2699

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Figure 21-3. Index Pulse Example.........................................................................................................................................2700

Figure 21-4. Using eQEP to Decode Signals from SinCos Transducer.................................................................................2703
Figure 21-5. Functional Block Diagram of the eQEP Peripheral........................................................................................... 2705
Figure 21-6. Functional Block Diagram of Decoder Unit....................................................................................................... 2707
Figure 21-7. Quadrature Decoder State Machine..................................................................................................................2708
Figure 21-8. Quadrature-clock and Direction Decoding........................................................................................................ 2709
Figure 21-9. Position Counter Reset by Index Pulse for 1000-Line Encoder (QPOSMAX = 3999 or 0xF9F)....................... 2711
Figure 21-10. Position Counter Underflow/Overflow (QPOSMAX = 4)..................................................................................2712
Figure 21-11. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)..................................................................2714
Figure 21-12. Strobe Event Latch (QEPCTL[SEL] = 1)......................................................................................................... 2714
Figure 21-13. Latching Position Counter on ADCSOCA/ADCSOCB Event.......................................................................... 2715
Figure 21-14. eQEP Position-compare Unit.......................................................................................................................... 2716
Figure 21-15. eQEP Position-compare Event Generation Points..........................................................................................2717
Figure 21-16. eQEP Position-compare Sync Output Pulse Stretcher................................................................................... 2717
Figure 21-17. eQEP Edge Capture Unit................................................................................................................................ 2719
Figure 21-18. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)...............................................2720
Figure 21-19. eQEP Edge Capture Unit - Timing Details...................................................................................................... 2720
Figure 21-20. eQEP Watchdog Timer....................................................................................................................................2722
Figure 21-21. eQEP Unit Timer Base.................................................................................................................................... 2722
Figure 21-22. QMA Module Block Diagram........................................................................................................................... 2723
Figure 21-23. QMA Mode-1................................................................................................................................................... 2724
Figure 21-24. QMA Mode-2................................................................................................................................................... 2725
Figure 21-25. eQEP Interrupt Generation..............................................................................................................................2726
Figure 21-26. QPOSCNT Register........................................................................................................................................ 2734
Figure 21-27. QPOSINIT Register.........................................................................................................................................2735
Figure 21-28. QPOSMAX Register........................................................................................................................................2736
Figure 21-29. QPOSCMP Register........................................................................................................................................2737
Figure 21-30. QPOSILAT Register........................................................................................................................................ 2738
Figure 21-31. QPOSSLAT Register....................................................................................................................................... 2739
Figure 21-32. QPOSLAT Register......................................................................................................................................... 2740
Figure 21-33. QUTMR Register.............................................................................................................................................2741
Figure 21-34. QUPRD Register............................................................................................................................................. 2742
Figure 21-35. QWDTMR Register......................................................................................................................................... 2743
Figure 21-36. QWDPRD Register..........................................................................................................................................2744
Figure 21-37. QDECCTL Register.........................................................................................................................................2745
Figure 21-38. QEPCTL Register............................................................................................................................................2747
Figure 21-39. QCAPCTL Register......................................................................................................................................... 2749
Figure 21-40. QPOSCTL Register.........................................................................................................................................2750
Figure 21-41. QEINT Register............................................................................................................................................... 2751
Figure 21-42. QFLG Register................................................................................................................................................ 2753
Figure 21-43. QCLR Register................................................................................................................................................ 2755
Figure 21-44. QFRC Register................................................................................................................................................2757
Figure 21-45. QEPSTS Register........................................................................................................................................... 2759
Figure 21-46. QCTMR Register.............................................................................................................................................2761
Figure 21-47. QCPRD Register............................................................................................................................................. 2762
Figure 21-48. QCTMRLAT Register.......................................................................................................................................2763
Figure 21-49. QCPRDLAT Register.......................................................................................................................................2764
Figure 21-50. REV Register...................................................................................................................................................2765
Figure 21-51. QEPSTROBESEL Register.............................................................................................................................2766
Figure 21-52. QMACTRL Register........................................................................................................................................ 2767
Figure 21-53. QEPSRCSEL Register.................................................................................................................................... 2768
Figure 22-1. SPI CPU Interface............................................................................................................................................. 2772
Figure 22-2. SPI Interrupt Flags and Enable Logic Generation.............................................................................................2775
Figure 22-3. SPI DMA Trigger Diagram.................................................................................................................................2776
Figure 22-4. SPI Controller/Peripheral Connection............................................................................................................... 2777
Figure 22-5. SPI Module Controller Configuration.................................................................................................................2779
Figure 22-6. SPI Module Peripheral Configuration................................................................................................................ 2780
Figure 22-7. SPICLK Signal Options..................................................................................................................................... 2783
Figure 22-8. SPI: SPICLK-LSPCLK Characteristic when (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1.................. 2784
Figure 22-9. SPI 3-wire Controller Mode............................................................................................................................... 2786
Figure 22-10. SPI 3-wire Peripheral Mode............................................................................................................................ 2787

42 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 22-11. Five Bits per Character.................................................................................................................................... 2790

Figure 22-12. SPI Digital Audio Receiver Configuration Using Two SPIs............................................................................. 2793
Figure 22-13. Standard Right-Justified Digital Audio Data Format........................................................................................2793
Figure 22-14. SPICCR Register............................................................................................................................................ 2800
Figure 22-15. SPICTL Register............................................................................................................................................. 2802
Figure 22-16. SPISTS Register............................................................................................................................................. 2804
Figure 22-17. SPIBRR Register.............................................................................................................................................2806
Figure 22-18. SPIRXEMU Register....................................................................................................................................... 2807
Figure 22-19. SPIRXBUF Register........................................................................................................................................ 2808
Figure 22-20. SPITXBUF Register........................................................................................................................................ 2809
Figure 22-21. SPIDAT Register............................................................................................................................................. 2810
Figure 22-22. SPIFFTX Register............................................................................................................................................2811
Figure 22-23. SPIFFRX Register...........................................................................................................................................2813
Figure 22-24. SPIFFCT Register........................................................................................................................................... 2815
Figure 22-25. SPIPRI Register.............................................................................................................................................. 2816
Figure 23-1. SCI CPU Interface.............................................................................................................................................2819
Figure 23-2. Serial Communications Interface (SCI) Module Block Diagram........................................................................2821
Figure 23-3. Typical SCI Data Frame Formats...................................................................................................................... 2823
Figure 23-4. Idle-Line Multiprocessor Communication Format..............................................................................................2825
Figure 23-5. Double-Buffered WUT and TXSHF................................................................................................................... 2826
Figure 23-6. Address-Bit Multiprocessor Communication Format......................................................................................... 2827
Figure 23-7. SCI Asynchronous Communications Format.................................................................................................... 2828
Figure 23-8. SCI RX Signals in Communication Modes........................................................................................................ 2829
Figure 23-9. SCI TX Signals in Communications Mode........................................................................................................ 2830
Figure 23-10. SCI FIFO Interrupt Flags and Enable Logic.................................................................................................... 2834
Figure 23-11. SCICCR Register.............................................................................................................................................2842
Figure 23-12. SCICTL1 Register........................................................................................................................................... 2844
Figure 23-13. SCIHBAUD Register....................................................................................................................................... 2846
Figure 23-14. SCILBAUD Register........................................................................................................................................ 2847
Figure 23-15. SCICTL2 Register........................................................................................................................................... 2848
Figure 23-16. SCIRXST Register.......................................................................................................................................... 2850
Figure 23-17. SCIRXEMU Register....................................................................................................................................... 2853
Figure 23-18. SCIRXBUF Register........................................................................................................................................2854
Figure 23-19. SCITXBUF Register........................................................................................................................................ 2856
Figure 23-20. SCIFFTX Register........................................................................................................................................... 2857
Figure 23-21. SCIFFRX Register...........................................................................................................................................2859
Figure 23-22. SCIFFCT Register...........................................................................................................................................2861
Figure 23-23. SCIPRI Register.............................................................................................................................................. 2862
Figure 24-1. USB Block Diagram...........................................................................................................................................2865
Figure 24-2. USB Scheme.....................................................................................................................................................2866
Figure 24-3. USBFADDR Register........................................................................................................................................ 2904
Figure 24-4. USBPOWER Register....................................................................................................................................... 2905
Figure 24-5. USBTXIS Register.............................................................................................................................................2906
Figure 24-6. USBRXIS Register............................................................................................................................................ 2907
Figure 24-7. USBTXIE Register.............................................................................................................................................2908
Figure 24-8. USBRXIE Register............................................................................................................................................ 2909
Figure 24-9. USBIS Register................................................................................................................................................. 2910
Figure 24-10. USBIE Register................................................................................................................................................2911
Figure 24-11. USBFRAME Register...................................................................................................................................... 2912
Figure 24-12. USBEPIDX Register........................................................................................................................................2913
Figure 24-13. USBTEST Register......................................................................................................................................... 2914
Figure 24-14. USBFIFO0 Register........................................................................................................................................ 2915
Figure 24-15. USBFIFO1 Register........................................................................................................................................ 2916
Figure 24-16. USBFIFO2 Register........................................................................................................................................ 2917
Figure 24-17. USBFIFO3 Register........................................................................................................................................ 2918
Figure 24-18. USBDEVCTL Register.................................................................................................................................... 2919
Figure 24-19. USBTXFIFOSZ Register................................................................................................................................. 2921
Figure 24-20. USBRXFIFOSZ Register.................................................................................................................................2922
Figure 24-21. USBTXFIFOADD Register.............................................................................................................................. 2923
Figure 24-22. USBRXFIFOADD Register..............................................................................................................................2932
Figure 24-23. USBCONTIM Register.................................................................................................................................... 2941

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Figure 24-24. USBFSEOF Register.......................................................................................................................................2942

Figure 24-25. USBLSEOF Register.......................................................................................................................................2943
Figure 24-26. USBTXFUNCADDR0 Register........................................................................................................................2944
Figure 24-27. USBTXHUBADDR0 Register.......................................................................................................................... 2945
Figure 24-28. USBTXHUBPORT0 Register...........................................................................................................................2946
Figure 24-29. USBTXFUNCADDR1 Register........................................................................................................................2947
Figure 24-30. USBTXHUBADDR1 Register.......................................................................................................................... 2948
Figure 24-31. USBTXHUBPORT1 Register...........................................................................................................................2949
Figure 24-32. USBRXFUNCADDR1 Register....................................................................................................................... 2950
Figure 24-33. USBRXHUBADDR1 Register..........................................................................................................................2951
Figure 24-34. USBRXHUBPORT1 Register.......................................................................................................................... 2952
Figure 24-35. USBTXFUNCADDR2 Register........................................................................................................................2953
Figure 24-36. USBTXHUBADDR2 Register.......................................................................................................................... 2954
Figure 24-37. USBTXHUBPORT2 Register...........................................................................................................................2955
Figure 24-38. USBRXFUNCADDR2 Register....................................................................................................................... 2956
Figure 24-39. USBRXHUBADDR2 Register..........................................................................................................................2957
Figure 24-40. USBRXHUBPORT2 Register.......................................................................................................................... 2958
Figure 24-41. USBTXFUNCADDR3 Register........................................................................................................................2959
Figure 24-42. USBTXHUBADDR3 Register.......................................................................................................................... 2960
Figure 24-43. USBTXHUBPORT3 Register...........................................................................................................................2961
Figure 24-44. USBRXFUNCADDR3 Register....................................................................................................................... 2962
Figure 24-45. USBRXHUBADDR3 Register..........................................................................................................................2963
Figure 24-46. USBRXHUBPORT3 Register.......................................................................................................................... 2964
Figure 24-47. USBCSRL0 Register....................................................................................................................................... 2965
Figure 24-48. USBCSRH0 Register...................................................................................................................................... 2967
Figure 24-49. USBCOUNT0 Register....................................................................................................................................2968
Figure 24-50. USBTYPE0 Register....................................................................................................................................... 2969
Figure 24-51. USBNAKLMT Register.................................................................................................................................... 2970
Figure 24-52. USBTXMAXP1 Register..................................................................................................................................2971
Figure 24-53. USBTXCSRL1 Register.................................................................................................................................. 2972
Figure 24-54. USBTXCSRH1 Register..................................................................................................................................2974
Figure 24-55. USBRXMAXP1 Register................................................................................................................................. 2976
Figure 24-56. USBRXCSRL1 Register.................................................................................................................................. 2977
Figure 24-57. USBRXCSRH1 Register................................................................................................................................. 2979
Figure 24-58. USBRXCOUNT1 Register...............................................................................................................................2981
Figure 24-59. USBTXTYPE1 Register...................................................................................................................................2982
Figure 24-60. USBTXINTERVAL1 Register...........................................................................................................................2983
Figure 24-61. USBRXTYPE1 Register.................................................................................................................................. 2984
Figure 24-62. USBRXINTERVAL1 Register.......................................................................................................................... 2985
Figure 24-63. USBTXMAXP2 Register..................................................................................................................................2986
Figure 24-64. USBTXCSRL2 Register.................................................................................................................................. 2987
Figure 24-65. USBTXCSRH2 Register..................................................................................................................................2989
Figure 24-66. USBRXMAXP2 Register................................................................................................................................. 2991
Figure 24-67. USBRXCSRL2 Register.................................................................................................................................. 2992
Figure 24-68. USBRXCSRH2 Register................................................................................................................................. 2994
Figure 24-69. USBRXCOUNT2 Register...............................................................................................................................2996
Figure 24-70. USBTXTYPE2 Register...................................................................................................................................2997
Figure 24-71. USBTXINTERVAL2 Register...........................................................................................................................2998
Figure 24-72. USBRXTYPE2 Register.................................................................................................................................. 2999
Figure 24-73. USBRXINTERVAL2 Register.......................................................................................................................... 3000
Figure 24-74. USBTXMAXP3 Register..................................................................................................................................3001
Figure 24-75. USBTXCSRL3 Register.................................................................................................................................. 3002
Figure 24-76. USBTXCSRH3 Register..................................................................................................................................3004
Figure 24-77. USBRXMAXP3 Register................................................................................................................................. 3006
Figure 24-78. USBRXCSRL3 Register.................................................................................................................................. 3007
Figure 24-79. USBRXCSRH3 Register................................................................................................................................. 3009
Figure 24-80. USBRXCOUNT3 Register............................................................................................................................... 3011
Figure 24-81. USBTXTYPE3 Register...................................................................................................................................3012
Figure 24-82. USBTXINTERVAL3 Register...........................................................................................................................3013
Figure 24-83. USBRXTYPE3 Register.................................................................................................................................. 3014
Figure 24-84. USBRXINTERVAL3 Register.......................................................................................................................... 3015

44 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 24-85. USBRQPKTCOUNT1 Register....................................................................................................................... 3016

Figure 24-86. USBRQPKTCOUNT2 Register....................................................................................................................... 3017
Figure 24-87. USBRQPKTCOUNT3 Register....................................................................................................................... 3018
Figure 24-88. USBRXDPKTBUFDIS Register.......................................................................................................................3019
Figure 24-89. USBTXDPKTBUFDIS Register....................................................................................................................... 3020
Figure 24-90. USBEPC Register........................................................................................................................................... 3021
Figure 24-91. USBEPCRIS Register..................................................................................................................................... 3023
Figure 24-92. USBEPCIM Register....................................................................................................................................... 3024
Figure 24-93. USBEPCISC Register..................................................................................................................................... 3025
Figure 24-94. USBDRRIS Register....................................................................................................................................... 3026
Figure 24-95. USBDRIM Register......................................................................................................................................... 3027
Figure 24-96. USBDRISC Register....................................................................................................................................... 3028
Figure 24-97. USBGPCS Register........................................................................................................................................ 3029
Figure 24-98. USBVDC Register........................................................................................................................................... 3030
Figure 24-99. USBVDCRIS Register..................................................................................................................................... 3031
Figure 24-100. USBVDCIM Register..................................................................................................................................... 3032
Figure 24-101. USBVDCISC Register................................................................................................................................... 3033
Figure 24-102. USBIDVRIS Register.....................................................................................................................................3034
Figure 24-103. USBIDVIM Register.......................................................................................................................................3035
Figure 24-104. USBIDVISC Register.....................................................................................................................................3036
Figure 24-105. USBDMASEL Register..................................................................................................................................3037
Figure 24-106. USB_GLB_INT_EN Register.........................................................................................................................3039
Figure 24-107. USB_GLB_INT_FLG Register.......................................................................................................................3040
Figure 24-108. USB_GLB_INT_FLG_CLR Register............................................................................................................. 3041
Figure 24-109. USBDMARIS Register...................................................................................................................................3042
Figure 24-110. USBDMAIM Register..................................................................................................................................... 3043
Figure 24-111. USBDMAISC Register................................................................................................................................... 3045
Figure 25-1. FSI Transmitter (FSITX) CPU Interface.............................................................................................................3049
Figure 25-2. FSI Receiver (FSIRX) CPU Interface with CLB.................................................................................................3050
Figure 25-3. FSI Transmitter Block Diagram......................................................................................................................... 3057
Figure 25-4. FSI Transmitter Core Block Diagram.................................................................................................................3058
Figure 25-5. FSI Receiver Block Diagram............................................................................................................................. 3063
Figure 25-6. FSI Receiver Core Block Diagram.................................................................................................................... 3064
Figure 25-7. Delay Line Control Circuit..................................................................................................................................3067
Figure 25-8. Flush Sequence Signals....................................................................................................................................3073
Figure 25-9. FSI with Internal Loopback................................................................................................................................3074
Figure 25-10. FSI Multi-Node TDM Configuration................................................................................................................. 3077
Figure 25-11. FSI Transmitter Multi-Node TDM Multiplexing.................................................................................................3077
Figure 25-12. Generated Signals for FSI Multi-Node TDM Configuration............................................................................. 3078
Figure 25-13. RX_TRIGx FSI Trigger.................................................................................................................................... 3079
Figure 25-14. FSITX as SPI Controller, Transmit Only..........................................................................................................3081
Figure 25-15. FSIRX as SPI Peripheral, Receive Only......................................................................................................... 3082
Figure 25-16. FSITX and FSIRX as SPI Controller, Full Duplex........................................................................................... 3083
Figure 25-17. Point to Point Connection................................................................................................................................3084
Figure 25-18. TX_MAIN_CTRL Register............................................................................................................................... 3100
Figure 25-19. TX_CLK_CTRL Register................................................................................................................................. 3101
Figure 25-20. TX_OPER_CTRL_LO Register....................................................................................................................... 3102
Figure 25-21. TX_OPER_CTRL_HI Register........................................................................................................................ 3104
Figure 25-22. TX_FRAME_CTRL Register........................................................................................................................... 3105
Figure 25-23. TX_FRAME_TAG_UDATA Register................................................................................................................ 3106
Figure 25-24. TX_BUF_PTR_LOAD Register....................................................................................................................... 3107
Figure 25-25. TX_BUF_PTR_STS Register.......................................................................................................................... 3108
Figure 25-26. TX_PING_CTRL Register............................................................................................................................... 3109
Figure 25-27. TX_PING_TAG Register..................................................................................................................................3110
Figure 25-28. TX_PING_TO_REF Register........................................................................................................................... 3111
Figure 25-29. TX_PING_TO_CNT Register...........................................................................................................................3112
Figure 25-30. TX_INT_CTRL Register...................................................................................................................................3113
Figure 25-31. TX_DMA_CTRL Register................................................................................................................................ 3115
Figure 25-32. TX_LOCK_CTRL Register...............................................................................................................................3116
Figure 25-33. TX_EVT_STS Register....................................................................................................................................3117
Figure 25-34. TX_EVT_CLR Register....................................................................................................................................3118

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Figure 25-35. TX_EVT_FRC Register................................................................................................................................... 3119

Figure 25-36. TX_USER_CRC Register................................................................................................................................3120
Figure 25-37. TX_ECC_DATA Register.................................................................................................................................3121
Figure 25-38. TX_ECC_VAL Register................................................................................................................................... 3122
Figure 25-39. TX_DLYLINE_CTRL Register......................................................................................................................... 3123
Figure 25-40. TX_BUF_BASE_y Register.............................................................................................................................3124
Figure 25-41. RX_MAIN_CTRL Register...............................................................................................................................3127
Figure 25-42. RX_OPER_CTRL Register............................................................................................................................. 3129
Figure 25-43. RX_FRAME_INFO Register............................................................................................................................3131
Figure 25-44. RX_FRAME_TAG_UDATA Register................................................................................................................3132
Figure 25-45. RX_DMA_CTRL Register................................................................................................................................3133
Figure 25-46. RX_EVT_STS Register................................................................................................................................... 3134
Figure 25-47. RX_CRC_INFO Register.................................................................................................................................3137
Figure 25-48. RX_EVT_CLR Register...................................................................................................................................3138
Figure 25-49. RX_EVT_FRC Register...................................................................................................................................3140
Figure 25-50. RX_BUF_PTR_LOAD Register.......................................................................................................................3143
Figure 25-51. RX_BUF_PTR_STS Register..........................................................................................................................3144
Figure 25-52. RX_FRAME_WD_CTRL Register................................................................................................................... 3145
Figure 25-53. RX_FRAME_WD_REF Register..................................................................................................................... 3146
Figure 25-54. RX_FRAME_WD_CNT Register..................................................................................................................... 3147
Figure 25-55. RX_PING_WD_CTRL Register.......................................................................................................................3148
Figure 25-56. RX_PING_TAG Register................................................................................................................................. 3149
Figure 25-57. RX_PING_WD_REF Register......................................................................................................................... 3150
Figure 25-58. RX_PING_WD_CNT Register.........................................................................................................................3151
Figure 25-59. RX_INT1_CTRL Register................................................................................................................................3152
Figure 25-60. RX_INT2_CTRL Register................................................................................................................................3155
Figure 25-61. RX_LOCK_CTRL Register..............................................................................................................................3158
Figure 25-62. RX_ECC_DATA Register................................................................................................................................ 3159
Figure 25-63. RX_ECC_VAL Register................................................................................................................................... 3160
Figure 25-64. RX_ECC_SEC_DATA Register....................................................................................................................... 3161
Figure 25-65. RX_ECC_LOG Register..................................................................................................................................3162
Figure 25-66. RX_FRAME_TAG_CMP Register................................................................................................................... 3163
Figure 25-67. RX_PING_TAG_CMP Register....................................................................................................................... 3164
Figure 25-68. RX_TRIG_CTRL_0 Register........................................................................................................................... 3165
Figure 25-69. RX_TRIG_WIDTH_0 Register.........................................................................................................................3166
Figure 25-70. RX_DLYLINE_CTRL Register......................................................................................................................... 3167
Figure 25-71. RX_TRIG_CTRL_1 Register........................................................................................................................... 3168
Figure 25-72. RX_TRIG_CTRL_2 Register........................................................................................................................... 3169
Figure 25-73. RX_TRIG_CTRL_3 Register........................................................................................................................... 3170
Figure 25-74. RX_VIS_1 Register......................................................................................................................................... 3171
Figure 25-75. RX_UDATA_FILTER Register......................................................................................................................... 3172
Figure 25-76. RX_BUF_BASE_y Register............................................................................................................................ 3173
Figure 26-1. Multiple I2C Modules Connected...................................................................................................................... 3175
Figure 26-2. I2C Module Conceptual Block Diagram............................................................................................................ 3178
Figure 26-3. Clocking Diagram for the I2C Module............................................................................................................... 3178
Figure 26-4. Roles of the Clock Divide-Down Values (ICCL and ICCH)................................................................................3179
Figure 26-5. Bit Transfer on the I2C bus................................................................................................................................3180
Figure 26-6. I2C Target TX / RX Flowchart............................................................................................................................3183
Figure 26-7. I2C Controller TX / RX Flowchart...................................................................................................................... 3184
Figure 26-8. I2C Module START and STOP Conditions........................................................................................................3185
Figure 26-9. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)......................................... 3186
Figure 26-10. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR).............................................................. 3187
Figure 26-11. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR).............................................................3187
Figure 26-12. I2C Module Free Data Format (FDF = 1 in I2CMDR)......................................................................................3188
Figure 26-13. Repeated START Condition (in This Case, 7-Bit Addressing Format)............................................................ 3188
Figure 26-14. Synchronization of Two I2C Clock Generators During Arbitration...................................................................3189
Figure 26-15. Automatic Clock Stretching............................................................................................................................. 3190
Figure 26-16. Extended Automatic Clock Stretching............................................................................................................. 3191
Figure 26-17. Arbitration Procedure Between Two Controller-Transmitters.......................................................................... 3192
Figure 26-18. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit.....................................................3193
Figure 26-19. Enable Paths of the I2C Interrupt Requests....................................................................................................3196

46 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 26-20. I2C FIFO Interrupt........................................................................................................................................... 3197

Figure 26-21. I2COAR Register.............................................................................................................................................3204
Figure 26-22. I2CIER Register.............................................................................................................................................. 3205
Figure 26-23. I2CSTR Register............................................................................................................................................. 3206
Figure 26-24. I2CCLKL Register........................................................................................................................................... 3210
Figure 26-25. I2CCLKH Register........................................................................................................................................... 3211
Figure 26-26. I2CCNT Register............................................................................................................................................. 3212
Figure 26-27. I2CDRR Register.............................................................................................................................................3213
Figure 26-28. I2CTAR Register..............................................................................................................................................3214
Figure 26-29. I2CDXR Register.............................................................................................................................................3215
Figure 26-30. I2CMDR Register............................................................................................................................................ 3216
Figure 26-31. I2CISRC Register............................................................................................................................................3220
Figure 26-32. I2CEMDR Register..........................................................................................................................................3221
Figure 26-33. I2CPSC Register............................................................................................................................................. 3223
Figure 26-34. I2CFFTX Register........................................................................................................................................... 3224
Figure 26-35. I2CFFRX Register........................................................................................................................................... 3226
Figure 27-1. PMBus Module Block Diagram..........................................................................................................................3229
Figure 27-2. Quick Command Message................................................................................................................................ 3231
Figure 27-3. Send Byte Message With and Without PEC..................................................................................................... 3232
Figure 27-4. Receive Byte Message With and Without PEC.................................................................................................3232
Figure 27-5. Write Byte and Write Word Messages With and Without PEC..........................................................................3233
Figure 27-6. Read Byte and Read Word Messages With and Without PEC......................................................................... 3234
Figure 27-7. Process Call Message With and Without PEC..................................................................................................3235
Figure 27-8. Block Write Message With and Without PEC.................................................................................................... 3235
Figure 27-9. Block Read Message With and Without PEC....................................................................................................3236
Figure 27-10. Block Write-Block Read Process Call Message With and Without PEC......................................................... 3237
Figure 27-11. Alert Response Message.................................................................................................................................3237
Figure 27-12. Extended Command Write Byte and Write Word Messages With and Without PEC...................................... 3238
Figure 27-13. Extended Command Read Byte and Read Word Messages With and Without PEC......................................3239
Figure 27-14. Group Command Message With and Without PEC........................................................................................ 3240
Figure 27-15. Quick Command Message.............................................................................................................................. 3241
Figure 27-16. Send Byte Message With and Without PEC................................................................................................... 3242
Figure 27-17. Receive Byte Message With and Without PEC...............................................................................................3242
Figure 27-18. Write Byte and Write Word Messages With and Without PEC........................................................................3243
Figure 27-19. Read Byte and Read Word Messages With and Without PEC....................................................................... 3244
Figure 27-20. Process Call Message With and Without PEC................................................................................................3245
Figure 27-21. Block Write Message With and Without PEC.................................................................................................. 3246
Figure 27-22. Block Read Message With and Without PEC..................................................................................................3247
Figure 27-23. Block Write-Block Read Process Call Message With and Without PEC......................................................... 3248
Figure 27-24. Alert Response Message................................................................................................................................ 3248
Figure 27-25. Extended Command Write Byte and Write Word Messages With and Without PEC...................................... 3249
Figure 27-26. Extended Command Read Byte and Read Word Messages With and Without PEC......................................3250
Figure 27-27. Group Command Message With and Without PEC........................................................................................ 3251
Figure 27-28. PMBCCR Register.......................................................................................................................................... 3255
Figure 27-29. PMBTXBUF Register...................................................................................................................................... 3257
Figure 27-30. PMBRXBUF Register...................................................................................................................................... 3258
Figure 27-31. PMBACK Register...........................................................................................................................................3259
Figure 27-32. PMBSTS Register........................................................................................................................................... 3260
Figure 27-33. PMBINTM Register......................................................................................................................................... 3262
Figure 27-34. PMBTCR Register...........................................................................................................................................3264
Figure 27-35. PMBHTA Register........................................................................................................................................... 3266
Figure 27-36. PMBCTRL Register.........................................................................................................................................3267
Figure 27-37. PMBTIMCTL Register..................................................................................................................................... 3269
Figure 27-38. PMBTIMCLK Register..................................................................................................................................... 3270
Figure 27-39. PMBTIMSTSETUP Register........................................................................................................................... 3271
Figure 27-40. PMBTIMBIDLE Register..................................................................................................................................3272
Figure 27-41. PMBTIMLOWTIMOUT Register...................................................................................................................... 3273
Figure 27-42. PMBTIMHIGHTIMOUT Register..................................................................................................................... 3274
Figure 28-1. MCAN Module Overview................................................................................................................................... 3276
Figure 28-2. MCAN Typical Bus Wiring................................................................................................................................. 3277
Figure 28-3. MCAN Integration..............................................................................................................................................3279

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Figure 28-4. MCAN Block Diagram....................................................................................................................................... 3281

Figure 28-5. CAN FD Frame..................................................................................................................................................3284
Figure 28-6. CAN Bit Timing.................................................................................................................................................. 3286
Figure 28-7. Transmitter Delay Measurement....................................................................................................................... 3287
Figure 28-8. Connection of Signals in Bus Monitoring Mode.................................................................................................3288
Figure 28-9. Auto Wakeup Enabled Exit from Power Down.................................................................................................. 3291
Figure 28-10. External Loop Back Mode............................................................................................................................... 3292
Figure 28-11. Internal Loop Back Mode.................................................................................................................................3293
Figure 28-12. External Timestamp Counter Interrupt............................................................................................................ 3294
Figure 28-13. Standard Message ID Filter Path.................................................................................................................... 3299
Figure 28-14. Extended Message ID Filter Path....................................................................................................................3300
Figure 28-15. Rx FIFO Status................................................................................................................................................3301
Figure 28-16. Rx FIFO Overflow Handling............................................................................................................................ 3302
Figure 28-17. Mixed Dedicated Tx Buffers /Tx FIFO (example)............................................................................................ 3306
Figure 28-18. Mixed Dedicated Tx Buffers /Tx Queue (example)..........................................................................................3306
Figure 28-19. Message RAM Configuration.......................................................................................................................... 3308
Figure 28-20. Rx Buffer/Rx FIFO Element Structure............................................................................................................. 3309
Figure 28-21. Tx Buffer Element Structure............................................................................................................................ 3311
Figure 28-22. Tx Event FIFO Element Structure................................................................................................................... 3313
Figure 28-23. Standard Message ID Filter Element Structure...............................................................................................3314
Figure 28-24. Extended Message ID Filter Element Structure.............................................................................................. 3316
Figure 28-25. MCANSS_PID Register...................................................................................................................................3327
Figure 28-26. MCANSS_CTRL Register............................................................................................................................... 3328
Figure 28-27. MCANSS_STAT Register................................................................................................................................ 3329
Figure 28-28. MCANSS_ICS Register...................................................................................................................................3330
Figure 28-29. MCANSS_IRS Register...................................................................................................................................3331
Figure 28-30. MCANSS_IECS Register................................................................................................................................ 3332
Figure 28-31. MCANSS_IE Register..................................................................................................................................... 3333
Figure 28-32. MCANSS_IES Register...................................................................................................................................3334
Figure 28-33. MCANSS_EOI Register.................................................................................................................................. 3335
Figure 28-34. MCANSS_EXT_TS_PRESCALER Register................................................................................................... 3336
Figure 28-35. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register........................................................................... 3337
Figure 28-36. MCAN_CREL Register....................................................................................................................................3340
Figure 28-37. MCAN_ENDN Register................................................................................................................................... 3341
Figure 28-38. MCAN_DBTP Register....................................................................................................................................3342
Figure 28-39. MCAN_TEST Register.................................................................................................................................... 3344
Figure 28-40. MCAN_RWD Register..................................................................................................................................... 3345
Figure 28-41. MCAN_CCCR Register................................................................................................................................... 3346
Figure 28-42. MCAN_NBTP Register....................................................................................................................................3349
Figure 28-43. MCAN_TSCC Register....................................................................................................................................3351
Figure 28-44. MCAN_TSCV Register....................................................................................................................................3352
Figure 28-45. MCAN_TOCC Register................................................................................................................................... 3353
Figure 28-46. MCAN_TOCV Register....................................................................................................................................3354
Figure 28-47. MCAN_ECR Register......................................................................................................................................3355
Figure 28-48. MCAN_PSR Register...................................................................................................................................... 3356
Figure 28-49. MCAN_TDCR Register................................................................................................................................... 3359
Figure 28-50. MCAN_IR Register..........................................................................................................................................3360
Figure 28-51. MCAN_IE Register.......................................................................................................................................... 3364
Figure 28-52. MCAN_ILS Register........................................................................................................................................ 3366
Figure 28-53. MCAN_ILE Register........................................................................................................................................ 3369
Figure 28-54. MCAN_GFC Register......................................................................................................................................3370
Figure 28-55. MCAN_SIDFC Register...................................................................................................................................3371
Figure 28-56. MCAN_XIDFC Register...................................................................................................................................3372
Figure 28-57. MCAN_XIDAM Register.................................................................................................................................. 3373
Figure 28-58. MCAN_HPMS Register................................................................................................................................... 3374
Figure 28-59. MCAN_NDAT1 Register.................................................................................................................................. 3375
Figure 28-60. MCAN_NDAT2 Register.................................................................................................................................. 3378
Figure 28-61. MCAN_RXF0C Register..................................................................................................................................3381
Figure 28-62. MCAN_RXF0S Register..................................................................................................................................3382
Figure 28-63. MCAN_RXF0A Register..................................................................................................................................3383
Figure 28-64. MCAN_RXBC Register................................................................................................................................... 3384

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Figure 28-65. MCAN_RXF1C Register..................................................................................................................................3385

Figure 28-66. MCAN_RXF1S Register..................................................................................................................................3386
Figure 28-67. MCAN_RXF1A Register..................................................................................................................................3387
Figure 28-68. MCAN_RXESC Register................................................................................................................................. 3388
Figure 28-69. MCAN_TXBC Register....................................................................................................................................3390
Figure 28-70. MCAN_TXFQS Register................................................................................................................................. 3392
Figure 28-71. MCAN_TXESC Register................................................................................................................................. 3393
Figure 28-72. MCAN_TXBRP Register................................................................................................................................. 3394
Figure 28-73. MCAN_TXBAR Register................................................................................................................................. 3397
Figure 28-74. MCAN_TXBCR Register................................................................................................................................. 3399
Figure 28-75. MCAN_TXBTO Register..................................................................................................................................3401
Figure 28-76. MCAN_TXBCF Register..................................................................................................................................3403
Figure 28-77. MCAN_TXBTIE Register.................................................................................................................................3405
Figure 28-78. MCAN_TXBCIE Register................................................................................................................................ 3409
Figure 28-79. MCAN_TXEFC Register..................................................................................................................................3413
Figure 28-80. MCAN_TXEFS Register..................................................................................................................................3414
Figure 28-81. MCAN_TXEFA Register.................................................................................................................................. 3415
Figure 28-82. MCANERR_REV Register.............................................................................................................................. 3418
Figure 28-83. MCANERR_VECTOR Register....................................................................................................................... 3419
Figure 28-84. MCANERR_STAT Register............................................................................................................................. 3420
Figure 28-85. MCANERR_WRAP_REV Register..................................................................................................................3421
Figure 28-86. MCANERR_CTRL Register............................................................................................................................ 3422
Figure 28-87. MCANERR_ERR_CTRL1 Register.................................................................................................................3424
Figure 28-88. MCANERR_ERR_CTRL2 Register.................................................................................................................3425
Figure 28-89. MCANERR_ERR_STAT1 Register..................................................................................................................3426
Figure 28-90. MCANERR_ERR_STAT2 Register..................................................................................................................3428
Figure 28-91. MCANERR_ERR_STAT3 Register..................................................................................................................3429
Figure 28-92. MCANERR_SEC_EOI Register...................................................................................................................... 3430
Figure 28-93. MCANERR_SEC_STATUS Register...............................................................................................................3431
Figure 28-94. MCANERR_SEC_ENABLE_SET Register..................................................................................................... 3432
Figure 28-95. MCANERR_SEC_ENABLE_CLR Register..................................................................................................... 3433
Figure 28-96. MCANERR_DED_EOI Register...................................................................................................................... 3434
Figure 28-97. MCANERR_DED_STATUS Register...............................................................................................................3435
Figure 28-98. MCANERR_DED_ENABLE_SET Register..................................................................................................... 3436
Figure 28-99. MCANERR_DED_ENABLE_CLR Register.....................................................................................................3437
Figure 28-100. MCANERR_AGGR_ENABLE_SET Register................................................................................................ 3438
Figure 28-101. MCANERR_AGGR_ENABLE_CLR Register................................................................................................3439
Figure 28-102. MCANERR_AGGR_STATUS_SET Register.................................................................................................3440
Figure 28-103. MCANERR_AGGR_STATUS_CLR Register................................................................................................ 3441
Figure 29-1. SCI Block Diagram............................................................................................................................................ 3446
Figure 29-2. SCI/LIN Block Diagram..................................................................................................................................... 3447
Figure 29-3. Typical SCI Data Frame Formats...................................................................................................................... 3448
Figure 29-4. Asynchronous Communication Bit Timing.........................................................................................................3449
Figure 29-5. Superfractional Divider Example....................................................................................................................... 3452
Figure 29-6. Idle-Line Multiprocessor Communication Format..............................................................................................3454
Figure 29-7. Address-Bit Multiprocessor Communication Format......................................................................................... 3455
Figure 29-8. Receive Buffers................................................................................................................................................. 3456
Figure 29-9. Transmit Buffers................................................................................................................................................ 3457
Figure 29-10. General Interrupt Scheme............................................................................................................................... 3458
Figure 29-11. Interrupt Generation for Given Flags............................................................................................................... 3459
Figure 29-12. LIN Protocol Message Frame Format: Commander Header and Responder Peripheral Response.............. 3467
Figure 29-13. Header 3 Fields: Synch Break, Synch, and ID................................................................................................ 3467
Figure 29-14. Response Format of LIN Message Frame...................................................................................................... 3468
Figure 29-15. Message Header in Terms of Tbit ................................................................................................................... 3471
Figure 29-16. ID Field............................................................................................................................................................ 3472
Figure 29-17. Measurements for Synchronization.................................................................................................................3474
Figure 29-18. Synchronization Validation Process and Baud Rate Adjustment.................................................................... 3475
Figure 29-19. Optional Embedded Checksum in Response for Extended Frames............................................................... 3476
Figure 29-20. Checksum Compare and Send for Extended Frames.....................................................................................3477
Figure 29-21. TXRX Error Detector....................................................................................................................................... 3479
Figure 29-22. Classic Checksum Generation at Transmitting Node......................................................................................3480

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Figure 29-23. LIN 2.0-Compliant Checksum Generation at Transmitting Node.................................................................... 3480

Figure 29-24. ID Reception, Filtering, and Validation............................................................................................................ 3481
Figure 29-25. LIN Message Frame Showing LIN Interrupt Timing and Sequence................................................................ 3485
Figure 29-26. Wakeup Signal Generation..............................................................................................................................3489
Figure 29-27. SCIGCR0 Register.......................................................................................................................................... 3499
Figure 29-28. SCIGCR1 Register.......................................................................................................................................... 3500
Figure 29-29. SCIGCR2 Register.......................................................................................................................................... 3505
Figure 29-30. SCISETINT Register....................................................................................................................................... 3507
Figure 29-31. SCICLEARINT Register...................................................................................................................................3511
Figure 29-32. SCISETINTLVL Register................................................................................................................................. 3514
Figure 29-33. SCICLEARINTLVL Register............................................................................................................................ 3517
Figure 29-34. SCIFLR Register............................................................................................................................................. 3520
Figure 29-35. SCIINTVECT0 Register...................................................................................................................................3528
Figure 29-36. SCIINTVECT1 Register...................................................................................................................................3529
Figure 29-37. SCIFORMAT Register..................................................................................................................................... 3530
Figure 29-38. BRSR Register................................................................................................................................................ 3531
Figure 29-39. SCIED Register............................................................................................................................................... 3533
Figure 29-40. SCIRD Register...............................................................................................................................................3534
Figure 29-41. SCITD Register............................................................................................................................................... 3535
Figure 29-42. SCIPIO0 Register............................................................................................................................................3536
Figure 29-43. SCIPIO2 Register............................................................................................................................................3537
Figure 29-44. LINCOMP Register..........................................................................................................................................3538
Figure 29-45. LINRD0 Register............................................................................................................................................. 3539
Figure 29-46. LINRD1 Register............................................................................................................................................. 3540
Figure 29-47. LINMASK Register.......................................................................................................................................... 3541
Figure 29-48. LINID Register.................................................................................................................................................3542
Figure 29-49. LINTD0 Register..............................................................................................................................................3543
Figure 29-50. LINTD1 Register..............................................................................................................................................3544
Figure 29-51. MBRSR Register............................................................................................................................................. 3545
Figure 29-52. IODFTCTRL Register......................................................................................................................................3546
Figure 29-53. LIN_GLB_INT_EN Register............................................................................................................................ 3549
Figure 29-54. LIN_GLB_INT_FLG Register.......................................................................................................................... 3550
Figure 29-55. LIN_GLB_INT_CLR Register.......................................................................................................................... 3551
Figure 30-1. Block Diagram of the CLB Subsystem in the Device........................................................................................ 3554
Figure 30-2. Block Diagram of a CLB Tile and CPU Interface...............................................................................................3554
Figure 30-3. CLB Clocking.....................................................................................................................................................3555
Figure 30-4. CLB Clock Prescalar......................................................................................................................................... 3556
Figure 30-5. GPIO to CLB Tile Connections..........................................................................................................................3557
Figure 30-6. CLB Input Mux and Filter...................................................................................................................................3558
Figure 30-7. CLB Input Synchronization Example.................................................................................................................3558
Figure 30-8. CLB Input Pipelining Example...........................................................................................................................3559
Figure 30-9. CLB Outputs......................................................................................................................................................3566
Figure 30-10. CLB Output Signal Multiplexer........................................................................................................................ 3567
Figure 30-11. CLB Tile Submodules...................................................................................................................................... 3570
Figure 30-12. Counter Block..................................................................................................................................................3573
Figure 30-13. LFSR Modes................................................................................................................................................... 3576
Figure 30-14. FSM Block....................................................................................................................................................... 3577
Figure 30-15. FSM LUT Block............................................................................................................................................... 3578
Figure 30-16. LUT4 Block......................................................................................................................................................3579
Figure 30-17. Output LUT Block............................................................................................................................................ 3579
Figure 30-18. AOC Block.......................................................................................................................................................3581
Figure 30-19. AOC Block and The CLB TILE........................................................................................................................ 3582
Figure 30-20. High Level Controller Block............................................................................................................................. 3583
Figure 30-21. CLB Control of SPI RX Buffer..........................................................................................................................3590
Figure 30-22. CLB_COUNT_RESET Register...................................................................................................................... 3603
Figure 30-23. CLB_COUNT_MODE_1 Register................................................................................................................... 3604
Figure 30-24. CLB_COUNT_MODE_0 Register................................................................................................................... 3605
Figure 30-25. CLB_COUNT_EVENT Register...................................................................................................................... 3606
Figure 30-26. CLB_FSM_EXTRA_IN0 Register....................................................................................................................3607
Figure 30-27. CLB_FSM_EXTERNAL_IN0 Register.............................................................................................................3608
Figure 30-28. CLB_FSM_EXTERNAL_IN1 Register.............................................................................................................3609

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Figure 30-29. CLB_FSM_EXTRA_IN1 Register....................................................................................................................3610

Figure 30-30. CLB_LUT4_IN0 Register................................................................................................................................. 3611
Figure 30-31. CLB_LUT4_IN1 Register.................................................................................................................................3612
Figure 30-32. CLB_LUT4_IN2 Register.................................................................................................................................3613
Figure 30-33. CLB_LUT4_IN3 Register.................................................................................................................................3614
Figure 30-34. CLB_FSM_LUT_FN1_0 Register....................................................................................................................3615
Figure 30-35. CLB_FSM_LUT_FN2 Register........................................................................................................................3616
Figure 30-36. CLB_LUT4_FN1_0 Register........................................................................................................................... 3617
Figure 30-37. CLB_LUT4_FN2 Register............................................................................................................................... 3618
Figure 30-38. CLB_FSM_NEXT_STATE_0 Register.............................................................................................................3619
Figure 30-39. CLB_FSM_NEXT_STATE_1 Register.............................................................................................................3620
Figure 30-40. CLB_FSM_NEXT_STATE_2 Register.............................................................................................................3621
Figure 30-41. CLB_MISC_CONTROL Register.................................................................................................................... 3622
Figure 30-42. CLB_OUTPUT_LUT_0 Register..................................................................................................................... 3625
Figure 30-43. CLB_OUTPUT_LUT_1 Register..................................................................................................................... 3626
Figure 30-44. CLB_OUTPUT_LUT_2 Register..................................................................................................................... 3627
Figure 30-45. CLB_OUTPUT_LUT_3 Register..................................................................................................................... 3628
Figure 30-46. CLB_OUTPUT_LUT_4 Register..................................................................................................................... 3629
Figure 30-47. CLB_OUTPUT_LUT_5 Register..................................................................................................................... 3630
Figure 30-48. CLB_OUTPUT_LUT_6 Register..................................................................................................................... 3631
Figure 30-49. CLB_OUTPUT_LUT_7 Register..................................................................................................................... 3632
Figure 30-50. CLB_HLC_EVENT_SEL Register................................................................................................................... 3633
Figure 30-51. CLB_COUNT_MATCH_TAP_SEL Register.................................................................................................... 3634
Figure 30-52. CLB_OUTPUT_COND_CTRL_0 Register...................................................................................................... 3635
Figure 30-53. CLB_OUTPUT_COND_CTRL_1 Register...................................................................................................... 3637
Figure 30-54. CLB_OUTPUT_COND_CTRL_2 Register...................................................................................................... 3639
Figure 30-55. CLB_OUTPUT_COND_CTRL_3 Register...................................................................................................... 3641
Figure 30-56. CLB_OUTPUT_COND_CTRL_4 Register...................................................................................................... 3643
Figure 30-57. CLB_OUTPUT_COND_CTRL_5 Register...................................................................................................... 3645
Figure 30-58. CLB_OUTPUT_COND_CTRL_6 Register...................................................................................................... 3647
Figure 30-59. CLB_OUTPUT_COND_CTRL_7 Register...................................................................................................... 3649
Figure 30-60. CLB_MISC_ACCESS_CTRL Register............................................................................................................3651
Figure 30-61. CLB_SPI_DATA_CTRL_HI Register............................................................................................................... 3652
Figure 30-62. CLB_LOAD_EN Register................................................................................................................................ 3655
Figure 30-63. CLB_LOAD_ADDR Register........................................................................................................................... 3656
Figure 30-64. CLB_LOAD_DATA Register............................................................................................................................ 3657
Figure 30-65. CLB_INPUT_FILTER Register........................................................................................................................ 3658
Figure 30-66. CLB_IN_MUX_SEL_0 Register.......................................................................................................................3661
Figure 30-67. CLB_LCL_MUX_SEL_1 Register....................................................................................................................3663
Figure 30-68. CLB_LCL_MUX_SEL_2 Register....................................................................................................................3664
Figure 30-69. CLB_BUF_PTR Register.................................................................................................................................3665
Figure 30-70. CLB_GP_REG Register.................................................................................................................................. 3666
Figure 30-71. CLB_OUT_EN Register.................................................................................................................................. 3668
Figure 30-72. CLB_GLBL_MUX_SEL_1 Register................................................................................................................. 3669
Figure 30-73. CLB_GLBL_MUX_SEL_2 Register................................................................................................................. 3670
Figure 30-74. CLB_PRESCALE_CTRL Register.................................................................................................................. 3671
Figure 30-75. CLB_INTR_TAG_REG Register......................................................................................................................3672
Figure 30-76. CLB_LOCK Register....................................................................................................................................... 3673
Figure 30-77. CLB_HLC_INSTR_READ_PTR Register........................................................................................................3674
Figure 30-78. CLB_HLC_INSTR_VALUE Register................................................................................................................3675
Figure 30-79. CLB_DBG_OUT_2 Register............................................................................................................................3676
Figure 30-80. CLB_DBG_R0 Register...................................................................................................................................3677
Figure 30-81. CLB_DBG_R1 Register...................................................................................................................................3678
Figure 30-82. CLB_DBG_R2 Register...................................................................................................................................3679
Figure 30-83. CLB_DBG_R3 Register...................................................................................................................................3680
Figure 30-84. CLB_DBG_C0 Register...................................................................................................................................3681
Figure 30-85. CLB_DBG_C1 Register...................................................................................................................................3682
Figure 30-86. CLB_DBG_C2 Register...................................................................................................................................3683
Figure 30-87. CLB_DBG_OUT Register................................................................................................................................3684
Figure 30-88. CLB_PUSH Register....................................................................................................................................... 3687
Figure 30-89. CLB_PULL Register........................................................................................................................................ 3688

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 51

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Figure 31-1. AES Block Diagram...........................................................................................................................................3690

Figure 31-2. AES - GCM Operation.......................................................................................................................................3694
Figure 31-3. AES - CCM Operation....................................................................................................................................... 3695
Figure 31-4. AES - XTS Operation........................................................................................................................................ 3696
Figure 31-5. AES - ECB Feedback Mode..............................................................................................................................3697
Figure 31-6. AES - CBC Feedback Mode..............................................................................................................................3698
Figure 31-7. AES Encryption With CTR/ICM Mode............................................................................................................... 3699
Figure 31-8. AES - CFB Feedback Mode.............................................................................................................................. 3700
Figure 31-9. AES - F8 Mode..................................................................................................................................................3701
Figure 31-10. AES - F9 Operation......................................................................................................................................... 3702
Figure 31-11. AES - CBC-MAC Authentication Mode............................................................................................................3703
Figure 31-12. AES Polling Mode........................................................................................................................................... 3707
Figure 31-13. AES Interrupt Service......................................................................................................................................3709
Figure 31-14. AES_KEY2_6 Register....................................................................................................................................3717
Figure 31-15. AES_KEY2_7 Register....................................................................................................................................3718
Figure 31-16. AES_KEY2_4 Register....................................................................................................................................3719
Figure 31-17. AES_KEY2_5 Register....................................................................................................................................3720
Figure 31-18. AES_KEY2_2 Register....................................................................................................................................3721
Figure 31-19. AES_KEY2_3 Register....................................................................................................................................3722
Figure 31-20. AES_KEY2_0 Register....................................................................................................................................3723
Figure 31-21. AES_KEY2_1 Register....................................................................................................................................3724
Figure 31-22. AES_KEY1_6 Register....................................................................................................................................3725
Figure 31-23. AES_KEY1_7 Register....................................................................................................................................3726
Figure 31-24. AES_KEY1_4 Register....................................................................................................................................3727
Figure 31-25. AES_KEY1_5 Register....................................................................................................................................3728
Figure 31-26. AES_KEY1_2 Register....................................................................................................................................3729
Figure 31-27. AES_KEY1_3 Register....................................................................................................................................3730
Figure 31-28. AES_KEY1_0 Register....................................................................................................................................3731
Figure 31-29. AES_KEY1_1 Register....................................................................................................................................3732
Figure 31-30. AES_IV_IN_OUT_0 Register.......................................................................................................................... 3733
Figure 31-31. AES_IV_IN_OUT_1 Register.......................................................................................................................... 3734
Figure 31-32. AES_IV_IN_OUT_2 Register.......................................................................................................................... 3735
Figure 31-33. AES_IV_IN_OUT_3 Register.......................................................................................................................... 3736
Figure 31-34. AES_CTRL Register....................................................................................................................................... 3737
Figure 31-35. AES_C_LENGTH_0 Register..........................................................................................................................3741
Figure 31-36. AES_C_LENGTH_1 Register..........................................................................................................................3742
Figure 31-37. AES_AUTH_LENGTH Register...................................................................................................................... 3743
Figure 31-38. AES_DATA_IN_OUT_0 Register.....................................................................................................................3744
Figure 31-39. AES_DATA_IN_OUT_1 Register.....................................................................................................................3745
Figure 31-40. AES_DATA_IN_OUT_2 Register.....................................................................................................................3746
Figure 31-41. AES_DATA_IN_OUT_3 Register.....................................................................................................................3747
Figure 31-42. AES_TAG_OUT_0 Register............................................................................................................................ 3748
Figure 31-43. AES_TAG_OUT_1 Register............................................................................................................................ 3749
Figure 31-44. AES_TAG_OUT_2 Register............................................................................................................................ 3750
Figure 31-45. AES_TAG_OUT_3 Register............................................................................................................................ 3751
Figure 31-46. AES_REV Register......................................................................................................................................... 3752
Figure 31-47. AES_SYSCONFIG Register............................................................................................................................3753
Figure 31-48. AES_SYSSTATUS Register............................................................................................................................ 3755
Figure 31-49. AES_IRQSTATUS Register.............................................................................................................................3756
Figure 31-50. AES_IRQENABLE Register............................................................................................................................ 3757
Figure 31-51. AES_DIRTY_BITS Register............................................................................................................................ 3758
Figure 31-52. AES_GLB_INT_FLG Register.........................................................................................................................3760
Figure 31-53. AES_GLB_INT_CLR Register.........................................................................................................................3761
Figure 32-1. EPG Overview Block Diagram.......................................................................................................................... 3763
Figure 32-2. EPG Detailed Block Diagram............................................................................................................................ 3764
Figure 32-3. EPG Clock Generator........................................................................................................................................3765
Figure 32-4. EPG Clock Stop................................................................................................................................................ 3766
Figure 32-5. EPG Signal Generator Detailed Overview........................................................................................................ 3768
Figure 32-6. EPG Peripheral Signal Muxing..........................................................................................................................3771
Figure 32-7. EPG Interrupt.................................................................................................................................................... 3776
Figure 32-8. GCTL0 Register................................................................................................................................................ 3782

52 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Figure 32-9. GCTL1 Register................................................................................................................................................ 3784

Figure 32-10. GCTL2 Register.............................................................................................................................................. 3785
Figure 32-11. GCTL3 Register...............................................................................................................................................3787
Figure 32-12. EPGLOCK Register.........................................................................................................................................3791
Figure 32-13. EPGCOMMIT Register....................................................................................................................................3792
Figure 32-14. GINTSTS Register.......................................................................................................................................... 3793
Figure 32-15. GINTEN Register............................................................................................................................................ 3794
Figure 32-16. GINTCLR Register.......................................................................................................................................... 3795
Figure 32-17. GINTFRC Register.......................................................................................................................................... 3796
Figure 32-18. CLKDIV0_CTL0 Register................................................................................................................................ 3797
Figure 32-19. CLKDIV0_CLKOFFSET Register....................................................................................................................3798
Figure 32-20. CLKDIV1_CTL0 Register................................................................................................................................ 3799
Figure 32-21. CLKDIV1_CLKOFFSET Register....................................................................................................................3800
Figure 32-22. SIGGEN0_CTL0 Register............................................................................................................................... 3801
Figure 32-23. SIGGEN0_CTL1 Register............................................................................................................................... 3803
Figure 32-24. SIGGEN0_DATA0 Register............................................................................................................................. 3804
Figure 32-25. SIGGEN0_DATA1 Register............................................................................................................................. 3805
Figure 32-26. SIGGEN0_DATA0_ACTIVE Register.............................................................................................................. 3806
Figure 32-27. SIGGEN0_DATA1_ACTIVE Register.............................................................................................................. 3807
Figure 32-28. REVISION Register.........................................................................................................................................3808
Figure 32-29. EPGMXSEL0 Register.................................................................................................................................... 3810
Figure 32-30. EPGMXSELLOCK Register............................................................................................................................ 3813
Figure 32-31. EPGMXSELCOMMIT Register........................................................................................................................3814

List of Tables
Table 1-1. C2000Ware Root Directories.................................................................................................................................... 92
Table 2-1. TMU Supported Instructions..................................................................................................................................... 96
Table 3-1. Access to EALLOW-Protected Registers................................................................................................................100
Table 3-2. Reset Signals..........................................................................................................................................................100
Table 3-3. PIE Channel Mapping............................................................................................................................................. 108
Table 3-4. CPU Interrupt Vectors..............................................................................................................................................111
Table 3-5. PIE Interrupt Vectors............................................................................................................................................... 112
Table 3-6. ALT Modes.............................................................................................................................................................. 123
Table 3-7. Clock Connections Sorted by Clock Domain.......................................................................................................... 126
Table 3-8. Clock Connections Sorted by Module Name.......................................................................................................... 127
Table 3-9. Clock Source (OSCCLK) Failure Detection............................................................................................................ 131
Table 3-10. Example Watchdog Key Sequences.....................................................................................................................135
Table 3-11. Effect of Clock-Gating Low-Power Modes on the Device......................................................................................137
Table 3-12. Local Shared RAM................................................................................................................................................141
Table 3-13. Global Shared RAM.............................................................................................................................................. 141
Table 3-14. Addressable Memory Range for MCAN Message RAMs..................................................................................... 142
Table 3-15. Error Handling in Different Scenarios....................................................................................................................146
Table 3-16. Mapping of ECC Bits in Read Data from ECC/Parity Address Map..................................................................... 147
Table 3-17. Mapping of Parity Bits in Read Data from ECC/Parity Address Map....................................................................147
Table 3-18. System Control Registers Impacted..................................................................................................................... 153
Table 3-19. SYSCTL Registers to Driverlib Functions............................................................................................................. 154
Table 3-20. CPUTIMER Registers to Driverlib Functions........................................................................................................ 163
Table 3-21. MEMCFG Registers to Driverlib Functions........................................................................................................... 164
Table 3-22. PIE Registers to Driverlib Functions..................................................................................................................... 168
Table 3-23. NMI Registers to Driverlib Functions.................................................................................................................... 169
Table 3-24. XINT Registers to Driverlib Functions...................................................................................................................170
Table 3-25. WWD Registers to Driverlib Functions..................................................................................................................171
Table 3-26. SYSCTRL Base Address Table............................................................................................................................ 178
Table 3-27. CPUTIMER_REGS Registers...............................................................................................................................179
Table 3-28. CPUTIMER_REGS Access Type Codes.............................................................................................................. 179
Table 3-29. TIM Register Field Descriptions............................................................................................................................180
Table 3-30. PRD Register Field Descriptions.......................................................................................................................... 181
Table 3-31. TCR Register Field Descriptions...........................................................................................................................182
Table 3-32. TPR Register Field Descriptions...........................................................................................................................184
Table 3-33. TPRH Register Field Descriptions........................................................................................................................ 185

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 53

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Table 3-34. PIE_CTRL_REGS Registers................................................................................................................................ 186

Table 3-35. PIE_CTRL_REGS Access Type Codes................................................................................................................186
Table 3-36. PIECTRL Register Field Descriptions...................................................................................................................188
Table 3-37. PIEACK Register Field Descriptions.....................................................................................................................189
Table 3-38. PIEIER1 Register Field Descriptions.................................................................................................................... 190
Table 3-39. PIEIFR1 Register Field Descriptions.................................................................................................................... 192
Table 3-40. PIEIER2 Register Field Descriptions.................................................................................................................... 194
Table 3-41. PIEIFR2 Register Field Descriptions.................................................................................................................... 196
Table 3-42. PIEIER3 Register Field Descriptions.................................................................................................................... 198
Table 3-43. PIEIFR3 Register Field Descriptions.................................................................................................................... 200
Table 3-44. PIEIER4 Register Field Descriptions.................................................................................................................... 202
Table 3-45. PIEIFR4 Register Field Descriptions.................................................................................................................... 204
Table 3-46. PIEIER5 Register Field Descriptions.................................................................................................................... 206
Table 3-47. PIEIFR5 Register Field Descriptions.................................................................................................................... 208
Table 3-48. PIEIER6 Register Field Descriptions.................................................................................................................... 210
Table 3-49. PIEIFR6 Register Field Descriptions.................................................................................................................... 212
Table 3-50. PIEIER7 Register Field Descriptions.................................................................................................................... 214
Table 3-51. PIEIFR7 Register Field Descriptions.................................................................................................................... 216
Table 3-52. PIEIER8 Register Field Descriptions.................................................................................................................... 218
Table 3-53. PIEIFR8 Register Field Descriptions.................................................................................................................... 220
Table 3-54. PIEIER9 Register Field Descriptions.................................................................................................................... 222
Table 3-55. PIEIFR9 Register Field Descriptions.................................................................................................................... 224
Table 3-56. PIEIER10 Register Field Descriptions.................................................................................................................. 226
Table 3-57. PIEIFR10 Register Field Descriptions.................................................................................................................. 228
Table 3-58. PIEIER11 Register Field Descriptions...................................................................................................................230
Table 3-59. PIEIFR11 Register Field Descriptions...................................................................................................................232
Table 3-60. PIEIER12 Register Field Descriptions.................................................................................................................. 234
Table 3-61. PIEIFR12 Register Field Descriptions.................................................................................................................. 236
Table 3-62. NMI_INTRUPT_REGS Registers......................................................................................................................... 238
Table 3-63. NMI_INTRUPT_REGS Access Type Codes.........................................................................................................238
Table 3-64. NMICFG Register Field Descriptions....................................................................................................................239
Table 3-65. NMIFLG Register Field Descriptions.................................................................................................................... 240
Table 3-66. NMIFLGCLR Register Field Descriptions............................................................................................................. 242
Table 3-67. NMIFLGFRC Register Field Descriptions............................................................................................................. 244
Table 3-68. NMIWDCNT Register Field Descriptions.............................................................................................................. 245
Table 3-69. NMIWDPRD Register Field Descriptions..............................................................................................................246
Table 3-70. NMISHDFLG Register Field Descriptions.............................................................................................................247
Table 3-71. ERRORSTS Register Field Descriptions.............................................................................................................. 249
Table 3-72. ERRORSTSCLR Register Field Descriptions.......................................................................................................250
Table 3-73. ERRORSTSFRC Register Field Descriptions.......................................................................................................251
Table 3-74. ERRORCTL Register Field Descriptions.............................................................................................................. 252
Table 3-75. ERRORLOCK Register Field Descriptions........................................................................................................... 253
Table 3-76. XINT_REGS Registers......................................................................................................................................... 254
Table 3-77. XINT_REGS Access Type Codes.........................................................................................................................254
Table 3-78. XINT1CR Register Field Descriptions...................................................................................................................255
Table 3-79. XINT2CR Register Field Descriptions...................................................................................................................256
Table 3-80. XINT3CR Register Field Descriptions...................................................................................................................257
Table 3-81. XINT4CR Register Field Descriptions...................................................................................................................258
Table 3-82. XINT5CR Register Field Descriptions...................................................................................................................259
Table 3-83. XINT1CTR Register Field Descriptions................................................................................................................ 260
Table 3-84. XINT2CTR Register Field Descriptions................................................................................................................ 261
Table 3-85. XINT3CTR Register Field Descriptions................................................................................................................ 262
Table 3-86. SYNC_SOC_REGS Registers..............................................................................................................................263
Table 3-87. SYNC_SOC_REGS Access Type Codes............................................................................................................. 263
Table 3-88. SYNCSELECT Register Field Descriptions.......................................................................................................... 264
Table 3-89. ADCSOCOUTSELECT Register Field Descriptions............................................................................................. 266
Table 3-90. SYNCSOCLOCK Register Field Descriptions...................................................................................................... 269
Table 3-91. DMA_CLA_SRC_SEL_REGS Registers.............................................................................................................. 270
Table 3-92. DMA_CLA_SRC_SEL_REGS Access Type Codes..............................................................................................270
Table 3-93. CLA1TASKSRCSELLOCK Register Field Descriptions........................................................................................271
Table 3-94. DMACHSRCSELLOCK Register Field Descriptions.............................................................................................272

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Table 3-95. CLA1TASKSRCSEL1 Register Field Descriptions................................................................................................273

Table 3-96. CLA1TASKSRCSEL2 Register Field Descriptions................................................................................................274
Table 3-97. DMACHSRCSEL1 Register Field Descriptions.................................................................................................... 275
Table 3-98. DMACHSRCSEL2 Register Field Descriptions.................................................................................................... 276
Table 3-99. LFU_REGS Registers...........................................................................................................................................277
Table 3-100. LFU_REGS Access Type Codes........................................................................................................................ 277
Table 3-101. LFUConfig Register Field Descriptions...............................................................................................................278
Table 3-102. LFUStatus Register Field Descriptions............................................................................................................... 279
Table 3-103. LFU_LOCK Register Field Descriptions............................................................................................................. 280
Table 3-104. LFU_COMMIT Register Field Descriptions.........................................................................................................281
Table 3-105. DEV_CFG_REGS Registers...............................................................................................................................283
Table 3-106. DEV_CFG_REGS Access Type Codes.............................................................................................................. 284
Table 3-107. PARTIDL Register Field Descriptions................................................................................................................. 285
Table 3-108. PARTIDH Register Field Descriptions.................................................................................................................287
Table 3-109. REVID Register Field Descriptions..................................................................................................................... 288
Table 3-110. TRIMERRSTS Register Field Descriptions......................................................................................................... 289
Table 3-111. SOFTPRES0 Register Field Descriptions........................................................................................................... 290
Table 3-112. SOFTPRES2 Register Field Descriptions........................................................................................................... 291
Table 3-113. SOFTPRES3 Register Field Descriptions........................................................................................................... 293
Table 3-114. SOFTPRES4 Register Field Descriptions........................................................................................................... 294
Table 3-115. SOFTPRES7 Register Field Descriptions........................................................................................................... 295
Table 3-116. SOFTPRES8 Register Field Descriptions........................................................................................................... 296
Table 3-117. SOFTPRES9 Register Field Descriptions........................................................................................................... 297
Table 3-118. SOFTPRES10 Register Field Descriptions......................................................................................................... 298
Table 3-119. SOFTPRES11 Register Field Descriptions......................................................................................................... 299
Table 3-120. SOFTPRES13 Register Field Descriptions.........................................................................................................300
Table 3-121. SOFTPRES14 Register Field Descriptions.........................................................................................................301
Table 3-122. SOFTPRES15 Register Field Descriptions.........................................................................................................302
Table 3-123. SOFTPRES16 Register Field Descriptions.........................................................................................................303
Table 3-124. SOFTPRES17 Register Field Descriptions.........................................................................................................304
Table 3-125. SOFTPRES18 Register Field Descriptions.........................................................................................................305
Table 3-126. SOFTPRES19 Register Field Descriptions.........................................................................................................306
Table 3-127. SOFTPRES20 Register Field Descriptions.........................................................................................................307
Table 3-128. SOFTPRES21 Register Field Descriptions.........................................................................................................308
Table 3-129. SOFTPRES26 Register Field Descriptions.........................................................................................................309
Table 3-130. SOFTPRES27 Register Field Descriptions.........................................................................................................310
Table 3-131. SOFTPRES28 Register Field Descriptions......................................................................................................... 311
Table 3-132. SOFTPRES30 Register Field Descriptions.........................................................................................................312
Table 3-133. SOFTPRES40 Register Field Descriptions.........................................................................................................313
Table 3-134. TAP_STATUS Register Field Descriptions..........................................................................................................314
Table 3-135. TAP_CONTROL Register Field Descriptions......................................................................................................315
Table 3-136. USBTYPE Register Field Descriptions............................................................................................................... 316
Table 3-137. ECAPTYPE Register Field Descriptions.............................................................................................................317
Table 3-138. MCUCNF3 Register Field Descriptions.............................................................................................................. 318
Table 3-139. MCUCNF8 Register Field Descriptions.............................................................................................................. 320
Table 3-140. MCUCNF11 Register Field Descriptions.............................................................................................................321
Table 3-141. MCUCNF12 Register Field Descriptions............................................................................................................ 322
Table 3-142. MCUCNF14 Register Field Descriptions............................................................................................................ 323
Table 3-143. MCUCNF16 Register Field Descriptions............................................................................................................ 324
Table 3-144. MCUCNF18 Register Field Descriptions............................................................................................................ 325
Table 3-145. MCUCNF20 Register Field Descriptions............................................................................................................ 327
Table 3-146. MCUCNF21 Register Field Descriptions............................................................................................................ 329
Table 3-147. MCUCNF23 Register Field Descriptions............................................................................................................ 330
Table 3-148. MCUCNF31 Register Field Descriptions............................................................................................................ 331
Table 3-149. MCUCNF32 Register Field Descriptions............................................................................................................ 333
Table 3-150. MCUCNF33 Register Field Descriptions............................................................................................................ 335
Table 3-151. MCUCNF34 Register Field Descriptions............................................................................................................ 337
Table 3-152. MCUCNF35 Register Field Descriptions............................................................................................................ 339
Table 3-153. MCUCNFLOCK Register Field Descriptions.......................................................................................................340
Table 3-154. CLK_CFG_REGS Registers............................................................................................................................... 341
Table 3-155. CLK_CFG_REGS Access Type Codes.............................................................................................................. 341

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Table 3-156. CLKCFGLOCK1 Register Field Descriptions......................................................................................................343

Table 3-157. CLKSRCCTL1 Register Field Descriptions.........................................................................................................345
Table 3-158. CLKSRCCTL2 Register Field Descriptions.........................................................................................................347
Table 3-159. CLKSRCCTL3 Register Field Descriptions.........................................................................................................348
Table 3-160. SYSPLLCTL1 Register Field Descriptions..........................................................................................................349
Table 3-161. SYSPLLMULT Register Field Descriptions......................................................................................................... 350
Table 3-162. SYSPLLSTS Register Field Descriptions........................................................................................................... 351
Table 3-163. SYSCLKDIVSEL Register Field Descriptions..................................................................................................... 352
Table 3-164. AUXCLKDIVSEL Register Field Descriptions.....................................................................................................353
Table 3-165. PERCLKDIVSEL Register Field Descriptions.....................................................................................................354
Table 3-166. XCLKOUTDIVSEL Register Field Descriptions.................................................................................................. 355
Table 3-167. CLBCLKCTL Register Field Descriptions........................................................................................................... 356
Table 3-168. LOSPCP Register Field Descriptions................................................................................................................. 357
Table 3-169. MCDCR Register Field Descriptions...................................................................................................................358
Table 3-170. X1CNT Register Field Descriptions.................................................................................................................... 360
Table 3-171. XTALCR Register Field Descriptions.................................................................................................................. 361
Table 3-172. XTALCR2 Register Field Descriptions................................................................................................................ 362
Table 3-173. CLKFAILCFG Register Field Descriptions.......................................................................................................... 363
Table 3-174. CPU_SYS_REGS Registers...............................................................................................................................364
Table 3-175. CPU_SYS_REGS Access Type Codes.............................................................................................................. 365
Table 3-176. CPUSYSLOCK1 Register Field Descriptions..................................................................................................... 366
Table 3-177. CPUSYSLOCK2 Register Field Descriptions..................................................................................................... 369
Table 3-178. PIEVERRADDR Register Field Descriptions...................................................................................................... 371
Table 3-179. PCLKCR0 Register Field Descriptions............................................................................................................... 372
Table 3-180. PCLKCR2 Register Field Descriptions............................................................................................................... 374
Table 3-181. PCLKCR3 Register Field Descriptions............................................................................................................... 376
Table 3-182. PCLKCR4 Register Field Descriptions............................................................................................................... 377
Table 3-183. PCLKCR7 Register Field Descriptions............................................................................................................... 378
Table 3-184. PCLKCR8 Register Field Descriptions............................................................................................................... 379
Table 3-185. PCLKCR9 Register Field Descriptions............................................................................................................... 380
Table 3-186. PCLKCR10 Register Field Descriptions............................................................................................................. 381
Table 3-187. PCLKCR11 Register Field Descriptions..............................................................................................................382
Table 3-188. PCLKCR12 Register Field Descriptions............................................................................................................. 383
Table 3-189. PCLKCR13 Register Field Descriptions............................................................................................................. 384
Table 3-190. PCLKCR14 Register Field Descriptions............................................................................................................. 385
Table 3-191. PCLKCR15 Register Field Descriptions............................................................................................................. 386
Table 3-192. PCLKCR16 Register Field Descriptions............................................................................................................. 387
Table 3-193. PCLKCR17 Register Field Descriptions............................................................................................................. 388
Table 3-194. PCLKCR18 Register Field Descriptions............................................................................................................. 389
Table 3-195. PCLKCR19 Register Field Descriptions............................................................................................................. 390
Table 3-196. PCLKCR20 Register Field Descriptions............................................................................................................. 391
Table 3-197. PCLKCR21 Register Field Descriptions............................................................................................................. 392
Table 3-198. PCLKCR26 Register Field Descriptions............................................................................................................. 393
Table 3-199. PCLKCR27 Register Field Descriptions............................................................................................................. 394
Table 3-200. SIMRESET Register Field Descriptions..............................................................................................................395
Table 3-201. LPMCR Register Field Descriptions................................................................................................................... 396
Table 3-202. GPIOLPMSEL0 Register Field Descriptions.......................................................................................................397
Table 3-203. GPIOLPMSEL1 Register Field Descriptions.......................................................................................................400
Table 3-204. TMR2CLKCTL Register Field Descriptions........................................................................................................ 403
Table 3-205. RESCCLR Register Field Descriptions...............................................................................................................404
Table 3-206. RESC Register Field Descriptions...................................................................................................................... 406
Table 3-207. CMPSSLPMSEL Register Field Descriptions..................................................................................................... 408
Table 3-208. MCANRAMACC Register Field Descriptions......................................................................................................410
Table 3-209. MCANWAKESTATUS Register Field Descriptions..............................................................................................411
Table 3-210. MCANWAKESTATUSCLR Register Field Descriptions...................................................................................... 412
Table 3-211. CLKSTOPREQ Register Field Descriptions........................................................................................................413
Table 3-212. CLKSTOPACK Register Field Descriptions........................................................................................................ 414
Table 3-213. USER_REG1_SYSRSn Register Field Descriptions.......................................................................................... 415
Table 3-214. USER_REG2_SYSRSn Register Field Descriptions.......................................................................................... 416
Table 3-215. USER_REG1_XRSn Register Field Descriptions...............................................................................................417
Table 3-216. USER_REG2_XRSn Register Field Descriptions...............................................................................................418

56 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 3-217. USER_REG1_PORESETn Register Field Descriptions..................................................................................... 419

Table 3-218. USER_REG2_PORESETn Register Field Descriptions..................................................................................... 420
Table 3-219. USER_REG3_PORESETn Register Field Descriptions..................................................................................... 421
Table 3-220. USER_REG4_PORESETn Register Field Descriptions..................................................................................... 422
Table 3-221. JTAG_MMR_REG Register Field Descriptions...................................................................................................423
Table 3-222. SYS_STATUS_REGS Registers.........................................................................................................................424
Table 3-223. SYS_STATUS_REGS Access Type Codes........................................................................................................ 424
Table 3-224. SYS_ERR_INT_FLG Register Field Descriptions.............................................................................................. 425
Table 3-225. SYS_ERR_INT_CLR Register Field Descriptions.............................................................................................. 427
Table 3-226. SYS_ERR_INT_SET Register Field Descriptions.............................................................................................. 429
Table 3-227. SYS_ERR_MASK Register Field Descriptions................................................................................................... 431
Table 3-228. PERIPH_AC_REGS Registers........................................................................................................................... 433
Table 3-229. PERIPH_AC_REGS Access Type Codes...........................................................................................................434
Table 3-230. ADCA_AC Register Field Descriptions............................................................................................................... 435
Table 3-231. ADCB_AC Register Field Descriptions............................................................................................................... 436
Table 3-232. ADCC_AC Register Field Descriptions...............................................................................................................437
Table 3-233. ADCD_AC Register Field Descriptions...............................................................................................................438
Table 3-234. ADCE_AC Register Field Descriptions............................................................................................................... 439
Table 3-235. CMPSS1_AC Register Field Descriptions.......................................................................................................... 440
Table 3-236. CMPSS2_AC Register Field Descriptions.......................................................................................................... 441
Table 3-237. CMPSS3_AC Register Field Descriptions.......................................................................................................... 442
Table 3-238. CMPSS4_AC Register Field Descriptions.......................................................................................................... 443
Table 3-239. DACA_AC Register Field Descriptions............................................................................................................... 444
Table 3-240. PGA1_AC Register Field Descriptions............................................................................................................... 445
Table 3-241. PGA2_AC Register Field Descriptions............................................................................................................... 446
Table 3-242. PGA3_AC Register Field Descriptions............................................................................................................... 447
Table 3-243. EPWM1_AC Register Field Descriptions............................................................................................................448
Table 3-244. EPWM2_AC Register Field Descriptions............................................................................................................449
Table 3-245. EPWM3_AC Register Field Descriptions............................................................................................................450
Table 3-246. EPWM4_AC Register Field Descriptions............................................................................................................451
Table 3-247. EPWM5_AC Register Field Descriptions............................................................................................................452
Table 3-248. EPWM6_AC Register Field Descriptions............................................................................................................453
Table 3-249. EPWM7_AC Register Field Descriptions............................................................................................................454
Table 3-250. EPWM8_AC Register Field Descriptions............................................................................................................455
Table 3-251. EPWM9_AC Register Field Descriptions............................................................................................................456
Table 3-252. EPWM10_AC Register Field Descriptions..........................................................................................................457
Table 3-253. EPWM11_AC Register Field Descriptions.......................................................................................................... 458
Table 3-254. EPWM12_AC Register Field Descriptions..........................................................................................................459
Table 3-255. EQEP1_AC Register Field Descriptions............................................................................................................. 460
Table 3-256. EQEP2_AC Register Field Descriptions............................................................................................................. 461
Table 3-257. EQEP3_AC Register Field Descriptions............................................................................................................. 462
Table 3-258. ECAP1_AC Register Field Descriptions............................................................................................................. 463
Table 3-259. ECAP2_AC Register Field Descriptions............................................................................................................. 464
Table 3-260. CLB1_AC Register Field Descriptions................................................................................................................ 465
Table 3-261. CLB2_AC Register Field Descriptions................................................................................................................ 466
Table 3-262. SCIA_AC Register Field Descriptions.................................................................................................................467
Table 3-263. SCIB_AC Register Field Descriptions.................................................................................................................468
Table 3-264. SCIC_AC Register Field Descriptions................................................................................................................ 469
Table 3-265. SPIA_AC Register Field Descriptions.................................................................................................................470
Table 3-266. SPIB_AC Register Field Descriptions.................................................................................................................471
Table 3-267. I2CA_AC Register Field Descriptions................................................................................................................. 472
Table 3-268. I2CB_AC Register Field Descriptions................................................................................................................. 473
Table 3-269. PMBUS_A_AC Register Field Descriptions........................................................................................................474
Table 3-270. LIN_A_AC Register Field Descriptions............................................................................................................... 475
Table 3-271. MCANA_AC Register Field Descriptions............................................................................................................ 476
Table 3-272. MCANB_AC Register Field Descriptions............................................................................................................ 477
Table 3-273. FSIATX_AC Register Field Descriptions.............................................................................................................478
Table 3-274. FSIARX_AC Register Field Descriptions............................................................................................................ 479
Table 3-275. USBA_AC Register Field Descriptions............................................................................................................... 480
Table 3-276. HRPWM_A_AC Register Field Descriptions.......................................................................................................481
Table 3-277. AESA_AC Register Field Descriptions............................................................................................................... 482

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 57

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Table 3-278. PERIPH_AC_LOCK Register Field Descriptions................................................................................................483

Table 3-279. MEM_CFG_REGS Registers..............................................................................................................................484
Table 3-280. MEM_CFG_REGS Access Type Codes............................................................................................................. 485
Table 3-281. DxLOCK Register Field Descriptions..................................................................................................................486
Table 3-282. DxCOMMIT Register Field Descriptions............................................................................................................. 487
Table 3-283. DxACCPROT0 Register Field Descriptions........................................................................................................ 488
Table 3-284. DxACCPROT1 Register Field Descriptions........................................................................................................ 489
Table 3-285. DxTEST Register Field Descriptions.................................................................................................................. 490
Table 3-286. DxINIT Register Field Descriptions.....................................................................................................................491
Table 3-287. DxINITDONE Register Field Descriptions.......................................................................................................... 492
Table 3-288. DxRAMTEST_LOCK Register Field Descriptions...............................................................................................493
Table 3-289. LSxLOCK Register Field Descriptions................................................................................................................ 494
Table 3-290. LSxCOMMIT Register Field Descriptions........................................................................................................... 496
Table 3-291. LSxMSEL Register Field Descriptions................................................................................................................ 498
Table 3-292. LSxCLAPGM Register Field Descriptions...........................................................................................................500
Table 3-293. LSxACCPROT0 Register Field Descriptions...................................................................................................... 502
Table 3-294. LSxACCPROT1 Register Field Descriptions...................................................................................................... 504
Table 3-295. LSxACCPROT2_y Register Field Descriptions.................................................................................................. 506
Table 3-296. LSxTEST Register Field Descriptions.................................................................................................................507
Table 3-297. LSxINIT Register Field Descriptions................................................................................................................... 510
Table 3-298. LSxINITDONE Register Field Descriptions.........................................................................................................512
Table 3-299. LSxRAMTEST_LOCK Register Field Descriptions.............................................................................................513
Table 3-300. GSxLOCK Register Field Descriptions............................................................................................................... 514
Table 3-301. GSxCOMMIT Register Field Descriptions.......................................................................................................... 516
Table 3-302. GSxACCPROT0 Register Field Descriptions..................................................................................................... 518
Table 3-303. GSxTEST Register Field Descriptions................................................................................................................520
Table 3-304. GSxINIT Register Field Descriptions.................................................................................................................. 522
Table 3-305. GSxINITDONE Register Field Descriptions........................................................................................................524
Table 3-306. GSxRAMTEST_LOCK Register Field Descriptions............................................................................................ 526
Table 3-307. MSGxLOCK Register Field Descriptions............................................................................................................ 527
Table 3-308. MSGxCOMMIT Register Field Descriptions....................................................................................................... 529
Table 3-309. MSGxTEST Register Field Descriptions.............................................................................................................531
Table 3-310. MSGxINIT Register Field Descriptions............................................................................................................... 533
Table 3-311. MSGxINITDONE Register Field Descriptions..................................................................................................... 534
Table 3-312. MSGxRAMTEST_LOCK Register Field Descriptions......................................................................................... 535
Table 3-313. ROM_LOCK Register Field Descriptions............................................................................................................536
Table 3-314. ROM_TEST Register Field Descriptions............................................................................................................ 537
Table 3-315. ROM_FORCE_ERROR Register Field Descriptions.......................................................................................... 538
Table 3-316. ACCESS_PROTECTION_REGS Registers....................................................................................................... 539
Table 3-317. ACCESS_PROTECTION_REGS Access Type Codes.......................................................................................539
Table 3-318. NMAVFLG Register Field Descriptions............................................................................................................... 541
Table 3-319. NMAVSET Register Field Descriptions............................................................................................................... 543
Table 3-320. NMAVCLR Register Field Descriptions...............................................................................................................545
Table 3-321. NMAVINTEN Register Field Descriptions........................................................................................................... 547
Table 3-322. NMCPURDAVADDR Register Field Descriptions............................................................................................... 549
Table 3-323. NMCPUWRAVADDR Register Field Descriptions.............................................................................................. 550
Table 3-324. NMCPUFAVADDR Register Field Descriptions.................................................................................................. 551
Table 3-325. NMDMAWRAVADDR Register Field Descriptions.............................................................................................. 552
Table 3-326. NMCLA1RDAVADDR Register Field Descriptions..............................................................................................553
Table 3-327. NMCLA1WRAVADDR Register Field Descriptions............................................................................................. 554
Table 3-328. NMCLA1FAVADDR Register Field Descriptions................................................................................................. 555
Table 3-329. NMDMARDAVADDR Register Field Descriptions...............................................................................................556
Table 3-330. MAVFLG Register Field Descriptions..................................................................................................................557
Table 3-331. MAVSET Register Field Descriptions..................................................................................................................558
Table 3-332. MAVCLR Register Field Descriptions................................................................................................................. 559
Table 3-333. MAVINTEN Register Field Descriptions..............................................................................................................560
Table 3-334. MCPUFAVADDR Register Field Descriptions..................................................................................................... 561
Table 3-335. MCPUWRAVADDR Register Field Descriptions................................................................................................. 562
Table 3-336. MDMAWRAVADDR Register Field Descriptions.................................................................................................563
Table 3-337. NMNPURDAVADDR Register Field Descriptions............................................................................................... 564
Table 3-338. NMNPUWRAVADDR Register Field Descriptions.............................................................................................. 565

58 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 3-339. MEMORY_ERROR_REGS Registers.................................................................................................................566

Table 3-340. MEMORY_ERROR_REGS Access Type Codes................................................................................................ 566
Table 3-341. UCERRFLG Register Field Descriptions............................................................................................................ 568
Table 3-342. UCERRSET Register Field Descriptions............................................................................................................ 569
Table 3-343. UCERRCLR Register Field Descriptions............................................................................................................ 570
Table 3-344. UCCPUREADDR Register Field Descriptions.................................................................................................... 571
Table 3-345. UCDMAREADDR Register Field Descriptions....................................................................................................572
Table 3-346. UCCLA1READDR Register Field Descriptions...................................................................................................573
Table 3-347. UCNPUREADDR Register Field Descriptions.................................................................................................... 574
Table 3-348. FLUCERRSTATUS Register Field Descriptions................................................................................................. 575
Table 3-349. FLCERRSTATUS Register Field Descriptions.................................................................................................... 576
Table 3-350. CERRFLG Register Field Descriptions...............................................................................................................578
Table 3-351. CERRSET Register Field Descriptions...............................................................................................................579
Table 3-352. CERRCLR Register Field Descriptions...............................................................................................................580
Table 3-353. CCPUREADDR Register Field Descriptions.......................................................................................................581
Table 3-354. CDMAREADDR Register Field Descriptions...................................................................................................... 582
Table 3-355. CCLA1READDR Register Field Descriptions..................................................................................................... 583
Table 3-356. CERRCNT Register Field Descriptions.............................................................................................................. 584
Table 3-357. CERRTHRES Register Field Descriptions..........................................................................................................585
Table 3-358. CEINTFLG Register Field Descriptions.............................................................................................................. 586
Table 3-359. CEINTCLR Register Field Descriptions.............................................................................................................. 587
Table 3-360. CEINTSET Register Field Descriptions.............................................................................................................. 588
Table 3-361. CEINTEN Register Field Descriptions................................................................................................................ 589
Table 3-362. TEST_ERROR_REGS Registers....................................................................................................................... 590
Table 3-363. TEST_ERROR_REGS Access Type Codes.......................................................................................................590
Table 3-364. CPU_RAM_TEST_ERROR_STS Register Field Descriptions........................................................................... 591
Table 3-365. CPU_RAM_TEST_ERROR_STS_CLR Register Field Descriptions.................................................................. 592
Table 3-366. CPU_RAM_TEST_ERROR_ADDR Register Field Descriptions........................................................................ 593
Table 3-367. UID_REGS Registers......................................................................................................................................... 594
Table 3-368. UID_REGS Access Type Codes.........................................................................................................................594
Table 3-369. UID_PSRAND0 Register Field Descriptions.......................................................................................................595
Table 3-370. UID_PSRAND1 Register Field Descriptions.......................................................................................................596
Table 3-371. UID_PSRAND2 Register Field Descriptions.......................................................................................................597
Table 3-372. UID_PSRAND3 Register Field Descriptions.......................................................................................................598
Table 3-373. UID_PSRAND4 Register Field Descriptions.......................................................................................................599
Table 3-374. UID_UNIQUE0 Register Field Descriptions........................................................................................................600
Table 3-375. UID_UNIQUE1 Register Field Descriptions........................................................................................................601
Table 3-376. UID_CHECKSUM Register Field Descriptions................................................................................................... 602
Table 4-1. Boot System Overview............................................................................................................................................604
Table 4-2. ROM Memory..........................................................................................................................................................604
Table 4-3. Device Boot ROM Sequence.................................................................................................................................. 605
Table 4-4. Device Default Boot Modes.................................................................................................................................... 605
Table 4-5. Custom Boot Modes............................................................................................................................................... 606
Table 4-6. BOOTPIN-CONFIG Bit Fields.................................................................................................................................607
Table 4-7. Standalone Boot Mode Select Pin Decoding.......................................................................................................... 608
Table 4-8. BOOTDEF Bit Fields...............................................................................................................................................609
Table 4-9. Zero Boot Pin Boot Table Result.............................................................................................................................610
Table 4-10. One Boot Pin Boot Table Result........................................................................................................................... 610
Table 4-11. Three Boot Pins Boot Table Result........................................................................................................................611
Table 4-12. Boot ROM Reset Causes and Actions..................................................................................................................615
Table 4-13. Boot ROM Exceptions and Actions.......................................................................................................................616
Table 4-14. Boot ROM Registers............................................................................................................................................. 617
Table 4-15. DCSM Z1 GPREG2 Bit Fields.............................................................................................................................. 618
Table 4-16. DCSM Z1/Z2 DIAG Bit Fields............................................................................................................................... 619
Table 4-17. Flash Entry Point Addresses.................................................................................................................................619
Table 4-18. RAM Entry Point Address..................................................................................................................................... 619
Table 4-19. Wait Boot Options................................................................................................................................................. 620
Table 4-20. Wait Point Addresses............................................................................................................................................620
Table 4-21. Secure Flash Tag and Key Details........................................................................................................................621
Table 4-22. Secure Flash Entry Point Addresses.................................................................................................................... 622
Table 4-23. Secure Flash Authentication Failure Actions........................................................................................................ 622

SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024 TMS320F28P55x Real-Time Microcontrollers 59

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Table 4-24. Secure Flash on all CPUs Recommended Flow...................................................................................................622

Table 4-25. FWU Application Image Format............................................................................................................................623
Table 4-26. FWU Entry Point Addresses................................................................................................................................. 623
Table 4-27. Boot ROM Memory Map....................................................................................................................................... 624
Table 4-28. Secure ROM Memory Map................................................................................................................................... 624
Table 4-29. CLA Data ROM Memory Map............................................................................................................................... 624
Table 4-30. Reserved RAM Memory Map................................................................................................................................625
Table 4-31. ROM Symbol Tables............................................................................................................................................. 625
Table 4-32. Boot Mode Availability...........................................................................................................................................625
Table 4-33. Wait Boot Options................................................................................................................................................. 625
Table 4-34. SPI 8-Bit Data Stream...........................................................................................................................................628
Table 4-35. I2C 8-Bit Data Stream...........................................................................................................................................633
Table 4-36. Parallel GPIO Boot 8-Bit Data Stream.................................................................................................................. 634
Table 4-37. Bit-Rate Value for Internal Oscillators................................................................................................................... 638
Table 4-38. CAN 8-Bit Data Stream.........................................................................................................................................639
Table 4-39. CAN-FD 8-Bit Data Stream...................................................................................................................................640
Table 4-40. USB 8-Bit Data Stream......................................................................................................................................... 642
Table 4-41. SCI Boot Options.................................................................................................................................................. 643
Table 4-42. CAN Boot Options.................................................................................................................................................643
Table 4-43. CAN-FD Boot Options...........................................................................................................................................643
Table 4-44. I2C Boot Options...................................................................................................................................................643
Table 4-45. SPI Boot Options.................................................................................................................................................. 644
Table 4-46. Parallel Boot Options............................................................................................................................................ 644
Table 4-47. USB Boot Options.................................................................................................................................................644
Table 4-48. Secure Copy Code Function.................................................................................................................................645
Table 4-49. Secure CRC Calculation Function........................................................................................................................ 645
Table 4-50. Secure CRC Calculation Function........................................................................................................................ 646
Table 4-51. CPU Boot Clock Sources......................................................................................................................................646
Table 4-52. CPU Clock State After Boot.................................................................................................................................. 646
Table 4-53. Boot Status Address............................................................................................................................................. 647
Table 4-54. Boot Status Bit Fields............................................................................................................................................647
Table 4-55. Boot Mode and MPOST Status Addresses...........................................................................................................648
Table 4-56. Boot ROM Version Information............................................................................................................................. 648
Table 4-57. LSB/MSB Loading Sequence in 8-Bit Data Stream.............................................................................................. 649
Table 4-58. Boot Loader Options............................................................................................................................................. 651
Table 5-1. RAM/Flash Status................................................................................................................................................... 654
Table 5-2. Security Levels........................................................................................................................................................654
Table 5-3. Default Value of ZxOTP (Programmed by TI)......................................................................................................... 655
Table 5-4. DCSM Registers to Driverlib Functions.................................................................................................................. 667
Table 5-5. DCSM Base Address Table.................................................................................................................................... 672
Table 5-6. DCSM_Z1_REGS Registers...................................................................................................................................673
Table 5-7. DCSM_Z1_REGS Access Type Codes.................................................................................................................. 673
Table 5-8. Z1_LINKPOINTER Register Field Descriptions......................................................................................................675
Table 5-9. Z1_OTPSECLOCK Register Field Descriptions..................................................................................................... 676
Table 5-10. Z1_JLM_ENABLE Register Field Descriptions.....................................................................................................677
Table 5-11. Z1_LINKPOINTERERR Register Field Descriptions.............................................................................................678
Table 5-12. Z1_GPREG1 Register Field Descriptions.............................................................................................................679
Table 5-13. Z1_GPREG2 Register Field Descriptions.............................................................................................................680
Table 5-14. Z1_GPREG3 Register Field Descriptions.............................................................................................................681
Table 5-15. Z1_GPREG4 Register Field Descriptions.............................................................................................................682
Table 5-16. Z1_CSMKEY0 Register Field Descriptions...........................................................................................................683
Table 5-17. Z1_CSMKEY1 Register Field Descriptions...........................................................................................................684
Table 5-18. Z1_CSMKEY2 Register Field Descriptions...........................................................................................................685
Table 5-19. Z1_CSMKEY3 Register Field Descriptions...........................................................................................................686
Table 5-20. Z1_CR Register Field Descriptions.......................................................................................................................687
Table 5-21. Z1_GRABSECT1R Register Field Descriptions................................................................................................... 689
Table 5-22. Z1_GRABSECT2R Register Field Descriptions................................................................................................... 693
Table 5-23. Z1_GRABSECT3R Register Field Descriptions................................................................................................... 697
Table 5-24. Z1_GRABRAM1R Register Field Descriptions..................................................................................................... 699
Table 5-25. Z1_EXEONLYSECT1R Register Field Descriptions............................................................................................. 702
Table 5-26. Z1_EXEONLYSECT2R Register Field Descriptions............................................................................................. 708

60 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 5-27. Z1_EXEONLYRAM1R Register Field Descriptions...............................................................................................710

Table 5-28. Z1_JTAGKEY0 Register Field Descriptions..........................................................................................................712
Table 5-29. Z1_JTAGKEY1 Register Field Descriptions..........................................................................................................713
Table 5-30. Z1_JTAGKEY2 Register Field Descriptions..........................................................................................................714
Table 5-31. Z1_JTAGKEY3 Register Field Descriptions..........................................................................................................715
Table 5-32. Z1_CMACKEY0 Register Field Descriptions........................................................................................................ 716
Table 5-33. Z1_CMACKEY1 Register Field Descriptions........................................................................................................ 717
Table 5-34. Z1_CMACKEY2 Register Field Descriptions........................................................................................................ 718
Table 5-35. Z1_CMACKEY3 Register Field Descriptions........................................................................................................ 719
Table 5-36. Z1_DIAG Register Field Descriptions................................................................................................................... 720
Table 5-37. DCSM_Z2_REGS Registers.................................................................................................................................721
Table 5-38. DCSM_Z2_REGS Access Type Codes................................................................................................................ 721
Table 5-39. Z2_LINKPOINTER Register Field Descriptions....................................................................................................722
Table 5-40. Z2_OTPSECLOCK Register Field Descriptions................................................................................................... 723
Table 5-41. Z2_LINKPOINTERERR Register Field Descriptions............................................................................................ 724
Table 5-42. Z2_GPREG1 Register Field Descriptions.............................................................................................................725
Table 5-43. Z2_GPREG2 Register Field Descriptions.............................................................................................................726
Table 5-44. Z2_GPREG3 Register Field Descriptions.............................................................................................................727
Table 5-45. Z2_GPREG4 Register Field Descriptions.............................................................................................................728
Table 5-46. Z2_CSMKEY0 Register Field Descriptions...........................................................................................................729
Table 5-47. Z2_CSMKEY1 Register Field Descriptions...........................................................................................................730
Table 5-48. Z2_CSMKEY2 Register Field Descriptions...........................................................................................................731
Table 5-49. Z2_CSMKEY3 Register Field Descriptions...........................................................................................................732
Table 5-50. Z2_CR Register Field Descriptions.......................................................................................................................733
Table 5-51. Z2_GRABSECT1R Register Field Descriptions................................................................................................... 735
Table 5-52. Z2_GRABSECT2R Register Field Descriptions................................................................................................... 739
Table 5-53. Z2_GRABSECT3R Register Field Descriptions................................................................................................... 743
Table 5-54. Z2_GRABRAM1R Register Field Descriptions..................................................................................................... 745
Table 5-55. Z2_EXEONLYSECT1R Register Field Descriptions............................................................................................. 748
Table 5-56. Z2_EXEONLYSECT2R Register Field Descriptions............................................................................................. 754
Table 5-57. Z2_EXEONLYRAM1R Register Field Descriptions...............................................................................................756
Table 5-58. DCSM_COMMON_REGS Registers.................................................................................................................... 758
Table 5-59. DCSM_COMMON_REGS Access Type Codes....................................................................................................758
Table 5-60. FLSEM Register Field Descriptions...................................................................................................................... 759
Table 5-61. SECTSTAT1 Register Field Descriptions..............................................................................................................760
Table 5-62. SECTSTAT2 Register Field Descriptions..............................................................................................................763
Table 5-63. SECTSTAT3 Register Field Descriptions..............................................................................................................766
Table 5-64. RAMSTAT1 Register Field Descriptions............................................................................................................... 768
Table 5-65. SECERRSTAT Register Field Descriptions.......................................................................................................... 770
Table 5-66. SECERRCLR Register Field Descriptions............................................................................................................771
Table 5-67. SECERRFRC Register Field Descriptions............................................................................................................772
Table 5-68. DENYCODE Register Field Descriptions..............................................................................................................773
Table 5-69. UID_UNIQUE_31_0 Register Field Descriptions..................................................................................................775
Table 5-70. UID_UNIQUE_63_32 Register Field Descriptions................................................................................................776
Table 5-71. PARTIDH Register Field Descriptions...................................................................................................................777
Table 5-72. PERSEM1 Register Field Descriptions.................................................................................................................778
Table 5-73. DCSM_Z1_OTP Registers....................................................................................................................................780
Table 5-74. DCSM_Z1_OTP Access Type Codes................................................................................................................... 780
Table 5-75. Z1OTP_LINKPOINTER1 Register Field Descriptions.......................................................................................... 781
Table 5-76. Z1OTP_LINKPOINTER2 Register Field Descriptions.......................................................................................... 782
Table 5-77. Z1OTP_LINKPOINTER3 Register Field Descriptions.......................................................................................... 783
Table 5-78. Z1OTP_JLM_ENABLE Register Field Descriptions............................................................................................. 784
Table 5-79. Z1OTP_GPREG1 Register Field Descriptions..................................................................................................... 785
Table 5-80. Z1OTP_GPREG2 Register Field Descriptions..................................................................................................... 786
Table 5-81. Z1OTP_GPREG3 Register Field Descriptions..................................................................................................... 787
Table 5-82. Z1OTP_GPREG4 Register Field Descriptions..................................................................................................... 788
Table 5-83. Z1OTP_PSWDLOCK Register Field Descriptions................................................................................................789
Table 5-84. Z1OTP_CRCLOCK Register Field Descriptions...................................................................................................790
Table 5-85. Z1OTP_JTAGPSWDH0 Register Field Descriptions............................................................................................ 791
Table 5-86. Z1OTP_JTAGPSWDH1 Register Field Descriptions............................................................................................ 792
Table 5-87. Z1OTP_CMACKEY0 Register Field Descriptions.................................................................................................793

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Table 5-88. Z1OTP_CMACKEY1 Register Field Descriptions.................................................................................................794

Table 5-89. Z1OTP_CMACKEY2 Register Field Descriptions.................................................................................................795
Table 5-90. Z1OTP_CMACKEY3 Register Field Descriptions.................................................................................................796
Table 5-91. DCSM_Z2_OTP Registers....................................................................................................................................797
Table 5-92. DCSM_Z2_OTP Access Type Codes................................................................................................................... 797
Table 5-93. Z2OTP_LINKPOINTER1 Register Field Descriptions.......................................................................................... 798
Table 5-94. Z2OTP_LINKPOINTER2 Register Field Descriptions.......................................................................................... 799
Table 5-95. Z2OTP_LINKPOINTER3 Register Field Descriptions.......................................................................................... 800
Table 5-96. Z2OTP_GPREG1 Register Field Descriptions..................................................................................................... 801
Table 5-97. Z2OTP_GPREG2 Register Field Descriptions..................................................................................................... 802
Table 5-98. Z2OTP_GPREG3 Register Field Descriptions..................................................................................................... 803
Table 5-99. Z2OTP_GPREG4 Register Field Descriptions..................................................................................................... 804
Table 5-100. Z2OTP_PSWDLOCK Register Field Descriptions..............................................................................................805
Table 5-101. Z2OTP_CRCLOCK Register Field Descriptions.................................................................................................806
Table 6-1. FLASH Registers to Driverlib Functions................................................................................................................. 820
Table 6-2. FLASH Base Address Table................................................................................................................................... 821
Table 6-3. FLASH_CTRL_REGS Registers.............................................................................................................................822
Table 6-4. FLASH_CTRL_REGS Access Type Codes............................................................................................................ 822
Table 6-5. FRDCNTL Register Field Descriptions................................................................................................................... 823
Table 6-6. FLPROT Register Field Descriptions......................................................................................................................824
Table 6-7. FRD_INTF_CTRL Register Field Descriptions....................................................................................................... 825
Table 6-8. FLASH_ECC_REGS Registers.............................................................................................................................. 826
Table 6-9. FLASH_ECC_REGS Access Type Codes..............................................................................................................826
Table 6-10. ECC_ENABLE Register Field Descriptions.......................................................................................................... 827
Table 6-11. FECC_CTRL Register Field Descriptions............................................................................................................. 828
Table 7-1. Configuration Options............................................................................................................................................. 834
Table 7-2. Write Followed by Read - Read Occurs First..........................................................................................................845
Table 7-3. Write Followed by Read - Write Occurs First.......................................................................................................... 845
Table 7-4. ADC to CLA Early Interrupt Response....................................................................................................................848
Table 7-5. CLA Registers to Driverlib Functions...................................................................................................................... 850
Table 7-6. Operand Nomenclature...........................................................................................................................................857
Table 7-7. INSTRUCTION dest, source1, source2 Short Description..................................................................................... 858
Table 7-8. Addressing Modes.................................................................................................................................................. 859
Table 7-9. Shift Field Encoding................................................................................................................................................ 859
Table 7-10. Operand Encoding................................................................................................................................................ 860
Table 7-11. Condition Field Encoding...................................................................................................................................... 860
Table 7-12. Pipeline Activity for MBCNDD, Branch Not Taken................................................................................................ 878
Table 7-13. Pipeline Activity for MBCNDD, Branch Taken.......................................................................................................878
Table 7-14. Pipeline Activity for MCCNDD, Call Not Taken..................................................................................................... 883
Table 7-15. Pipeline Activity for MCCNDD, Call Taken............................................................................................................884
Table 7-16. Pipeline Activity for MMOV16 MARx, MRa , #16I................................................................................................. 924
Table 7-17. Pipeline Activity for MMOV16 MAR0/MAR1, mem16........................................................................................... 927
Table 7-18. Pipeline Activity for MMOVI16 MAR0/MAR1, #16I............................................................................................... 945
Table 7-19. Pipeline Activity for MRCNDD, Return Not Taken.................................................................................................969
Table 7-20. Pipeline Activity for MRCNDD, Return Taken....................................................................................................... 969
Table 7-21. Pipeline Activity for MSTOP.................................................................................................................................. 972
Table 7-22. CLA Base Address Table...................................................................................................................................... 988
Table 7-23. CLA_ONLY_REGS Registers............................................................................................................................... 989
Table 7-24. CLA_ONLY_REGS Access Type Codes...............................................................................................................989
Table 7-25. _MVECTBGRNDACTIVE Register Field Descriptions......................................................................................... 990
Table 7-26. _MPSACTL Register Field Descriptions............................................................................................................... 991
Table 7-27. _MPSA1 Register Field Descriptions....................................................................................................................993
Table 7-28. _MPSA2 Register Field Descriptions....................................................................................................................994
Table 7-29. SOFTINTEN Register Field Descriptions..............................................................................................................995
Table 7-30. SOFTINTFRC Register Field Descriptions........................................................................................................... 997
Table 7-31. CLA_SOFTINT_REGS Registers......................................................................................................................... 998
Table 7-32. CLA_SOFTINT_REGS Access Type Codes.........................................................................................................998
Table 7-33. SOFTINTEN Register Field Descriptions..............................................................................................................999
Table 7-34. SOFTINTFRC Register Field Descriptions......................................................................................................... 1001
Table 7-35. CLA_REGS Registers.........................................................................................................................................1002
Table 7-36. CLA_REGS Access Type Codes........................................................................................................................ 1002

62 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 7-37. MVECT1 Register Field Descriptions................................................................................................................. 1004

Table 7-38. MVECT2 Register Field Descriptions................................................................................................................. 1005
Table 7-39. MVECT3 Register Field Descriptions................................................................................................................. 1006
Table 7-40. MVECT4 Register Field Descriptions................................................................................................................. 1007
Table 7-41. MVECT5 Register Field Descriptions................................................................................................................. 1008
Table 7-42. MVECT6 Register Field Descriptions................................................................................................................. 1009
Table 7-43. MVECT7 Register Field Descriptions................................................................................................................. 1010
Table 7-44. MVECT8 Register Field Descriptions..................................................................................................................1011
Table 7-45. MCTL Register Field Descriptions...................................................................................................................... 1012
Table 7-46. _MVECTBGRNDACTIVE Register Field Descriptions....................................................................................... 1013
Table 7-47. SOFTINTEN Register Field Descriptions............................................................................................................1014
Table 7-48. _MSTSBGRND Register Field Descriptions....................................................................................................... 1016
Table 7-49. _MCTLBGRND Register Field Descriptions....................................................................................................... 1017
Table 7-50. _MVECTBGRND Register Field Descriptions.................................................................................................... 1018
Table 7-51. MIFR Register Field Descriptions....................................................................................................................... 1019
Table 7-52. MIOVF Register Field Descriptions.....................................................................................................................1023
Table 7-53. MIFRC Register Field Descriptions.....................................................................................................................1026
Table 7-54. MICLR Register Field Descriptions.....................................................................................................................1028
Table 7-55. MICLROVF Register Field Descriptions............................................................................................................. 1030
Table 7-56. MIER Register Field Descriptions....................................................................................................................... 1032
Table 7-57. MIRUN Register Field Descriptions.................................................................................................................... 1035
Table 7-58. _MPC Register Field Descriptions...................................................................................................................... 1037
Table 7-59. _MAR0 Register Field Descriptions.................................................................................................................... 1038
Table 7-60. _MAR1 Register Field Descriptions.................................................................................................................... 1039
Table 7-61. _MSTF Register Field Descriptions.................................................................................................................... 1040
Table 7-62. _MR0 Register Field Descriptions...................................................................................................................... 1043
Table 7-63. _MR1 Register Field Descriptions...................................................................................................................... 1044
Table 7-64. _MR2 Register Field Descriptions...................................................................................................................... 1045
Table 7-65. _MR3 Register Field Descriptions...................................................................................................................... 1046
Table 7-66. _MPSACTL Register Field Descriptions............................................................................................................. 1047
Table 7-67. _MPSA1 Register Field Descriptions..................................................................................................................1049
Table 7-68. _MPSA2 Register Field Descriptions..................................................................................................................1050
Table 9-1. DCC Registers to Driverlib Functions................................................................................................................... 1062
Table 9-2. DCC Base Address Table..................................................................................................................................... 1064
Table 9-3. DCC_REGS Registers..........................................................................................................................................1065
Table 9-4. DCC_REGS Access Type Codes......................................................................................................................... 1065
Table 9-5. DCCGCTRL Register Field Descriptions.............................................................................................................. 1066
Table 9-6. DCCCNTSEED0 Register Field Descriptions....................................................................................................... 1067
Table 9-7. DCCVALIDSEED0 Register Field Descriptions.................................................................................................... 1068
Table 9-8. DCCCNTSEED1 Register Field Descriptions....................................................................................................... 1069
Table 9-9. DCCSTATUS Register Field Descriptions.............................................................................................................1070
Table 9-10. DCCCNT0 Register Field Descriptions...............................................................................................................1071
Table 9-11. DCCVALID0 Register Field Descriptions............................................................................................................ 1072
Table 9-12. DCCCNT1 Register Field Descriptions...............................................................................................................1073
Table 9-13. DCCCLKSRC1 Register Field Descriptions........................................................................................................1074
Table 9-14. DCCCLKSRC0 Register Field Descriptions........................................................................................................1075
Table 10-1. GPIO access by different controllers...................................................................................................................1078
Table 10-2. AGPIO Configuration.......................................................................................................................................... 1080
Table 10-3. The Combinations of Use Cases for a Specific Analog Input Pin....................................................................... 1081
Table 10-4. Sampling Period..................................................................................................................................................1084
Table 10-5. Sampling Frequency........................................................................................................................................... 1084
Table 10-6. Case 1: Three-Sample Sampling-Window Width................................................................................................1085
Table 10-7. Case 2: Six-Sample Sampling-Window Width.................................................................................................... 1085
Table 10-8. GPIO Muxed Pins............................................................................................................................................... 1089
Table 10-9. GPIO and Peripheral Muxing.............................................................................................................................. 1094
Table 10-10. Peripheral Muxing (Multiple Pins Assigned)..................................................................................................... 1095
Table 10-11. GPIO Registers to Driverlib Functions.............................................................................................................. 1096
Table 10-12. GPIO Base Address Table................................................................................................................................ 1102
Table 10-13. GPIO_CTRL_REGS Registers..........................................................................................................................1103
Table 10-14. GPIO_CTRL_REGS Access Type Codes......................................................................................................... 1105
Table 10-15. GPACTRL Register Field Descriptions..............................................................................................................1106

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Table 10-16. GPAQSEL1 Register Field Descriptions........................................................................................................... 1107

Table 10-17. GPAQSEL2 Register Field Descriptions............................................................................................................1110
Table 10-18. GPAMUX1 Register Field Descriptions............................................................................................................. 1113
Table 10-19. GPAMUX2 Register Field Descriptions............................................................................................................. 1115
Table 10-20. GPADIR Register Field Descriptions................................................................................................................. 1117
Table 10-21. GPAPUD Register Field Descriptions................................................................................................................1119
Table 10-22. GPAINV Register Field Descriptions................................................................................................................. 1121
Table 10-23. GPAODR Register Field Descriptions............................................................................................................... 1123
Table 10-24. GPAAMSEL Register Field Descriptions...........................................................................................................1125
Table 10-25. GPAGMUX1 Register Field Descriptions.......................................................................................................... 1127
Table 10-26. GPAGMUX2 Register Field Descriptions.......................................................................................................... 1129
Table 10-27. GPACSEL1 Register Field Descriptions............................................................................................................1131
Table 10-28. GPACSEL2 Register Field Descriptions............................................................................................................1132
Table 10-29. GPACSEL3 Register Field Descriptions............................................................................................................1133
Table 10-30. GPACSEL4 Register Field Descriptions............................................................................................................1134
Table 10-31. GPALOCK Register Field Descriptions............................................................................................................. 1135
Table 10-32. GPACR Register Field Descriptions..................................................................................................................1137
Table 10-33. GPBCTRL Register Field Descriptions............................................................................................................. 1139
Table 10-34. GPBQSEL1 Register Field Descriptions........................................................................................................... 1140
Table 10-35. GPBQSEL2 Register Field Descriptions........................................................................................................... 1142
Table 10-36. GPBMUX1 Register Field Descriptions.............................................................................................................1145
Table 10-37. GPBMUX2 Register Field Descriptions.............................................................................................................1146
Table 10-38. GPBDIR Register Field Descriptions.................................................................................................................1148
Table 10-39. GPBPUD Register Field Descriptions............................................................................................................... 1150
Table 10-40. GPBINV Register Field Descriptions.................................................................................................................1152
Table 10-41. GPBODR Register Field Descriptions...............................................................................................................1154
Table 10-42. GPBAMSEL Register Field Descriptions...........................................................................................................1156
Table 10-43. GPBGMUX1 Register Field Descriptions.......................................................................................................... 1158
Table 10-44. GPBGMUX2 Register Field Descriptions.......................................................................................................... 1159
Table 10-45. GPBCSEL1 Register Field Descriptions........................................................................................................... 1161
Table 10-46. GPBCSEL2 Register Field Descriptions........................................................................................................... 1162
Table 10-47. GPBCSEL3 Register Field Descriptions........................................................................................................... 1163
Table 10-48. GPBCSEL4 Register Field Descriptions........................................................................................................... 1164
Table 10-49. GPBLOCK Register Field Descriptions............................................................................................................. 1165
Table 10-50. GPBCR Register Field Descriptions..................................................................................................................1167
Table 10-51. GPCCTRL Register Field Descriptions............................................................................................................. 1169
Table 10-52. GPCQSEL1 Register Field Descriptions........................................................................................................... 1170
Table 10-53. GPCQSEL2 Register Field Descriptions........................................................................................................... 1173
Table 10-54. GPCMUX1 Register Field Descriptions.............................................................................................................1174
Table 10-55. GPCMUX2 Register Field Descriptions.............................................................................................................1176
Table 10-56. GPCDIR Register Field Descriptions................................................................................................................ 1177
Table 10-57. GPCPUD Register Field Descriptions............................................................................................................... 1179
Table 10-58. GPCINV Register Field Descriptions.................................................................................................................1181
Table 10-59. GPCODR Register Field Descriptions...............................................................................................................1183
Table 10-60. GPCAMSEL Register Field Descriptions.......................................................................................................... 1185
Table 10-61. GPCGMUX1 Register Field Descriptions..........................................................................................................1187
Table 10-62. GPCGMUX2 Register Field Descriptions..........................................................................................................1189
Table 10-63. GPCCSEL1 Register Field Descriptions........................................................................................................... 1190
Table 10-64. GPCCSEL2 Register Field Descriptions........................................................................................................... 1191
Table 10-65. GPCCSEL3 Register Field Descriptions........................................................................................................... 1192
Table 10-66. GPCLOCK Register Field Descriptions.............................................................................................................1193
Table 10-67. GPCCR Register Field Descriptions................................................................................................................. 1195
Table 10-68. GPGCTRL Register Field Descriptions............................................................................................................. 1197
Table 10-69. GPGQSEL2 Register Field Descriptions...........................................................................................................1198
Table 10-70. GPGMUX2 Register Field Descriptions............................................................................................................ 1200
Table 10-71. GPGDIR Register Field Descriptions................................................................................................................1202
Table 10-72. GPGPUD Register Field Descriptions.............................................................................................................. 1204
Table 10-73. GPGINV Register Field Descriptions................................................................................................................ 1206
Table 10-74. GPGODR Register Field Descriptions.............................................................................................................. 1208
Table 10-75. GPGAMSEL Register Field Descriptions..........................................................................................................1210
Table 10-76. GPGGMUX2 Register Field Descriptions......................................................................................................... 1213

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Table 10-77. GPGCSEL3 Register Field Descriptions...........................................................................................................1215

Table 10-78. GPGLOCK Register Field Descriptions............................................................................................................ 1216
Table 10-79. GPGCR Register Field Descriptions.................................................................................................................1218
Table 10-80. GPHCTRL Register Field Descriptions.............................................................................................................1220
Table 10-81. GPHQSEL1 Register Field Descriptions...........................................................................................................1221
Table 10-82. GPHQSEL2 Register Field Descriptions...........................................................................................................1223
Table 10-83. GPHMUX1 Register Field Descriptions............................................................................................................ 1225
Table 10-84. GPHMUX2 Register Field Descriptions............................................................................................................ 1227
Table 10-85. GPHDIR Register Field Descriptions................................................................................................................ 1229
Table 10-86. GPHPUD Register Field Descriptions...............................................................................................................1231
Table 10-87. GPHINV Register Field Descriptions................................................................................................................ 1237
Table 10-88. GPHODR Register Field Descriptions.............................................................................................................. 1241
Table 10-89. GPHAMSEL Register Field Descriptions.......................................................................................................... 1243
Table 10-90. GPHGMUX1 Register Field Descriptions......................................................................................................... 1249
Table 10-91. GPHGMUX2 Register Field Descriptions......................................................................................................... 1251
Table 10-92. GPHCSEL1 Register Field Descriptions...........................................................................................................1253
Table 10-93. GPHCSEL2 Register Field Descriptions...........................................................................................................1254
Table 10-94. GPHCSEL3 Register Field Descriptions...........................................................................................................1255
Table 10-95. GPHCSEL4 Register Field Descriptions...........................................................................................................1256
Table 10-96. GPHLOCK Register Field Descriptions............................................................................................................ 1257
Table 10-97. GPHCR Register Field Descriptions................................................................................................................. 1261
Table 10-98. GPIO_DATA_REGS Registers..........................................................................................................................1264
Table 10-99. GPIO_DATA_REGS Access Type Codes......................................................................................................... 1264
Table 10-100. GPADAT Register Field Descriptions..............................................................................................................1266
Table 10-101. GPASET Register Field Descriptions..............................................................................................................1268
Table 10-102. GPACLEAR Register Field Descriptions.........................................................................................................1270
Table 10-103. GPATOGGLE Register Field Descriptions...................................................................................................... 1272
Table 10-104. GPBDAT Register Field Descriptions..............................................................................................................1274
Table 10-105. GPBSET Register Field Descriptions............................................................................................................. 1276
Table 10-106. GPBCLEAR Register Field Descriptions........................................................................................................ 1278
Table 10-107. GPBTOGGLE Register Field Descriptions......................................................................................................1280
Table 10-108. GPCDAT Register Field Descriptions............................................................................................................. 1282
Table 10-109. GPCSET Register Field Descriptions............................................................................................................. 1284
Table 10-110. GPCCLEAR Register Field Descriptions.........................................................................................................1286
Table 10-111. GPCTOGGLE Register Field Descriptions......................................................................................................1288
Table 10-112. GPGDAT Register Field Descriptions............................................................................................................. 1290
Table 10-113. GPGSET Register Field Descriptions............................................................................................................. 1292
Table 10-114. GPGCLEAR Register Field Descriptions........................................................................................................ 1294
Table 10-115. GPGTOGGLE Register Field Descriptions..................................................................................................... 1296
Table 10-116. GPHDAT Register Field Descriptions..............................................................................................................1298
Table 10-117. GPHSET Register Field Descriptions..............................................................................................................1305
Table 10-118. GPHCLEAR Register Field Descriptions.........................................................................................................1307
Table 10-119. GPHTOGGLE Register Field Descriptions......................................................................................................1309
Table 10-120. GPIO_DATA_READ_REGS Registers............................................................................................................1311
Table 10-121. GPIO_DATA_READ_REGS Access Type Codes........................................................................................... 1311
Table 10-122. GPADAT_R Register Field Descriptions......................................................................................................... 1312
Table 10-123. GPBDAT_R Register Field Descriptions......................................................................................................... 1313
Table 10-124. GPCDAT_R Register Field Descriptions.........................................................................................................1314
Table 10-125. GPGDAT_R Register Field Descriptions.........................................................................................................1315
Table 10-126. GPHDAT_R Register Field Descriptions.........................................................................................................1316
Table 11-1. Input X-BAR Destinations....................................................................................................................................1320
Table 11-2. CLB Input X-BAR Destinations............................................................................................................................1321
Table 11-3. EPWM X-BAR Mux Configuration Table............................................................................................................. 1323
Table 11-4. CLB X-BAR Mux Configuration Table..................................................................................................................1326
Table 11-5. Output X-BAR Mux Configuration Table..............................................................................................................1328
Table 11-6. INPUTXBAR Registers to Driverlib Functions.....................................................................................................1331
Table 11-7. EPWMXBAR Registers to Driverlib Functions.................................................................................................... 1331
Table 11-8. CLBXBAR Registers to Driverlib Functions.........................................................................................................1333
Table 11-9. OUTPUTXBAR Registers to Driverlib Functions.................................................................................................1334
Table 11-10. XBAR Registers to Driverlib Functions..............................................................................................................1335
Table 11-11. XBAR Base Address Table................................................................................................................................1336

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Table 11-12. INPUT_XBAR_REGS Registers....................................................................................................................... 1337

Table 11-13. INPUT_XBAR_REGS Access Type Codes.......................................................................................................1337
Table 11-14. INPUT1SELECT Register Field Descriptions....................................................................................................1338
Table 11-15. INPUT2SELECT Register Field Descriptions....................................................................................................1339
Table 11-16. INPUT3SELECT Register Field Descriptions....................................................................................................1340
Table 11-17. INPUT4SELECT Register Field Descriptions....................................................................................................1341
Table 11-18. INPUT5SELECT Register Field Descriptions....................................................................................................1342
Table 11-19. INPUT6SELECT Register Field Descriptions....................................................................................................1343
Table 11-20. INPUT7SELECT Register Field Descriptions....................................................................................................1344
Table 11-21. INPUT8SELECT Register Field Descriptions....................................................................................................1345
Table 11-22. INPUT9SELECT Register Field Descriptions....................................................................................................1346
Table 11-23. INPUT10SELECT Register Field Descriptions..................................................................................................1347
Table 11-24. INPUT11SELECT Register Field Descriptions..................................................................................................1348
Table 11-25. INPUT12SELECT Register Field Descriptions..................................................................................................1349
Table 11-26. INPUT13SELECT Register Field Descriptions..................................................................................................1350
Table 11-27. INPUT14SELECT Register Field Descriptions..................................................................................................1351
Table 11-28. INPUT15SELECT Register Field Descriptions..................................................................................................1352
Table 11-29. INPUT16SELECT Register Field Descriptions..................................................................................................1353
Table 11-30. INPUTSELECTLOCK Register Field Descriptions............................................................................................1354
Table 11-31. XBAR_REGS Registers.................................................................................................................................... 1356
Table 11-32. XBAR_REGS Access Type Codes....................................................................................................................1356
Table 11-33. XBARFLG1 Register Field Descriptions............................................................................................................1357
Table 11-34. XBARFLG2 Register Field Descriptions............................................................................................................1360
Table 11-35. XBARFLG3 Register Field Descriptions............................................................................................................1365
Table 11-36. XBARFLG4 Register Field Descriptions............................................................................................................1368
Table 11-37. XBARCLR1 Register Field Descriptions........................................................................................................... 1371
Table 11-38. XBARCLR2 Register Field Descriptions........................................................................................................... 1373
Table 11-39. XBARCLR3 Register Field Descriptions........................................................................................................... 1376
Table 11-40. XBARCLR4 Register Field Descriptions........................................................................................................... 1378
Table 11-41. EPWM_XBAR_REGS Registers....................................................................................................................... 1380
Table 11-42. EPWM_XBAR_REGS Access Type Codes...................................................................................................... 1380
Table 11-43. TRIP4MUX0TO15CFG Register Field Descriptions..........................................................................................1382
Table 11-44. TRIP4MUX16TO31CFG Register Field Descriptions........................................................................................1385
Table 11-45. TRIP5MUX0TO15CFG Register Field Descriptions..........................................................................................1388
Table 11-46. TRIP5MUX16TO31CFG Register Field Descriptions........................................................................................1391
Table 11-47. TRIP7MUX0TO15CFG Register Field Descriptions..........................................................................................1394
Table 11-48. TRIP7MUX16TO31CFG Register Field Descriptions........................................................................................1397
Table 11-49. TRIP8MUX0TO15CFG Register Field Descriptions..........................................................................................1400
Table 11-50. TRIP8MUX16TO31CFG Register Field Descriptions........................................................................................1403
Table 11-51. TRIP9MUX0TO15CFG Register Field Descriptions..........................................................................................1406
Table 11-52. TRIP9MUX16TO31CFG Register Field Descriptions........................................................................................1409
Table 11-53. TRIP10MUX0TO15CFG Register Field Descriptions........................................................................................1412
Table 11-54. TRIP10MUX16TO31CFG Register Field Descriptions......................................................................................1415
Table 11-55. TRIP11MUX0TO15CFG Register Field Descriptions........................................................................................1418
Table 11-56. TRIP11MUX16TO31CFG Register Field Descriptions......................................................................................1421
Table 11-57. TRIP12MUX0TO15CFG Register Field Descriptions........................................................................................1424
Table 11-58. TRIP12MUX16TO31CFG Register Field Descriptions......................................................................................1427
Table 11-59. TRIP4MUXENABLE Register Field Descriptions.............................................................................................. 1430
Table 11-60. TRIP5MUXENABLE Register Field Descriptions.............................................................................................. 1435
Table 11-61. TRIP7MUXENABLE Register Field Descriptions.............................................................................................. 1440
Table 11-62. TRIP8MUXENABLE Register Field Descriptions.............................................................................................. 1445
Table 11-63. TRIP9MUXENABLE Register Field Descriptions.............................................................................................. 1450
Table 11-64. TRIP10MUXENABLE Register Field Descriptions............................................................................................ 1455
Table 11-65. TRIP11MUXENABLE Register Field Descriptions............................................................................................ 1460
Table 11-66. TRIP12MUXENABLE Register Field Descriptions............................................................................................ 1465
Table 11-67. TRIPOUTINV Register Field Descriptions.........................................................................................................1470
Table 11-68. TRIPLOCK Register Field Descriptions............................................................................................................ 1472
Table 11-69. CLB_XBAR_REGS Registers........................................................................................................................... 1473
Table 11-70. CLB_XBAR_REGS Access Type Codes...........................................................................................................1473
Table 11-71. AUXSIG0MUX0TO15CFG Register Field Descriptions.................................................................................... 1475
Table 11-72. AUXSIG0MUX16TO31CFG Register Field Descriptions.................................................................................. 1478

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Table 11-73. AUXSIG1MUX0TO15CFG Register Field Descriptions.................................................................................... 1481

Table 11-74. AUXSIG1MUX16TO31CFG Register Field Descriptions.................................................................................. 1484
Table 11-75. AUXSIG2MUX0TO15CFG Register Field Descriptions.................................................................................... 1487
Table 11-76. AUXSIG2MUX16TO31CFG Register Field Descriptions.................................................................................. 1490
Table 11-77. AUXSIG3MUX0TO15CFG Register Field Descriptions.................................................................................... 1493
Table 11-78. AUXSIG3MUX16TO31CFG Register Field Descriptions.................................................................................. 1496
Table 11-79. AUXSIG4MUX0TO15CFG Register Field Descriptions.................................................................................... 1499
Table 11-80. AUXSIG4MUX16TO31CFG Register Field Descriptions.................................................................................. 1502
Table 11-81. AUXSIG5MUX0TO15CFG Register Field Descriptions.................................................................................... 1505
Table 11-82. AUXSIG5MUX16TO31CFG Register Field Descriptions.................................................................................. 1508
Table 11-83. AUXSIG6MUX0TO15CFG Register Field Descriptions.................................................................................... 1511
Table 11-84. AUXSIG6MUX16TO31CFG Register Field Descriptions.................................................................................. 1514
Table 11-85. AUXSIG7MUX0TO15CFG Register Field Descriptions.................................................................................... 1517
Table 11-86. AUXSIG7MUX16TO31CFG Register Field Descriptions.................................................................................. 1520
Table 11-87. AUXSIG0MUXENABLE Register Field Descriptions.........................................................................................1523
Table 11-88. AUXSIG1MUXENABLE Register Field Descriptions.........................................................................................1528
Table 11-89. AUXSIG2MUXENABLE Register Field Descriptions.........................................................................................1533
Table 11-90. AUXSIG3MUXENABLE Register Field Descriptions.........................................................................................1538
Table 11-91. AUXSIG4MUXENABLE Register Field Descriptions.........................................................................................1543
Table 11-92. AUXSIG5MUXENABLE Register Field Descriptions.........................................................................................1548
Table 11-93. AUXSIG6MUXENABLE Register Field Descriptions.........................................................................................1553
Table 11-94. AUXSIG7MUXENABLE Register Field Descriptions.........................................................................................1558
Table 11-95. AUXSIGOUTINV Register Field Descriptions................................................................................................... 1563
Table 11-96. AUXSIGLOCK Register Field Descriptions....................................................................................................... 1565
Table 11-97. OUTPUT_XBAR_REGS Registers................................................................................................................... 1566
Table 11-98. OUTPUT_XBAR_REGS Access Type Codes...................................................................................................1566
Table 11-99. OUTPUT1MUX0TO15CFG Register Field Descriptions................................................................................... 1568
Table 11-100. OUTPUT1MUX16TO31CFG Register Field Descriptions............................................................................... 1571
Table 11-101. OUTPUT2MUX0TO15CFG Register Field Descriptions................................................................................. 1574
Table 11-102. OUTPUT2MUX16TO31CFG Register Field Descriptions............................................................................... 1577
Table 11-103. OUTPUT3MUX0TO15CFG Register Field Descriptions................................................................................. 1580
Table 11-104. OUTPUT3MUX16TO31CFG Register Field Descriptions............................................................................... 1583
Table 11-105. OUTPUT4MUX0TO15CFG Register Field Descriptions................................................................................. 1586
Table 11-106. OUTPUT4MUX16TO31CFG Register Field Descriptions............................................................................... 1589
Table 11-107. OUTPUT5MUX0TO15CFG Register Field Descriptions................................................................................. 1592
Table 11-108. OUTPUT5MUX16TO31CFG Register Field Descriptions............................................................................... 1595
Table 11-109. OUTPUT6MUX0TO15CFG Register Field Descriptions................................................................................. 1598
Table 11-110. OUTPUT6MUX16TO31CFG Register Field Descriptions............................................................................... 1601
Table 11-111. OUTPUT7MUX0TO15CFG Register Field Descriptions..................................................................................1604
Table 11-112. OUTPUT7MUX16TO31CFG Register Field Descriptions............................................................................... 1607
Table 11-113. OUTPUT8MUX0TO15CFG Register Field Descriptions................................................................................. 1610
Table 11-114. OUTPUT8MUX16TO31CFG Register Field Descriptions............................................................................... 1613
Table 11-115. OUTPUT1MUXENABLE Register Field Descriptions......................................................................................1616
Table 11-116. OUTPUT2MUXENABLE Register Field Descriptions......................................................................................1621
Table 11-117. OUTPUT3MUXENABLE Register Field Descriptions......................................................................................1626
Table 11-118. OUTPUT4MUXENABLE Register Field Descriptions......................................................................................1631
Table 11-119. OUTPUT5MUXENABLE Register Field Descriptions......................................................................................1636
Table 11-120. OUTPUT6MUXENABLE Register Field Descriptions..................................................................................... 1641
Table 11-121. OUTPUT7MUXENABLE Register Field Descriptions..................................................................................... 1646
Table 11-122. OUTPUT8MUXENABLE Register Field Descriptions..................................................................................... 1651
Table 11-123. OUTPUTLATCH Register Field Descriptions.................................................................................................. 1656
Table 11-124. OUTPUTLATCHCLR Register Field Descriptions...........................................................................................1658
Table 11-125. OUTPUTLATCHFRC Register Field Descriptions...........................................................................................1660
Table 11-126. OUTPUTLATCHENABLE Register Field Descriptions....................................................................................1662
Table 11-127. OUTPUTINV Register Field Descriptions........................................................................................................1664
Table 11-128. OUTPUTLOCK Register Field Descriptions....................................................................................................1666
Table 11-129. OUTPUT_XBAR_REGS Registers................................................................................................................. 1667
Table 11-130. OUTPUT_XBAR_REGS Access Type Codes.................................................................................................1667
Table 11-131. OUTPUT1MUX0TO15CFG Register Field Descriptions................................................................................. 1669
Table 11-132. OUTPUT1MUX16TO31CFG Register Field Descriptions............................................................................... 1672
Table 11-133. OUTPUT2MUX0TO15CFG Register Field Descriptions................................................................................. 1675

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Table 11-134. OUTPUT2MUX16TO31CFG Register Field Descriptions............................................................................... 1678

Table 11-135. OUTPUT3MUX0TO15CFG Register Field Descriptions................................................................................. 1681
Table 11-136. OUTPUT3MUX16TO31CFG Register Field Descriptions............................................................................... 1684
Table 11-137. OUTPUT4MUX0TO15CFG Register Field Descriptions................................................................................. 1687
Table 11-138. OUTPUT4MUX16TO31CFG Register Field Descriptions............................................................................... 1690
Table 11-139. OUTPUT5MUX0TO15CFG Register Field Descriptions................................................................................. 1693
Table 11-140. OUTPUT5MUX16TO31CFG Register Field Descriptions............................................................................... 1696
Table 11-141. OUTPUT6MUX0TO15CFG Register Field Descriptions................................................................................. 1699
Table 11-142. OUTPUT6MUX16TO31CFG Register Field Descriptions............................................................................... 1702
Table 11-143. OUTPUT7MUX0TO15CFG Register Field Descriptions................................................................................. 1705
Table 11-144. OUTPUT7MUX16TO31CFG Register Field Descriptions............................................................................... 1708
Table 11-145. OUTPUT8MUX0TO15CFG Register Field Descriptions................................................................................. 1711
Table 11-146. OUTPUT8MUX16TO31CFG Register Field Descriptions............................................................................... 1714
Table 11-147. OUTPUT1MUXENABLE Register Field Descriptions..................................................................................... 1717
Table 11-148. OUTPUT2MUXENABLE Register Field Descriptions..................................................................................... 1722
Table 11-149. OUTPUT3MUXENABLE Register Field Descriptions..................................................................................... 1727
Table 11-150. OUTPUT4MUXENABLE Register Field Descriptions..................................................................................... 1732
Table 11-151. OUTPUT5MUXENABLE Register Field Descriptions..................................................................................... 1737
Table 11-152. OUTPUT6MUXENABLE Register Field Descriptions..................................................................................... 1742
Table 11-153. OUTPUT7MUXENABLE Register Field Descriptions..................................................................................... 1747
Table 11-154. OUTPUT8MUXENABLE Register Field Descriptions..................................................................................... 1752
Table 11-155. OUTPUTLATCH Register Field Descriptions.................................................................................................. 1757
Table 11-156. OUTPUTLATCHCLR Register Field Descriptions...........................................................................................1759
Table 11-157. OUTPUTLATCHFRC Register Field Descriptions...........................................................................................1761
Table 11-158. OUTPUTLATCHENABLE Register Field Descriptions....................................................................................1763
Table 11-159. OUTPUTINV Register Field Descriptions........................................................................................................1765
Table 11-160. OUTPUTLOCK Register Field Descriptions....................................................................................................1767
Table 12-1. DMA Trigger Source Options.............................................................................................................................. 1773
Table 12-2. BURSTSIZE versus DATASIZE Behavior........................................................................................................... 1778
Table 12-3. DMA Registers to Driverlib Functions................................................................................................................. 1786
Table 12-4. DMA Base Address Table................................................................................................................................... 1788
Table 12-5. DMA_REGS Registers........................................................................................................................................1789
Table 12-6. DMA_REGS Access Type Codes....................................................................................................................... 1789
Table 12-7. DMACTRL Register Field Descriptions...............................................................................................................1790
Table 12-8. DEBUGCTRL Register Field Descriptions..........................................................................................................1791
Table 12-9. PRIORITYCTRL1 Register Field Descriptions....................................................................................................1792
Table 12-10. PRIORITYSTAT Register Field Descriptions.................................................................................................... 1793
Table 12-11. DMA_CH_REGS Registers...............................................................................................................................1794
Table 12-12. DMA_CH_REGS Access Type Codes..............................................................................................................1794
Table 12-13. MODE Register Field Descriptions................................................................................................................... 1795
Table 12-14. CONTROL Register Field Descriptions............................................................................................................ 1797
Table 12-15. BURST_SIZE Register Field Descriptions........................................................................................................1799
Table 12-16. BURST_COUNT Register Field Descriptions................................................................................................... 1800
Table 12-17. SRC_BURST_STEP Register Field Descriptions.............................................................................................1801
Table 12-18. DST_BURST_STEP Register Field Descriptions............................................................................................. 1802
Table 12-19. TRANSFER_SIZE Register Field Descriptions.................................................................................................1803
Table 12-20. TRANSFER_COUNT Register Field Descriptions............................................................................................1804
Table 12-21. SRC_TRANSFER_STEP Register Field Descriptions......................................................................................1805
Table 12-22. DST_TRANSFER_STEP Register Field Descriptions...................................................................................... 1806
Table 12-23. SRC_WRAP_SIZE Register Field Descriptions................................................................................................1807
Table 12-24. SRC_WRAP_COUNT Register Field Descriptions...........................................................................................1808
Table 12-25. SRC_WRAP_STEP Register Field Descriptions.............................................................................................. 1809
Table 12-26. DST_WRAP_SIZE Register Field Descriptions................................................................................................ 1810
Table 12-27. DST_WRAP_COUNT Register Field Descriptions............................................................................................1811
Table 12-28. DST_WRAP_STEP Register Field Descriptions...............................................................................................1812
Table 12-29. SRC_BEG_ADDR_SHADOW Register Field Descriptions.............................................................................. 1813
Table 12-30. SRC_ADDR_SHADOW Register Field Descriptions........................................................................................ 1814
Table 12-31. SRC_BEG_ADDR_ACTIVE Register Field Descriptions..................................................................................1815
Table 12-32. SRC_ADDR_ACTIVE Register Field Descriptions........................................................................................... 1816
Table 12-33. DST_BEG_ADDR_SHADOW Register Field Descriptions...............................................................................1817
Table 12-34. DST_ADDR_SHADOW Register Field Descriptions........................................................................................ 1818

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Table 12-35. DST_BEG_ADDR_ACTIVE Register Field Descriptions.................................................................................. 1819

Table 12-36. DST_ADDR_ACTIVE Register Field Descriptions............................................................................................1820
Table 13-1. Event Selector Mux Signals................................................................................................................................ 1827
Table 13-2. CPU Interfaces Monitored by CRC Units............................................................................................................1834
Table 13-3. Event Selector Mux Signals................................................................................................................................ 1838
Table 13-4. Trace Memory Entry Bit Fields............................................................................................................................1842
Table 13-5. ERAD Registers to Driverlib Functions............................................................................................................... 1845
Table 13-6. ERAD Base Address Table................................................................................................................................. 1855
Table 13-7. ERAD_GLOBAL_REGS Registers..................................................................................................................... 1856
Table 13-8. ERAD_GLOBAL_REGS Access Type Codes.....................................................................................................1856
Table 13-9. GLBL_EVENT_STAT Register Field Descriptions.............................................................................................. 1857
Table 13-10. GLBL_HALT_STAT Register Field Descriptions............................................................................................... 1859
Table 13-11. GLBL_ENABLE Register Field Descriptions..................................................................................................... 1861
Table 13-12. GLBL_CTM_RESET Register Field Descriptions............................................................................................. 1863
Table 13-13. GLBL_NMI_CTL Register Field Descriptions................................................................................................... 1864
Table 13-14. GLBL_OWNER Register Field Descriptions..................................................................................................... 1866
Table 13-15. GLBL_EVENT_AND_MASK Register Field Descriptions................................................................................. 1867
Table 13-16. GLBL_EVENT_OR_MASK Register Field Descriptions................................................................................... 1872
Table 13-17. GLBL_AND_EVENT_INT_MASK Register Field Descriptions......................................................................... 1877
Table 13-18. GLBL_OR_EVENT_INT_MASK Register Field Descriptions........................................................................... 1878
Table 13-19. ERAD_HWBP_REGS Registers.......................................................................................................................1879
Table 13-20. ERAD_HWBP_REGS Access Type Codes...................................................................................................... 1879
Table 13-21. HWBP_MASK Register Field Descriptions....................................................................................................... 1880
Table 13-22. HWBP_REF Register Field Descriptions.......................................................................................................... 1881
Table 13-23. HWBP_CLEAR Register Field Descriptions..................................................................................................... 1882
Table 13-24. HWBP_CNTL Register Field Descriptions........................................................................................................1883
Table 13-25. HWBP_STATUS Register Field Descriptions....................................................................................................1885
Table 13-26. ERAD_COUNTER_REGS Registers................................................................................................................1886
Table 13-27. ERAD_COUNTER_REGS Access Type Codes............................................................................................... 1886
Table 13-28. CTM_CNTL Register Field Descriptions...........................................................................................................1887
Table 13-29. CTM_STATUS Register Field Descriptions.......................................................................................................1889
Table 13-30. CTM_REF Register Field Descriptions............................................................................................................. 1890
Table 13-31. CTM_COUNT Register Field Descriptions....................................................................................................... 1891
Table 13-32. CTM_MAX_COUNT Register Field Descriptions..............................................................................................1892
Table 13-33. CTM_INPUT_SEL Register Field Descriptions.................................................................................................1893
Table 13-34. CTM_CLEAR Register Field Descriptions........................................................................................................ 1894
Table 13-35. CTM_INPUT_SEL_2 Register Field Descriptions.............................................................................................1895
Table 13-36. CTM_INPUT_COND Register Field Descriptions.............................................................................................1896
Table 13-37. ERAD_CRC_GLOBAL_REGS Registers......................................................................................................... 1897
Table 13-38. ERAD_CRC_GLOBAL_REGS Access Type Codes.........................................................................................1897
Table 13-39. CRC_GLOBAL_CTRL Register Field Descriptions.......................................................................................... 1898
Table 13-40. ERAD_CRC_REGS Registers..........................................................................................................................1900
Table 13-41. ERAD_CRC_REGS Access Type Codes......................................................................................................... 1900
Table 13-42. CRC_CURRENT Register Field Descriptions...................................................................................................1901
Table 13-43. CRC_SEED Register Field Descriptions.......................................................................................................... 1902
Table 13-44. CRC_QUALIFIER Register Field Descriptions................................................................................................. 1903
Table 13-45. PCTRACE_REGS Registers............................................................................................................................ 1904
Table 13-46. PCTRACE_REGS Access Type Codes............................................................................................................1904
Table 13-47. PCTRACE_GLOBAL Register Field Descriptions............................................................................................ 1905
Table 13-48. PCTRACE_BUFFER Register Field Descriptions............................................................................................ 1906
Table 13-49. PCTRACE_QUAL1 Register Field Descriptions............................................................................................... 1907
Table 13-50. PCTRACE_QUAL2 Register Field Descriptions............................................................................................... 1908
Table 13-51. PCTRACE_LOGPC_SOFTENABLE Register Field Descriptions.................................................................... 1909
Table 13-52. PCTRACE_LOGPC_SOFTDISABLE Register Field Descriptions................................................................... 1910
Table 13-53. PCTRACE_BUFFER_REGS Registers............................................................................................................ 1911
Table 13-54. PCTRACE_BUFFER_REGS Access Type Codes............................................................................................1911
Table 13-55. PCTRACE_BUFFER_BASE_y Register Field Descriptions............................................................................. 1912
Table 14-1. CMPSS Input Mux Options................................................................................................................................. 1918
Table 14-2. AGPIO Configuration.......................................................................................................................................... 1919
Table 14-3. The Combinations of Use Cases for a Specific Analog Input Pin....................................................................... 1921
Table 14-4. Analog Pins and Internal Connections................................................................................................................1922

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Table 14-5. Analog Signal Descriptions................................................................................................................................. 1924

Table 14-6. Reference Summary........................................................................................................................................... 1925
Table 14-7. ASYSCTL Registers to Driverlib Functions.........................................................................................................1926
Table 14-8. ASBSYS Base Address Table.............................................................................................................................1928
Table 14-9. ANALOG_SUBSYS_REGS Registers................................................................................................................ 1929
Table 14-10. ANALOG_SUBSYS_REGS Access Type Codes............................................................................................. 1929
Table 14-11. ADCOSDETECT Register Field Descriptions................................................................................................... 1931
Table 14-12. REFCONFIGB Register Field Descriptions...................................................................................................... 1932
Table 14-13. INTERNALTESTCTL Register Field Descriptions.............................................................................................1934
Table 14-14. CONFIGLOCK Register Field Descriptions...................................................................................................... 1936
Table 14-15. TSNSCTL Register Field Descriptions..............................................................................................................1937
Table 14-16. ANAREFPCTL Register Field Descriptions...................................................................................................... 1938
Table 14-17. ANAREFNCTL Register Field Descriptions...................................................................................................... 1940
Table 14-18. VMONCTL Register Field Descriptions............................................................................................................ 1941
Table 14-19. CMPHPMXSEL Register Field Descriptions.....................................................................................................1942
Table 14-20. CMPLPMXSEL Register Field Descriptions..................................................................................................... 1943
Table 14-21. CMPHNMXSEL Register Field Descriptions.....................................................................................................1944
Table 14-22. CMPLNMXSEL Register Field Descriptions..................................................................................................... 1945
Table 14-23. ADCDACLOOPBACK Register Field Descriptions........................................................................................... 1946
Table 14-24. CMPSSCTL Register Field Descriptions.......................................................................................................... 1948
Table 14-25. CMPSSDACBUFCONFIG Register Field Descriptions.................................................................................... 1949
Table 14-26. LOCK Register Field Descriptions.................................................................................................................... 1950
Table 14-27. AGPIOCTRLA Register Field Descriptions.......................................................................................................1952
Table 14-28. AGPIOCTRLB Register Field Descriptions.......................................................................................................1954
Table 14-29. AGPIOCTRLG Register Field Descriptions...................................................................................................... 1956
Table 14-30. AGPIOCTRLH Register Field Descriptions.......................................................................................................1958
Table 14-31. GPIOINENACTRL Register Field Descriptions.................................................................................................1960
Table 14-32. IO_DRVSEL Register Field Descriptions.......................................................................................................... 1961
Table 14-33. IO_MODESEL Register Field Descriptions.......................................................................................................1962
Table 14-34. ADCSOCFRCGB Register Field Descriptions.................................................................................................. 1963
Table 14-35. ADCSOCFRCGBSEL Register Field Descriptions........................................................................................... 1965
Table 15-1. ADC Options and Configuration Levels.............................................................................................................. 1970
Table 15-2. Analog to 12-bit Digital Formulas........................................................................................................................1972
Table 15-3. 12-Bit Digital-to-Analog Formulas....................................................................................................................... 1972
Table 15-4. Channel Selection of Input Pins..........................................................................................................................1984
Table 15-5. Example Requirements for Multiple Signal Sampling......................................................................................... 1992
Table 15-6. Example Connections for Multiple Signal Sampling........................................................................................... 1992
Table 15-7. DETECTCFG Settings........................................................................................................................................ 2008
Table 15-8. ADC Timing Parameter Descriptions.................................................................................................................. 2011
Table 15-9. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 0............................................................................ 2014
Table 15-10. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 1.......................................................................... 2014
Table 15-11. PPB Result Timings (One PPB per SOC)......................................................................................................... 2016
Table 15-12. PPB Result Timings (Multiple PPBs Configured to Same SOC).......................................................................2016
Table 15-13. ADC Registers to Driverlib Functions............................................................................................................... 2026
Table 15-14. ADC Base Address Table................................................................................................................................. 2039
Table 15-15. ADC_RESULT_REGS Registers...................................................................................................................... 2040
Table 15-16. ADC_RESULT_REGS Access Type Codes......................................................................................................2041
Table 15-17. ADCRESULT0 Register Field Descriptions.......................................................................................................2042
Table 15-18. ADCRESULT1 Register Field Descriptions.......................................................................................................2043
Table 15-19. ADCRESULT2 Register Field Descriptions.......................................................................................................2044
Table 15-20. ADCRESULT3 Register Field Descriptions.......................................................................................................2045
Table 15-21. ADCRESULT4 Register Field Descriptions.......................................................................................................2046
Table 15-22. ADCRESULT5 Register Field Descriptions.......................................................................................................2047
Table 15-23. ADCRESULT6 Register Field Descriptions.......................................................................................................2048
Table 15-24. ADCRESULT7 Register Field Descriptions.......................................................................................................2049
Table 15-25. ADCRESULT8 Register Field Descriptions.......................................................................................................2050
Table 15-26. ADCRESULT9 Register Field Descriptions.......................................................................................................2051
Table 15-27. ADCRESULT10 Register Field Descriptions.....................................................................................................2052
Table 15-28. ADCRESULT11 Register Field Descriptions.....................................................................................................2053
Table 15-29. ADCRESULT12 Register Field Descriptions.....................................................................................................2054
Table 15-30. ADCRESULT13 Register Field Descriptions.....................................................................................................2055

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Table 15-31. ADCRESULT14 Register Field Descriptions.....................................................................................................2056

Table 15-32. ADCRESULT15 Register Field Descriptions.....................................................................................................2057
Table 15-33. ADCPPB1RESULT Register Field Descriptions............................................................................................... 2058
Table 15-34. ADCPPB2RESULT Register Field Descriptions............................................................................................... 2059
Table 15-35. ADCPPB3RESULT Register Field Descriptions............................................................................................... 2060
Table 15-36. ADCPPB4RESULT Register Field Descriptions............................................................................................... 2061
Table 15-37. ADCPPB1SUM Register Field Descriptions..................................................................................................... 2062
Table 15-38. ADCPPB1COUNT Register Field Descriptions................................................................................................ 2063
Table 15-39. ADCPPB2SUM Register Field Descriptions..................................................................................................... 2064
Table 15-40. ADCPPB2COUNT Register Field Descriptions................................................................................................ 2065
Table 15-41. ADCPPB3SUM Register Field Descriptions..................................................................................................... 2066
Table 15-42. ADCPPB3COUNT Register Field Descriptions................................................................................................ 2067
Table 15-43. ADCPPB4SUM Register Field Descriptions..................................................................................................... 2068
Table 15-44. ADCPPB4COUNT Register Field Descriptions................................................................................................ 2069
Table 15-45. ADCPPB1MAX Register Field Descriptions..................................................................................................... 2070
Table 15-46. ADCPPB1MAXI Register Field Descriptions.................................................................................................... 2071
Table 15-47. ADCPPB1MIN Register Field Descriptions.......................................................................................................2072
Table 15-48. ADCPPB1MINI Register Field Descriptions......................................................................................................2073
Table 15-49. ADCPPB2MAX Register Field Descriptions..................................................................................................... 2074
Table 15-50. ADCPPB2MAXI Register Field Descriptions.................................................................................................... 2075
Table 15-51. ADCPPB2MIN Register Field Descriptions.......................................................................................................2076
Table 15-52. ADCPPB2MINI Register Field Descriptions......................................................................................................2077
Table 15-53. ADCPPB3MAX Register Field Descriptions..................................................................................................... 2078
Table 15-54. ADCPPB3MAXI Register Field Descriptions.................................................................................................... 2079
Table 15-55. ADCPPB3MIN Register Field Descriptions.......................................................................................................2080
Table 15-56. ADCPPB3MINI Register Field Descriptions......................................................................................................2081
Table 15-57. ADCPPB4MAX Register Field Descriptions..................................................................................................... 2082
Table 15-58. ADCPPB4MAXI Register Field Descriptions.................................................................................................... 2083
Table 15-59. ADCPPB4MIN Register Field Descriptions.......................................................................................................2084
Table 15-60. ADCPPB4MINI Register Field Descriptions......................................................................................................2085
Table 15-61. ADC_REGS Registers...................................................................................................................................... 2086
Table 15-62. ADC_REGS Access Type Codes..................................................................................................................... 2089
Table 15-63. ADCCTL1 Register Field Descriptions..............................................................................................................2090
Table 15-64. ADCCTL2 Register Field Descriptions..............................................................................................................2092
Table 15-65. ADCBURSTCTL Register Field Descriptions................................................................................................... 2093
Table 15-66. ADCINTFLG Register Field Descriptions..........................................................................................................2095
Table 15-67. ADCINTFLGCLR Register Field Descriptions.................................................................................................. 2098
Table 15-68. ADCINTOVF Register Field Descriptions......................................................................................................... 2099
Table 15-69. ADCINTOVFCLR Register Field Descriptions.................................................................................................. 2100
Table 15-70. ADCINTSEL1N2 Register Field Descriptions................................................................................................... 2101
Table 15-71. ADCINTSEL3N4 Register Field Descriptions................................................................................................... 2103
Table 15-72. ADCSOCPRICTL Register Field Descriptions..................................................................................................2105
Table 15-73. ADCINTSOCSEL1 Register Field Descriptions................................................................................................ 2107
Table 15-74. ADCSOCFLG1 Register Field Descriptions...................................................................................................... 2110
Table 15-75. ADCSOCFRC1 Register Field Descriptions......................................................................................................2114
Table 15-76. ADCSOCOVF1 Register Field Descriptions......................................................................................................2119
Table 15-77. ADCSOCOVFCLR1 Register Field Descriptions.............................................................................................. 2122
Table 15-78. ADCSOC0CTL Register Field Descriptions......................................................................................................2125
Table 15-79. ADCSOC1CTL Register Field Descriptions......................................................................................................2128
Table 15-80. ADCSOC2CTL Register Field Descriptions......................................................................................................2131
Table 15-81. ADCSOC3CTL Register Field Descriptions......................................................................................................2134
Table 15-82. ADCSOC4CTL Register Field Descriptions......................................................................................................2137
Table 15-83. ADCSOC5CTL Register Field Descriptions......................................................................................................2140
Table 15-84. ADCSOC6CTL Register Field Descriptions......................................................................................................2143
Table 15-85. ADCSOC7CTL Register Field Descriptions......................................................................................................2146
Table 15-86. ADCSOC8CTL Register Field Descriptions......................................................................................................2149
Table 15-87. ADCSOC9CTL Register Field Descriptions......................................................................................................2152
Table 15-88. ADCSOC10CTL Register Field Descriptions....................................................................................................2155
Table 15-89. ADCSOC11CTL Register Field Descriptions.................................................................................................... 2158
Table 15-90. ADCSOC12CTL Register Field Descriptions....................................................................................................2161
Table 15-91. ADCSOC13CTL Register Field Descriptions....................................................................................................2164

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Table 15-92. ADCSOC14CTL Register Field Descriptions....................................................................................................2167

Table 15-93. ADCSOC15CTL Register Field Descriptions....................................................................................................2170
Table 15-94. ADCEVTSTAT Register Field Descriptions.......................................................................................................2173
Table 15-95. ADCEVTCLR Register Field Descriptions........................................................................................................ 2176
Table 15-96. ADCEVTSEL Register Field Descriptions.........................................................................................................2178
Table 15-97. ADCEVTINTSEL Register Field Descriptions...................................................................................................2180
Table 15-98. ADCCOUNTER Register Field Descriptions.....................................................................................................2182
Table 15-99. ADCREV Register Field Descriptions............................................................................................................... 2183
Table 15-100. ADCOFFTRIM Register Field Descriptions.................................................................................................... 2184
Table 15-101. ADCCONFIG2 Register Field Descriptions.................................................................................................... 2185
Table 15-102. ADCPPB1CONFIG Register Field Descriptions............................................................................................. 2186
Table 15-103. ADCPPB1STAMP Register Field Descriptions............................................................................................... 2188
Table 15-104. ADCPPB1OFFCAL Register Field Descriptions............................................................................................. 2189
Table 15-105. ADCPPB1OFFREF Register Field Descriptions.............................................................................................2190
Table 15-106. ADCPPB1TRIPHI Register Field Descriptions............................................................................................... 2191
Table 15-107. ADCPPB1TRIPLO Register Field Descriptions.............................................................................................. 2192
Table 15-108. ADCPPBTRIP1FILCTL Register Field Descriptions....................................................................................... 2193
Table 15-109. ADCPPBTRIP1FILCLKCTL Register Field Descriptions................................................................................ 2194
Table 15-110. ADCPPB2CONFIG Register Field Descriptions..............................................................................................2195
Table 15-111. ADCPPB2STAMP Register Field Descriptions................................................................................................2197
Table 15-112. ADCPPB2OFFCAL Register Field Descriptions............................................................................................. 2198
Table 15-113. ADCPPB2OFFREF Register Field Descriptions............................................................................................. 2199
Table 15-114. ADCPPB2TRIPHI Register Field Descriptions................................................................................................2200
Table 15-115. ADCPPB2TRIPLO Register Field Descriptions...............................................................................................2201
Table 15-116. ADCPPBTRIP2FILCTL Register Field Descriptions....................................................................................... 2202
Table 15-117. ADCPPBTRIP2FILCLKCTL Register Field Descriptions................................................................................ 2203
Table 15-118. ADCPPB3CONFIG Register Field Descriptions..............................................................................................2204
Table 15-119. ADCPPB3STAMP Register Field Descriptions............................................................................................... 2206
Table 15-120. ADCPPB3OFFCAL Register Field Descriptions............................................................................................. 2207
Table 15-121. ADCPPB3OFFREF Register Field Descriptions.............................................................................................2208
Table 15-122. ADCPPB3TRIPHI Register Field Descriptions............................................................................................... 2209
Table 15-123. ADCPPB3TRIPLO Register Field Descriptions.............................................................................................. 2210
Table 15-124. ADCPPBTRIP3FILCTL Register Field Descriptions....................................................................................... 2211
Table 15-125. ADCPPBTRIP3FILCLKCTL Register Field Descriptions................................................................................ 2212
Table 15-126. ADCPPB4CONFIG Register Field Descriptions............................................................................................. 2213
Table 15-127. ADCPPB4STAMP Register Field Descriptions............................................................................................... 2215
Table 15-128. ADCPPB4OFFCAL Register Field Descriptions............................................................................................. 2216
Table 15-129. ADCPPB4OFFREF Register Field Descriptions.............................................................................................2217
Table 15-130. ADCPPB4TRIPHI Register Field Descriptions............................................................................................... 2218
Table 15-131. ADCPPB4TRIPLO Register Field Descriptions.............................................................................................. 2219
Table 15-132. ADCPPBTRIP4FILCTL Register Field Descriptions....................................................................................... 2220
Table 15-133. ADCPPBTRIP4FILCLKCTL Register Field Descriptions................................................................................ 2221
Table 15-134. ADCINTCYCLE Register Field Descriptions...................................................................................................2222
Table 15-135. ADCINLTRIM1 Register Field Descriptions.................................................................................................... 2223
Table 15-136. ADCINLTRIM2 Register Field Descriptions.................................................................................................... 2224
Table 15-137. ADCINLTRIM3 Register Field Descriptions.................................................................................................... 2225
Table 15-138. ADCINLTRIM4 Register Field Descriptions.................................................................................................... 2226
Table 15-139. ADCINLTRIM5 Register Field Descriptions.................................................................................................... 2227
Table 15-140. ADCINLTRIM6 Register Field Descriptions.................................................................................................... 2228
Table 15-141. ADCREV2 Register Field Descriptions........................................................................................................... 2229
Table 15-142. REP1CTL Register Field Descriptions............................................................................................................2230
Table 15-143. REP1N Register Field Descriptions................................................................................................................ 2233
Table 15-144. REP1PHASE Register Field Descriptions...................................................................................................... 2234
Table 15-145. REP1SPREAD Register Field Descriptions....................................................................................................2235
Table 15-146. REP1FRC Register Field Descriptions........................................................................................................... 2236
Table 15-147. REP2CTL Register Field Descriptions............................................................................................................2237
Table 15-148. REP2N Register Field Descriptions................................................................................................................ 2240
Table 15-149. REP2PHASE Register Field Descriptions...................................................................................................... 2241
Table 15-150. REP2SPREAD Register Field Descriptions....................................................................................................2242
Table 15-151. REP2FRC Register Field Descriptions........................................................................................................... 2243
Table 15-152. ADCPPB1LIMIT Register Field Descriptions.................................................................................................. 2244

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Table 15-153. ADCPPBP1PCOUNT Register Field Descriptions..........................................................................................2245

Table 15-154. ADCPPB1CONFIG2 Register Field Descriptions........................................................................................... 2246
Table 15-155. ADCPPB1PSUM Register Field Descriptions.................................................................................................2248
Table 15-156. ADCPPB1PMAX Register Field Descriptions................................................................................................. 2249
Table 15-157. ADCPPB1PMAXI Register Field Descriptions................................................................................................ 2250
Table 15-158. ADCPPB1PMIN Register Field Descriptions.................................................................................................. 2251
Table 15-159. ADCPPB1PMINI Register Field Descriptions................................................................................................. 2252
Table 15-160. ADCPPB1TRIPLO2 Register Field Descriptions............................................................................................ 2253
Table 15-161. ADCPPB2LIMIT Register Field Descriptions.................................................................................................. 2254
Table 15-162. ADCPPBP2PCOUNT Register Field Descriptions..........................................................................................2255
Table 15-163. ADCPPB2CONFIG2 Register Field Descriptions........................................................................................... 2256
Table 15-164. ADCPPB2PSUM Register Field Descriptions.................................................................................................2258
Table 15-165. ADCPPB2PMAX Register Field Descriptions................................................................................................. 2259
Table 15-166. ADCPPB2PMAXI Register Field Descriptions................................................................................................ 2260
Table 15-167. ADCPPB2PMIN Register Field Descriptions.................................................................................................. 2261
Table 15-168. ADCPPB2PMINI Register Field Descriptions................................................................................................. 2262
Table 15-169. ADCPPB2TRIPLO2 Register Field Descriptions............................................................................................ 2263
Table 15-170. ADCPPB3LIMIT Register Field Descriptions.................................................................................................. 2264
Table 15-171. ADCPPBP3PCOUNT Register Field Descriptions..........................................................................................2265
Table 15-172. ADCPPB3CONFIG2 Register Field Descriptions........................................................................................... 2266
Table 15-173. ADCPPB3PSUM Register Field Descriptions.................................................................................................2268
Table 15-174. ADCPPB3PMAX Register Field Descriptions................................................................................................. 2269
Table 15-175. ADCPPB3PMAXI Register Field Descriptions................................................................................................ 2270
Table 15-176. ADCPPB3PMIN Register Field Descriptions.................................................................................................. 2271
Table 15-177. ADCPPB3PMINI Register Field Descriptions................................................................................................. 2272
Table 15-178. ADCPPB3TRIPLO2 Register Field Descriptions............................................................................................ 2273
Table 15-179. ADCPPB4LIMIT Register Field Descriptions.................................................................................................. 2274
Table 15-180. ADCPPBP4PCOUNT Register Field Descriptions..........................................................................................2275
Table 15-181. ADCPPB4CONFIG2 Register Field Descriptions........................................................................................... 2276
Table 15-182. ADCPPB4PSUM Register Field Descriptions.................................................................................................2278
Table 15-183. ADCPPB4PMAX Register Field Descriptions................................................................................................. 2279
Table 15-184. ADCPPB4PMAXI Register Field Descriptions................................................................................................ 2280
Table 15-185. ADCPPB4PMIN Register Field Descriptions.................................................................................................. 2281
Table 15-186. ADCPPB4PMINI Register Field Descriptions................................................................................................. 2282
Table 15-187. ADCPPB4TRIPLO2 Register Field Descriptions............................................................................................ 2283
Table 16-1. DAC Supported Gain Mode Combinations......................................................................................................... 2286
Table 16-2. DAC Registers to Driverlib Functions................................................................................................................. 2288
Table 16-3. DAC Base Address Table................................................................................................................................... 2289
Table 16-4. DAC_REGS Registers........................................................................................................................................ 2290
Table 16-5. DAC_REGS Access Type Codes....................................................................................................................... 2290
Table 16-6. DACREV Register Field Descriptions................................................................................................................. 2291
Table 16-7. DACCTL Register Field Descriptions..................................................................................................................2292
Table 16-8. DACVALA Register Field Descriptions................................................................................................................2293
Table 16-9. DACVALS Register Field Descriptions................................................................................................................2294
Table 16-10. DACOUTEN Register Field Descriptions..........................................................................................................2295
Table 16-11. DACLOCK Register Field Descriptions............................................................................................................. 2296
Table 16-12. DACTRIM Register Field Descriptions..............................................................................................................2297
Table 17-1. CMPSS Registers to Driverlib Functions............................................................................................................ 2309
Table 17-2. CMPSS Base Address Table.............................................................................................................................. 2313
Table 17-3. CMPSS_REGS Registers...................................................................................................................................2314
Table 17-4. CMPSS_REGS Access Type Codes.................................................................................................................. 2315
Table 17-5. COMPCTL Register Field Descriptions.............................................................................................................. 2316
Table 17-6. COMPHYSCTL Register Field Descriptions....................................................................................................... 2318
Table 17-7. COMPSTS Register Field Descriptions.............................................................................................................. 2319
Table 17-8. COMPSTSCLR Register Field Descriptions....................................................................................................... 2320
Table 17-9. COMPDACHCTL Register Field Descriptions.................................................................................................... 2321
Table 17-10. COMPDACHCTL2 Register Field Descriptions................................................................................................ 2323
Table 17-11. DACHVALS Register Field Descriptions........................................................................................................... 2324
Table 17-12. DACHVALA Register Field Descriptions........................................................................................................... 2325
Table 17-13. RAMPHREFA Register Field Descriptions........................................................................................................2326
Table 17-14. RAMPHREFS Register Field Descriptions....................................................................................................... 2327

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Table 17-15. RAMPHSTEPVALA Register Field Descriptions...............................................................................................2328

Table 17-16. RAMPHCTLA Register Field Descriptions........................................................................................................2329
Table 17-17. RAMPHSTEPVALS Register Field Descriptions...............................................................................................2330
Table 17-18. RAMPHCTLS Register Field Descriptions........................................................................................................2331
Table 17-19. RAMPHSTS Register Field Descriptions.......................................................................................................... 2332
Table 17-20. DACLVALS Register Field Descriptions............................................................................................................2333
Table 17-21. DACLVALA Register Field Descriptions............................................................................................................2334
Table 17-22. RAMPHDLYA Register Field Descriptions........................................................................................................ 2335
Table 17-23. RAMPHDLYS Register Field Descriptions........................................................................................................ 2336
Table 17-24. CTRIPLFILCTL Register Field Descriptions..................................................................................................... 2337
Table 17-25. CTRIPLFILCLKCTL Register Field Descriptions.............................................................................................. 2338
Table 17-26. CTRIPHFILCTL Register Field Descriptions.....................................................................................................2339
Table 17-27. CTRIPHFILCLKCTL Register Field Descriptions..............................................................................................2340
Table 17-28. COMPLOCK Register Field Descriptions......................................................................................................... 2341
Table 17-29. COMPDACLCTL Register Field Descriptions...................................................................................................2342
Table 17-30. COMPDACLCTL2 Register Field Descriptions.................................................................................................2344
Table 17-31. RAMPLREFA Register Field Descriptions........................................................................................................ 2345
Table 17-32. RAMPLREFS Register Field Descriptions........................................................................................................ 2346
Table 17-33. RAMPLSTEPVALA Register Field Descriptions............................................................................................... 2347
Table 17-34. RAMPLCTLA Register Field Descriptions........................................................................................................ 2348
Table 17-35. RAMPLSTEPVALS Register Field Descriptions............................................................................................... 2349
Table 17-36. RAMPLCTLS Register Field Descriptions........................................................................................................ 2350
Table 17-37. RAMPLSTS Register Field Descriptions...........................................................................................................2351
Table 17-38. RAMPLDLYA Register Field Descriptions.........................................................................................................2352
Table 17-39. RAMPLDLYS Register Field Descriptions.........................................................................................................2353
Table 17-40. CTRIPLFILCLKCTL2 Register Field Descriptions............................................................................................ 2354
Table 17-41. CTRIPHFILCLKCTL2 Register Field Descriptions............................................................................................2355
Table 18-1. Different Gain Values and Corresponding Resistor Values.................................................................................2358
Table 18-2. Modes of Operation............................................................................................................................................ 2359
Table 18-3. Minimum Filter Resistance..................................................................................................................................2363
Table 18-4. PGA and ADC Connection..................................................................................................................................2367
Table 18-5. PGA Registers to Driverlib Functions................................................................................................................. 2375
Table 18-6. PGA Base Address Table................................................................................................................................... 2376
Table 18-7. PGA_REGS Registers........................................................................................................................................ 2377
Table 18-8. PGA_REGS Access Type Codes....................................................................................................................... 2377
Table 18-9. PGACTL Register Field Descriptions..................................................................................................................2378
Table 18-10. MUXSEL Register Field Descriptions............................................................................................................... 2379
Table 18-11. OFFSETTRIM Register Field Descriptions....................................................................................................... 2380
Table 18-12. PGATYPE Register Field Descriptions............................................................................................................. 2381
Table 18-13. PGALOCK Register Field Descriptions.............................................................................................................2382
Table 19-1. Submodule Configuration Parameters................................................................................................................2391
Table 19-2. Key Time-Base Signals.......................................................................................................................................2395
Table 19-3. ePWM SYNC Selection...................................................................................................................................... 2400
Table 19-4. Action-Qualifier Submodule Possible Input Events.............................................................................................2415
Table 19-5. Action-Qualifier Event Priority for Up-Down-Count Mode................................................................................... 2417
Table 19-6. Action-Qualifier Event Priority for Up-Count Mode............................................................................................. 2417
Table 19-7. Action-Qualifier Event Priority for Down-Count Mode.........................................................................................2417
Table 19-8. Behavior if CMPA/CMPB is Greater than the Period.......................................................................................... 2418
Table 19-9. Classical Dead-Band Operating Modes..............................................................................................................2431
Table 19-10. Additional Dead-Band Operating Modes.......................................................................................................... 2431
Table 19-11. Dead-Band Delay Values in μs as a Function of DBFED and DBRED............................................................. 2433
Table 19-12. Possible Pulse Width Values for EPWMCLK = 80MHz.....................................................................................2436
Table 19-13. Possible Actions On a Trip Event......................................................................................................................2440
Table 19-14. Lock Bits and Corresponding Registers............................................................................................................2478
Table 19-15. Resolution for PWM and HRPWM.................................................................................................................... 2480
Table 19-16. Relationship Between MEP Steps, PWM Frequency, and Resolution..............................................................2486
Table 19-17. CMPA versus Duty (left), and [CMPA:CMPAHR] versus Duty (right)................................................................2487
Table 19-18. Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles................................................................. 2490
Table 19-19. SFO Library Features....................................................................................................................................... 2502
Table 19-20. Factor Values.................................................................................................................................................... 2503
Table 19-21. EPWM Registers to Driverlib Functions............................................................................................................2505

74 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024

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Table 19-22. HRPWM Registers to Driverlib Functions......................................................................................................... 2512

Table 19-23. EPWM Base Address Table..............................................................................................................................2524
Table 19-24. EPWM_REGS Registers.................................................................................................................................. 2525
Table 19-25. EPWM_REGS Access Type Codes..................................................................................................................2527
Table 19-26. TBCTL Register Field Descriptions...................................................................................................................2528
Table 19-27. TBCTL2 Register Field Descriptions.................................................................................................................2530
Table 19-28. EPWMSYNCINSEL Register Field Descriptions.............................................................................................. 2531
Table 19-29. TBCTR Register Field Descriptions.................................................................................................................. 2532
Table 19-30. TBSTS Register Field Descriptions.................................................................................................................. 2533
Table 19-31. EPWMSYNCOUTEN Register Field Descriptions............................................................................................ 2534
Table 19-32. TBCTL3 Register Field Descriptions.................................................................................................................2536
Table 19-33. CMPCTL Register Field Descriptions............................................................................................................... 2537
Table 19-34. CMPCTL2 Register Field Descriptions............................................................................................................. 2539
Table 19-35. DBCTL Register Field Descriptions.................................................................................................................. 2541
Table 19-36. DBCTL2 Register Field Descriptions................................................................................................................ 2544
Table 19-37. AQCTL Register Field Descriptions.................................................................................................................. 2545
Table 19-38. AQTSRCSEL Register Field Descriptions........................................................................................................ 2547
Table 19-39. PCCTL Register Field Descriptions.................................................................................................................. 2548
Table 19-40. VCAPCTL Register Field Descriptions............................................................................................................. 2550
Table 19-41. VCNTCFG Register Field Descriptions.............................................................................................................2552
Table 19-42. HRCNFG Register Field Descriptions...............................................................................................................2554
Table 19-43. HRPWR Register Field Descriptions................................................................................................................ 2556
Table 19-44. HRMSTEP Register Field Descriptions............................................................................................................ 2557
Table 19-45. HRCNFG2 Register Field Descriptions.............................................................................................................2558
Table 19-46. HRPCTL Register Field Descriptions................................................................................................................2559
Table 19-47. TRREM Register Field Descriptions................................................................................................................. 2561
Table 19-48. GLDCTL Register Field Descriptions................................................................................................................2562
Table 19-49. GLDCFG Register Field Descriptions............................................................................................................... 2564
Table 19-50. EPWMXLINK Register Field Descriptions........................................................................................................ 2566
Table 19-51. AQCTLA Register Field Descriptions................................................................................................................2568
Table 19-52. AQCTLA2 Register Field Descriptions..............................................................................................................2570
Table 19-53. AQCTLB Register Field Descriptions................................................................................................................2571
Table 19-54. AQCTLB2 Register Field Descriptions..............................................................................................................2573
Table 19-55. AQSFRC Register Field Descriptions............................................................................................................... 2574
Table 19-56. AQCSFRC Register Field Descriptions............................................................................................................ 2575
Table 19-57. DBREDHR Register Field Descriptions............................................................................................................ 2576
Table 19-58. DBRED Register Field Descriptions................................................................................................................. 2577
Table 19-59. DBFEDHR Register Field Descriptions.............................................................................................................2578
Table 19-60. DBFED Register Field Descriptions..................................................................................................................2579
Table 19-61. TBPHS Register Field Descriptions.................................................................................................................. 2580
Table 19-62. TBPRDHR Register Field Descriptions.............................................................................................................2581
Table 19-63. TBPRD Register Field Descriptions..................................................................................................................2582
Table 19-64. CMPA Register Field Descriptions.................................................................................................................... 2583
Table 19-65. CMPB Register Field Descriptions....................................................................................................................2584
Table 19-66. CMPC Register Field Descriptions................................................................................................................... 2585
Table 19-67. CMPD Register Field Descriptions................................................................................................................... 2586
Table 19-68. GLDCTL2 Register Field Descriptions..............................................................................................................2587
Table 19-69. SWVDELVAL Register Field Descriptions.........................................................................................................2588
Table 19-70. TZSEL Register Field Descriptions...................................................................................................................2589
Table 19-71. TZDCSEL Register Field Descriptions..............................................................................................................2591
Table 19-72. TZCTL Register Field Descriptions...................................................................................................................2592
Table 19-73. TZCTL2 Register Field Descriptions.................................................................................................................2594
Table 19-74. TZCTLDCA Register Field Descriptions........................................................................................................... 2596
Table 19-75. TZCTLDCB Register Field Descriptions........................................................................................................... 2598
Table 19-76. TZEINT Register Field Descriptions................................................................................................................. 2600
Table 19-77. TZFLG Register Field Descriptions...................................................................................................................2601
Table 19-78. TZCBCFLG Register Field Descriptions........................................................................................................... 2603
Table 19-79. TZOSTFLG Register Field Descriptions........................................................................................................... 2605
Table 19-80. TZCLR Register Field Descriptions.................................................................................................................. 2607
Table 19-81. TZCBCCLR Register Field Descriptions...........................................................................................................2609
Table 19-82. TZOSTCLR Register Field Descriptions........................................................................................................... 2610

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Table 19-83. TZFRC Register Field Descriptions...................................................................................................................2611

Table 19-84. ETSEL Register Field Descriptions...................................................................................................................2612
Table 19-85. ETPS Register Field Descriptions.....................................................................................................................2615
Table 19-86. ETFLG Register Field Descriptions.................................................................................................................. 2618
Table 19-87. ETCLR Register Field Descriptions.................................................................................................................. 2619
Table 19-88. ETFRC Register Field Descriptions.................................................................................................................. 2620
Table 19-89. ETINTPS Register Field Descriptions...............................................................................................................2621
Table 19-90. ETSOCPS Register Field Descriptions.............................................................................................................2622
Table 19-91. ETCNTINITCTL Register Field Descriptions.................................................................................................... 2624
Table 19-92. ETCNTINIT Register Field Descriptions........................................................................................................... 2625
Table 19-93. DCTRIPSEL Register Field Descriptions..........................................................................................................2626
Table 19-94. DCACTL Register Field Descriptions................................................................................................................2628
Table 19-95. DCBCTL Register Field Descriptions................................................................................................................2630
Table 19-96. DCFCTL Register Field Descriptions................................................................................................................2632
Table 19-97. DCCAPCTL Register Field Descriptions...........................................................................................................2634
Table 19-98. DCFOFFSET Register Field Descriptions........................................................................................................ 2636
Table 19-99. DCFOFFSETCNT Register Field Descriptions................................................................................................. 2637
Table 19-100. DCFWINDOW Register Field Descriptions.....................................................................................................2638
Table 19-101. DCFWINDOWCNT Register Field Descriptions............................................................................................. 2639
Table 19-102. BLANKPULSEMIXSEL Register Field Descriptions....................................................................................... 2640
Table 19-103. DCCAP Register Field Descriptions............................................................................................................... 2642
Table 19-104. DCAHTRIPSEL Register Field Descriptions...................................................................................................2643
Table 19-105. DCALTRIPSEL Register Field Descriptions....................................................................................................2645
Table 19-106. DCBHTRIPSEL Register Field Descriptions...................................................................................................2647
Table 19-107. DCBLTRIPSEL Register Field Descriptions....................................................................................................2649
Table 19-108. EPWMLOCK Register Field Descriptions....................................................................................................... 2651
Table 19-109. HWVDELVAL Register Field Descriptions...................................................................................................... 2653
Table 19-110. VCNTVAL Register Field Descriptions............................................................................................................ 2654
Table 20-1. eCAP Input Selection..........................................................................................................................................2658
Table 20-2. ECAP Registers to Driverlib Functions............................................................................................................... 2676
Table 20-3. ECAP Base Address Table................................................................................................................................. 2678
Table 20-4. ECAP_REGS Registers......................................................................................................................................2679
Table 20-5. ECAP_REGS Access Type Codes..................................................................................................................... 2679
Table 20-6. TSCTR Register Field Descriptions.................................................................................................................... 2680
Table 20-7. CTRPHS Register Field Descriptions................................................................................................................. 2681
Table 20-8. CAP1 Register Field Descriptions.......................................................................................................................2682
Table 20-9. CAP2 Register Field Descriptions.......................................................................................................................2683
Table 20-10. CAP3 Register Field Descriptions.....................................................................................................................2684
Table 20-11. CAP4 Register Field Descriptions..................................................................................................................... 2685
Table 20-12. ECCTL0 Register Field Descriptions................................................................................................................ 2686
Table 20-13. ECCTL1 Register Field Descriptions................................................................................................................ 2687
Table 20-14. ECCTL2 Register Field Descriptions................................................................................................................ 2689
Table 20-15. ECEINT Register Field Descriptions.................................................................................................................2691
Table 20-16. ECFLG Register Field Descriptions.................................................................................................................. 2693
Table 20-17. ECCLR Register Field Descriptions..................................................................................................................2695
Table 20-18. ECFRC Register Field Descriptions..................................................................................................................2696
Table 20-19. ECAPSYNCINSEL Register Field Descriptions................................................................................................2697
Table 21-1. eQEP Input Source Select Table........................................................................................................................ 2704
Table 21-2. EQEP Memory Map............................................................................................................................................ 2706
Table 21-3. Quadrature Decoder Truth Table........................................................................................................................ 2708
Table 21-4. EQEP Registers to Driverlib Functions............................................................................................................... 2727
Table 21-5. EQEP Base Address Table................................................................................................................................. 2731
Table 21-6. EQEP_REGS Registers......................................................................................................................................2732
Table 21-7. EQEP_REGS Access Type Codes..................................................................................................................... 2732
Table 21-8. QPOSCNT Register Field Descriptions.............................................................................................................. 2734
Table 21-9. QPOSINIT Register Field Descriptions...............................................................................................................2735
Table 21-10. QPOSMAX Register Field Descriptions............................................................................................................2736
Table 21-11. QPOSCMP Register Field Descriptions............................................................................................................ 2737
Table 21-12. QPOSILAT Register Field Descriptions............................................................................................................ 2738
Table 21-13. QPOSSLAT Register Field Descriptions........................................................................................................... 2739
Table 21-14. QPOSLAT Register Field Descriptions............................................................................................................. 2740

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Table 21-15. QUTMR Register Field Descriptions.................................................................................................................2741

Table 21-16. QUPRD Register Field Descriptions................................................................................................................. 2742
Table 21-17. QWDTMR Register Field Descriptions............................................................................................................. 2743
Table 21-18. QWDPRD Register Field Descriptions..............................................................................................................2744
Table 21-19. QDECCTL Register Field Descriptions.............................................................................................................2745
Table 21-20. QEPCTL Register Field Descriptions................................................................................................................2747
Table 21-21. QCAPCTL Register Field Descriptions............................................................................................................. 2749
Table 21-22. QPOSCTL Register Field Descriptions.............................................................................................................2750
Table 21-23. QEINT Register Field Descriptions................................................................................................................... 2751
Table 21-24. QFLG Register Field Descriptions.................................................................................................................... 2753
Table 21-25. QCLR Register Field Descriptions.................................................................................................................... 2755
Table 21-26. QFRC Register Field Descriptions....................................................................................................................2757
Table 21-27. QEPSTS Register Field Descriptions............................................................................................................... 2759
Table 21-28. QCTMR Register Field Descriptions.................................................................................................................2761
Table 21-29. QCPRD Register Field Descriptions................................................................................................................. 2762
Table 21-30. QCTMRLAT Register Field Descriptions...........................................................................................................2763
Table 21-31. QCPRDLAT Register Field Descriptions...........................................................................................................2764
Table 21-32. REV Register Field Descriptions.......................................................................................................................2765
Table 21-33. QEPSTROBESEL Register Field Descriptions.................................................................................................2766
Table 21-34. QMACTRL Register Field Descriptions............................................................................................................ 2767
Table 21-35. QEPSRCSEL Register Field Descriptions........................................................................................................ 2768
Table 22-1. SPI Module Signal Summary.............................................................................................................................. 2773
Table 22-2. SPI Interrupt Flag Modes.................................................................................................................................... 2775
Table 22-3. SPI Clocking Scheme Selection Guide...............................................................................................................2783
Table 22-4. 4-wire versus 3-wire SPI Pin Functions.............................................................................................................. 2786
Table 22-5. 3-Wire SPI Pin Configuration.............................................................................................................................. 2787
Table 22-6. SPI Registers to Driverlib Functions................................................................................................................... 2794
Table 22-7. SPI Base Address Table..................................................................................................................................... 2798
Table 22-8. SPI_REGS Registers..........................................................................................................................................2799
Table 22-9. SPI_REGS Access Type Codes......................................................................................................................... 2799
Table 22-10. SPICCR Register Field Descriptions................................................................................................................ 2800
Table 22-11. SPICTL Register Field Descriptions..................................................................................................................2802
Table 22-12. SPISTS Register Field Descriptions................................................................................................................. 2804
Table 22-13. SPIBRR Register Field Descriptions.................................................................................................................2806
Table 22-14. SPIRXEMU Register Field Descriptions........................................................................................................... 2807
Table 22-15. SPIRXBUF Register Field Descriptions............................................................................................................ 2808
Table 22-16. SPITXBUF Register Field Descriptions............................................................................................................ 2809
Table 22-17. SPIDAT Register Field Descriptions................................................................................................................. 2810
Table 22-18. SPIFFTX Register Field Descriptions................................................................................................................2811
Table 22-19. SPIFFRX Register Field Descriptions...............................................................................................................2813
Table 22-20. SPIFFCT Register Field Descriptions............................................................................................................... 2815
Table 22-21. SPIPRI Register Field Descriptions.................................................................................................................. 2816
Table 23-1. SCI Module Signal Summary..............................................................................................................................2820
Table 23-2. Programming the Data Format Using SCICCR.................................................................................................. 2823
Table 23-3. Asynchronous Baud Register Values for Common SCI Bit Rates...................................................................... 2832
Table 23-4. SCI Interrupt Flags..............................................................................................................................................2834
Table 23-5. SCI Registers to Driverlib Functions................................................................................................................... 2836
Table 23-6. SCI Base Address Table..................................................................................................................................... 2840
Table 23-7. SCI_REGS Registers..........................................................................................................................................2841
Table 23-8. SCI_REGS Access Type Codes......................................................................................................................... 2841
Table 23-9. SCICCR Register Field Descriptions.................................................................................................................. 2842
Table 23-10. SCICTL1 Register Field Descriptions............................................................................................................... 2844
Table 23-11. SCIHBAUD Register Field Descriptions............................................................................................................2846
Table 23-12. SCILBAUD Register Field Descriptions............................................................................................................ 2847
Table 23-13. SCICTL2 Register Field Descriptions............................................................................................................... 2848
Table 23-14. SCIRXST Register Field Descriptions.............................................................................................................. 2850
Table 23-15. SCIRXEMU Register Field Descriptions........................................................................................................... 2853
Table 23-16. SCIRXBUF Register Field Descriptions............................................................................................................2854
Table 23-17. SCITXBUF Register Field Descriptions............................................................................................................ 2856
Table 23-18. SCIFFTX Register Field Descriptions............................................................................................................... 2857
Table 23-19. SCIFFRX Register Field Descriptions...............................................................................................................2859

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Table 23-20. SCIFFCT Register Field Descriptions...............................................................................................................2861

Table 23-21. SCIPRI Register Field Descriptions.................................................................................................................. 2862
Table 24-1. USB Memory Access from Software...................................................................................................................2877
Table 24-2. USB Memory Access from CCS IDE.................................................................................................................. 2878
Table 24-3. USB Registers to Driverlib Functions..................................................................................................................2880
Table 24-4. USB Base Address Table....................................................................................................................................2899
Table 24-5. USB_REGS Registers........................................................................................................................................ 2900
Table 24-6. USB_REGS Access Type Codes........................................................................................................................2902
Table 24-7. USBFADDR Register Field Descriptions............................................................................................................ 2904
Table 24-8. USBPOWER Register Field Descriptions........................................................................................................... 2905
Table 24-9. USBTXIS Register Field Descriptions.................................................................................................................2906
Table 24-10. USBRXIS Register Field Descriptions.............................................................................................................. 2907
Table 24-11. USBTXIE Register Field Descriptions............................................................................................................... 2908
Table 24-12. USBRXIE Register Field Descriptions.............................................................................................................. 2909
Table 24-13. USBIS Register Field Descriptions................................................................................................................... 2910
Table 24-14. USBIE Register Field Descriptions....................................................................................................................2911
Table 24-15. USBFRAME Register Field Descriptions.......................................................................................................... 2912
Table 24-16. USBEPIDX Register Field Descriptions............................................................................................................2913
Table 24-17. USBTEST Register Field Descriptions............................................................................................................. 2914
Table 24-18. USBFIFO0 Register Field Descriptions............................................................................................................ 2915
Table 24-19. USBFIFO1 Register Field Descriptions............................................................................................................ 2916
Table 24-20. USBFIFO2 Register Field Descriptions............................................................................................................ 2917
Table 24-21. USBFIFO3 Register Field Descriptions............................................................................................................ 2918
Table 24-22. USBDEVCTL Register Field Descriptions........................................................................................................ 2919
Table 24-23. USBTXFIFOSZ Register Field Descriptions..................................................................................................... 2921
Table 24-24. USBRXFIFOSZ Register Field Descriptions.....................................................................................................2922
Table 24-25. USBTXFIFOADD Register Field Descriptions.................................................................................................. 2923
Table 24-26. USBRXFIFOADD Register Field Descriptions..................................................................................................2932
Table 24-27. USBCONTIM Register Field Descriptions........................................................................................................ 2941
Table 24-28. USBFSEOF Register Field Descriptions...........................................................................................................2942
Table 24-29. USBLSEOF Register Field Descriptions...........................................................................................................2943
Table 24-30. USBTXFUNCADDR0 Register Field Descriptions............................................................................................2944
Table 24-31. USBTXHUBADDR0 Register Field Descriptions.............................................................................................. 2945
Table 24-32. USBTXHUBPORT0 Register Field Descriptions...............................................................................................2946
Table 24-33. USBTXFUNCADDR1 Register Field Descriptions............................................................................................2947
Table 24-34. USBTXHUBADDR1 Register Field Descriptions.............................................................................................. 2948
Table 24-35. USBTXHUBPORT1 Register Field Descriptions...............................................................................................2949
Table 24-36. USBRXFUNCADDR1 Register Field Descriptions........................................................................................... 2950
Table 24-37. USBRXHUBADDR1 Register Field Descriptions..............................................................................................2951
Table 24-38. USBRXHUBPORT1 Register Field Descriptions.............................................................................................. 2952
Table 24-39. USBTXFUNCADDR2 Register Field Descriptions............................................................................................2953
Table 24-40. USBTXHUBADDR2 Register Field Descriptions.............................................................................................. 2954
Table 24-41. USBTXHUBPORT2 Register Field Descriptions...............................................................................................2955
Table 24-42. USBRXFUNCADDR2 Register Field Descriptions........................................................................................... 2956
Table 24-43. USBRXHUBADDR2 Register Field Descriptions..............................................................................................2957
Table 24-44. USBRXHUBPORT2 Register Field Descriptions.............................................................................................. 2958
Table 24-45. USBTXFUNCADDR3 Register Field Descriptions............................................................................................2959
Table 24-46. USBTXHUBADDR3 Register Field Descriptions.............................................................................................. 2960
Table 24-47. USBTXHUBPORT3 Register Field Descriptions...............................................................................................2961
Table 24-48. USBRXFUNCADDR3 Register Field Descriptions........................................................................................... 2962
Table 24-49. USBRXHUBADDR3 Register Field Descriptions..............................................................................................2963
Table 24-50. USBRXHUBPORT3 Register Field Descriptions.............................................................................................. 2964
Table 24-51. USBCSRL0 Register Field Descriptions........................................................................................................... 2965
Table 24-52. USBCSRH0 Register Field Descriptions.......................................................................................................... 2967
Table 24-53. USBCOUNT0 Register Field Descriptions........................................................................................................2968
Table 24-54. USBTYPE0 Register Field Descriptions........................................................................................................... 2969
Table 24-55. USBNAKLMT Register Field Descriptions........................................................................................................ 2970
Table 24-56. USBTXMAXP1 Register Field Descriptions......................................................................................................2971
Table 24-57. USBTXCSRL1 Register Field Descriptions...................................................................................................... 2972
Table 24-58. USBTXCSRH1 Register Field Descriptions......................................................................................................2974
Table 24-59. USBRXMAXP1 Register Field Descriptions..................................................................................................... 2976

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Table 24-60. USBRXCSRL1 Register Field Descriptions...................................................................................................... 2977

Table 24-61. USBRXCSRH1 Register Field Descriptions..................................................................................................... 2979
Table 24-62. USBRXCOUNT1 Register Field Descriptions...................................................................................................2981
Table 24-63. USBTXTYPE1 Register Field Descriptions.......................................................................................................2982
Table 24-64. USBTXINTERVAL1 Register Field Descriptions...............................................................................................2983
Table 24-65. USBRXTYPE1 Register Field Descriptions...................................................................................................... 2984
Table 24-66. USBRXINTERVAL1 Register Field Descriptions.............................................................................................. 2985
Table 24-67. USBTXMAXP2 Register Field Descriptions......................................................................................................2986
Table 24-68. USBTXCSRL2 Register Field Descriptions...................................................................................................... 2987
Table 24-69. USBTXCSRH2 Register Field Descriptions......................................................................................................2989
Table 24-70. USBRXMAXP2 Register Field Descriptions..................................................................................................... 2991
Table 24-71. USBRXCSRL2 Register Field Descriptions...................................................................................................... 2992
Table 24-72. USBRXCSRH2 Register Field Descriptions..................................................................................................... 2994
Table 24-73. USBRXCOUNT2 Register Field Descriptions...................................................................................................2996
Table 24-74. USBTXTYPE2 Register Field Descriptions.......................................................................................................2997
Table 24-75. USBTXINTERVAL2 Register Field Descriptions...............................................................................................2998
Table 24-76. USBRXTYPE2 Register Field Descriptions...................................................................................................... 2999
Table 24-77. USBRXINTERVAL2 Register Field Descriptions.............................................................................................. 3000
Table 24-78. USBTXMAXP3 Register Field Descriptions......................................................................................................3001
Table 24-79. USBTXCSRL3 Register Field Descriptions...................................................................................................... 3002
Table 24-80. USBTXCSRH3 Register Field Descriptions......................................................................................................3004
Table 24-81. USBRXMAXP3 Register Field Descriptions..................................................................................................... 3006
Table 24-82. USBRXCSRL3 Register Field Descriptions...................................................................................................... 3007
Table 24-83. USBRXCSRH3 Register Field Descriptions..................................................................................................... 3009
Table 24-84. USBRXCOUNT3 Register Field Descriptions................................................................................................... 3011
Table 24-85. USBTXTYPE3 Register Field Descriptions.......................................................................................................3012
Table 24-86. USBTXINTERVAL3 Register Field Descriptions...............................................................................................3013
Table 24-87. USBRXTYPE3 Register Field Descriptions...................................................................................................... 3014
Table 24-88. USBRXINTERVAL3 Register Field Descriptions.............................................................................................. 3015
Table 24-89. USBRQPKTCOUNT1 Register Field Descriptions........................................................................................... 3016
Table 24-90. USBRQPKTCOUNT2 Register Field Descriptions........................................................................................... 3017
Table 24-91. USBRQPKTCOUNT3 Register Field Descriptions........................................................................................... 3018
Table 24-92. USBRXDPKTBUFDIS Register Field Descriptions...........................................................................................3019
Table 24-93. USBTXDPKTBUFDIS Register Field Descriptions........................................................................................... 3020
Table 24-94. USBEPC Register Field Descriptions............................................................................................................... 3021
Table 24-95. USBEPCRIS Register Field Descriptions......................................................................................................... 3023
Table 24-96. USBEPCIM Register Field Descriptions........................................................................................................... 3024
Table 24-97. USBEPCISC Register Field Descriptions......................................................................................................... 3025
Table 24-98. USBDRRIS Register Field Descriptions........................................................................................................... 3026
Table 24-99. USBDRIM Register Field Descriptions............................................................................................................. 3027
Table 24-100. USBDRISC Register Field Descriptions......................................................................................................... 3028
Table 24-101. USBGPCS Register Field Descriptions.......................................................................................................... 3029
Table 24-102. USBVDC Register Field Descriptions............................................................................................................. 3030
Table 24-103. USBVDCRIS Register Field Descriptions....................................................................................................... 3031
Table 24-104. USBVDCIM Register Field Descriptions......................................................................................................... 3032
Table 24-105. USBVDCISC Register Field Descriptions....................................................................................................... 3033
Table 24-106. USBIDVRIS Register Field Descriptions.........................................................................................................3034
Table 24-107. USBIDVIM Register Field Descriptions...........................................................................................................3035
Table 24-108. USBIDVISC Register Field Descriptions.........................................................................................................3036
Table 24-109. USBDMASEL Register Field Descriptions......................................................................................................3037
Table 24-110. USB_GLB_INT_EN Register Field Descriptions............................................................................................. 3039
Table 24-111. USB_GLB_INT_FLG Register Field Descriptions........................................................................................... 3040
Table 24-112. USB_GLB_INT_FLG_CLR Register Field Descriptions..................................................................................3041
Table 24-113. USBDMARIS Register Field Descriptions....................................................................................................... 3042
Table 24-114. USBDMAIM Register Field Descriptions......................................................................................................... 3043
Table 24-115. USBDMAISC Register Field Descriptions....................................................................................................... 3045
Table 25-1. FSI Receiver Core Signals..................................................................................................................................3051
Table 25-2. FSI Transmitter Core Signals..............................................................................................................................3051
Table 25-3. External Trigger Sources and Their Index.......................................................................................................... 3055
Table 25-4. Basic Frame Structure........................................................................................................................................ 3069
Table 25-5. Frame Types and the 4-bit Codes.......................................................................................................................3071

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Table 25-6. Ping Frame......................................................................................................................................................... 3071

Table 25-7. Error Frame.........................................................................................................................................................3072
Table 25-8. Data Frame......................................................................................................................................................... 3072
Table 25-9. Multi-Lane Frame Format................................................................................................................................... 3072
Table 25-10. Loopback Connections..................................................................................................................................... 3074
Table 25-11. RX_TRIGx Trigger Select Signals.....................................................................................................................3079
Table 25-12. FSI-SPI Compatibility Frame Structure.............................................................................................................3080
Table 25-13. Contents of Data Received by a Standard SPI.................................................................................................3080
Table 25-14. FSI as Controller Transmitter, SPI as Peripheral Receiver............................................................................... 3081
Table 25-15. SPI as Controller Transmitter, FSI as Peripheral Receiver............................................................................... 3082
Table 25-16. FSI Registers to Driverlib Functions................................................................................................................. 3087
Table 25-17. FSI Base Address Table................................................................................................................................... 3097
Table 25-18. FSI_TX_REGS Registers................................................................................................................................. 3098
Table 25-19. FSI_TX_REGS Access Type Codes.................................................................................................................3098
Table 25-20. TX_MAIN_CTRL Register Field Descriptions................................................................................................... 3100
Table 25-21. TX_CLK_CTRL Register Field Descriptions..................................................................................................... 3101
Table 25-22. TX_OPER_CTRL_LO Register Field Descriptions........................................................................................... 3102
Table 25-23. TX_OPER_CTRL_HI Register Field Descriptions............................................................................................ 3104
Table 25-24. TX_FRAME_CTRL Register Field Descriptions............................................................................................... 3105
Table 25-25. TX_FRAME_TAG_UDATA Register Field Descriptions.................................................................................... 3106
Table 25-26. TX_BUF_PTR_LOAD Register Field Descriptions........................................................................................... 3107
Table 25-27. TX_BUF_PTR_STS Register Field Descriptions.............................................................................................. 3108
Table 25-28. TX_PING_CTRL Register Field Descriptions................................................................................................... 3109
Table 25-29. TX_PING_TAG Register Field Descriptions......................................................................................................3110
Table 25-30. TX_PING_TO_REF Register Field Descriptions............................................................................................... 3111
Table 25-31. TX_PING_TO_CNT Register Field Descriptions...............................................................................................3112
Table 25-32. TX_INT_CTRL Register Field Descriptions.......................................................................................................3113
Table 25-33. TX_DMA_CTRL Register Field Descriptions.................................................................................................... 3115
Table 25-34. TX_LOCK_CTRL Register Field Descriptions...................................................................................................3116
Table 25-35. TX_EVT_STS Register Field Descriptions........................................................................................................3117
Table 25-36. TX_EVT_CLR Register Field Descriptions........................................................................................................3118
Table 25-37. TX_EVT_FRC Register Field Descriptions....................................................................................................... 3119
Table 25-38. TX_USER_CRC Register Field Descriptions....................................................................................................3120
Table 25-39. TX_ECC_DATA Register Field Descriptions.....................................................................................................3121
Table 25-40. TX_ECC_VAL Register Field Descriptions....................................................................................................... 3122
Table 25-41. TX_DLYLINE_CTRL Register Field Descriptions............................................................................................. 3123
Table 25-42. TX_BUF_BASE_y Register Field Descriptions.................................................................................................3124
Table 25-43. FSI_RX_REGS Registers................................................................................................................................. 3125
Table 25-44. FSI_RX_REGS Access Type Codes................................................................................................................ 3126
Table 25-45. RX_MAIN_CTRL Register Field Descriptions...................................................................................................3127
Table 25-46. RX_OPER_CTRL Register Field Descriptions................................................................................................. 3129
Table 25-47. RX_FRAME_INFO Register Field Descriptions................................................................................................3131
Table 25-48. RX_FRAME_TAG_UDATA Register Field Descriptions....................................................................................3132
Table 25-49. RX_DMA_CTRL Register Field Descriptions....................................................................................................3133
Table 25-50. RX_EVT_STS Register Field Descriptions....................................................................................................... 3134
Table 25-51. RX_CRC_INFO Register Field Descriptions.....................................................................................................3137
Table 25-52. RX_EVT_CLR Register Field Descriptions.......................................................................................................3138
Table 25-53. RX_EVT_FRC Register Field Descriptions.......................................................................................................3140
Table 25-54. RX_BUF_PTR_LOAD Register Field Descriptions...........................................................................................3143
Table 25-55. RX_BUF_PTR_STS Register Field Descriptions..............................................................................................3144
Table 25-56. RX_FRAME_WD_CTRL Register Field Descriptions....................................................................................... 3145
Table 25-57. RX_FRAME_WD_REF Register Field Descriptions......................................................................................... 3146
Table 25-58. RX_FRAME_WD_CNT Register Field Descriptions......................................................................................... 3147
Table 25-59. RX_PING_WD_CTRL Register Field Descriptions...........................................................................................3148
Table 25-60. RX_PING_TAG Register Field Descriptions..................................................................................................... 3149
Table 25-61. RX_PING_WD_REF Register Field Descriptions............................................................................................. 3150
Table 25-62. RX_PING_WD_CNT Register Field Descriptions.............................................................................................3151
Table 25-63. RX_INT1_CTRL Register Field Descriptions....................................................................................................3152
Table 25-64. RX_INT2_CTRL Register Field Descriptions....................................................................................................3155
Table 25-65. RX_LOCK_CTRL Register Field Descriptions..................................................................................................3158
Table 25-66. RX_ECC_DATA Register Field Descriptions.................................................................................................... 3159

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Table 25-67. RX_ECC_VAL Register Field Descriptions....................................................................................................... 3160

Table 25-68. RX_ECC_SEC_DATA Register Field Descriptions........................................................................................... 3161
Table 25-69. RX_ECC_LOG Register Field Descriptions......................................................................................................3162
Table 25-70. RX_FRAME_TAG_CMP Register Field Descriptions....................................................................................... 3163
Table 25-71. RX_PING_TAG_CMP Register Field Descriptions........................................................................................... 3164
Table 25-72. RX_TRIG_CTRL_0 Register Field Descriptions............................................................................................... 3165
Table 25-73. RX_TRIG_WIDTH_0 Register Field Descriptions.............................................................................................3166
Table 25-74. RX_DLYLINE_CTRL Register Field Descriptions............................................................................................. 3167
Table 25-75. RX_TRIG_CTRL_1 Register Field Descriptions............................................................................................... 3168
Table 25-76. RX_TRIG_CTRL_2 Register Field Descriptions............................................................................................... 3169
Table 25-77. RX_TRIG_CTRL_3 Register Field Descriptions............................................................................................... 3170
Table 25-78. RX_VIS_1 Register Field Descriptions............................................................................................................. 3171
Table 25-79. RX_UDATA_FILTER Register Field Descriptions............................................................................................. 3172
Table 25-80. RX_BUF_BASE_y Register Field Descriptions................................................................................................ 3173
Table 26-1. Dependency of Delay d on the Divide-Down Value IPSC................................................................................... 3179
Table 26-2. Operating Modes of the I2C Module................................................................................................................... 3181
Table 26-3. Controller-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR..................... 3182
Table 26-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR...........................................3188
Table 26-5. Ways to Generate a NACK Bit............................................................................................................................ 3194
Table 26-6. Descriptions of the Basic I2C Interrupt Requests............................................................................................... 3195
Table 26-7. I2C Registers to Driverlib Functions................................................................................................................... 3198
Table 26-8. I2C Base Address Table..................................................................................................................................... 3202
Table 26-9. I2C_REGS Registers.......................................................................................................................................... 3203
Table 26-10. I2C_REGS Access Type Codes....................................................................................................................... 3203
Table 26-11. I2COAR Register Field Descriptions................................................................................................................. 3204
Table 26-12. I2CIER Register Field Descriptions.................................................................................................................. 3205
Table 26-13. I2CSTR Register Field Descriptions................................................................................................................. 3206
Table 26-14. I2CCLKL Register Field Descriptions............................................................................................................... 3210
Table 26-15. I2CCLKH Register Field Descriptions............................................................................................................... 3211
Table 26-16. I2CCNT Register Field Descriptions................................................................................................................. 3212
Table 26-17. I2CDRR Register Field Descriptions.................................................................................................................3213
Table 26-18. I2CTAR Register Field Descriptions..................................................................................................................3214
Table 26-19. I2CDXR Register Field Descriptions.................................................................................................................3215
Table 26-20. I2CMDR Register Field Descriptions................................................................................................................ 3216
Table 26-21. I2CISRC Register Field Descriptions................................................................................................................3220
Table 26-22. I2CEMDR Register Field Descriptions..............................................................................................................3221
Table 26-23. I2CPSC Register Field Descriptions................................................................................................................. 3223
Table 26-24. I2CFFTX Register Field Descriptions............................................................................................................... 3224
Table 26-25. I2CFFRX Register Field Descriptions............................................................................................................... 3226
Table 27-1. PMBUS Registers to Driverlib Functions............................................................................................................ 3252
Table 27-2. PMBUS Base Address Table.............................................................................................................................. 3253
Table 27-3. PMBUS_REGS Registers...................................................................................................................................3254
Table 27-4. PMBUS_REGS Access Type Codes.................................................................................................................. 3254
Table 27-5. PMBCCR Register Field Descriptions................................................................................................................ 3255
Table 27-6. PMBTXBUF Register Field Descriptions............................................................................................................ 3257
Table 27-7. PMBRXBUF Register Field Descriptions............................................................................................................ 3258
Table 27-8. PMBACK Register Field Descriptions.................................................................................................................3259
Table 27-9. PMBSTS Register Field Descriptions................................................................................................................. 3260
Table 27-10. PMBINTM Register Field Descriptions............................................................................................................. 3262
Table 27-11. PMBTCR Register Field Descriptions............................................................................................................... 3264
Table 27-12. PMBHTA Register Field Descriptions............................................................................................................... 3266
Table 27-13. PMBCTRL Register Field Descriptions.............................................................................................................3267
Table 27-14. PMBTIMCTL Register Field Descriptions......................................................................................................... 3269
Table 27-15. PMBTIMCLK Register Field Descriptions......................................................................................................... 3270
Table 27-16. PMBTIMSTSETUP Register Field Descriptions............................................................................................... 3271
Table 27-17. PMBTIMBIDLE Register Field Descriptions......................................................................................................3272
Table 27-18. PMBTIMLOWTIMOUT Register Field Descriptions.......................................................................................... 3273
Table 27-19. PMBTIMHIGHTIMOUT Register Field Descriptions......................................................................................... 3274
Table 28-1. MCAN I/O Description.........................................................................................................................................3278
Table 28-2. MCAN Clocks and Resets.................................................................................................................................. 3280
Table 28-3. MCAN Hardware Requests.................................................................................................................................3280

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Table 28-4. Steps to Configure MCAN Module......................................................................................................................3283

Table 28-5. CAN FD Frame Description................................................................................................................................ 3284
Table 28-6. DLC Coding in CAN FD...................................................................................................................................... 3285
Table 28-7. Rx Buffer/Rx FIFO Element Size........................................................................................................................ 3301
Table 28-8. Example Filter Configuration for Rx Buffers........................................................................................................3303
Table 28-9. Possible Configurations for Message Transmission........................................................................................... 3303
Table 28-10. Tx Buffer, Tx FIFO, Tx Queue Element Size.....................................................................................................3304
Table 28-11. Rx Buffer/Rx FIFO Element Field Descriptions................................................................................................. 3309
Table 28-12. Tx Buffer Element Field Descriptions................................................................................................................ 3311
Table 28-13. Tx Event FIFO Element Field Descriptions.......................................................................................................3313
Table 28-14. Standard Message ID Filter Element Field Descriptions.................................................................................. 3315
Table 28-15. Extended Message ID Filter Element Field Descriptions..................................................................................3316
Table 28-16. MCAN Registers to Driverlib Functions............................................................................................................ 3318
Table 28-17. MCAN Base Address Table.............................................................................................................................. 3325
Table 28-18. MCANSS_REGS Registers.............................................................................................................................. 3326
Table 28-19. MCANSS_REGS Access Type Codes..............................................................................................................3326
Table 28-20. MCANSS_PID Register Field Descriptions.......................................................................................................3327
Table 28-21. MCANSS_CTRL Register Field Descriptions................................................................................................... 3328
Table 28-22. MCANSS_STAT Register Field Descriptions.................................................................................................... 3329
Table 28-23. MCANSS_ICS Register Field Descriptions.......................................................................................................3330
Table 28-24. MCANSS_IRS Register Field Descriptions.......................................................................................................3331
Table 28-25. MCANSS_IECS Register Field Descriptions.................................................................................................... 3332
Table 28-26. MCANSS_IE Register Field Descriptions......................................................................................................... 3333
Table 28-27. MCANSS_IES Register Field Descriptions.......................................................................................................3334
Table 28-28. MCANSS_EOI Register Field Descriptions...................................................................................................... 3335
Table 28-29. MCANSS_EXT_TS_PRESCALER Register Field Descriptions....................................................................... 3336
Table 28-30. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register Field Descriptions............................................... 3337
Table 28-31. MCAN_REGS Registers................................................................................................................................... 3338
Table 28-32. MCAN_REGS Access Type Codes.................................................................................................................. 3339
Table 28-33. MCAN_CREL Register Field Descriptions........................................................................................................3340
Table 28-34. MCAN_ENDN Register Field Descriptions....................................................................................................... 3341
Table 28-35. MCAN_DBTP Register Field Descriptions........................................................................................................3342
Table 28-36. MCAN_TEST Register Field Descriptions........................................................................................................ 3344
Table 28-37. MCAN_RWD Register Field Descriptions......................................................................................................... 3345
Table 28-38. MCAN_CCCR Register Field Descriptions....................................................................................................... 3346
Table 28-39. MCAN_NBTP Register Field Descriptions........................................................................................................3349
Table 28-40. MCAN_TSCC Register Field Descriptions........................................................................................................3351
Table 28-41. MCAN_TSCV Register Field Descriptions........................................................................................................3352
Table 28-42. MCAN_TOCC Register Field Descriptions....................................................................................................... 3353
Table 28-43. MCAN_TOCV Register Field Descriptions........................................................................................................3354
Table 28-44. MCAN_ECR Register Field Descriptions..........................................................................................................3355
Table 28-45. MCAN_PSR Register Field Descriptions.......................................................................................................... 3356
Table 28-46. MCAN_TDCR Register Field Descriptions....................................................................................................... 3359
Table 28-47. MCAN_IR Register Field Descriptions..............................................................................................................3360
Table 28-48. MCAN_IE Register Field Descriptions.............................................................................................................. 3364
Table 28-49. MCAN_ILS Register Field Descriptions............................................................................................................ 3366
Table 28-50. MCAN_ILE Register Field Descriptions............................................................................................................ 3369
Table 28-51. MCAN_GFC Register Field Descriptions..........................................................................................................3370
Table 28-52. MCAN_SIDFC Register Field Descriptions.......................................................................................................3371
Table 28-53. MCAN_XIDFC Register Field Descriptions.......................................................................................................3372
Table 28-54. MCAN_XIDAM Register Field Descriptions...................................................................................................... 3373
Table 28-55. MCAN_HPMS Register Field Descriptions....................................................................................................... 3374
Table 28-56. MCAN_NDAT1 Register Field Descriptions...................................................................................................... 3375
Table 28-57. MCAN_NDAT2 Register Field Descriptions...................................................................................................... 3378
Table 28-58. MCAN_RXF0C Register Field Descriptions......................................................................................................3381
Table 28-59. MCAN_RXF0S Register Field Descriptions......................................................................................................3382
Table 28-60. MCAN_RXF0A Register Field Descriptions......................................................................................................3383
Table 28-61. MCAN_RXBC Register Field Descriptions....................................................................................................... 3384
Table 28-62. MCAN_RXF1C Register Field Descriptions......................................................................................................3385
Table 28-63. MCAN_RXF1S Register Field Descriptions......................................................................................................3386
Table 28-64. MCAN_RXF1A Register Field Descriptions......................................................................................................3387

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Table 28-65. MCAN_RXESC Register Field Descriptions..................................................................................................... 3388

Table 28-66. MCAN_TXBC Register Field Descriptions........................................................................................................3390
Table 28-67. MCAN_TXFQS Register Field Descriptions..................................................................................................... 3392
Table 28-68. MCAN_TXESC Register Field Descriptions..................................................................................................... 3393
Table 28-69. MCAN_TXBRP Register Field Descriptions..................................................................................................... 3394
Table 28-70. MCAN_TXBAR Register Field Descriptions..................................................................................................... 3397
Table 28-71. MCAN_TXBCR Register Field Descriptions..................................................................................................... 3399
Table 28-72. MCAN_TXBTO Register Field Descriptions......................................................................................................3401
Table 28-73. MCAN_TXBCF Register Field Descriptions......................................................................................................3403
Table 28-74. MCAN_TXBTIE Register Field Descriptions.....................................................................................................3405
Table 28-75. MCAN_TXBCIE Register Field Descriptions.................................................................................................... 3409
Table 28-76. MCAN_TXEFC Register Field Descriptions......................................................................................................3413
Table 28-77. MCAN_TXEFS Register Field Descriptions......................................................................................................3414
Table 28-78. MCAN_TXEFA Register Field Descriptions...................................................................................................... 3415
Table 28-79. MCAN_ERROR_REGS Registers.................................................................................................................... 3416
Table 28-80. MCAN_ERROR_REGS Access Type Codes................................................................................................... 3416
Table 28-81. MCANERR_REV Register Field Descriptions.................................................................................................. 3418
Table 28-82. MCANERR_VECTOR Register Field Descriptions........................................................................................... 3419
Table 28-83. MCANERR_STAT Register Field Descriptions................................................................................................. 3420
Table 28-84. MCANERR_WRAP_REV Register Field Descriptions......................................................................................3421
Table 28-85. MCANERR_CTRL Register Field Descriptions................................................................................................ 3422
Table 28-86. MCANERR_ERR_CTRL1 Register Field Descriptions.....................................................................................3424
Table 28-87. MCANERR_ERR_CTRL2 Register Field Descriptions.....................................................................................3425
Table 28-88. MCANERR_ERR_STAT1 Register Field Descriptions......................................................................................3426
Table 28-89. MCANERR_ERR_STAT2 Register Field Descriptions......................................................................................3428
Table 28-90. MCANERR_ERR_STAT3 Register Field Descriptions......................................................................................3429
Table 28-91. MCANERR_SEC_EOI Register Field Descriptions.......................................................................................... 3430
Table 28-92. MCANERR_SEC_STATUS Register Field Descriptions...................................................................................3431
Table 28-93. MCANERR_SEC_ENABLE_SET Register Field Descriptions......................................................................... 3432
Table 28-94. MCANERR_SEC_ENABLE_CLR Register Field Descriptions......................................................................... 3433
Table 28-95. MCANERR_DED_EOI Register Field Descriptions.......................................................................................... 3434
Table 28-96. MCANERR_DED_STATUS Register Field Descriptions...................................................................................3435
Table 28-97. MCANERR_DED_ENABLE_SET Register Field Descriptions......................................................................... 3436
Table 28-98. MCANERR_DED_ENABLE_CLR Register Field Descriptions.........................................................................3437
Table 28-99. MCANERR_AGGR_ENABLE_SET Register Field Descriptions...................................................................... 3438
Table 28-100. MCANERR_AGGR_ENABLE_CLR Register Field Descriptions....................................................................3439
Table 28-101. MCANERR_AGGR_STATUS_SET Register Field Descriptions.....................................................................3440
Table 28-102. MCANERR_AGGR_STATUS_CLR Register Field Descriptions.................................................................... 3441
Table 29-1. Superfractional Bit Modulation for SCI Mode (Normal Configuration)................................................................ 3451
Table 29-2. Superfractional Bit Modulation for SCI Mode (Maximum Configuration)............................................................ 3452
Table 29-3. SCI Mode (Minimum Configuration)....................................................................................................................3452
Table 29-4. SCI/LIN Interrupts............................................................................................................................................... 3460
Table 29-5. SCI Receiver Status Flags..................................................................................................................................3461
Table 29-6. SCI Transmitter Status Flags.............................................................................................................................. 3461
Table 29-7. Response Length Info Using IDBYTE Field Bits [5:4] for LIN Standards Earlier than v1.3................................ 3468
Table 29-8. Response Length with SCIFORMAT[18:16] Programming................................................................................. 3468
Table 29-9. Superfractional Bit Modulation for LIN Commander Mode and Responder Mode..............................................3470
Table 29-10. Timeout Values in Tbit Units.............................................................................................................................. 3478
Table 29-11. LIN Registers to Driverlib Functions..................................................................................................................3491
Table 29-12. LIN Base Address Table................................................................................................................................... 3496
Table 29-13. LIN_REGS Registers........................................................................................................................................ 3497
Table 29-14. LIN_REGS Access Type Codes....................................................................................................................... 3497
Table 29-15. SCIGCR0 Register Field Descriptions.............................................................................................................. 3499
Table 29-16. SCIGCR1 Register Field Descriptions.............................................................................................................. 3500
Table 29-17. SCIGCR2 Register Field Descriptions.............................................................................................................. 3505
Table 29-18. SCISETINT Register Field Descriptions........................................................................................................... 3507
Table 29-19. SCICLEARINT Register Field Descriptions.......................................................................................................3511
Table 29-20. SCISETINTLVL Register Field Descriptions..................................................................................................... 3514
Table 29-21. SCICLEARINTLVL Register Field Descriptions................................................................................................ 3517
Table 29-22. SCIFLR Register Field Descriptions................................................................................................................. 3520
Table 29-23. SCIINTVECT0 Register Field Descriptions.......................................................................................................3528

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Table 29-24. SCIINTVECT1 Register Field Descriptions.......................................................................................................3529

Table 29-25. SCIFORMAT Register Field Descriptions......................................................................................................... 3530
Table 29-26. BRSR Register Field Descriptions.................................................................................................................... 3531
Table 29-27. SCIED Register Field Descriptions................................................................................................................... 3533
Table 29-28. SCIRD Register Field Descriptions...................................................................................................................3534
Table 29-29. SCITD Register Field Descriptions................................................................................................................... 3535
Table 29-30. SCIPIO0 Register Field Descriptions................................................................................................................3536
Table 29-31. SCIPIO2 Register Field Descriptions................................................................................................................3537
Table 29-32. LINCOMP Register Field Descriptions..............................................................................................................3538
Table 29-33. LINRD0 Register Field Descriptions................................................................................................................. 3539
Table 29-34. LINRD1 Register Field Descriptions................................................................................................................. 3540
Table 29-35. LINMASK Register Field Descriptions.............................................................................................................. 3541
Table 29-36. LINID Register Field Descriptions.....................................................................................................................3542
Table 29-37. LINTD0 Register Field Descriptions..................................................................................................................3543
Table 29-38. LINTD1 Register Field Descriptions..................................................................................................................3544
Table 29-39. MBRSR Register Field Descriptions................................................................................................................. 3545
Table 29-40. IODFTCTRL Register Field Descriptions..........................................................................................................3546
Table 29-41. LIN_GLB_INT_EN Register Field Descriptions................................................................................................ 3549
Table 29-42. LIN_GLB_INT_FLG Register Field Descriptions.............................................................................................. 3550
Table 29-43. LIN_GLB_INT_CLR Register Field Descriptions.............................................................................................. 3551
Table 30-1. Example CLB Clocking Configuration.................................................................................................................3555
Table 30-2. Global Signals and Mux Selection...................................................................................................................... 3559
Table 30-3. Local Signals and Mux Selection........................................................................................................................ 3563
Table 30-4. CLB Output Signal Multiplexer Table.................................................................................................................. 3567
Table 30-5. Output Table........................................................................................................................................................3571
Table 30-6. Input Table.......................................................................................................................................................... 3572
Table 30-7. Ports Tied Off to Prevent Combinatorial Loops...................................................................................................3572
Table 30-8. Counter Block Operating Modes.........................................................................................................................3575
Table 30-9. HLC Event List.................................................................................................................................................... 3584
Table 30-10. HLC ALT Event List...........................................................................................................................................3585
Table 30-11. HLC Instruction Address Ranges...................................................................................................................... 3586
Table 30-12. HLC Instruction Format.....................................................................................................................................3586
Table 30-13. HLC Instruction Description.............................................................................................................................. 3586
Table 30-14. HLC Register Encoding.................................................................................................................................... 3587
Table 30-15. Non-Memory Mapped Register Addresses.......................................................................................................3589
Table 30-16. CLB to SPI RX Access......................................................................................................................................3590
Table 30-17. CLB Registers to Driverlib Functions................................................................................................................ 3591
Table 30-18. CLB Base Address Table.................................................................................................................................. 3600
Table 30-19. CLB_LOGIC_CONFIG_REGS Registers......................................................................................................... 3601
Table 30-20. CLB_LOGIC_CONFIG_REGS Access Type Codes.........................................................................................3602
Table 30-21. CLB_COUNT_RESET Register Field Descriptions.......................................................................................... 3603
Table 30-22. CLB_COUNT_MODE_1 Register Field Descriptions....................................................................................... 3604
Table 30-23. CLB_COUNT_MODE_0 Register Field Descriptions....................................................................................... 3605
Table 30-24. CLB_COUNT_EVENT Register Field Descriptions.......................................................................................... 3606
Table 30-25. CLB_FSM_EXTRA_IN0 Register Field Descriptions........................................................................................3607
Table 30-26. CLB_FSM_EXTERNAL_IN0 Register Field Descriptions.................................................................................3608
Table 30-27. CLB_FSM_EXTERNAL_IN1 Register Field Descriptions.................................................................................3609
Table 30-28. CLB_FSM_EXTRA_IN1 Register Field Descriptions........................................................................................3610
Table 30-29. CLB_LUT4_IN0 Register Field Descriptions..................................................................................................... 3611
Table 30-30. CLB_LUT4_IN1 Register Field Descriptions.....................................................................................................3612
Table 30-31. CLB_LUT4_IN2 Register Field Descriptions.....................................................................................................3613
Table 30-32. CLB_LUT4_IN3 Register Field Descriptions.....................................................................................................3614
Table 30-33. CLB_FSM_LUT_FN1_0 Register Field Descriptions........................................................................................3615
Table 30-34. CLB_FSM_LUT_FN2 Register Field Descriptions............................................................................................3616
Table 30-35. CLB_LUT4_FN1_0 Register Field Descriptions............................................................................................... 3617
Table 30-36. CLB_LUT4_FN2 Register Field Descriptions................................................................................................... 3618
Table 30-37. CLB_FSM_NEXT_STATE_0 Register Field Descriptions.................................................................................3619
Table 30-38. CLB_FSM_NEXT_STATE_1 Register Field Descriptions.................................................................................3620
Table 30-39. CLB_FSM_NEXT_STATE_2 Register Field Descriptions.................................................................................3621
Table 30-40. CLB_MISC_CONTROL Register Field Descriptions........................................................................................ 3622
Table 30-41. CLB_OUTPUT_LUT_0 Register Field Descriptions......................................................................................... 3625

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Table 30-42. CLB_OUTPUT_LUT_1 Register Field Descriptions......................................................................................... 3626

Table 30-43. CLB_OUTPUT_LUT_2 Register Field Descriptions......................................................................................... 3627
Table 30-44. CLB_OUTPUT_LUT_3 Register Field Descriptions......................................................................................... 3628
Table 30-45. CLB_OUTPUT_LUT_4 Register Field Descriptions......................................................................................... 3629
Table 30-46. CLB_OUTPUT_LUT_5 Register Field Descriptions......................................................................................... 3630
Table 30-47. CLB_OUTPUT_LUT_6 Register Field Descriptions......................................................................................... 3631
Table 30-48. CLB_OUTPUT_LUT_7 Register Field Descriptions......................................................................................... 3632
Table 30-49. CLB_HLC_EVENT_SEL Register Field Descriptions....................................................................................... 3633
Table 30-50. CLB_COUNT_MATCH_TAP_SEL Register Field Descriptions........................................................................ 3634
Table 30-51. CLB_OUTPUT_COND_CTRL_0 Register Field Descriptions.......................................................................... 3635
Table 30-52. CLB_OUTPUT_COND_CTRL_1 Register Field Descriptions.......................................................................... 3637
Table 30-53. CLB_OUTPUT_COND_CTRL_2 Register Field Descriptions.......................................................................... 3639
Table 30-54. CLB_OUTPUT_COND_CTRL_3 Register Field Descriptions.......................................................................... 3641
Table 30-55. CLB_OUTPUT_COND_CTRL_4 Register Field Descriptions.......................................................................... 3643
Table 30-56. CLB_OUTPUT_COND_CTRL_5 Register Field Descriptions.......................................................................... 3645
Table 30-57. CLB_OUTPUT_COND_CTRL_6 Register Field Descriptions.......................................................................... 3647
Table 30-58. CLB_OUTPUT_COND_CTRL_7 Register Field Descriptions.......................................................................... 3649
Table 30-59. CLB_MISC_ACCESS_CTRL Register Field Descriptions................................................................................3651
Table 30-60. CLB_SPI_DATA_CTRL_HI Register Field Descriptions................................................................................... 3652
Table 30-61. CLB_LOGIC_CONTROL_REGS Registers......................................................................................................3653
Table 30-62. CLB_LOGIC_CONTROL_REGS Access Type Codes..................................................................................... 3653
Table 30-63. CLB_LOAD_EN Register Field Descriptions.................................................................................................... 3655
Table 30-64. CLB_LOAD_ADDR Register Field Descriptions............................................................................................... 3656
Table 30-65. CLB_LOAD_DATA Register Field Descriptions................................................................................................ 3657
Table 30-66. CLB_INPUT_FILTER Register Field Descriptions............................................................................................ 3658
Table 30-67. CLB_IN_MUX_SEL_0 Register Field Descriptions...........................................................................................3661
Table 30-68. CLB_LCL_MUX_SEL_1 Register Field Descriptions........................................................................................3663
Table 30-69. CLB_LCL_MUX_SEL_2 Register Field Descriptions........................................................................................3664
Table 30-70. CLB_BUF_PTR Register Field Descriptions.....................................................................................................3665
Table 30-71. CLB_GP_REG Register Field Descriptions...................................................................................................... 3666
Table 30-72. CLB_OUT_EN Register Field Descriptions...................................................................................................... 3668
Table 30-73. CLB_GLBL_MUX_SEL_1 Register Field Descriptions..................................................................................... 3669
Table 30-74. CLB_GLBL_MUX_SEL_2 Register Field Descriptions..................................................................................... 3670
Table 30-75. CLB_PRESCALE_CTRL Register Field Descriptions...................................................................................... 3671
Table 30-76. CLB_INTR_TAG_REG Register Field Descriptions..........................................................................................3672
Table 30-77. CLB_LOCK Register Field Descriptions........................................................................................................... 3673
Table 30-78. CLB_HLC_INSTR_READ_PTR Register Field Descriptions............................................................................3674
Table 30-79. CLB_HLC_INSTR_VALUE Register Field Descriptions....................................................................................3675
Table 30-80. CLB_DBG_OUT_2 Register Field Descriptions................................................................................................3676
Table 30-81. CLB_DBG_R0 Register Field Descriptions.......................................................................................................3677
Table 30-82. CLB_DBG_R1 Register Field Descriptions.......................................................................................................3678
Table 30-83. CLB_DBG_R2 Register Field Descriptions.......................................................................................................3679
Table 30-84. CLB_DBG_R3 Register Field Descriptions.......................................................................................................3680
Table 30-85. CLB_DBG_C0 Register Field Descriptions.......................................................................................................3681
Table 30-86. CLB_DBG_C1 Register Field Descriptions.......................................................................................................3682
Table 30-87. CLB_DBG_C2 Register Field Descriptions.......................................................................................................3683
Table 30-88. CLB_DBG_OUT Register Field Descriptions....................................................................................................3684
Table 30-89. CLB_DATA_EXCHANGE_REGS Registers..................................................................................................... 3686
Table 30-90. CLB_DATA_EXCHANGE_REGS Access Type Codes.....................................................................................3686
Table 30-91. CLB_PUSH Register Field Descriptions........................................................................................................... 3687
Table 30-92. CLB_PULL Register Field Descriptions............................................................................................................ 3688
Table 31-1. AES Subsystem DMA Interface.......................................................................................................................... 3692
Table 31-2. Key-Block-Round Combinations......................................................................................................................... 3693
Table 31-3. Interrupts and Events..........................................................................................................................................3704
Table 31-4. AES Registers to Driverlib Functions..................................................................................................................3710
Table 31-5. AES_SS Registers to Driverlib Functions........................................................................................................... 3712
Table 31-6. AES Base Address Table....................................................................................................................................3714
Table 31-7. AES_REGS Registers........................................................................................................................................ 3715
Table 31-8. AES_REGS Access Type Codes........................................................................................................................3716
Table 31-9. AES_KEY2_6 Register Field Descriptions..........................................................................................................3717
Table 31-10. AES_KEY2_7 Register Field Descriptions........................................................................................................3718

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Table 31-11. AES_KEY2_4 Register Field Descriptions........................................................................................................ 3719

Table 31-12. AES_KEY2_5 Register Field Descriptions........................................................................................................3720
Table 31-13. AES_KEY2_2 Register Field Descriptions........................................................................................................3721
Table 31-14. AES_KEY2_3 Register Field Descriptions........................................................................................................3722
Table 31-15. AES_KEY2_0 Register Field Descriptions........................................................................................................3723
Table 31-16. AES_KEY2_1 Register Field Descriptions........................................................................................................3724
Table 31-17. AES_KEY1_6 Register Field Descriptions........................................................................................................3725
Table 31-18. AES_KEY1_7 Register Field Descriptions........................................................................................................3726
Table 31-19. AES_KEY1_4 Register Field Descriptions........................................................................................................3727
Table 31-20. AES_KEY1_5 Register Field Descriptions........................................................................................................3728
Table 31-21. AES_KEY1_2 Register Field Descriptions........................................................................................................3729
Table 31-22. AES_KEY1_3 Register Field Descriptions........................................................................................................3730
Table 31-23. AES_KEY1_0 Register Field Descriptions........................................................................................................3731
Table 31-24. AES_KEY1_1 Register Field Descriptions........................................................................................................3732
Table 31-25. AES_IV_IN_OUT_0 Register Field Descriptions.............................................................................................. 3733
Table 31-26. AES_IV_IN_OUT_1 Register Field Descriptions.............................................................................................. 3734
Table 31-27. AES_IV_IN_OUT_2 Register Field Descriptions.............................................................................................. 3735
Table 31-28. AES_IV_IN_OUT_3 Register Field Descriptions.............................................................................................. 3736
Table 31-29. AES_CTRL Register Field Descriptions........................................................................................................... 3737
Table 31-30. AES_C_LENGTH_0 Register Field Descriptions..............................................................................................3741
Table 31-31. AES_C_LENGTH_1 Register Field Descriptions..............................................................................................3742
Table 31-32. AES_AUTH_LENGTH Register Field Descriptions.......................................................................................... 3743
Table 31-33. AES_DATA_IN_OUT_0 Register Field Descriptions.........................................................................................3744
Table 31-34. AES_DATA_IN_OUT_1 Register Field Descriptions.........................................................................................3745
Table 31-35. AES_DATA_IN_OUT_2 Register Field Descriptions.........................................................................................3746
Table 31-36. AES_DATA_IN_OUT_3 Register Field Descriptions.........................................................................................3747
Table 31-37. AES_TAG_OUT_0 Register Field Descriptions................................................................................................ 3748
Table 31-38. AES_TAG_OUT_1 Register Field Descriptions................................................................................................ 3749
Table 31-39. AES_TAG_OUT_2 Register Field Descriptions................................................................................................ 3750
Table 31-40. AES_TAG_OUT_3 Register Field Descriptions................................................................................................ 3751
Table 31-41. AES_REV Register Field Descriptions............................................................................................................. 3752
Table 31-42. AES_SYSCONFIG Register Field Descriptions................................................................................................3753
Table 31-43. AES_SYSSTATUS Register Field Descriptions................................................................................................ 3755
Table 31-44. AES_IRQSTATUS Register Field Descriptions.................................................................................................3756
Table 31-45. AES_IRQENABLE Register Field Descriptions................................................................................................ 3757
Table 31-46. AES_DIRTY_BITS Register Field Descriptions................................................................................................ 3758
Table 31-47. AES_SS_REGS Registers................................................................................................................................3759
Table 31-48. AES_SS_REGS Access Type Codes............................................................................................................... 3759
Table 31-49. AES_GLB_INT_FLG Register Field Descriptions.............................................................................................3760
Table 31-50. AES_GLB_INT_CLR Register Field Descriptions.............................................................................................3761
Table 32-1. SIGGENx Active Register Loading..................................................................................................................... 3767
Table 32-2. EPG Data Input Connections..............................................................................................................................3770
Table 32-3. EPG Input Connections...................................................................................................................................... 3772
Table 32-4. EPG Output Connections....................................................................................................................................3772
Table 32-5. EPG Registers to Driverlib Functions................................................................................................................. 3777
Table 32-6. EPG Base Address Table................................................................................................................................... 3779
Table 32-7. EPG_REGS Registers........................................................................................................................................ 3780
Table 32-8. EPG_REGS Access Type Codes....................................................................................................................... 3780
Table 32-9. GCTL0 Register Field Descriptions.................................................................................................................... 3782
Table 32-10. GCTL1 Register Field Descriptions.................................................................................................................. 3784
Table 32-11. GCTL2 Register Field Descriptions...................................................................................................................3785
Table 32-12. GCTL3 Register Field Descriptions.................................................................................................................. 3787
Table 32-13. EPGLOCK Register Field Descriptions.............................................................................................................3791
Table 32-14. EPGCOMMIT Register Field Descriptions........................................................................................................3792
Table 32-15. GINTSTS Register Field Descriptions.............................................................................................................. 3793
Table 32-16. GINTEN Register Field Descriptions................................................................................................................ 3794
Table 32-17. GINTCLR Register Field Descriptions.............................................................................................................. 3795
Table 32-18. GINTFRC Register Field Descriptions.............................................................................................................. 3796
Table 32-19. CLKDIV0_CTL0 Register Field Descriptions.................................................................................................... 3797
Table 32-20. CLKDIV0_CLKOFFSET Register Field Descriptions........................................................................................3798
Table 32-21. CLKDIV1_CTL0 Register Field Descriptions.................................................................................................... 3799

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Table 32-22. CLKDIV1_CLKOFFSET Register Field Descriptions........................................................................................3800

Table 32-23. SIGGEN0_CTL0 Register Field Descriptions................................................................................................... 3801
Table 32-24. SIGGEN0_CTL1 Register Field Descriptions................................................................................................... 3803
Table 32-25. SIGGEN0_DATA0 Register Field Descriptions................................................................................................. 3804
Table 32-26. SIGGEN0_DATA1 Register Field Descriptions................................................................................................. 3805
Table 32-27. SIGGEN0_DATA0_ACTIVE Register Field Descriptions.................................................................................. 3806
Table 32-28. SIGGEN0_DATA1_ACTIVE Register Field Descriptions.................................................................................. 3807
Table 32-29. REVISION Register Field Descriptions.............................................................................................................3808
Table 32-30. EPG_MUX_REGS Registers............................................................................................................................ 3809
Table 32-31. EPG_MUX_REGS Access Type Codes........................................................................................................... 3809
Table 32-32. EPGMXSEL0 Register Field Descriptions........................................................................................................ 3810
Table 32-33. EPGMXSELLOCK Register Field Descriptions................................................................................................ 3813
Table 32-34. EPGMXSELCOMMIT Register Field Descriptions............................................................................................3814

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www.ti.com Read This First

Preface
Read This First

About This Manual

This Technical Reference Manual (TRM) details the integration, the environment, the functional description, and
the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data sheet, rather a companion guide that can be used
alongside the device-specific data sheet to understand the details to program the device. The primary purpose
of the TRM is to abstract the programming details of the device from the data sheet. This allows the data sheet
to outline the high-level features of the device without unnecessary information about register descriptions or
programming models.

Note
Texas Instruments is transitioning to use more inclusive terminology. Some language may be different
than what you would expect to see for certain technology areas.

Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers can be shown with the suffix h or the prefix 0x. For example, the following number is
40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field
is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties with
default reset value below. A legend explains the notation used for the properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be avoided.
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments
For a complete listing of related documentation and development-support tools for these devices, visit the Texas
Instruments website at www.ti.com.
Additionally, the TMS320C28x DSP CPU and Instruction Set Reference Guide and the TMS320C28x Floating
Point Unit and Instruction Set Reference Guide must be used in conjunction with this TRM.
Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.

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Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Trademarks
TI E2E™, C2000™, Code Composer Studio™, and Texas Instruments™ are trademarks of Texas Instruments.
USB Specification Revision 2.0™ is a trademark of Compaq Computer Corp.
All trademarks are the property of their respective owners.

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www.ti.com C2000™ Microcontrollers Software Support

Chapter 1
C2000™ Microcontrollers Software Support

This chapter discusses the C2000Ware for the C2000™ microcontrollers. The C2000Ware can be downloaded
from: www.ti.com/tool/C2000WARE

1.1 Introduction.................................................................................................................................................................92
1.2 C2000Ware Structure................................................................................................................................................. 92
1.3 Documentation............................................................................................................................................................92
1.4 Devices........................................................................................................................................................................ 92
1.5 Libraries...................................................................................................................................................................... 92
1.6 Code Composer Studio™ Integrated Development Environment (IDE)................................................................92
1.7 SysConfig and PinMUX Tool......................................................................................................................................93

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1.1 Introduction
C2000Ware for the C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
C2000Ware can be downloaded from: www.ti.com/tool/C2000WARE
1.2 C2000Ware Structure
The C2000Ware software package is organized into the following directory structure as shown in Table 1-1.
Table 1-1. C2000Ware Root Directories
Directory Name Description
boards Contains the hardware design schematics, BOM, Gerber files, and documentation for C2000 controlCARDS.
device_support Contains all device-specific support files, bit field headers and device development user's guides.
docs Contains the C2000Ware package user's guides and the HTML index page of all package documentation.
driverlib Contains the device-specific driver library and driver-based peripheral examples.
libraries Contains the device-specific and core libraries.

1.3 Documentation
Within C2000Ware, there is an extensive amount of development documentation ranging from board design
documentation, to library user's guides, to driver API documentation. The "boards" directory contains all the
hardware design, BOM, Gerber files, and more for controlCARDs. To assist with locating the necessary
documentation, an HTML page is provided that contains a full list of all the documents in the C2000Ware
package. Locate this page in the "docs" directory.
1.4 Devices
C2000Ware contains the necessary software and documentation to jumpstart development for C2000™
microcontrollers. Each device includes device-specific common source files, peripheral example projects, bit
field headers, and if available, a device peripheral driver library. Additionally, documentation is provided for each
device on how to set up a CCS project, as well as give an overview of all the included example projects and
assist with troubleshooting. For devices with a driver library, documentation is also included that details all the
peripheral APIs available.
To learn more about C2000™ microcontrollers, visit: www.ti.com/c2000.
1.5 Libraries
The libraries included in C2000Ware range from fixed-point and floating-point math libraries, to specialized DSP
libraries, as well as calibration libraries. Each library includes documentation and examples, where applicable.
Additionally, the Flash API files and boot ROM source code are located in the "libraries" directory.
1.6 Code Composer Studio™ Integrated Development Environment (IDE)
Code Composer Studio™ is an integrated development environment (IDE) that supports TI's microcontroller and
embedded processors portfolio. The Code Composer Studio™ IDE comprises a suite of tools used to develop
and debug embedded applications. The latest version of Code Composer Studio™ IDE can be obtained at:
www.ti.com/ccstudio
All projects and examples in C2000Ware are built for and tested with the Code Composer Studio™ IDE.
Although the Code Composer Studio™ IDE is not included with the C2000Ware installer, Code Composer
Studio™ IDE is easily obtainable in a variety of versions.

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1.7 SysConfig and PinMUX Tool

To help simplify configuration challenges and accelerate software development, Texas Instruments™ created
SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring pins, peripherals,
subsystems, and other components. SysConfig helps you manage, expose, and resolve conflicts visually so that
you have more time to create differentiated applications.
The tool's output includes C header and code files that can be used with C2000Ware examples or used to
configure custom software.
The SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The
SysConfig tool is delivered integrated in the Code Composer Studio™ IDE, in the C2000Ware GPIO example,
as a standalone installer, or can be used by way of the cloud tools portal at: dev.ti.com

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Chapter 2
C28x Processor

This chapter contains a short description of the C28x processor and extended instruction sets.
Further information can be found in the following documents:
• TMS320C28x CPU and Instruction Set Reference Guide
• TMS320C28x Extended Instruction Sets Technical Reference Manual
• Accelerators: Enhancing the Capabilities of the C2000 MCU Family Technical Brief
• TMS320C28x FPU Primer Application Report

2.1 Introduction.................................................................................................................................................................95
2.2 C28X Related Collateral............................................................................................................................................. 95
2.3 Features.......................................................................................................................................................................95
2.4 Floating-Point Unit (FPU)...........................................................................................................................................96
2.5 Trigonometric Math Unit (TMU)................................................................................................................................. 96
2.6 VCRC Unit....................................................................................................................................................................97

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2.1 Introduction
The C28x CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing, reduced instruction set computing (RISC), microcontroller architectures, firmware, and tool sets.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
2.2 C28X Related Collateral

Foundational Materials
• C2000 Academy - C28x
• C2000 C28x Migration from COFF to EABI
• C2000 C28x Optimization Guide
• C2000 Performance Tips and Tricks
• C2000 Software Guide
• CGT Data Blocking C2000
• Enhancing the Computational Performance of the C2000™ Microcontroller Family Application Report

Getting Started Materials

• C2000 Multicore Development User Guide
• C2000 VCU, Viterbi, Complex Math, and CRC (Video)
• C2000Ware - CLAMath
• C2000Ware - FPU Fast RTS
• C2000Ware - FPU Library
• C2000Ware - Fast Integer Division
• C2000Ware - Fixed Point Library
• C2000Ware - IQMath
• C2000Ware - VCU Library
• C28x Context Save and Restore
• CRC Engines in C2000 Devices Application Report
• Migrating Software From 8-Bit (Byte) Addressable CPU's to C28x CPU Application Report
• TMS320C28x Extended Instruction Sets Application Report
• TMS320C28x FPU Primer Application Report

Expert Materials
• Fast Integer Division - A Differentiated Offering From C2000 Product Family Application Report
2.3 Features
The CPU features include a modified Harvard architecture and circular addressing. The RISC features
are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking,
and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while the CPU writes data simultaneously to
maintain the single-cycle instruction operation across the pipeline.

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2.4 Floating-Point Unit (FPU)

The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in
high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
2.5 Trigonometric Math Unit (TMU)
The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU by adding instructions and
leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic
operations listed in Table 2-1.
Table 2-1. TMU Supported Instructions
Instructions C Equivalent Operation Pipeline Cycles
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5

Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support computation
of floating-point power function for the nonlinear proportional integral derivative control (NLPID) component of
the C2000 Digital Control Library. These two added instructions reduce the power function calculations from a
typical of 300 cycles using library emulation to less than 10 cycles.
No changes have been made to existing instructions, pipeline, or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out the operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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2.6 VCRC Unit

Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. A CRC result register contains the current CRC, which is updated whenever a CRC instruction
is executed.
The following are the CRC polynomials used by the CRC calculation logic of VCRC:
• CRC8 polynomial = 0x07
• CRC16 polynomial1 = 0x8005
• CRC16 polynomial2 = 0x1021
• CRC24 polynomial = 0x5D 6DCB
• CRC32 polynomial1 = 0x04C1 1DB7
• CRC32 polynomial2 = 0x1EDC 6F41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24 and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to 3 cycles when using a custom polynomial.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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Chapter 3
System Control and Interrupts

The system-level functionality of this microcontroller configures the clocking, resets, and interrupts of the CPU
and peripherals, as well as the operation of the on-chip memories, timers, and security features.

3.1 Introduction.................................................................................................................................................................99
3.2 Power Management..................................................................................................................................................100
3.3 Device Identification and Configuration Registers............................................................................................... 100
3.4 Resets........................................................................................................................................................................100
3.5 Peripheral Interrupts................................................................................................................................................ 103
3.6 Exceptions and Non-Maskable Interrupts.............................................................................................................. 117
3.7 Clocking.....................................................................................................................................................................118
3.8 32-Bit CPU Timers 0/1/2........................................................................................................................................... 133
3.9 Watchdog Timer........................................................................................................................................................134
3.10 Low-Power Modes.................................................................................................................................................. 137
3.11 Memory Controller Module.................................................................................................................................... 140
3.12 JTAG........................................................................................................................................................................ 148
3.13 Live Firmware Update............................................................................................................................................ 148
3.14 System Control Register Configuration Restrictions......................................................................................... 153
3.15 Software.................................................................................................................................................................. 154
3.16 SYSCTRL Registers............................................................................................................................................... 178

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3.1 Introduction
System-level configuration is controlled by a group of submodules that are collectively referred to as the system
control module. The system control module provides the following capabilities:
• System-level resets, including power-on and brownout resets
• Clock source selection and PLL configuration
• Missing clock detection
• Clock-gating low-power modes
• Peripheral interrupt handling
• Non-maskable interrupts for certain fault conditions
• Three 32-bit timers
• Windowed watchdog timer, which can generate an interrupt or a reset
• RAM initialization, write protection, and controller control
• Flash memory ECC, wait state, and cache configuration
• Dual-zone code security module

3.1.1 SYSCTL Related Collateral

Foundational Materials
• C2000 MCU JTAG Connectivity Debug Application Report

Getting Started Materials

• C28x Interrupt Nesting
• Debugging JTAG
• Enhancing Device Security by Using JTAGLOCK Feature Application Report
• Interrupt FAQ for C2000
• XDS Target Connection Guide

Expert Materials
• C2000 CPU Memory Built-In Self-Test Application Report
• Live Firmware Update Without Device Reset on C2000 MCUs Application Report
• Programming of External Nonvolatile Memory Using SDFlash for TMS320C28x Devices Application Report
• Software Phased-Locked Loop (PLL) Design Using C2000 Microcontrollers Application Report
3.1.2 LOCK Protection on System Configuration Registers
Several system configuration registers are protected from spurious CPU writes by LOCK registers. Once these
associated LOCK register bits are set, the respective locked registers can no longer be modified by software.
See the register descriptions for details.
3.1.3 EALLOW Protection
Some registers in the system are protected from spurious CPU writes by the EALLOW protection mechanism.
This uses the special CPU instructions EALLOW and EDIS to enable and disable access to protected registers.
The current protection state is given by the EALLOW bit in the CPU ST1 register, as shown in Table 3-1.
Register protection is enabled by default at startup. While protected, all writes to protected registers by the CPU
are ignored. Only CPU reads, JTAG reads, and JTAG writes are allowed. If protection is disabled by executing
the EALLOW instruction, the CPU is allowed to write freely to protected registers. After modifying registers, the
registers can once again be protected by executing the EDIS instruction to clear the EALLOW bit.
Writes to the clock configuration and peripheral clock enable registers can be disabled until the next reset by
writing to special lock registers.

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Table 3-1. Access to EALLOW-Protected Registers

EALLOW Bit CPU Writes CPU Reads JTAG Writes JTAG Reads
0 Ignored Allowed(1) Allowed Allowed
1 Allowed Allowed Allowed Allowed

(1) The EALLOW bit is overridden by way of the JTAG port, allowing full access of protected registers during debug from the Code
Composer Studio™ IDE interface.

3.2 Power Management

The TMS320F28P55x MCU supports both internal generation of the 1.2V rail for single-supply operation or
externally supplied 1.2V into the device. The internal VREG is controlled using the VREGENZ pin: if enabled,
the 1.2V rail is generated by the device; if disabled, the 1.2V rail is supplied from an external source. For more
details, see TMS320F28P55x Real-Time Microcontrollers.
3.3 Device Identification and Configuration Registers
The device identification registers and configuration registers provide information on the part number, product
family, revision, pin count, qualification status, and feature availability of the device.
All of the device information is part of the DEV_CFG_REGS space. The identification registers are PARTIDL,
PARTIDH, and REVID.
A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
• UID_PSRAND0-4: 160 bits of pseudo-random data
• UID_UNIQUE: 64-bit unique data; the value in this register is unique across all devices in the same PARTIDH
• UID_CHECKSUM: 32-bit Fletcher checksum of UID_PSRAND0-4 and UID_UNIQUE and calculated as either
little-endian or big-endian during factory testing

3.4 Resets
This section explains the types and effects of the different resets on this device.
3.4.1 Reset Sources
Table 3-2 summarizes the various reset signals and the effect on the device.
Table 3-2. Reset Signals
Reset Source CPU Core Reset Peripherals JTAG / Debug IOs XRS Output
(C28x, FPU, VCU) Reset Logic Reset
POR Yes Yes Yes Hi-Z Yes
BOR Yes Yes Yes Hi-Z Yes
XRS Pin Yes Yes No Hi-Z -
WDRS Yes Yes No Hi-Z Yes
NMIWDRS Yes Yes No Hi-Z Yes
SYSRS (Debugger Reset) Yes Yes No Hi-Z No
SCCRESET Yes Yes No Hi-Z No
SIMRESET.XRS Yes Yes No Hi-Z Yes
SIMRESET.CPU1RS Yes Yes No Hi-Z No

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The resets can be divided into two groups:

• Chip-level resets (XRS, POR, BOR, WDRS, SIMRESET.XRS, and NMIWDRS), which reset all or almost all
of the device.
• System resets (SYSRS, SIMRESET.CPU1RS, and SCCRESET), which reset a large subset of the device but
maintain some system-level configuration.

After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register maintain
the state across multiple resets. The bits can only be cleared by a power-on reset (POR) or by writing ones to
the RESCCLR register. Some are cleared by the boot ROM as part of the start-up routines.
Many peripheral modules have individual resets accessible through the SOFTPRESx registers. For information
about a module's reset state, refer to the appropriate chapter for that module.
After any reset, the CPU begins execution from address 0x3FFFC0 (the reset vector), which is in the boot ROM.
After running the boot ROM code, the CPU typically branches to the start of the Flash memory at address
0x80000. For more information on controlling the boot process, see Chapter 4 .

Note
After a POR, the boot ROMs clear the M0/M1, LSx, GSx, and message RAMs to make sure that the
memories contain valid ECC or parity.

3.4.2 External Reset (XRS)

The external reset (XRS) is the main chip-level reset for the device and resets the CPU, all peripherals and I/O
pin configurations, and most of the system control registers. There is a dedicated open-drain pin for XRS. This
pin can be used to drive reset pins for other ICs in the application, and can be driven by an external source. The
XRS is driven internally during watchdog, NMI, and power-on resets.
The XRSn bit in the RESC register is set whenever XRS is driven low for any reason. This bit is then cleared by
the boot ROM.
3.4.3 Simulate External Reset (SIMRESET.XRS)
In some cases, the user can need to simulate the external reset (XRS) in software. This can be done using
software by setting XRSn bit to 1 in SIMRESET register. This toggles the XRS pin and resets the full device (just
like an external reset).
After this reset, the SIMRESET_XRSn and XRSn bits in the RESC register are set. Software can read these bits
to know the cause of reset and clear the status by writing a 1 into corresponding bits in RESCCLR register.
3.4.4 Power-On Reset (POR)
The power-on reset (POR) circuit creates a clean reset throughout the device during power-up, suppressing
glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most applications, XRS is held
low long enough to reset other system ICs, but some applications can require a longer pulse. In these cases,
the XRS pin can be driven low externally to provide the correct reset duration. A POR resets everything that
XRS does, along with a few other registers – the reset cause register (RESC), the NMI shadow flag register
(NMISHDFLG), and the X1 clock counter register (X1CNT). A POR also resets the debug logic used by the
JTAG port.
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.

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3.4.5 Brown-Out Reset (BOR)

The brown-out reset (BOR) is an internal supply voltage supervisor (SVS) circuit that monitors the VDDIO
supply for glitches or supply interruptions. If the VDDIO supply voltage drops below operational voltage range,
this circuit forces the XRSn pin low until the fault is removed and the supply voltage returns to the minimum
operational voltage. A BOR resets everything in the same manner as a POR reset.
The BOR circuit is enabled by default and is always active during power up or after any type of reset. To disable
the BOR circuit, set the BORLVMONDIS bit in the VMONCTL register.
3.4.6 Debugger Reset (SYSRS)
During development, it is sometimes necessary to reset the CPU and the peripherals without disconnecting the
debugger or disrupting the system-level configuration. To facilitate this, the CPU has a subsystem reset, which
can be triggered by a debugger using Code Composer Studio™ IDE. This reset (SYSRS) resets the CPU, the
peripherals, many system control registers (including the clock gating and LPM configuration), and all I/O pin
configurations.
The SYSRS does not reset the ICEPick debug module, the device capability registers, the clock source and PLL
configurations, the missing clock detection state, the PIE vector fetch error handler address, the NMI flags, the
analog trims, or anything reset only by a POR (see Section 3.4.4).
3.4.7 Simulate CPU Reset (SIMRESET)
In some cases, you can simulate the CPU reset (SYSRS) in software. This can be done by setting the CPU1RSn
bit to 1 in the SIMRESET register by CPU1 software. This toggles CPU1.SYSRS signals, resetting the CPU (just
like the debugger reset).
After this reset, the SIMRESET_CPU1RSn bit in the RESC register is set. Software can read this bit to know the
cause of the reset and clear the status by writing a 1 into the corresponding bit in the RESCCLR register.
3.4.8 Watchdog Reset (WDRS)
The device has a watchdog timer that can optionally trigger a reset if it is not serviced by the CPU within a
user-specified amount of time. This watchdog reset (WDRS) produces an XRS that lasts for 512 INTOSC1
cycles.
After a watchdog reset, the WDRSn and XRSn bits in RESC are set.
3.4.9 NMI Watchdog Reset (NMIWDRS)
The device has a non-maskable interrupt (NMI) module that detects hardware errors in the system. The NMI
module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a user-specified
amount of time. This NMI watchdog reset (NMIWDRS) produces an XRS that lasts for 512 INTOSC1 cycles.
After an NMI watchdog reset, the NMIWDRSn and XRSn bits in RESC are set.
3.4.10 DCSM Safe Code Copy Reset (SCCRESET)
The device has a dual-zone code security module (DCSM) that blocks read access to certain areas of the
Flash memory. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to securely
access those memory areas. To prevent security breaches, interrupts must be disabled before calling these
functions. If a vector fetch occurs in a safe copy or CRC function, the DCSM triggers a reset. This security reset
(SCCRESET) is similar to a SYSRS. However, the security reset also resets the debug logic to deny access to a
potential attacker.
After a security reset, the SCCRESETn bit in RESC is set.

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3.5 Peripheral Interrupts

This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered in
Section 3.6. Software interrupts and emulation interrupts are not covered in this chapter (see the TMS320C28x
CPU and Instruction Set Reference Guide).
3.5.1 Interrupt Concepts
An interrupt is a signal that causes the CPU to pause the current execution and branch to a different piece of
code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral events,
and involves less CPU overhead or program complexity than register polling. However, because interrupts are
asynchronous to the program flow, care must be taken to avoid conflicts over resources that are accessed both
in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the
interrupt until the interrupt is processed. The enable registers block the propagation of the interrupt. When an
interrupt signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the vector
table.
3.5.2 Interrupt Architecture
The C28x CPU has 14 peripheral interrupt lines. Two of the interrupts (INT13 and INT14) are connected directly
to CPU timers 1 and 2, respectively. The remaining 12 interrupts are connected to peripheral interrupt signals
through the enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened version). The PIE
multiplexes up to 16 peripheral interrupts into each CPU interrupt line and also expands the vector table to allow
each interrupt to have an ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages: the peripheral, the PIE, and the CPU. Each stage has enable
and flag registers. This system allows the CPU to handle one interrupt while others are pending, implement and
prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 3-1 shows the interrupt architecture for this device.
TINT0
TIMER0

LPM Logic LPMINT

WAKEINT
WDINT NMI module NMI
WD

INPUTXBAR4 XINT1 Control CPU

INPUTXBAR5 XINT2 Control
GPIO0 ePIE INT1
Input
to INPUTXBAR6 XINT3 Control to
X-BAR
GPIOx INT12
INPUTXBAR13 XINT4 Control
INPUTXBAR14 XINT5 Control

TIMER1 INT13

TIMER2 INT14
Peripherals
See ePIE Table

Figure 3-1. Device Interrupt Architecture

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3.5.2.1 Peripheral Stage

Each peripheral has a unique interrupt configuration, which is described in that peripheral's chapter. Some
peripherals allow multiple events to trigger the same interrupt signal. For example, a communications peripheral
can use the same interrupt to indicate that data has been received or that there has been a transmission error.
The cause of the interrupt can be determined by reading the peripheral's status register. Often, the bits in the
status register must be cleared manually before another interrupt is generated.
3.5.2.2 PIE Stage
The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which are
sometimes called PIE channels. These channels are grouped according to the associated CPU interrupt. Each
PIE group has one 8-bit enable register (PIEIERx), one 8-bit flag register (PIEIFRx) , and one bit in the PIE
acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt mask for the entire PIE
group.
When the CPU receives an interrupt, the CPU fetches the address of the ISR from the PIE. The PIE returns
the vector for the lowest-numbered channel in the group that is both flagged and enabled. This gives lower-
numbered interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition does not
happen unless software changes the state of the PIE while an interrupt is propagating. Section 3.5.4 contains
procedures for safely modifying the PIE configuration once interrupts have been enabled.
3.5.2.3 CPU Stage
Like the PIE, the CPU provides flag and enable register bits for each of the interrupts. There is one enable
register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global
interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared using
the CPU's SETC and CLRC instructions. In C code, C2000Ware's DINT and EINT macros can be used for this
purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is set, the next instruction in the pipeline
runs with interrupts disabled. No software delays are needed.

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3.5.3 Interrupt Entry Sequence

Figure 3-2 shows how peripheral interrupts propagate to the CPU.

Figure 3-2. Interrupt Propagation Path

When a peripheral generates an interrupt (on PIE group x, channel y), the interrupt triggers the following
sequence of events:
1. The interrupt is latched in PIEIFRx.y.
2. If PIEIERx.y is set, the interrupt propagates.
3. If PIEACK.x is clear, the interrupt propagates and PIEACK.x is set.
4. The interrupt is latched in IFR.x.
5. If IER.x is set, the interrupt propagates.
6. If INTM is clear, the CPU receives the interrupt.
7. Any instructions in the D2 or later stage of the pipeline are run to completion. Instructions in earlier stages
are flushed.
8. The CPU saves the context on the stack.
9. IFR.x and IER.x are cleared. INTM is set. EALLOW is cleared.
10. The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared.
11. The CPU branches to the ISR.

The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction entering
the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles. Wait states on the
ISR or stack memories add to the latency. External interrupts add a minimum of two SYSCLK cycles for GPIO
synchronization plus extra time for input qualification (if used). Loops created using the C28x RPT instruction
cannot be interrupted.

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3.5.4 Configuring and Using Interrupts

At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is set.
The application code is responsible for configuring and enabling all peripheral interrupts.
3.5.4.1 Enabling Interrupts
To enable a peripheral interrupt, perform the following steps:
1. Disable interrupts globally (DINT or SETC INTM).
2. Enable the PIE by setting the ENPIE bit of the PIECTRL register.
3. Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which can be found
in Section 3.5.8. Note that the vector table is EALLOW-protected.
4. Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments can be found in
Section 3.5.8.
5. Set the CPU IER bit for any PIE group containing enabled interrupts.
6. Enable the interrupt in the peripheral.
7. Enable interrupts globally (EINT or CLRC INTM).
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.
3.5.4.2 Handling Interrupts
ISRs are similar to normal functions, but must do the following:
1. Save and restore the state of certain CPU registers (if used).
2. Clear the PIEACK bit for the interrupt group.
3. Return using the IRET instruction.
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined
using the __interrupt keyword. For information on this keyword, see the Keywords section of the TMS320C28x
Optimizing C/C++ Compiler v6.2.4 User's Guide. For information on writing assembly code to handle interrupts,
see the Standard Operation for Maskable Interrupts section of the TMS320C28x CPU and Instruction Set
Reference Guide.
The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at the end
of the ISR. If the PIEACK bit is not cleared, the CPU does not receive any further interrupts from that group. This
does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.
3.5.4.3 Disabling Interrupts
To disable all interrupts, set the CPUs global interrupt mask using DINT or SETC INTM. It is not necessary to
add NOPs after setting INTM or modifying IER – the next instruction executes with interrupts disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, the interrupt signal
can reach the CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
1. Disable interrupts globally (DINT or SETC INTM).
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
6. Enable interrupts globally (EINT or CLRC INTM).
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no special
procedure is needed.

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The PIEIFR bits must never be cleared in software since the read/modify/write operation can cause incoming
interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The following
procedure can be used to bypass the normal ISR:
1. Disable interrupts globally (DINT or SETC INTM).
2. Modify the PIE vector table to map the PIEIFR bit's interrupt vector to an empty ISR. This ISR only contains
a return from interrupt instruction (IRET).
3. Disable the interrupt in the peripheral registers.
4. Enable interrupts globally (EINT or CLRC INTM).
5. Wait for the pending interrupt to be serviced by the empty ISR.
6. Disable interrupts globally.
7. Modify the PIE vector table to map the interrupt vector back to the original ISR.
8. Clear the PIEACK bit for the interrupt's PIE group.
9. Enable interrupts globally.

3.5.4.4 Nesting Interrupts

By default, interrupts do not nest. It is possible to nest and prioritize interrupts using software control of the
IER and PIEIERx registers. Example code can be found in C2000Ware and documentation is available at
software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html.
3.5.4.5 Vector Address Validity Check
The ePIE vector table memory is protected using a parity check. Upon each vector fetch from the ePIE, a parity
check is performed. If a parity failure occurs during vector fetch, the ePIE returns either a user defined error
handler routine (if PIEVERRADDR is defined with a non 0x003FFFFF value), or the default boot ROM handler at
address 0x3FFFBE. The ePIE also sends trip signals to the EPWMs.
The parity check only returns the error handler value if the failure occurs during vector fetch. Parity errors
during data read is handled by the memory controller module and logged by UCERRFLG register in
MEMORY_ERROR_REGS. The address that caused the error is located in the UCCPUREADDR register. If
the error address logged is between 0xD00 to 0xDFF, then the error is a PIE parity error. Additionally, a parity
error during vector fetch does not flag an uncorrectable error NMI.

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3.5.5 PIE Channel Mapping

Table 3-3 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a group, and each column is a channel within that
group. When multiple interrupts are pending, the lowest-numbered channel is the lowest-numbered group is serviced first. Thus, the interrupts at the top
of the table have the highest priority, and the interrupts at the bottom have the lowest priority.

Note
Cells that are empty are Reserved.

Table 3-3. PIE Channel Mapping

INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 INTx.9 INTx.10 INTx.11 INTx.12 INTx.13 INTx.14 INTx.15 INTx.16
SYS_ER
INT1.y ADCA1 ADCB1 ADCC1 XINT1 XINT2 TIMER0 WAKE ADCD1 ADCE1
R
EPWM1 EPWM2_ EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10_ EPWM11_ EPWM12_
INT2.y
_TZ TZ _TZ _TZ _TZ _TZ _TZ _TZ _TZ TZ TZ TZ
INT3.y EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10 EPWM11 EPWM12
INT4.y ECAP1 ECAP2
INT5.y EQEP1 EQEP2 EQEP3 CLB1 CLB2
SPIA_R SPIB_R
INT6.y SPIA_TX SPIB_TX DCC0 DCC1
X X
DMA_C DMA_CH DMA_C DMA_C DMA_C DMA_C PMBUS FSITXA_I FSITXA_I FSIRXA_I FSIRXA_I
INT7.y
H1 2 H3 H4 H5 H6 A NT1 NT2 NT1 NT2
I2CA_FI I2CB_FI SCIC_R SCIC_T
INT8.y I2CA I2CB LINA_0 LINA_1
FO FO X X
MCANBS
MCANBS
SCIA_R SCIB_R MCANA MCANA MCANB MCANBS S_WAKE_
INT9.y SCIA_TX SCIB_TX S_ECC_C USB NPU
X X SS0 SS1 SS0 S1 AND_TS_
ORR_PLS
PLS
ADCA_E ADCB_E ADCC_E ADCD_EV
INT10.y ADCA2 ADCA3 ADCA4 ADCB2 ADCB3 ADCB4 ADCC2 ADCC3 ADCC4 ADCD2 ADCD3 ADCD4
VT VT VT T
ADCE_E
INT11.y CLA1_1 CLA1_2 CLA1_3 CLA1_4 CLA1_5 CLA1_6 CLA1_7 CLA1_8 ADCE2 ADCE3 ADCE4
VT
MCANA MCANA
FLSS_IN SS_WAK SS_ECC
INT12.y XINT3 XINT4 XINT5 AES_INT
T E_AND_ _CORR_
TS_PLS PLS

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3.5.6 PIE Interrupt Priority

3.5.6.1 Channel Priority
For every PIE group, the low number channels in the group have the highest priority. For instance in PIE group
1, channel 1.1 has priority over channel 1.3. If those two enabled interrupts occurred simultaneously, channel
1.1 is serviced first with channel 1.3 left pending. Once the ISR for channel 1.1 completes and provided there
are no other enabled and pending interrupts for PIE group 1, channel 1.3 is serviced. However, for the CPU to
service any more interrupts from a PIE group, PIEACK for the group must be cleared. For this specific example,
for channel 1.3 to be serviced, channel 1.1’s ISR has to clear PIEACK for group 1.
The following example describes an alternative scenario: channel 1.1 is currently being serviced by the CPU,
channel 1.3 is pending and before channel 1.1’s ISR completes, channel 1.2 that is enabled also comes in.
Since channel 1.2 has a higher priority than channel 1.3, the CPU services channel 1.2 and channel 1.3 is
still left pending. Using the steps from the Interrupt Entry Sequence (Section 3.5.3), channel 1.2 interrupt can
happen as late as step 10 (the CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared) and the channel
is still serviced ahead of channel 1.3.
3.5.6.2 Group Priority
Generally, the lowest channel in the lowest PIE group has the highest priority. An example of this is channels
1.1 and 2.1. Those two channels have the highest priority in the respective groups. If the interrupts for those two
enabled channels happened simultaneously and provided there are no other enabled and pending interrupts,
channel 1.1 is serviced first by the CPU with channel 2.1 left pending.
However, there are cases where channel priority supersedes group priority. This special case happens
depending on which step the CPU is currently at in the Interrupt Entry Sequence (Section 3.5.3).
The following illustrates an example of this special case.
The CPU is about to service channel 2.3 and is currently going through the steps in the Interrupt Entry Sequence
(Section 3.5.3).
1. As the CPU reaches step 10 (the CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared), two
enabled interrupts: channel 1.1 and channel 2.1 come in.
2. Due to channel priority, channel 2.1 is serviced ahead of channel 2.3. However, group priority dictates that
channel 1.1 be serviced ahead of channels 2.1 and 2.3.
3. Channel priority supersedes here and channel 2.1 is serviced ahead of channels 1.1 and 2.3.
4. After channel 2.1 completes, channel 1.1 is serviced followed by channel 2.3.
Group priority is only specified if no interrupts are currently being serviced, that is, the Interrupt Entry Sequence
(Section 3.5.3) is not executing.

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3.5.7 System Error

SYS_ERR consolidate several sources of interrupts (see Figure 3-3). These sources set the respective bit in
the SYS_ERR_INT_FLG register. Any set bit in the SYS_ERR_INT_FLG register also sets the global interrupt
(GINT) bit. The GINT bit has to be cleared before any SYS_ERR interrupt is generated. If the GINT bit is cleared
with the source flags still set, another SYS_ERR interrupt is fired; therefore, it is recommended to clear the
source flags before clearing the GINT bit.

Figure 3-3. System Error

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3.5.8 Vector Tables

Table 3-4 shows the CPU interrupt vector table. The vectors for INT1–INT12 are not used in this device. The
reset vector is fetched from the boot ROM instead of from this table. All vectors are EALLOW-protected.
Table 3-5 shows the PIE vector table.
Table 3-4. CPU Interrupt Vectors
Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
Reset 0 0x0000 0D00 2 Reset is always fetched from location 1 (Highest) -
0x003F_FFC0 in Boot ROM
INT1 1 0x0000 0D02 2 Not used. See PIE Group 1 5 -
INT2 2 0x0000 0D04 2 Not used. See PIE Group 2 6 -
INT3 3 0x0000 0D06 2 Not used. See PIE Group 3 7 -
INT4 4 0x0000 0D08 2 Not used. See PIE Group 4 8 -
INT5 5 0x0000 0D0A 2 Not used. See PIE Group 5 9 -
INT6 6 0x0000 0D0C 2 Not used. See PIE Group 6 10 -
INT7 7 0x0000 0D0E 2 Not used. See PIE Group 7 11 -
INT8 8 0x0000 0D10 2 Not used. See PIE Group 8 12 -
INT9 9 0x0000 0D12 2 Not used. See PIE Group 9 13 -
INT10 10 0x0000 0D14 2 Not used. See PIE Group 10 14 -
INT11 11 0x0000 0D16 2 Not used. See PIE Group 11 15 -
INT12 12 0x0000 0D18 2 Not used. See PIE Group 12 16 -
INT13 13 0x0000 0D1A 2 CPU TIMER1 Interrupt 17 -
INT14 14 0x0000 0D1C 2 CPU TIMER2 Interrupt 18 -
DATALOG 15 0x0000 0D1E 2 CPU Data Logging Interrupt 19 (lowest) -
RTOSINT 16 0x0000 0D20 2 CPU Real-Time OS Interrupt 4 -
RSVD 17 0x0000 0D22 2 Reserved 2 -
NMI 18 0x0000 0D24 2 Non-Maskable Interrupt 3 -
ILLEGAL 19 0x0000 0D26 2 Illegal Instruction (ITRAP) - -
USER 1 20 0x0000 0D28 2 User-Defined Trap - -
USER 2 21 0x0000 0D2A 2 User-Defined Trap - -
USER 3 22 0x0000 0D2C 2 User-Defined Trap - -
USER 4 23 0x0000 0D2E 2 User-Defined Trap - -
USER 5 24 0x0000 0D30 2 User-Defined Trap - -
USER 6 25 0x0000 0D32 2 User-Defined Trap - -
USER 7 26 0x0000 0D34 2 User-Defined Trap - -
USER 8 27 0x0000 0D36 2 User-Defined Trap - -
USER 9 28 0x0000 0D38 2 User-Defined Trap - -
USER 10 29 0x0000 0D3A 2 User-Defined Trap - -
USER 11 30 0x0000 0D3C 2 User-Defined Trap - -
USER 12 31 0x0000 0D3E 2 User-Defined Trap - -

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Table 3-5. PIE Interrupt Vectors

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
PIE Group 1 Vectors - Muxed into CPU INT1
INT1.1 32 0x0000 0D40 2 ADCA1 interrupt 5 1 (Highest)
INT1.2 33 0x0000 0D42 2 ADCB1 interrupt 5 2
INT1.3 34 0x0000 0D44 2 ADCC1 interrupt 5 3
INT1.4 35 0x0000 0D46 2 XINT1 interrupt 5 4
INT1.5 36 0x0000 0D48 2 XINT2 interrupt 5 5
INT1.6 37 0x0000 0D4A 2 SYS_ERR interrupt 5 6
INT1.7 38 0x0000 0D4C 2 TIMER0 interrupt 5 7
INT1.8 39 0x0000 0D4E 2 WAKE interrupt 5 8
INT1.9 128 0x0000 0E00 2 ADCD1 interrupt 5 9
INT1.10 129 0x0000 0E02 2 ADCE1 interrupt 5 10
INT1.11 130 0x0000 0E04 2 Reserved 5 11
INT1.12 131 0x0000 0E06 2 Reserved 5 12
INT1.13 132 0x0000 0E08 2 Reserved 5 13
INT1.14 133 0x0000 0E0A 2 Reserved 5 14
INT1.15 134 0x0000 0E0C 2 Reserved 5 15
INT1.16 135 0x0000 0E0E 2 Reserved 5 16 (Lowest)
PIE Group 2 Vectors - Muxed into CPU INT2
INT2.1 40 0x0000 0D50 2 EPWM1 trip zone interrupt 6 1 (Highest)
INT2.2 41 0x0000 0D52 2 EPWM2 trip zone interrupt 6 2
INT2.3 42 0x0000 0D54 2 EPWM3 trip zone interrupt 6 3
INT2.4 43 0x0000 0D56 2 EPWM4 trip zone interrupt 6 4
INT2.5 44 0x0000 0D58 2 EPWM5 trip zone interrupt 6 5
INT2.6 45 0x0000 0D5A 2 EPWM6 trip zone interrupt 6 6
INT2.7 46 0x0000 0D5C 2 EPWM7 trip zone interrupt 6 7
INT2.8 47 0x0000 0D5E 2 EPWM8 trip zone interrupt 6 8
INT2.9 136 0x0000 0E10 2 EPWM9 trip zone interrupt 6 9
INT2.10 137 0x0000 0E12 2 EPWM10 trip zone interrupt 6 10
INT2.11 138 0x0000 0E14 2 EPWM11 trip zone interrupt 6 11
INT2.12 139 0x0000 0E16 2 EPWM12 trip zone interrupt 6 12
INT2.13 140 0x0000 0E18 2 Reserved 6 13
INT2.14 141 0x0000 0E1A 2 Reserved 6 14
INT2.15 142 0x0000 0E1C 2 Reserved 6 15
INT2.16 143 0x0000 0E1E 2 Reserved 6 16 (Lowest)
PIE Group 3 Vectors - Muxed into CPU INT3
INT3.1 48 0x0000 0D60 2 EPWM1 interrupt 7 1 (Highest)
INT3.2 49 0x0000 0D62 2 EPWM2 interrupt 7 2
INT3.3 50 0x0000 0D64 2 EPWM3 interrupt 7 3
INT3.4 51 0x0000 0D66 2 EPWM4 interrupt 7 4
INT3.5 52 0x0000 0D68 2 EPWM5 interrupt 7 5
INT3.6 53 0x0000 0D6A 2 EPWM6 interrupt 7 6
INT3.7 54 0x0000 0D6C 2 EPWM7 interrupt 7 7
INT3.8 55 0x0000 0D6E 2 EPWM8 interrupt 7 8
INT3.9 144 0x0000 0E20 2 EPWM9 interrupt 7 9

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
INT3.10 145 0x0000 0E22 2 EPWM10 interrupt 7 10
INT3.11 146 0x0000 0E24 2 EPWM11 interrupt 7 11
INT3.12 147 0x0000 0E26 2 EPWM12 interrupt 7 12
INT3.13 148 0x0000 0E28 2 Reserved 7 13
INT3.14 149 0x0000 0E2A 2 Reserved 7 14
INT3.15 150 0x0000 0E2C 2 Reserved 7 15
INT3.16 151 0x0000 0E2E 2 Reserved 7 16 (Lowest)
PIE Group 4 Vectors - Muxed into CPU INT4
INT4.1 56 0x0000 0D70 2 ECAP1 interrupt 8 1 (Highest)
INT4.2 57 0x0000 0D72 2 ECAP2 interrupt 8 2
INT4.3 58 0x0000 0D74 2 Reserved 8 3
INT4.4 59 0x0000 0D76 2 Reserved 8 4
INT4.5 60 0x0000 0D78 2 Reserved 8 5
INT4.6 61 0x0000 0D7A 2 Reserved 8 6
INT4.7 62 0x0000 0D7C 2 Reserved 8 7
INT4.8 63 0x0000 0D7E 2 Reserved 8 8
INT4.9 152 0x0000 0E30 2 Reserved 8 9
INT4.10 153 0x0000 0E32 2 Reserved 8 10
INT4.11 154 0x0000 0E34 2 Reserved 8 11
INT4.12 155 0x0000 0E36 2 Reserved 8 12
INT4.13 156 0x0000 0E38 2 Reserved 8 13
INT4.14 157 0x0000 0E3A 2 Reserved 8 14
INT4.15 158 0x0000 0E3C 2 Reserved 8 15
INT4.16 159 0x0000 0E3E 2 Reserved 8 16 (Lowest)
PIE Group 5 Vectors - Muxed into CPU INT5
INT5.1 64 0x0000 0D80 2 EQEP1 interrupt 9 1 (Highest)
INT5.2 65 0x0000 0D82 2 EQEP2 interrupt 9 2
INT5.3 66 0x0000 0D84 2 EQEP3 interrupt 9 3
INT5.4 67 0x0000 0D86 2 Reserved 9 4
INT5.5 68 0x0000 0D88 2 CLB1 interrupt 9 5
INT5.6 69 0x0000 0D8A 2 CLB2 interrupt 9 6
INT5.7 70 0x0000 0D8C 2 Reserved 9 7
INT5.8 71 0x0000 0D8E 2 Reserved 9 8
INT5.9 160 0x0000 0E40 2 Reserved 9 9
INT5.10 161 0x0000 0E42 2 Reserved 9 10
INT5.11 162 0x0000 0E44 2 Reserved 9 11
INT5.12 163 0x0000 0E46 2 Reserved 9 12
INT5.13 164 0x0000 0E48 2 Reserved 9 13
INT5.14 165 0x0000 0E4A 2 Reserved 9 14
INT5.15 166 0x0000 0E4C 2 Reserved 9 15
INT5.16 167 0x0000 0E4E 2 Reserved 9 16 (Lowest)

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
PIE Group 6 Vectors - Muxed into CPU INT6
INT6.1 72 0x0000 0D90 2 SPIA RX interrupt 10 1 (Highest)
INT6.2 73 0x0000 0D92 2 SPIA TX interrupt 10 2
INT6.3 74 0x0000 0D94 2 SPIB RX interrupt 10 3
INT6.4 75 0x0000 0D96 2 SPIB TX interrupt 10 4
INT6.5 76 0x0000 0D98 2 Reserved 10 5
INT6.6 77 0x0000 0D9A 2 Reserved 10 6
INT6.7 78 0x0000 0D9C 2 DCC0 interrupt 10 7
INT6.8 79 0x0000 0D9E 2 DCC1 interrupt 10 8
INT6.9 168 0x0000 0E50 2 Reserved 10 9
INT6.10 169 0x0000 0E52 2 Reserved 10 10
INT6.11 170 0x0000 0E54 2 Reserved 10 11
INT6.12 171 0x0000 0E56 2 Reserved 10 12
INT6.13 172 0x0000 0E58 2 Reserved 10 13
INT6.14 173 0x0000 0E5A 2 Reserved 10 14
INT6.15 174 0x0000 0E5C 2 Reserved 10 15
INT6.16 175 0x0000 0E5E 2 Reserved 10 16 (Lowest)
PIE Group 7 Vectors - Muxed into CPU INT7
INT7.1 80 0x0000 0DA0 2 DMA CH1 Interrupt 11 1 (Highest)
INT7.2 81 0x0000 0DA2 2 DMA CH2 Interrupt 11 2
INT7.3 82 0x0000 0DA4 2 DMA CH3 Interrupt 11 3
INT7.4 83 0x0000 0DA6 2 DMA CH4 Interrupt 11 4
INT7.5 84 0x0000 0DA8 2 DMA CH5 Interrupt 11 5
INT7.6 85 0x0000 0DAA 2 DMA CH6 Interrupt 11 6
INT7.7 86 0x0000 0DAC 2 PMBUSA 11 7
INT7.8 87 0x0000 0DAE 2 Reserved 11 8
INT7.9 176 0x0000 0E60 2 Reserved 11 9
INT7.10 177 0x0000 0E62 2 Reserved 11 10
INT7.11 178 0x0000 0E64 2 FSITX INT1 Interrupt 11 11
INT7.12 179 0x0000 0E66 2 FSITX INT2 Interrupt 11 12
INT7.13 180 0x0000 0E68 2 FSIRX INT1 Interrupt 11 13
INT7.14 181 0x0000 0E6A 2 FSIRX INT2 Interrupt 11 14
INT7.15 182 0x0000 0E6C 2 Reserved 11 15
INT7.16 183 0x0000 0E6E 2 Reserved 11 16 (Lowest)
PIE Group 8 Vectors - Muxed into CPU INT8
INT8.1 88 0x0000 0DB0 2 I2CA interrupt 12 1 (Highest)
INT8.2 89 0x0000 0DB2 2 I2CA FIFO interrupt 12 2
INT8.3 90 0x0000 0DB4 2 I2CB interrupt 12 3
INT8.4 91 0x0000 0DB6 2 I2CB FIFO interrupt 12 4
INT8.5 92 0x0000 0DB8 2 SCIC RX interrupt 12 5
INT8.6 93 0x0000 0DBA 2 SCIC TX interrupt 12 6
INT8.7 94 0x0000 0DBC 2 Reserved 12 7
INT8.8 95 0x0000 0DBE 2 Reserved 12 8
INT8.9 184 0x0000 0E70 2 LINA INT1 Interrupt 12 9

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
INT8.10 185 0x0000 0E72 2 LINA INT2 Interrupt 12 10
INT8.11 186 0x0000 0E74 2 Reserved 12 11
INT8.12 187 0x0000 0E76 2 Reserved 12 12
INT8.13 188 0x0000 0E78 2 Reserved 12 13
INT8.14 189 0x0000 0E7A 2 Reserved 12 14
INT8.15 190 0x0000 0E7C 2 Reserved 12 15
INT8.16 191 0x0000 0E7E 2 Reserved 12 16 (Lowest)
PIE Group 9 Vectors - Muxed into CPU INT9
INT9.1 96 0x0000 0DC0 2 SCIA RX interrupt 13 1 (Highest)
INT9.2 97 0x0000 0DC2 2 SCIA TX interrupt 13 2
INT9.3 98 0x0000 0DC4 2 SCIB RX interrupt 13 3
INT9.4 99 0x0000 0DC6 2 SCIB TX interrupt 13 4
INT9.5 100 0x0000 0DC8 2 Reserved 13 5
INT9.6 101 0x0000 0DCA 2 Reserved 13 6
INT9.7 102 0x0000 0DCC 2 MCANA INT0 interrupt 13 7
INT9.8 103 0x0000 0DCE 2 MCANA INT1 interrupt 13 8
INT9.9 192 0x0000 0E80 2 MCANB INT0 interrupt 13 9
INT9.10 193 0x0000 0E82 2 MCANB INT1 interrupt 13 10
INT9.11 194 0x0000 0E84 2 MCANB ECC interrupt 13 11
INT9.12 195 0x0000 0E86 2 MCANB WAKE interrupt 13 12
INT9.13 196 0x0000 0E88 2 Reserved 13 13
INT9.14 197 0x0000 0E8A 2 Reserved 13 14
INT9.15 198 0x0000 0E8C 2 USB Interrupt 13 15
INT9.16 199 0x0000 0E8E 2 NPU Interrupt 13 16 (Lowest)
PIE Group 10 Vectors - Muxed into CPU INT10
INT10.1 104 0x0000 0DD0 2 ADCA event interrupt 14 1 (Highest)
INT10.2 105 0x0000 0DD2 2 ADCA2 interrupt 14 2
INT10.3 106 0x0000 0DD4 2 ADCA3 interrupt 14 3
INT10.4 107 0x0000 0DD6 2 ADCA4 interrupt 14 4
INT10.5 108 0x0000 0DD8 2 ADCB event interrupt 14 5
INT10.6 109 0x0000 0DDA 2 ADCB2 interrupt 14 6
INT10.7 110 0x0000 0DDC 2 ADCB3 interrupt 14 7
INT10.8 111 0x0000 0DDE 2 ADCB4 interrupt 14 8
INT10.9 200 0x0000 0E90 2 ADCC event interrupt 14 9
INT10.10 201 0x0000 0E92 2 ADCC2 interrupt 14 10
INT10.11 202 0x0000 0E94 2 ADCC3 interrupt 14 11
INT10.12 203 0x0000 0E96 2 ADCC4 interrupt 14 12
INT10.13 204 0x0000 0E98 2 ADCD event interrupt 14 13
INT10.14 205 0x0000 0E9A 2 ADCD2 interrupt 14 14
INT10.15 206 0x0000 0E9C 2 ADCD3 interrupt 14 15
INT10.16 207 0x0000 0E9E 2 ADCD4 interrupt 14 16 (Lowest)

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
priority
PIE Group 11 Vectors - Muxed into CPU INT11
INT11.1 112 0x0000 0DE0 2 CLA_1 interrupt 15 1 (Highest)
INT11.2 113 0x0000 0DE2 2 CLA_2 interrupt 15 2
INT11.3 114 0x0000 0DE4 2 CLA_3 interrupt 15 3
INT11.4 115 0x0000 0DE6 2 CLA_4 interrupt 15 4
INT11.5 116 0x0000 0DE8 2 CLA_5 interrupt 15 5
INT11.6 117 0x0000 0DEA 2 CLA_6 interrupt 15 6
INT11.7 118 0x0000 0DEC 2 CLA_7 interrupt 15 7
INT11.8 119 0x0000 0DEE 2 CLA_8 interrupt 15 8
INT11.9 208 0x0000 0EA0 2 ADCE event interrupt 15 9
INT11.10 209 0x0000 0EA2 2 ADCE2 interrupt 15 10
INT11.11 210 0x0000 0EA4 2 ADCE3 interrupt 15 11
INT11.12 211 0x0000 0EA6 2 ADCE4 interrupt 15 12
INT11.13 212 0x0000 0EA8 2 Reserved 15 13
INT11.14 213 0x0000 0EAA 2 Reserved 15 14
INT11.15 214 0x0000 0EAC 2 Reserved 15 15
INT11.16 215 0x0000 0EAE 2 Reserved 15 16 (Lowest)
PIE Group 12 Vectors - Muxed into CPU INT12
INT12.1 120 0x0000 0DF0 2 XINT3 interrupt 16 1 (Highest)
INT12.2 121 0x0000 0DF2 2 XINT4 interrupt 16 2
INT12.3 122 0x0000 0DF4 2 XINT5 interrupt 16 3
INT12.4 123 0x0000 0DF6 2 Reserved 16 4
INT12.5 124 0x0000 0DF8 2 FLSS_INT interrupt 16 5
INT12.6 125 0x0000 0DFA 2 VCRC 16 6
INT12.7 126 0x0000 0DFC 2 MCANA ECC interrupt 16 7
INT12.8 127 0x0000 0DFE 2 MCANA WAKE interrupt 16 8
INT12.9 216 0x0000 0EB0 2 Reserved 16 9
INT12.10 217 0x0000 0EB2 2 Reserved 16 10
INT12.11 218 0x0000 0EB4 2 Reserved 16 11
INT12.12 219 0x0000 0EB6 2 Reserved 16 12
INT12.13 220 0x0000 0EB8 2 AES Interrupt 16 13
INT12.14 221 0x0000 0EBA 2 Reserved 16 14
INT12.15 222 0x0000 0EBC 2 Reserved 16 15
INT12.16 223 0x0000 0EBE 2 Reserved 16 16 (Lowest)

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3.6 Exceptions and Non-Maskable Interrupts

This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The
interrupt allows the application to respond to the error.
3.6.1 Configuring and Using NMIs
An incoming NMI sets a status bit in the NMIFLG register and starts the NMI watchdog counter. This counter is
clocked by the SYSCLK, and if the count reaches the value in the NMIWDPRD register, the counter triggers an
NMI watchdog reset (NMIWDRS). To prevent this, the NMI handler must clear the flag bit using the NMIFLGCLR
register. Once all flag bits are clear, the NMIINT bit in the NMIFLG register can also be cleared to allow future
NMIs to be taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI handler
vector must be written to the PIE vector table.
3.6.2 Emulation Considerations
The NMI watchdog counter behaves as follows under debug conditions:

CPU Suspended When the CPU is suspended, the NMI watchdog counter is suspended.
Run-Free Mode When the CPU is placed in run-free mode, the NMI watchdog counter
resumes operation as normal.
Real-Time Single-Step Mode When the CPU is in real-time single-step mode, the NMI watchdog
counter is suspended. The counter remains suspended even within real-
time interrupts.
Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the NMI watchdog counter
operates as normal.

3.6.3 NMI Sources

There are several types of hardware errors that can trigger an NMI. Additional information about the error is
usually available from the module that detects it.
3.6.3.1 Missing Clock Detection
The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is
bypassed, OSCCLK is connected to INTOSC1, and an NMI is fired to the CPU. For more information on missing
clock detection, see Section 3.7.12.1.
3.6.3.2 RAM Uncorrectable Error
A single-bit parity error, double-bit ECC data error, or single-bit ECC address error in a RAM read triggers an
NMI. This applies to CPU and DMA reads. Single-bit ECC data errors do not trigger an NMI, but can optionally
trigger a normal peripheral interrupt. For more information on RAM error detection, see Section 3.11.1.9.
3.6.3.3 Flash Uncorrectable ECC Error
A double-bit ECC data error or single-bit ECC address error in a Flash read triggers an NMI. Single-bit ECC data
errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt.
3.6.3.4 Software-Forced Error
There is a special NMI source that can only be triggered by writing to the SWERR bit in the NMIFLGFRC
register. Since the SWERR flag is never set by a real hardware fail, it can be used to implement a self-test mode
for the NMI subsystem.

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3.6.3.5 ERAD NMI

The ERAD module can generate NMI based on different events. This is configurable in the GLBL_NMI_CTL
register.
3.6.4 Illegal Instruction Trap (ITRAP)
If the CPU tries to execute an illegal instruction, the CPU generates a special interrupt called an illegal
instruction trap (ITRAP). This interrupt is non-maskable and has a vector in the PIE vector table. For more
information about ITRAPs, see the Illegal-Instruction Trap section of the TMS320C28x DSP CPU and Instruction
Set Reference Guide.

Note
A RAM fetch access violation triggers an ITRAP in addition to the normal peripheral interrupt for RAM
access violations. The CPU handles the ITRAP first.

3.6.5 ERRORSTS Pin

The ERRORSTS pin is an ‘always output’ pin and remains high until an error is detected inside the chip. On
an error, the ERRORSTS pin goes low (default polarity) until the corresponding internal error status flag for that
error source is cleared. Figure 3-4 shows the functionality of the ERRORSTS pin.
The ERRORSTS pin is tri-stated until the chip power rails ramp up to the lower operational limit. As the
ERRORSTS pin is an active-low pin (default polarity), users who care about the state of this pin during power-up
can connect an external pull-down on this pin.
Following enhancement has been made on this device for ERRORSTS pin logic:
• Polarity of Error pin has been made configurable through the ERRORCTL register (default setting is active-
low polarity).
• To enable testing of the Error pin, capability to force and clear the Error pin from software has been provided.
• Additional sources of Error have been added to ERRORSTS:
– CPU1 Watchdog reset
– Error on a PIE vector fetch
CPU1's NMI Shadow flags
(Cleared by PORn or Software)

NMISHDFLG.Bit-0
PGIO
NMISHDFLG.Bit-1
3.3 1.2 IN (not used)
ERROR
3.3 1.2 ERR
Edge
STS
detect
REG

‘0’
NMISHDFLG.Bit-15
(Always
Output)

PGIO_33
(from PMM)

Figure 3-4. ERRORSTS Pin Diagram

3.7 Clocking
This section explains the clock sources and clock domains on this device, and how to configure them for
application use. Figure 3-5 and Figure 3-6 provide an overview of the device's clocking system.

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WDCLK Watchdog
Timer
PERCLKDIVSEL.USBCLKDIV

/1 CLBCLKCTL
/2
. SYSCLK
USBBITCLK
.
.
/8 CLB_TILE_CLK
/1 /1 or /2
PLLCLK
/2
.
.
CLB_REG_CLK
.
SYSCLKDIVSEL /8
SYSCLK
SYS PLLSYSCLK
Divider NMIWD
INTOSC1 SYSPLL PLLRAWCLK

INTOSC2 OSCCLK
PLLCLKEN
X1 (XTAL)

OSCCLKRCSEL CPUCLK
CPU FPU
TMU

GSx RAMs
Boot ROM CLA ROM LSx RAMs
SYSCLK SYSCLK ePIE DCSM Mx RAMs
FLASH XINT Message RAM
GPIO WD System Control
KDIV

Flash Wrapper Clock FLCLK

Flash Wrapper
Divider

One per SYSCLK peripheral

ADC
CLA AES
PCLKCRx CMPSS
CPUTIMERs CLB
PERx.SYSCLK GPDAC
EPWM ERAD
PGA
ECAP EPG
DCC
EQEP FSI
PMBUS
HRCAL I2C
USB
One per SYSCLK peripheral
LSPCLKDIV
PCLKCRx
LSP LSPCLK PERx.LSPCLK SCI
Divider SPI

One per SYSCLK peripheral

LINACLKDIV PLLRAWCLK LIN Xmit
PCLKCRx Clock Gen
PERx.LINACLK
LIN Clock LINACLK LIN
Divider

One per SYSCLK peripheral

NPUCLKDIV
PCLKCRx
PERx.NPUCLK
NPU Clock NPUCLK NPU
Divider

AUXCLKDIVSEL.MCANxCLKDIV

/1
0
/2
Reserved 1
.
AUXCLKIN(GPIO29) MCAN Bit Clock
2 .
PLLRAWCLK 3 .
/20

CLKSRCCTL2.MCANxBCLKSEL

Figure 3-5. Clocking System

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SYSPLL

OSCCLK ÷ INTCLK VCOCLK ÷ PLLRAWCLK

VCO
(REFDIV+1) (ODIV+1)

÷
IMULT

Figure 3-6. System PLL

fOSCCLK
fPLLRAWCLK = × IMULT (1)
REFDIV + 1 ODIV + 1

3.7.1 Clock Sources

All of the clocks in the device are derived from one of four clock sources.
3.7.1.1 Primary Internal Oscillator (INTOSC2)
At power-up, the device is clocked from an on-chip 10MHz oscillator (INTOSC2). INTOSC2 is the primary
internal clock source and is the default system clock at reset. INTOSC2 is used to run the boot ROM and can be
used as the system clock source for the application. Note that the INTOSC2 frequency tolerance is too loose to
meet the timing requirements for CAN. Use of the CAN modules requires an external oscillator. When INTOSC2
is used as the system clock source, GPIO19 (X1) and GPIO18 (X2) are available as GPIO pins.
3.7.1.2 Backup Internal Oscillator (INTOSC1)
The device also includes a redundant on-chip 10MHz oscillator (INTOSC1). INTOSC1 is a backup clock source
that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is enabled
and a missing system clock is detected, the system PLL is bypassed and all system clocks are connected
to INTOSC1 automatically. INTOSC1 can also be manually selected as the system clock source for debug
purposes.

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3.7.1.3 Auxiliary Clock Input (AUXCLKIN)

An additional external clock source is supported on GPIO29 (AUXCLKIN). This must be a single-ended 3.3V
external clock as shown in Figure 3-7 and can be used as the clock source for MCAN. Frequency limits and
timing requirements are found in the TMS320F28P55x Real-Time Microcontrollers Data Sheet. The external
clock can be connected directly to the GPIO29 pin.
Microcontroller

GPIO29
VSS (AUXCLKIN)

+3.3 V

VDD Out

3.3-V Oscillator

Gnd

Figure 3-7. AUXCLKIN

3.7.1.4 External Oscillator (XTAL)

The device supports an external clock source (XTAL), which can be used as the main system and CAN
bit clock source. Frequency limits and timing requirements can be found in the TMS320F28P55x Real-Time
Microcontrollers Data Sheet. External clock sources use the X1/GPIO19 and X2/GPIO18 pins. After power-up,
the X1 and X2 pin functionality can be enabled by following the procedure in Section 3.7.6.

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Three types of external clock sources are supported:

• A single-ended 3.3V external clock. The clock signal can be connected to X1, as shown in Figure 3-8.

Figure 3-8. Single-ended 3.3V External Clock

• An external crystal. The crystal can be connected across X1 and X2 with the load capacitors connected to
VSS as shown in Figure 3-9.

Figure 3-9. External Crystal

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• An external resonator. The resonator can be connected across X1 and X2 with the ground connected to VSS
as shown in Figure 3-10.

Figure 3-10. External Resonator

Table 3-6. ALT Modes

XTALCR Bit(1)
GPIO19 Available on GPIO18 Available on
OSCOFF SE Operating Mode X1? X2?
0 0 Crystal Mode: Quartz crystal connected to X1/X2 No No
0 1 Single-Ended Mode: External clock on X1 No Yes
1 0 Oscillator off Yes Yes
1 1 Single-Ended Mode: External clock on X1(2) No Yes

(1) OSCOFF and SE determine the ALT mode of GPIO18 and GPIO19.
(2) There is an approximately 1Kohm pull-down on X1 in this mode, external single-ended clock must be able to drive this load.

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3.7.2 Derived Clocks

The clock sources discussed in the previous section can be multiplied (using PLL) and divided down to produce
the desired clock frequencies for the application. This process produces a set of derived clocks, which are
described in this section.
3.7.2.1 Oscillator Clock (OSCCLK)
One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the reference clock (OSCCLK) for the CPU and
most of the peripherals. OSCCLK can be used directly or applied through the system PLL to reach a higher
frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.
3.7.2.2 System PLL Output Clock (PLLRAWCLK)
The system PLL allows the device to run at the maximum rated operating frequency, and in most applications
generates the main system clock. This PLL uses OSCCLK as a reference. PLLRAWCLK is the output of the PLL
voltage-controlled oscillator (VCO). For configuration instructions, see Section 3.7.6.
3.7.3 Device Clock Domains
The device clock domains feed the clock inputs of the various modules in the device. They are connected to the
derived clocks, either directly or through an additional divider.
3.7.3.1 System Clock (PLLSYSCLK)
The NMI watchdog timer has a clock domain (PLLSYSCLK). Despite the name, PLLSYSCLK can be connected
to the system PLL (PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a frequency divider,
which is configured using the SYSCLKDIVSEL register. PLLSYSCLK is gated in HALT mode.
3.7.3.2 CPU Clock (CPUCLK)
The CPU has a clock (CPUCLK) that is used to clock the CPU and Flash wrapper. This clock is identical to
PLLSYSCLK, but is gated when the CPU enters IDLE or HALT mode.
3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
Each peripheral clock has independent clock gating that is controlled by the PCLKCRx registers.

Note
The application needs to wait for 5 SYSCLK cycles after enabling the clock to the peripherals when
using PCLKCRx.

3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)

The SCI and SPI modules can communicate at bit rates that are much slower than the CPU frequency. These
modules are connected to a shared clock divider, which generates a low-speed peripheral clock (LSPCLK)
derived from SYSCLK. LSPCLK uses a /4 divider by default, but the ratio can be changed using the LOSPCP
register. Each SCI and SPI module's clock (PERx.LSPCLK) can be gated independently using the PCLKCRx
registers.
3.7.3.5 USB Bit Clock
The USB module requires a fixed 60MHz clock for bit sampling. When the PLLSYSCLK equals 150MHz, the
PLLCLK output is 300MHz, which can be divided down evenly by 5 to achieve the 60MHz requirement.
USB clock tolerances are very tight. As stated in section 7.1.11 of the USB 2.0 specification, low-speed devices
(1.50 b/s) have a tolerance of ±1.5% , while high-speed devices (12.000Mb/s) have a tolerance of ±0.25%.
Typically these tolerances are achieved by using an external crystal or resonator as the clock source for the
device.

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3.7.3.6 CAN Bit Clock

The required frequency tolerance for the CAN bit clock depends on the bit timing setup and network
configuration, and can be as tight as 0.1%. Since the main system clock (in the form of SYSCLK) can not
be precise, the bit clock can also be connected to the AUXCLKIN path using the CLKSRCCTL2 register. There is
an independent selection for each CAN module.
To maintain correct operation, the frequency of the CAN bit clock must be less than or equal to the SYSCLK
frequency.
3.7.3.7 CLB Clock
Both the CLB registers and CLB tiles can be clocked directly from SYSCLK domain. There is additional option to
divide down PLLCLK directly and feed to one or both of the above depending on the system need.
3.7.3.8 LIN Clock
To give further granularity for the LIN module, an additional divider from SYSCLK can be implemented before the
clock reaches the LIN peripheral.
3.7.3.9 CPU Timer2 Clock (TIMER2CLK)
CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default, but
can also be connected to INTOSC1, INTOSC2, or XTAL using the TMR2CLKCTL register. This register also
provides a separate prescale divider for timer 2. If a non-SYSCLK source is used, the source must be divided
down to no more than half the SYSCLK frequency.
The main reason to use a non-SYSCLK source is for internal frequency measurement. In most applications,
timer 2 runs off of SYSCLK.
3.7.4 XCLKOUT
It is sometimes necessary to observe a clock directly for debug and testing purposes. The external clock
output (XCLKOUT) feature supports this by connecting a clock to an external pin, which can be GPIO16,
GPIO18, or GPIO71. GPIO16 has digital input and output functionality; so, to use it for monitoring XCLKOUT, the
register GPAAMSEL should be set to 0. The available clock sources are PLLSYSCLK, PLLRAWCLK, SYSCLK,
INTOSC1, INTOSC2, and XTAL.
To use XCLKOUT, first select the clock source using the CLKSRCCTL3 register. Next, select the desired output
divider using the XCLKOUTDIVSEL register. Finally, connect GPIO16 or GPIO18 to mux channel 11 using the
GPIO configuration registers.
3.7.5 Clock Connectivity
Table 3-7 shows the clock connections sorted by the clock domain and Table 3-8 shows the clock connections
sorted by the module name.

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Table 3-7. Clock Connections Sorted by Clock Domain

Clock Domain Module Name
CPUCLK FPU
TMU
SYSCLK ePIE
Boot ROM
CAN Bit Clock
DCSM
Flash
GPIO Input Sync and Qual
GSx RAMs
LSx RAMs
Mx RAMs
WD
XINT
PLLCLK CLB REG Clock
CLB TILE Clock
USB Bit Clock
PLLSYSCLK CPU
NMIWD
PERx.SYSCLK ADCA,B,C,D,E
AES
CLB
CMPSS1-4
DCC0-1
eCAP1-2
ePWM1-12
eQEP1-3
EPG
ERAD
FSI
GPDACA
HRCAL
I2CA,B
MCANA,B
PGA1-3
PMBUSA
Timer0-2
PERx.LSPCLK SCIA,B,C
SPIA,B
LINACLK LINA
CAN Bit Clock MCANA,B
USB Bit Clock USB
WDCLK (INTOSC1) Watchdog Timer

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Table 3-8. Clock Connections Sorted by Module Name

Module Name Clock Domain
ADCA,B,C,D,E PERx.SYSCLK
AES PERx.SYSCLK
Boot ROM SYSCLK
CAN Bit Clock SYSCLK
CLB PERx.SYSCLK
CLB_REG_CLK PLLCLK
CLB_TILE_CLK PLLCLK
CMPSS1-4 PERx.SYSCLK
CPU PLLSYSCLK
CPU Timers (0-2) PERx.SYSCLK
DCC0 PERx.SYSCLK
DCSM SYSCLK
eCAP1-2 PERx.SYSCLK
ePIE SYSCLK
ePWM1-12 PERx.SYSCLK
eQEP1-3 PERx.SYSCLK
EPG PERx.SYSCLK
ERAD PERx.SYSCLK
Flash SYSCLK
FPU CPUCLK
FSI PERx.SYSCLK
GPDAC PERx.SYSCLK
GPIO Input Sync and Qual SYSCLK
GSx RAMs SYSCLK
I2CA,B PERx.SYSCLK
LINA LINACLK
LSx RAMs SYSCLK
Mx RAMs SYSCLK
MCANA,B PERx.SYSCLK
NMIWD PLLSYSCLK
SCIA,B,C PERx.LSPCLK
SPIA,B PERx.LSPCLK
TMU CPUCLK
USB USBBITCLK
USB Bit Clock PLLCLK
Watchdog Timer WDCLK (INTOSC1)

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3.7.6 Clock Source and PLL Setup

The needs of the application are what ultimately determine the clock configuration. Specific concerns such
as application performance, power consumption, total system cost, and EMC are beyond the scope of this
document, but can provide answers to the following questions:
1. What is the desired CPU frequency?
2. Is CAN required?
3. What types of external oscillators or clock sources are available?
If CAN is required, an external clock source with a precise frequency must be used as a reference
clock;.otherwise, use only INTOSC2 and avoid the need for more external components.
3.7.7 Using an External Crystal or Resonator
The X1 and X2 pins double as GPIO19 and GPIO18. At power-up, these pins are in GPIO mode and the on-chip
crystal oscillator is powered off. The following procedure can be used to switch the pins to X1 and X2 mode and
enable the oscillator:
1. Clear the XTALCR.OSCOFF bit.
2. Wait for the crystal to power up. 1ms is the typical wait time but this depends on the crystal that is being
used.
3. Clear the X1 counter by writing a 1 to X1CNT.CLR and keep clearing until the X1 counter value in the
X1CNT register is no longer saturated 2047 (0x7FF).
4. Repeat steps 3-4 three additional times.
5. Wait for the X1 counter value in the X1CNT register to reach 2047 (0x7FF). Repeat steps 3-4 three
additional times.
6. Select XTAL as the OSCCLK source by writing a 1 to CLKSRCCTL1.OSCCLKSRCSEL.
7. Check the MCLKSTS bit in the MCDCR register. If it's set, the oscillator has not finished powering up, and
more time is required:
a. Clear the missing clock status by writing a 1 to MCDCR.MCLKCLR.
b. Repeat steps 2-7. Do not reset the device. Doing so powers down the oscillator, which requires the
procedure to be restarted from step 1.
c. If the oscillator has not finished powering up in 10 milliseconds, there is a real clock failure.
8. If MCDCR.MCLKSTS is clear, the oscillator startup is a success. The system clock is now derived from
XTAL.
3.7.7.1 X1/X2 Precondition Circuit
The GPIO19/18 alternate functionality on X1/X2 can be used to speed up the start-up time of the crystal by as
much as 30% if needed. This functionality is achieved by preconditioning the load capacitors CL1 and CL2 to a
known state before the XTAL is turned on.
The steps below outline the procedure to precondition X1/X2 before turning on the XTAL:
1. ClkCfgRegs.XTALCR2.bit.XIF = 1; // Precondition X1 to High
2. ClkCfgRegs.XTALCR2.bit.XOF = 1; // Precondition X2 to High
3. ClkCfgRegs.XTALCR2.bit.FEN = 1; // Enable X1/X2 Precondition
4. DEVICE_DELAY_US(1);
5. ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Removes Precondition and Turns on the XTAL
6. ClkCfgRegs.XTALCR2.bit.FEN = 0; // Disables X1/X2 Precondition

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3.7.8 Using an External Oscillator

The procedure for using an external oscillator connected to the X1 pin is similar to the procedure for using a
crystal or resonator:
1. Clear the XTALCR.OSCOFF bit.
2. Set the XTALCR.SE bit to enable single-ended mode.
3. Clear the X1 counter by writing a 1 to X1CNT.CLR and keep clearing until the X1 counter value in the
X1CNT register is no longer saturated 2047 (0x7FF).
4. Wait for the X1 counter value in the X1CNT register to reach 2047 (0x7FF).
5. Repeat steps 3 and 4 three additional times.
6. Select XTAL as the OSCCLK source by writing a 1 to CLKSRCCTL1.OSCCLKSRCSEL.
7. Check the MCLKSTS bit in the MCDCR register. If the bit is set, either the external oscillator or the device
has failed.
8. If MCLKSTS is clear, the switch to the external clock is a success. The system clock is now derived from
XTAL.
3.7.9 Choosing PLL Settings
The equation shown in Figure 3-6 can be used to configure the PLL.
• IMULT is the integer value of the multiplier
• REFDIV is the reference divider for the OSCCLK
• ODIV is the output divider of the PLLRAWCLK
• PLLSYSCLKDIV is the system clock divider
For the permissible values of the multipliers and dividers, see the documentation for the respective registers.
Many combinations of multiplier and divider can produce the same output frequency. However, the product of the
reference clock frequency and the multiplier (known as the VCO frequency) must be in the range specified in the
TMS320F28P55x Real-Time Microcontrollers Data Sheet.

Note
The system clock frequency (PLLSYSCLK) can not exceed the limit specified in the TMS320F28P55x
Real-Time Microcontrollers Data Sheet. This limit does not allow for oscillator tolerance.

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3.7.10 System Clock Setup

Once the application requirements are understood, a specific clock configuration can be determined. The default
configuration is for INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1. The following
procedure can be used to set up the desired application configuration:
Refer to your device SysCtl_setClock() function inside C2000Ware installation for an example.
Recommended sequence to set up the system PLL:
1. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN]. Allow at least 60 NOP instructions for this to take
effect.
2. Power down the PLL by writing to SYSPLLCTL1.PLLEN = 0 and allow at least 60 NOP instructions for this to
take effect.
3. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL. Allow at least
300 NOP instructions for this to take effect.
4. Set the system clock divider to /1 to make sure the fastest PLL configuration by clearing
SYSCLKDIVSEL[ PLLSYSCLKDIV].
5. Set the IMULT, REFDIV, and ODIV simultaneously by writing 32-bit value in SYSPLLMULT at once. This
automatically enables the PLL. Be sure the settings for multiplier and dividers do not violate the frequency
specifications as defined in the TMS320F28P55x Real-Time Microcontrollers Data Sheet.
6. Wait for PLL to lock by polling for lock status bit to go high, SYSPLLSTS.LOCKS = 1
7. Configure DCC with reference clock as OSCCLK and clock under measurement as PLLRAWCLK, and verify
the frequency of the PLL. If the frequency is out of range, do not enable PLLRAWCLK as SYSCLK, stop
here and troubleshoot. Refer to Chapter 9 for more information on the configuration and usage.
8. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN].

Note
1. SYSPLL must be bypassed and powered down manually before changing the OSCCLK source.
2. At least 60 CPU clock cycles delay is needed after bypassing PLL, SYSPLLCTL1.PLLCLKEN = 0.
3. At least 60 CPU clock cycles delay is needed after PLL is powered down, that is,
SYSPLLCTL1.PLLEN = 0.
4. At least 300 CPU clock cycles delay is needed after OSSCLK source is changed.
5. PLL SLIP bit is not supported. The DCC can be used to check the validity of the PLL clock. This
feature is included as part of SysCtl_setClock() function inside C2000Ware.

3.7.11 SYS PLL Bypass

If the application requires the PLL clock to be bypassed from the system, configure
SYSPLLCTL1.PLLCLKEN=0. It takes up to 60 CPU clock cycles before the bypass is effective. In the meantime
if PLLSYSCLKDIV is reduced to a lower value (for example from /2 to /1 or /4 to /2), the device can be clocked
above the maximum rated frequency and can lead to unpredictable device behavior. Hence, a delay of 60 CPU
clock cycles is required after bypassing the PLL from the enable state, that is, going from PLLCLKEN=1 to
PLLCLKEN=0.

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3.7.12 Clock (OSCCLK) Failure Detection

To achieve safety diagnostic, Missing Clock Detection (MCD) can be used. Table 3-9 lists the details.
Table 3-9. Clock Source (OSCCLK) Failure Detection
Clock Failure Time for Detection
Clocks Detected Limitations
Detection Circuitry (in Cycles)
Missing Clock Detection (MCD) INTOSC2, XTAL/X1 8192 INTOSC1 cycles Cannot detect INTOSC1 clock failure.

3.7.12.1 Missing Clock Detection

The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock source.
This circuit only detects complete loss of OSCCLK and does not perform any detection of frequency drift on the
OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10MHz clock provided by the INTOSC1 (secondary
clock) as a backup clock. This circuit functions as:
1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter is
asynchronously reset with XRSn.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This counter is
asynchronously reset with XRSn.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or is not
slower than INTOSC1 by a factor of 64, MCDSCNT never overflows.
4. If OSCCLK stops for some reason, or is slower than INTOSC1 by at least a factor of 64, the MCDSCNT
overflows and a missing clock condition is detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making the
MCLKOFF bit 1)
6. If the circuit ever detects a missing OSCCLK, the following occurs:
• The MCDSTS flag is set
• The MCDSCNT counter is frozen to prevent further missing clock detection
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs to
CPU1.NMIWD.
• PLL is forcefully bypassed and OSCCLK source is switched to INTOSC1 (New, System Clock Frequency
= INTOSC1 Freq 10MHz)/SYSDIV). In the meantime when the clock switches to INTOSC1, the System
runs on PLL limp Clock.
• SYSPLLMULT.IMULT is zeroed out automatically in this case.
• While the MCDSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically
7. If the MCLKCLR bit is written (this is a W=1 bit), MCDSTS bit is cleared and OSCCLK source is decided
by the OSCCLKSRCSEL bits. Writing to MCLKCLR also clears the MCDPCNT and MCDSCNT counters
to allow the circuit to re-evaluate missing clock detection. If the user wants to lock the PLL after missing
clock detection, switch the clock source to INTOSC1 (using OSCCLKSRCSEL register), do a MCLKCLR,
and re-lock the PLL.
8. The MCD is enabled at power up.
Figure 3-11 shows the missing clock logic functional flow.

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Figure 3-11. Missing Clock Detection Logic

Note
On a complete clock failure when OSCCLK is dead, it can take a maximum time of 8192 INTOSC1
cycles (that is, 0.8192ms) before the CLOCKFAIL signal goes high, after which:
• NMI is generated
• OSCCLK is switched to INTOSC1
• PWM Trip happens

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3.8 32-Bit CPU Timers 0/1/2

This section describes the three 32-bit CPU timers (TIMER0/1/2) shown in Figure 3-12.
Timer0 and Timer1 can be used in user applications. Timer2 is reserved for real-time operating system uses (for
example, TI-RTOS). If the application is not using an operating system that utilizes this timer, then Timer2 can be
used in the application. timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 3-13.
The general operation of a CPU timer is as follows:
• The 32-bit counter register, TIMH:TIM, is loaded with the value in the period register PRDH:PRD
• The counter decrements once every (TPR[TDDRH:TDDR] + 1) SYSCLK cycles, where TDDRH:TDDR is the
timer divider.
• When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse.
The registers listed in Section 3.16 are used to configure the timers.

Figure 3-12. CPU Timers

A. The timer registers are connected to the memory bus of the C28x processor.
B. The CPU timers are synchronized to SYSCLKOUT.

Figure 3-13. CPU Timer Interrupt Signals and Output Signal

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3.9 Watchdog Timer

The watchdog module consists of an 8-bit counter sourced from a prescaled clock (WDCLK, which is
connected to INTOSC1). When the counter reaches the maximum value, the module generates an output pulse
512 WDCLKs wide. This pulse can generate an interrupt or a reset. The CPU must periodically write a 0x55 +
0xAA sequence into the watchdog key register to reset the watchdog counter. The counter can also be disabled.
The counter's clock is divided down from WDCLK by two dividers. The prescaler is adjustable from /1 to /64 in
powers of two. The pre-divider defaults to /512 for backwards compatibility, but is adjustable from /2 to /4096 in
powers of two. This allows a wide range of timeout values for safety-critical applications.
Figure 3-14 shows the various functional blocks within the watchdog module.

Figure 3-14. Watchdog Timer Module

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3.9.1 Servicing the Watchdog Timer

The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register before
the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is written to the
WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is reset. Any value
written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55 and 0xAA values can
be written to the WDKEY without causing a system reset; only a write of 0x55 followed by a write of 0xAA to the
WDKEY resets the WDCNTR.
The first action that enables the WDCNTR to be reset is shown in Step 3 in Table 3-10. The WDCNTR is not
actually reset until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR.
Step 10 again re-enables the WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11
causes no action, however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now has no
effect.
If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to the
WDCR[WDCHK] bits resets the device and sets the watchdog flag (WDRSn) in the reset cause register (RESC).
After a reset, the program can read the state of this flag to determine whether the reset was caused by the
watchdog. After doing this, the program can clear WDRSn to allow subsequent watchdog resets to be detected.
Watchdog resets are not prevented when the flag is set.
Table 3-10. Example Watchdog Key Sequences
Step Value Written to WDKEY Result
1 0xAA No action
2 0xAA No action
3 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
4 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
5 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
6 0xAA WDCNTR is reset.
7 0xAA No action
8 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
9 0xAA WDCNTR is reset.
10 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
11 0x32 Improper value written to WDKEY.
No action, WDCNTR no longer enabled to be reset by next 0xAA.
12 0xAA No action due to previous invalid value.
13 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
14 0xAA WDCNTR is reset.

3.9.2 Minimum Window Check

To complement the timeout mechanism, the watchdog also contains an optional "windowing" feature that
requires a minimum delay between counter resets. This can help protect against error conditions that bypass
large parts of the normal program flow but still include watchdog handling.
To set the window minimum, write the desired minimum watchdog count to the WDWCR register. This value
takes effect after the next WDKEY sequence. From then on, any attempt to service the watchdog when
WDCNTR is less than WDWCR triggers a watchdog interrupt or reset. When WDCNTR is greater than or equal
to WDWCR, the watchdog can be serviced normally.
At reset, the window minimum is zero, which disables the windowing feature.

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3.9.3 Watchdog Reset or Watchdog Interrupt Mode

The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an interrupt
(WDINT), if the watchdog counter reaches the maximum value. The behavior of each condition is:
• Reset mode: If the watchdog is configured to reset the device, then the WDRST signal pulls the device reset
(XRS) pin low for 512 INTOSC1 cycles when the watchdog counter reaches the maximum value.
• Interrupt mode: When the watchdog counter expires, the counter asserts an interrupt by driving the WDINT
signal low for 512 INTOSC1 cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE, if
the interrupt is enabled. Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active
does not produce a duplicate interrupt.
To avoid unexpected behavior, software must not change the configuration of the watchdog while WDINT is
active. For example, changing from interrupt mode to reset mode while WDINT is active immediately resets
the device. Disabling the watchdog while WDINT is active causes a duplicate interrupt, if the watchdog is
later re-enabled. If a debug reset is issued while WDINT is active, the reset cause register (RESC) shows a
watchdog reset. The WDINTS bit in the SCSR register can be read to determine the current state of WDINT.

3.9.4 Watchdog Operation in Low-Power Modes

Note
If the watchdog interrupt is used to wake-up from an IDLE low-power mode condition, software must
make sure that the WDINT signal goes back high before attempting to reenter the IDLE mode. The
WDINT signal is held low for 512 INTOSC1 cycles when the watchdog interrupt is generated. The
current state of WDINT can be determined by reading the watchdog interrupt status bit (WDINTS) bit
in the SCSR register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles.

In IDLE mode, the watchdog interrupt (WDINT) signal can generate an interrupt to the CPU to take the CPU out
of IDLE mode. As with any other peripheral, the watchdog interrupt triggers a WAKE interrupt in the PIE during
IDLE mode. User software must determine which peripheral caused the interrupt.
In HALT mode, the internal oscillators and watchdog timer are kept active if the user sets
CLKSRCCTL1.WDHALTI = 1. A watchdog reset can wake the system from HALT mode, but a watchdog
interrupt cannot.
3.9.5 Emulation Considerations
The watchdog module behaves as follows under various debug conditions:

CPU Suspended When the CPU is suspended, the watchdog clock (WDCLK) is
suspended.
Run-Free Mode When the CPU is placed in run-free mode, then the watchdog module
resumes operation as normal.
Real-Time Single-Step Mode When the CPU is in real-time single-step mode, the watchdog clock
(WDCLK) is suspended. The watchdog remains suspended even within
real-time interrupts.
Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the watchdog operates as
normal.

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3.10 Low-Power Modes

This device has HALT, IDLE, and STANDBY as clock-gating low-power modes.
All low-power modes are entered by setting the LPMCR register and executing the IDLE instruction. More
information about this instruction can be found in the TMS320C28x CPU and Instruction Set Reference Guide.
Low-power modes must not be entered into while a Flash program or erase operation is ongoing. Entering
HALT stops all CPU and peripheral activities. This includes active transmissions and control algorithms. When
preparing to enter HALT mode, the application must make sure that the system is prepared to enter a period of
inactivity.
Before entering HALT mode, check the value of the GPIODAT register of the pin selected for HALT wake-up
(GPIOLPMSEL0/1) prior to entering the low-power mode to make sure that the wake event has not already been
asserted.
3.10.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 3-11 describes the effect
on the system when any of the clock-gating low-power modes are entered.
Table 3-11. Effect of Clock-Gating Low-Power Modes on the Device
Modules/
IDLE STANDBY HALT
Clock Domain
SYSCLK Active Gated Gated
CPUCLK Gated Gated Gated
Clock to modules connected Active Gated Gated
to PERx.SYSCLK
WDCLK Active Active Gated if CLKSRCCTL1.WDHALTI = 0
PLL Powered Powered Software must power down PLL before entering HALT.
INTOSC1 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
Flash(1) Powered Powered Powered
XTAL(2) Powered Powered Powered

(1) The Flash module is not powered down by hardware in any LPM. The Flash module can be powered down using software if required
by the application. For more information, see the Flash Module chapter.
(2) The XTAL is not powered down by hardware in any LPM. The XTAL can be powered down using software by setting the
XTALCR.OSCOFF bit to 1. This can be done at any time during the application if the XTAL is not required.

3.10.2 IDLE
IDLE is a standard feature of the C28x CPU. In this mode, the CPU clock is gated while all peripheral clocks are
left running. IDLE can thus be used to conserve power while a CPU is waiting for peripheral events.
Any enabled interrupt wakes up the CPU from IDLE mode.
To enter IDLE mode, set LPMCR.LPM to 0x0 and execute the IDLE instruction.
The CPU resumes normal operations upon any enabled interrupt event.

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3.10.3 STANDBY
STANDBY is a more aggressive low-power mode that gates both the CPU clock and any peripheral clocks
derived from the CPU's SYSCLK. The watchdog however, is left active. STANDBY is best suited for an
application where the wake-up signal comes from an external system (or CPU subsystem) rather than a
peripheral input.
An NMI (or optionally) a watchdog interrupt or a configured GPIO can wake the CPU from STANDBY mode.
Each GPIO can be configured to wake up the CPU when the GPIOs are driven active low. Upon wake up, the
CPU receives the WAKEINT interrupt if configured.
To enter STANDBY mode:
1. Set LPMCR.LPM to 0x1.
2. Enable the WAKEINT interrupt in the PIE.
3. For watchdog interrupt wakeup, set LPMCR.WDINTE to 1 and configure the watchdog to generate
interrupts.
4. For GPIO wakeup, set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module, and set LPMCR.QUALSTDBY to select the number of OSCCLK cycles for input qualification.
5. Execute the IDLE instruction to enter STANDBY.
To wake up from STANDBY mode:
1. Configure the desired GPIO to trigger the wakeup.
2. Drive the selected GPIO signal low; the signal must remain low for the number of OSCCLK cycles specified
in the QUALSTDBY bits in the LPMCR register. If the signal is sampled high during this period, the count
restarts.
At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt is
latched in the PIE block.
The CPU is now out of STANDBY mode and can resume normal execution.

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3.10.4 HALT
HALT is a global low-power mode that gates almost all system clocks and allows for power-down of oscillators
and analog blocks.
Unlike on other C2000™ devices, HALT mode does not automatically power down the XTAL upon HALT entry.
Additionally, if the XTAL is not powered on, waking up from HALT mode does not automatically power on the
XTAL. The XTALCR.OSCOFF bit has been added to power on and off the XTAL circuitry when not needed
through application software.
For applications that require minimal power consumption during HALT mode, application software can power off
the XTAL prior to entering HALT. If the OSCCLK source is configured to be XTAL, the application can first switch
the OSSCLK source to INTOSC1 or INTOSC2 prior to setting XTALCR.OSCOFF.
Each GPIO can be configured to wake up the system from HALT. No other wake up option is available. However,
the watchdog timer can still be clocked, and can be configured to produce a watchdog reset if a timeout
mechanism is needed. On wake up, the CPU receives a WAKEINT interrupt.
To enter HALT mode:
1. Enable the WAKEINT interrupt in the PIE.
2. Set LPMCR.LPM to 0x2. Set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module.
3. Set CLKSRCCTL1.WDHALTI to 1 to keep the watchdog timer active and INTOSC1 and INTOSC2 powered
up in HALT.
4. Set CLKSRCCTL1.WDHALTI to 0 to disable the watchdog timer and power down INTOSC1 and INTOSC2 in
HALT.
5. Execute the IDLE instruction to enter HALT.
If an interrupt or NMI is received while the IDLE instruction is in the pipeline, the system begins executing the
WAKEINT ISR. After HALT wake up, ISR execution resumes where execution left off.

Note
Before entering HALT mode, if the system PLL is locked (SYSPLL.LOCKS = 1), the PLL must also be
connected to the system clock (PLLCTL1.PLLCLKEN = 1). Otherwise, the device never wakes up.

To wake up from HALT mode:

1. Drive the selected GPIO low for a minimum 5µs. This activates the WAKEINT PIE interrupt.
2. Drive the wake-up GPIO high again to initiate the powering up of the SYSPLL.
3. Wait 16µs plus 1024 OSCLK cycles to allow the PLLs to lock and the WAKEINT ISR to be latched.
4. Execute the WAKEINT ISR.
The device is now out of HALT mode and can resume normal execution.

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3.11 Memory Controller Module

On this device, the RAMs have different characteristics. These are:
• Dedicated to the CPU: M0 and M1 RAMs
• Shared between the CPU and CLA: LSx RAMs
• Shared between the CPU, DMA, and NPU: GSx RAMs
• Used to send and receive messages between the processors: MSG RAMs
All these RAMs are highly configurable to achieve control for write access and fetch access from different
peripherals. All dedicated RAMs are enabled with the ECC feature (both data and address) and shared RAMs
are enabled with the parity feature (both data and address). Some of the dedicated memories are secure
memory as well. Refer to Chapter 5 for more details. Each RAM has a controller that takes care of the
access protection and security related checks and ECC/Parity features for that RAM. Figure 3-15 shows the
configuration of these RAMs.

LSx RAM GSx RAM

CPU
CPU TO CLA MSGRAM M0/M1
CLA
CLA TO CPU MSGRAM RAM
DMA TO CLA MSGRAM
DMA NPU
CLA TO DMA MSGRAM

Figure 3-15. Memory Architecture

3.11.1 Functional Description

This section further defines and discusses the dedicated and shared RAMs on this device.
3.11.1.1 Dedicated RAM (Mx RAM)
This device has two dedicated RAM blocks: M0 and M1. M0 and M1 memories are small blocks of memory
which are tightly coupled with the CPU. Only the CPU has access to these memories.
All dedicated RAMs have the ECC feature.
3.11.1.2 Local Shared RAM (LSx RAM)
Local shared RAMs (LSx RAMs) are secure memories and have ECC. These memories are shared between
the CPU and CLA but are by default dedicated to the CPU only. CLA access can be enabled by configuring
MSEL_LSx bit field in the LSxMSEL register.
Further, when these memories are shared between the CPU and CLA, the user can choose to use these
memories as CLA program memory by configuring the CLAPGM_LSx bit field in the LSxCLAPGM registers.
CPU access to all memory blocks, which are programmed as CLA program memory, are blocked.
All these RAMs have the access protection (CPU write and CPU fetch) feature. Each type of access protection
for each RAM block can be enabled or disabled by configuring the specific bit in the local shared RAM access
protection registers, mapped to each CPU subsystem. Table 3-12 shows the LSx RAM features.

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Table 3-12. Local Shared RAM

MSEL_LSx CLAPGM_LSx CPUx CPUx.CLA1 Comment
Allowed Access Allowed Access

00 X All - LSx memory is configured as CPU dedicated RAM

01 0 All Data Read LSx memory is shared between CPU and CLA1
Data Write

01 1 Emulation Read Fetch Only LSx memory is CLA1 program memory

Emulation Write Emulation Read
Emulation Write

3.11.1.3 Global Shared RAM (GSx RAM)

RAM blocks that are accessible from the CPU and DMA are called global shared RAMs (GSx RAMs). Table 3-13
shows the features of the GSx RAM.
Table 3-13. Global Shared RAM
CPU (Fetch) CPU (Read) CPU (Write) CPU.DMA CPU.DMA NPU (Read) NPU (Write)
(Read) (Write)
Yes Yes Yes Yes Yes Yes Yes

The shared RAM has different levels of access protection that can be enabled or disabled by configuring specific
bits in the GSxACCPROT registers.
Access protection configuration for the GSx RAM block can be locked by the user to prevent further updates to
this bit field. The user can also choose to permanently lock the configuration to individual bit fields by setting
the specific bit fields in the GSxCOMMIT register (refer to the register description for more details). Once a
configuration is committed for a particular GSx RAM block, the configuration can not be changed further until
CPU.SYSRS is issued.

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3.11.1.4 CAN Message RAM

Note
Control of the CAN message RAMs can only be given to the CPU if the MCAN module is not used by
the system. The reset source for the MCANRAMACC register is PORSn (Power On Reset) and not
XRSn. This is to align the behavior with other CPU controlled RAMs. It is not recommended to change
the MCANRAMACC bit once the bit is set, as the contents of the RAM are not compatible with the
MCAN module. Even if the MCAN module is only used for boot purposes, it is not recommended to
change the ownership to the CPU.

Each MCAN module has 4KB of message RAM embedded locally and exclusively accessible by the MCAN
module.
In systems that do not use one or both MCAN modules, there is the ability to re-assign the RAM to the CPU
memory domain in data space only. The MCANRAMACC register in the Section 3.16.11 provides control of each
MCAN instance RAM assignment individually. Once set, the MCAN module has no access to these RAMs. If the
MCAN module is used at all in the system, it is not recommended to allocate this RAM to the CPU.
The C28x is a 16-bit word based CPU, as such the addressable memory is reduced to 2KB in size as shown in
Table 3-14.
Table 3-14. Addressable Memory Range for MCAN Message RAMs
MCANRAMACC MCANA Memory Addresses MCANB Memory Addresses
0 (owned by MCAN) 0x58000-0x58FFF 0x5A000-0x5AFFF
1 (owned by C28x) 0x58000-0x587FF 0x5A000-0x5A7FF

3.11.1.5 CLA-CPU Message RAM

These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access
to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU
and CLA both have read access to both MSGRAMs.
3.11.1.6 CLA-DMA Message RAM
These RAMs blocks can be used to share data between CLA and DMA. The CLA has read and write access to
the "CLA to DMA MSGRAM." The DMA has read and write access to the "DMA to CLA MSGRAM." The CLA
and DMA both have read access to both MSGRAMs.

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3.11.1.7 Access Arbitration

For a shared RAM, multiple accesses can happen at any given time. The maximum number of accesses to any
shared RAM at any given time depends on the type of shared RAM. On this device, a combination of a fixed and
alternating scheme is followed to arbitrate multiple access at any given time.
The following is the order of fixed priority for CPU accesses:
1. Data Write/Program Write
2. Data Read
3. Program Read/Program Fetch
The following is the order of fixed priority for CLA accesses:
1. Data Write
2. Data Read/Program Fetch
Figure 3-16 represents the arbitration scheme on local shared memories.
Figure 3-17 represents the arbitration scheme on global shared memories

Figure 3-16. Arbitration Scheme on Local Shared Memories

C28x CPU
Fixed Round Robin Arbitra
on
DATA WRITE

CPU RR CPU
DATA READ Fixed
Priority
Arbiter
PROGRAM
READ/FETCH

RR NPU RR DMA

DMA READ/WRITE

Figure 3-17. Arbitration Scheme on Global Shared Memories

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3.11.1.8 Access Protection

All RAM blocks except for M0/M1 have different levels of protection. This feature allows the user to enable
or disable specific access to individual RAM blocks from individual controllers. There is no protection for read
accesses, hence reads are always allowed from all the controllers which have access to that RAM block.
The following sections describe the different kinds of protection available for RAM blocks on this device.

Note
For debug accesses, all the protections are disabled.

3.11.1.8.1 CPU Fetch Protection

Fetch accesses from the CPU can be protected by setting the FETCHPROTx bit of the specific register to 1. If
fetch access is done by the CPU to a memory where CPU fetch protection is enabled, a fetch protection violation
occurs.
If a fetch protection violation occurs, the violation results in an ITRAP for the CPU. A flag gets set in the
appropriate access violation flag register, and the memory address for which the access violation occurred, gets
latched into the appropriate CPU fetch access violation address register.
3.11.1.8.2 CPU Write Protection
Write accesses from the CPU can be protected by setting the CPUWRPROTx bit of the specific register to 1. If
write access is done by a CPU to memory where the write is protected, a write protection violation occurs.
If a write protection violation occurs, the write gets ignored, a flag gets set in the appropriate access violation flag
register, and the memory address for which the access violation occurred, gets latched into the appropriate CPU
write access violation address register. Also, an access violation interrupt is generated if enabled in the interrupt
enable register.
3.11.1.8.3 CPU Read Protection
If a read protection violation occurs, a flag gets set in the appropriate access violation flag register, and the
memory address for which the access violation occurred, gets latched in the appropriate CPU read access
violation address register. Also, an access violation interrupt is generated, if enabled in the interrupt enable
register.
3.11.1.8.4 CLA Fetch Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if the RAM is configured as data RAM for
the CLA, any fetch access from the CLA to that particular LSx RAM results in a CLA fetch protection violation,
which is a non-controller access violation.
If a CLA fetch protection violation occurs, the violation results in a MSTOP. A flag gets set in the appropriate
access violation flag register, and the memory address for which the access violation occurred, gets latched in
the appropriate CLA fetch access violation address register. Also, an access violation interrupt is generated to
the CPU if enabled in the interrupt enable register.
3.11.1.8.5 CLA Write Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if the RAM is configured as program RAM
for the CLA, any data write access from the CLA to that particular LSx RAM results in a CLA write protection
violation, which is a non-controller access violation.
If a CLA write protection violation occurs, the write gets ignored, a flag gets set in the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched in the
appropriate CLA write access violation address register. Also, an access violation interrupt is generated to the
CPU if enabled in the interrupt enable register.

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3.11.1.8.6 CLA Read Protection

If local shared RAM is configured as dedicated RAM for the CPU, or if the RAM is configured as program RAM
for the CLA, any data read access from the CLA to that particular LSx RAM results in a CLA read protection
violation, which is a non-controller access violation.
If a CLA read protection violation occurs, a flag gets set in the appropriate access violation flag register, and
the memory address for which the access violation occurred, gets latched in the appropriate CLA read access
violation address register. Also, an access violation interrupt is generated to the CPU if enabled in the interrupt
enable register.
3.11.1.8.7 DMA Write Protection
Write accesses from the DMA can be protected by setting the DMAWRPROTx bit of a specific register to 1. If a
write access is done by the DMA to protected memory, a write protection violation occurs.
If a write access is made to a dedicated or shared memory by a DMA, and DMAWRPROTx is set to 1 for that
memory, the write is called a DMA write protection violation.
A flag gets set in the DMA access violation flag register, and the memory address where the violation happened
gets latched in the DMA fetch access violation address register. These are dedicated registers for each
subsystem.

Note 1: All access protections are ignored during debug accesses. Write access to a protected
memory go through when the write is done using the debugger, irrespective of the write
protection configuration for that memory.
Note 2: Access protection is not implemented for M0 and M1 memories.

3.11.1.8.8 NPU Write Protection

Write accesses from the NPU module can be protected by setting the NPUWRPROTx bit of a specific register to
1. If a write access is done by the NPU module to protected memory, a write protection violation occurs.
If a write access is made to a dedicated or shared memory by the NPU module, and NPUWRPROTx is set to 1
for that memory, the write is called a NPU write protection violation.
A flag gets set in the NPU access violation flag register, and the memory address where the violation happened
gets latched in the NPU fetch access violation address register. These are dedicated registers for each
subsystem.

Note 1: All access protections are ignored during debug accesses. Write access to a protected
memory go through when the write is done using the debugger, irrespective of the write
protection configuration for that memory.

3.11.1.9 Memory Error Detection, Correction, and Error Handling

These devices have memory error detection and correction features to satisfy safety standards requirements.
These requirements warrant the addition of detection mechanisms for finite dangerous failures.
In this device, all dedicated RAMs support error correction code (ECC) protection and the shared RAMs have
parity protection. The ECC scheme used is Single Error Correction Double Error Detection (SECDED). The
parity scheme used is even parity. ECC/Parity covers the data bits stored in memory as well as address.
ECC/Parity calculation is done inside the memory controller module and calculated. ECC/Parity is written into the
memory along with the data. ECC/Parity is computed for 16-bit data; hence, for each 32-bits of data, there are
three 7-bit ECC codes (or 3-bit parity), two of which are for data and a third one for the address.

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3.11.1.9.1 Error Detection and Correction

Error detection is done while reading the data from memory. The error detection is performed for data as well as
address. For parity memory, only a single-bit error gets detected, whereas in case of ECC memory, along with
a single-bit error, a double-bit error also gets detected. These errors are called correctable and uncorrectable
errors. The following are characteristics of these errors:
• Parity errors are always uncorrectable errors
• Single-bit ECC errors are correctable errors
• Double-bit ECC errors are uncorrectable errors
• Address ECC errors are also uncorrectable errors
Correctable errors get corrected by the memory controller module and then the correct data is given back as
read data. The correct data is also written back into the memory to prevent a double-bit error due to another
single-bit error at the same memory address.
3.11.1.9.2 Error Handling
For each correctable error, the count in the correctable error count register increments by one. When the value in
this count register becomes equal to the value configured in the correctable error threshold register, an interrupt
is generated to the CPU, if the interrupt is enabled in the correctable interrupt enable register. The user needs to
configure the correctable error threshold register based on the system requirements. Also, the address for which
the error occurred, gets latched into a register and a flag also gets set in a status register.
If there are uncorrectable errors, an NMI gets generated for the CPU. In this case also, the address for which the
error occurred gets latched into a register, and a flag gets set in a status register.
Table 3-15 summarizes different error situations that can arise. These need to be handled appropriately in the
software, using the status and interrupt indications provided.
Table 3-15. Error Handling in Different Scenarios
Access Type Error Found In Error Type Status Indication Error Notification
Reads Data read from Uncorrectable Error Yes - CPU Read Error Address Register NMI for CPU access
memory (Single-bit error for Data returned to CPU is incorrect
Parity RAMs OR
Double bit Error for
ECC RAMs)
Reads Data read from Single-bit error for Yes - CPU Read Error Address Register Interrupt when error counter reaches the
memory ECC RAMs Increment single error counter user programmable threshold for single
errors
Reads Data read from PIE Parity error Yes - PIE Parity Error sets bit in Bit set in MEM_CFG_REGS
memory MEM_CFG_REGS
Reads Address Address error Yes - CPU Read Address Error Register NMI to CPU for CPU access
Data returned to CPU is incorrect

Note
In the case of an uncorrectable error during fetch on the CPU, there is the possibility of getting an
ITRAP before an NMI exception, since garbage instructions enter into the CPU pipeline before the
NMI gets generated.
During debug accesses, correctable as well as uncorrectable errors are masked.

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3.11.1.10 Application Test Hooks for Error Detection and Correction

Since error detection and correction logic is part of safety critical logic, safety applications need to make sure
that the logic is always working fine (during run time also). To enable this, a test mode is provided, in which
a user can modify the data bits (without modifying the ECC/Parity bits) or ECC/Parity bits directly. Using this
feature, an ECC/Parity error can be injected into data.

Note
The memory map for ECC/Parity bits and data bits are the same. The user must choose a different
test mode to access ECC/Parity bits. In test mode, all access to memories (data as well as ECC/
Parity) can be done as 32-bit access only.

Table 3-16 and Table 3-17 show the bit mapping for the ECC/Parity bits when the bits are read in RAMTEST
mode using the respective addresses.
Table 3-16. Mapping of ECC Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (ECC Memory)
6:0 ECC Code for lower 16 bits of data
7 Not Used
14:8 ECC Code for upper 16 bits of data
15 Not Used
22:16 ECC Code for address
31:23 Not Used

Table 3-17. Mapping of Parity Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (Parity Memory)
0 Parity for lower 16 bits of data
7:1 Not Used
8 Parity for upper 16 bits of data
15:9 Not Used
16 Parity for address
31:17 Not Used

3.11.1.11 RAM Initialization

To make sure that a read/fetch from uninitialized RAM locations do not cause ECC or parity errors, the
RAM_INIT feature is provided for each memory block. Using this feature, any RAM block can be initialized
with 0x0 data and the respective ECC/Parity bits accordingly. This can be initiated by setting the INIT bit to 1
for the specific RAM block in INIT registers. To check the status of RAM initialization, software must poll for the
INITDONE bit for that RAM block in the INITDONE register to be set. Unless this bit gets set, no access can be
made to that RAM memory block.

Note
None of the hosts must access the memory while initialization is taking place. If memory is accessed
before RAMINITDONE is set, the memory read/write as well as initialization does not happen
correctly.

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3.12 JTAG
Gel files perform certain initialization tasks. This helps the users in a debug environment. However, when
executed standalone (without the emulator connected) the application can not work as expected, since there is
no gel file to perform those initializations. For example, gel file disables watchdog. If user code does not service
the watchdog in the application (or fails to disable the watchdog), there is a difference in how the application
behaves with the debugger and without the debugger.
Common tasks performed by the gel files (but not boot-ROM):
• On Reset:
– Disable Flash ECC on some devices.
• Disabling ECC only when using Flash API functions, see the Flash API User Guide for details.
Otherwise, TI suggests to always program ECC and enable ECC-check.
– Disable Watchdog
– Enable CLA clock
– Select real-time mode or C28x mode
• On Restart:
– Select real-time mode or C28x mode
– Clear IER and IFR
• On Target Connect:
– Select real-time mode or C28x mode

For more information, see C2000 MCU JTAG Connectivity Debug.

3.12.1 JTAG Noise and TAP_STATUS
The TAP_STATUS register reflects the status of the JTAG TAP at any given time. Normally when no JTAG
is connected to the device, the status can be IDLE. In some cases with excessive PCB noise, there can be
unwanted TMS and TCK toggles that take JTAG out of the IDLE state. When persistent, this can ultimately
lead to unwanted activation of the JTAG Boundary Scan or some other JTAG mode that can interfere with the
intended application. To avoid this scenario, place strong enough pull resistors on the board to prevent noise
from activating JTAG. As a debug tool, the TAP_STATUS register can be polled by the application code to detect
if this is a cause of device disturbance. The SOFTPRES40[JTAG_nTRST] register can also be used to reset the
JTAG TAP through software. Use this reset register with caution, as this prevents connecting a debugger unless
the code qualifies writes to this register with some other GPIO state or other means to distinguish between noise
and debugger accesses.
The TAP_CONTROL register can be used to disable the TAP state machine's control of the device. Using the
TAP_CONTROL register can help to prevent noise from activating JTAG.
3.13 Live Firmware Update
This device includes hardware hooks to streamline firmware updates. These hardware hooks enable seamless
switching from the old firmware to the new firmware without resetting the application.
This section discusses the Live Firmware Update (LFU) and the hardware features present on the device to
support LFU.
3.13.1 LFU Background
End equipment like Server Power Supply (PSU) are high availability systems that need to have minimum
downtime, even during firmware upgrades. Firmware upgrades are essential to add additional functionality,
enhance performance and fix software bugs/vulnerabilities. LFU helps update firmware while the application
is running, thus eliminating downtime (with respect to critical real-time interrupts) and also providing a more
cost-effective alternative compared to manually updating firmware.
LFU has traditionally been implemented in the C2000 family of MCUs using software-only techniques. This
impacts LFU switchover time, which is the time to switchover to new firmware once the transition has begun.

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User application code initiates this transition, typically by jumping to an entry point in the new firmware. There,
a compiler provided initialization routine specific to LFU is called. This initializes user-specified data variables.
When execution arrives in main() of the new application, user application code performs minimal initialization to
get the new application running.
3.13.2 LFU Switchover Steps
A simplified representation of the LFU switchover is shown in Figure 3-18 and is described in the following steps:
1. In typical systems, a host – typically a PC or another MCU, initiates the LFU (depicted as LFU Request) on
the application MCU (in this case, the C2000 MCU) that is executing the real-time control application. This
initiates the Flash Program sequence in the application MCU. This runs as a background process even as
the application MCU continues executing firmware (depicted as Firmware - 1).
2. Since the compiler can move existing PIE vectors and function pointers to new locations between firmware
versions, PIE vectors or function pointers can get added or removed between firmware versions. User
application code needs to manage these properly and efficiently during LFU. In the absence of Flash
remapping (where different Flash memory banks can be mapped to the same address), PIE vector table
remapping, that is “swapping” and RAM memory block swapping are features supported on the device.
Without swapping, user application code needs to individually update each PIE vector and each function
pointer, adding valuable cycles to the LFU switchover time. With swapping, prior to LFU switchover, user
application code can populate a different PIE vector table (depicted as PIE Swap Memory Update) and a
different LS RAM region (depicted as LSx Swap Memory Update).
3. When complete (depicted as LFU Switchover – waiting for appropriate time), user application code initiates
the transition to new firmware. Once the compiler LFU initialization routine completes and transfers
execution to the new application (depicted as Firmware – 2), user application code needs to perform
necessary initialization before the new application can begin running. Since PIE vectors and function
pointers have already been populated in the “swap” locations, all that is required is a PIE vector table
swap and LSx RAM Memory Swap (depicted as PIE Vector Swap, LSx Memory Swap).

LFU switchover - waiting PIE vector swap

LFU Request for appropriate time LSx Memory swap

PIE swap LSx swap

Flash Program
Memory update Memory update
Compiler LFU
Firmware - 1 Initialization Firmware - 2
Routine

Figure 3-18. Simplified LFU Representation

3.13.3 Device Features Supporting LFU

The new hardware capabilities implemented in the device to support LFU are:
1. Multi-Bank Flash
2. PIE Vector Table Swap
3. LS0/LS1 RAM Memory Swap

3.13.3.1 Multi-Bank Flash

The device has up to five Flash banks, the maximum bank size is 256KB, with support for 128KB and 64KB
banks based on the device part number (see the TMS320F28P55x Real-Time Microcontrollers Data Sheet for
this information). With multiple banks, you can Program/Erase a bank while other banks are in read mode.

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3.13.3.2 PIE Vector Table Swap

The device contains an additional PIE vector table, in addition to the typical PIE vector table that is present.
This allows PIE vector addresses for the new firmware to be populated prior to the LFU switchover. During LFU
switchover, a simple swap operation which activates the PIE vector swap table and deactivates the previously
active PIE vector table is initiated by user application code, and this operation takes just 1 CPU clock cycle. To
initiate the swap, user application code sets LFUConfig.PieVectorSwap = 1. The PIE vector table swap features
are also implemented on a redundant PIE vector table implemented for safety. Therefore, to implement PIE
vector table swap, the sizes of PIE vector memory and redundant PIE vector memory are both doubled.
The changes are summarized in Figure 3-19. In this device, there exists a duplicate PIE RAM mapped to
a different memory address. There are now two physical PIE vector RAM memories – PIE-1 and PIE-2. By
default, PIE-1 is active, and mapped to addresses 0x0000_0D00-0x0000_0EFF. PIE-2 is inactive, and mapped
to addresses 0x0100_0900-0x0100_0AFF.
When user application code initiates a PIE vector table swap by setting LFUConfig.PieVectorSwap = 1, PIE-2
becomes active, and is mapped to addresses 0x0000_0D00-0x0000_0EFF. PIE-1 becomes inactive, and is
mapped to addresses 0x0100_0900-0x0100_0AFF.
Note that the PIE vector RAM active addresses are always 0x0000_0D00-0x0000_0EFF. The inactive addresses
are always 0x0100_0900-0x0100_0AFF. As mentioned above, prior to the LFU switchover, user application code
needs to write to the inactive addresses with the PIE vector locations corresponding to the new firmware.
The register bit LFUStatus.PieVectorSwap provides the status of Pie Vector Swap.
The PIE vector RAM utilizes a parity scheme to detect address and data errors.
PIE Vector Map PIE Vector Map
Before Swap A er Swap

0x0000 0D00 0x0100 0900

Ac
ve Vector Table

PIE-1 PIE-1 Inac ve Vector Table,

ready for swap

0x0000 0EFF 0x0100 0AFF

0x0100 0900 0x0000 0D00

PIE-2 PIE-2

0x0100 0AFF 0x0000 0EFF

Figure 3-19. PIE Vector Table Swap

3.13.3.3 LS0/LS1 RAM Memory Swap

Similar to PIE Vector Table Swap, LS0 and LS1 physical RAM memory blocks can also be swapped. The
memory architecture is similar to PIE vector table swap, and is shown in Figure 3-20. By default, physical Block
1 is assigned to addresses 0x8000-0x87FF (that is, the address range for LS0), and physical Block 2 is assigned
to addresses 0x8800-0x8FFF (that is, the address range for LS1). By configuring LFUConfig.LS01Swap
= 1, user application code can execute a swap, where physical Block 2 is now assigned to addresses
0x8000-0x87FF (that is, the address range for LS0), and physical Block 1 is now assigned to addresses
0x8800-0x8FFF (that is, the address range for LS1).

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If physical memory Block 1 contains function pointers for the current firmware, the same relative locations in
physical memory Block 2 can be populated with function pointers for the new firmware prior to LFU switchover.
During LFU switchover, a simple swap operation is initiated by user application code, and this operation takes
just 1 CPU clock cycle. This allows user application code to always have function pointers in LS0, yet have two
different physical blocks that can map to the LS0 address range.
For example, if current firmware contains 10 function pointers present at the start of Block 1 (LS0 address
space). If the new firmware contains the same 10 function pointers that now need to be updated, user
application code can place these at the start of Block 2 (LS1 address space) prior to LFU switchover. During
LFU switchover, user application code executes a LS0/LS1 RAM memory swap, where the physical RAM block
previously mapped to the LS1 address space can now be mapped to the LS0 address space, and hence can be
used seamlessly for function pointer addressing for the new firmware.
The register bit LFUStatus.LS01Swap provides the status of LS0/LS1 RAM memory swap.

Figure 3-20. LS0/LS1 RAM Memory Swap

Additional points pertaining to LS0/LS1 RAM memory swap are:

1. LFU registers can be accessed from both CPU and CLA.
2. Only LS0 and LS1 blocks can be swapped. LS2 to LS7 blocks cannot be swapped.
3. LS0 and LS1 blocks have parity protection. Address parity is computed based on the physical address and
hence the address does not change based on the memory swap.
4. A number of LSx RAM registers are available to the user application code
to configure options such as select (LSxMSEL.MSEL_LS0, LSxMSEL.MSEL_LS1), fetch
protect (LSxACCPROT0.FETCHPROT_LS0, LSxACCPROT0.FETCHPROT_LS1), write protect
(LSxACCPROT0.CPUWRPROT_LS0, LSxACCPROT0.CPUWRPROT_LS1), CLA program memory
LSxCLAPGM.CLAPGM_LS0, LSxCLAPGM.CLAPGM_LS1). These register bits indicate the status of the
memory block that is deemed as LS0 (CPU address 0x8000 to 0x87FF) and LS1 (CPU address 0x8800 to
0x8FFF) at any point of time. When a LS0/LS1 RAM memory swap occurs, the corresponding control/status
bits also automatically swap.
5. Service all pending errors (access violation and parity) associated with the memory before initiating a
LS0/LS1 RAM memory swap.
6. LS0/LS1 RAM memory swap shall be initiated only after completion of RAM initialization for both LS0 and
LS1 memories (LSxINITDONE.INITDONE_LS0 = 1 and LSxINITDONE.INITDONE_LS1 = 1).

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7. LS0/LS1 RAM memory swap shall not be initiated when RAM-test (LSxTEST.TEST_LS0 = 1 or
LSxTEST.TEST_LS1 = 1) is in progress for LS0 or LS1 blocks.
8. With DCSM security on the device, in general, LS0 and LS1 RAM blocks can be assigned to different
security zones. However, with LS0/LS1 RAM memory swaps, different physical RAM blocks can get mapped
to the same address space. Application software shall therefore make sure that both LS0 and LS1 have the
same security settings (for example, zone, EXE protection), if there is a plan to implement LS0/LS1 RAM
memory swap. Hardware logic is implemented on the device to prevent swap of LS0 and LS1 if the blocks
have different security configurations.
9. To prevent security vulnerabilities, LS0/LS1 RAM memory swap is not allowed if the memory swap is
initiated by code from a different zone. For example:
• if LS0 and LS1 are part of Zone1, the swap is not allowed if the code that initiates the swap resides in
Zone2 or unsecure zone
• if LS0 and LS1 are part of Zone2, the swap is not allowed if the code that initiates the swap resides in
Zone1 or unsecure zone
• if LS0 and LS1 are part of the same zone that is unsecure, the swap is allowed in all cases irrespective of
where the code that initiates the swap resides
• if LS0 and LS1 are part of the same zone and is unlocked, the swap can be initiated from code residing
anywhere (including from the debugger)
10. Once the swap is initiated, the swap happens in the next cycle, subject to the swap meeting the security
requirements previously mentioned. After initiation of a swap, application software shall check if the swap
was correctly configured by checking the LFUStatus.LS01Swap status register. Consistency between
LFUStatus.LS01Swap and LFUConfig.LS01Swap helps determine if the swap was correctly configured. If
LFUStatus.LS01Swap does not match LFUConfig.LS01Swap, LFUConfig.LS01Swap needs to be cleared by
user application code.

3.13.3.3.1 Applicability to CLA LFU

The device does not support a swap table for the CLA task vectors (MVECTs). CLA LFU is implemented typically
on the CPU side, where the MVECTs are updated sequentially at an appropriate time. The techniques for
when to update the MVECTs are described in the LFU system reference design guide, but noted here that the
approach is different from the CPU PIE vector table case, where a simple single cycle swap achieves the switch
to the new PIE vector table.
For the LS0/LS1 RAM memory swap feature to be useful for CLA LFU switchover, two conditions need to be
satisfied:
• CLA code has to fit into a single LSx block. The MVECT table contains CLA task vectors, whose addresses
correspond to locations in the LSx block. For example, if the current firmware CLA code is present in LS0,
MVECTs point to various locations in LS0. If the new firmware CLA code is present in LS1, MVECTs point to
various locations in LS1.
• When switching over from current to new firmware, the MVECTs need to be updated, unless the MVECTs
reside at the same relative location in both LS0 and LS1. If that is the case, then simply swapping LS0/LS1
RAM memory blocks effectively updates the MVECT table, without the need to sequentially update the
MVECTs.

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3.13.4 LFU Switchover

After the new firmware has been programmed to Flash, the user application code needs to determine when
appropriate to switchover to the new firmware. The techniques to determine this difference between real-time
critical firmware running on the CPU and CLA and these techniques are beyond the scope of this document. The
techniques are described in the LFU system reference design guide.
The device supports two register bits that can be set or reset to indicate that LFU switchover is in progress on
the CPU (LFUConfig.LFU_CPU) and CLA (LFUConfig.LFU_CLA1). These bits do not impact any hardware logic
on the device. For example, LFUConfig.LFU_CPU can be set by user application code at the start of switchover,
and then tested in the initialization code in main(). This can enable only LFU switchover specific initialization
to be performed (for example, PIE vector table swap, LS0/LS1 RAM memory swap), while bypassing all other
initialization that typically happens after a device reset.
3.13.5 LFU Resources
The following are additional LFU resources available:
• Live Firmware Update Without Device Reset on C2000™ MCUs User's Guide
• Live Firmware Update With Device Reset on C2000™ MCUs User's Guide
• Live Firmware Update Reference Design with C2000™ Real-Time MCUs

3.14 System Control Register Configuration Restrictions

Memory-mapped registers in the system control operate on INTOSC1 clock domain. Any CPU writes to these
registers requires a delay in between subsequent writes; otherwise, a second write can be lost. The application
needs to take this into consideration and add a delay in terms of the number of NOP instructions after every
write to the registers listed in Table 3-18. The formula to compute the delay between subsequent writes:
Delay (in SYSCLK cycles) = 3 × (FSYSCLK ÷ FINTOSC1) + 9

For Example: for SYSCLK = 100MHz

Delay (in SYSCLK cycles) = 3 × (100MHz ÷ 10MHz) + 9 = 39 SYSCLK cycles

Table 3-18. System Control Registers Impacted

Registers requiring delay after every write
AUXCLKDIVSEL
CLBCLKCTL
PERCLKDIVSEL
SYSCLKDIVSEL
SYSPLLCTL1
SYSPLLMULT
WDCR
XCLKOUTDIVSEL
XTALCR
CLKSRCCTL1
CLKSRCCTL2
CLKSRCCTL3
CPU1TMR2CTL

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3.15 Software
3.15.1 SYSCTL Registers to Driverlib Functions
Table 3-19. SYSCTL Registers to Driverlib Functions
File Driverlib Function
PARTIDL
sysctl.c SysCtl_getDeviceParametric
PARTIDH
sysctl.c SysCtl_getDeviceParametric
REVID
sysctl.h SysCtl_getDeviceRevision
TRIMERRSTS
-
SOFTPRES0
sysctl.h SysCtl_resetPeripheral
SOFTPRES2
- See SOFTPRES0
SOFTPRES3
- See SOFTPRES0
SOFTPRES4
- See SOFTPRES0
SOFTPRES7
- See SOFTPRES0
SOFTPRES8
- See SOFTPRES0
SOFTPRES9
- See SOFTPRES0
SOFTPRES10
- See SOFTPRES0
SOFTPRES11
- See SOFTPRES0
SOFTPRES13
- See SOFTPRES0
SOFTPRES14
- See SOFTPRES0
SOFTPRES15
- See SOFTPRES0
SOFTPRES16
- See SOFTPRES0
SOFTPRES17
-
SOFTPRES18
-
SOFTPRES19
-
SOFTPRES20
-

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
SOFTPRES21
-
SOFTPRES26
-
SOFTPRES27
-
SOFTPRES28
-
SOFTPRES30
-
TAP_STATUS
-
TAP_CONTROL
-
USBTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
ECAPTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
MCUCNF3
sysctl.c SysCtl_emulateDevice
MCUCNF8
sysctl.c SysCtl_emulateDevice
MCUCNF11
sysctl.c SysCtl_emulateDevice
MCUCNF12
sysctl.c SysCtl_emulateDevice
MCUCNF14
sysctl.c SysCtl_emulateDevice
MCUCNF16
sysctl.c SysCtl_emulateDevice
MCUCNF18
sysctl.c SysCtl_emulateDevice
MCUCNF20
sysctl.c SysCtl_emulateDevice
MCUCNF21
sysctl.c SysCtl_emulateDevice
MCUCNF23
sysctl.c SysCtl_emulateDevice
MCUCNF31
sysctl.c SysCtl_emulateDevice
MCUCNF32
sysctl.c SysCtl_emulateDevice
MCUCNF33

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.c SysCtl_emulateDevice
MCUCNF34
sysctl.c SysCtl_emulateDevice
MCUCNF35
sysctl.c SysCtl_emulateDevice
MCUCNFLOCK
-
CLKCFGLOCK1
sysctl.c SysCtl_lockClkConfig
CLKSRCCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.c SysCtl_selectOscSource
sysctl.h SysCtl_enableWatchdogInHalt
sysctl.h SysCtl_disableWatchdogInHalt
CLKSRCCTL2
-
CLKSRCCTL3
sysctl.h SysCtl_selectClockOutSource
SYSPLLCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLMULT
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLSTS
sysctl.c SysCtl_setClock
SYSCLKDIVSEL
sysctl.c SysCtl_getClock
sysctl.h SysCtl_setPLLSysClk
AUXCLKDIVSEL
sysctl.h SysCtl_setMCANClk
PERCLKDIVSEL
sysctl.h SysCtl_setUSBClockDivider
sysctl.h SysCtl_setLINAClockDivider
sysctl.h SysCtl_setTINIEClockDivider
XCLKOUTDIVSEL
sysctl.h SysCtl_setXClk
CLBCLKCTL
sysctl.h SysCtl_setCLBClk
sysctl.h SysCtl_setCLBClkDivider
sysctl.h SysCtl_CLBClkConfig
LOSPCP

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.c SysCtl_getLowSpeedClock
sysctl.h SysCtl_setLowSpeedClock
MCDCR
sysctl.h SysCtl_enableMCD
sysctl.h SysCtl_disableMCD
sysctl.h SysCtl_isMCDClockFailureDetected
sysctl.h SysCtl_resetMCD
sysctl.h SysCtl_connectMCDClockSource
sysctl.h SysCtl_disconnectMCDClockSource
X1CNT
sysctl.c SysCtl_pollX1Counter
sysctl.h SysCtl_getExternalOscCounterValue
sysctl.h SysCtl_clearExternalOscCounterValue
XTALCR
sysctl.c SysCtl_setClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.h SysCtl_setExternalOscMode
sysctl.h SysCtl_turnOnOsc
sysctl.h SysCtl_turnOffOsc
XTALCR2
sysctl.c SysCtl_selectXTAL
CLKFAILCFG
-
CPUSYSLOCK1
sysctl.c SysCtl_lockSysConfig
CPUSYSLOCK2
-
PIEVERRADDR
sysctl.h SysCtl_getPIEVErrAddr
PCLKCR0
sysctl.h SysCtl_enablePeripheral
sysctl.h SysCtl_disablePeripheral
PCLKCR2
- See PCLKCR0
PCLKCR3
- See PCLKCR0
PCLKCR4
- See PCLKCR0
PCLKCR7
- See PCLKCR0
PCLKCR8
- See PCLKCR0
PCLKCR9
- See PCLKCR0

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
PCLKCR10
- See PCLKCR0
PCLKCR11
- See PCLKCR0
PCLKCR12
- See PCLKCR0
PCLKCR13
- See PCLKCR0
PCLKCR14
- See PCLKCR0
PCLKCR15
- See PCLKCR0
PCLKCR16
- See PCLKCR0
PCLKCR17
-
PCLKCR18
-
PCLKCR19
-
PCLKCR20
-
PCLKCR21
-
PCLKCR26
-
PCLKCR27
-
SIMRESET
sysctl.h SysCtl_simulateReset
LPMCR
sysctl.h SysCtl_enterIdleMode
sysctl.h SysCtl_enterStandbyMode
sysctl.h SysCtl_enterHaltMode
sysctl.h SysCtl_setStandbyQualificationPeriod
sysctl.h SysCtl_enableWatchdogStandbyWakeup
sysctl.h SysCtl_disableWatchdogStandbyWakeup
GPIOLPMSEL0
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
GPIOLPMSEL1
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
TMR2CLKCTL
cputimer.h CPUTimer_selectClockSource

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_setCputimer2Clk
RESCCLR
sysctl.h SysCtl_clearResetCause
sysctl.h SysCtl_clearWatchdogResetStatus
RESC
sysctl.h SysCtl_getResetCause
sysctl.h SysCtl_clearResetCause
sysctl.h SysCtl_getWatchdogResetStatus
sysctl.h SysCtl_clearWatchdogResetStatus
CMPSSLPMSEL
sysctl.h SysCtl_enableCMPSSLPMWakeupPin
sysctl.h SysCtl_disableCMPSSLPMWakeupPin
MCANRAMACC
-
MCANWAKESTATUS
sysctl.h SysCtl_isMCANWakeStatusSet
sysctl.h SysCtl_clearMCANWakeStatus
MCANWAKESTATUSCLR
sysctl.h SysCtl_clearMCANWakeStatus
CLKSTOPREQ
-
CLKSTOPACK
-
USER_REG1_SYSRSN
sysctl.h SysCtl_setUserRegister
sysctl.h SysCtl_getUserRegister
USER_REG2_SYSRSN
-
USER_REG1_XRSN
-
USER_REG2_XRSN
-
USER_REG1_PORESETN
-
USER_REG2_PORESETN
-
USER_REG3_PORESETN
-
USER_REG4_PORESETN
-
SCSR
sysctl.h SysCtl_setWatchdogMode
sysctl.h SysCtl_isWatchdogInterruptActive
sysctl.h SysCtl_clearWatchdogOverride
WDCNTR

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_getWatchdogCounterValue
WDKEY
sysctl.h SysCtl_serviceWatchdog
sysctl.h SysCtl_enableWatchdogReset
sysctl.h SysCtl_resetWatchdog
WDCR
sysctl.h SysCtl_resetDevice
sysctl.h SysCtl_disableWatchdog
sysctl.h SysCtl_enableWatchdog
sysctl.h SysCtl_isWatchdogEnabled
sysctl.h SysCtl_setWatchdogPredivider
sysctl.h SysCtl_setWatchdogPrescaler
WDWCR
sysctl.h SysCtl_setWatchdogWindowValue
CLA1TASKSRCSELLOCK
-
DMACHSRCSELLOCK
-
CLA1TASKSRCSEL1
cla.c CLA_setTriggerSource
CLA1TASKSRCSEL2
cla.c CLA_setTriggerSource
DMACHSRCSEL1
dma.c DMA_configMode
DMACHSRCSEL2
dma.c DMA_configMode
ADCA_AC
-
ADCB_AC
-
ADCC_AC
-
ADCD_AC
-
ADCE_AC
-
CMPSS1_AC
-
CMPSS2_AC
-
CMPSS3_AC
-
CMPSS4_AC
-
DACA_AC

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
-
PGA1_AC
-
PGA2_AC
-
PGA3_AC
-
EPWM1_AC
-
EPWM2_AC
-
EPWM3_AC
-
EPWM4_AC
-
EPWM5_AC
-
EPWM6_AC
-
EPWM7_AC
-
EPWM8_AC
-
EPWM9_AC
-
EPWM10_AC
-
EPWM11_AC
-
EPWM12_AC
-
EQEP1_AC
-
EQEP2_AC
-
EQEP3_AC
-
ECAP1_AC
-
ECAP2_AC
-
CLB1_AC
-
CLB2_AC
-

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
SCIA_AC
-
SCIB_AC
-
SCIC_AC
-
SPIA_AC
-
SPIB_AC
-
I2CA_AC
-
I2CB_AC
-
PMBUS_A_AC
-
LIN_A_AC
-
MCANA_AC
-
MCANB_AC
-
FSIATX_AC
-
FSIARX_AC
-
USBA_AC
-
HRPWM_A_AC
-
AESA_AC
-
PERIPH_AC_LOCK
sysctl.h SysCtl_lockAccessControlRegs
SYNCSELECT
sysctl.h SysCtl_setSyncOutputConfig
ADCSOCOUTSELECT
sysctl.h SysCtl_enableExtADCSOCSource
sysctl.h SysCtl_disableExtADCSOCSource
SYNCSOCLOCK
sysctl.h SysCtl_lockExtADCSOCSelect
sysctl.h SysCtl_lockSyncSelect
LFUCONFIG
sysctl.h SysCtl_setLFUCPU
sysctl.h SysCtl_getLFUCPU

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Table 3-19. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_setLFUCLA1
sysctl.h SysCtl_getLFUCLA1
sysctl.h SysCtl_swapPieVectorAndLS01
sysctl.h SysCtl_swapPieVector
sysctl.h SysCtl_swapLS01
LFUSTATUS
sysctl.h SysCtl_isPieVectorSwap
sysctl.h SysCtl_isLS01Swap
LFU_LOCK
sysctl.h SysCtl_lockLFUConfigRegister
sysctl.h SysCtl_lockLFUUserRegister
sysctl.h SysCtl_unlockLFUConfigRegister
sysctl.h SysCtl_unlockLFUUserRegister
LFU_COMMIT
sysctl.h SysCtl_commitLFUConfigRegister
sysctl.h SysCtl_commitLFUUserRegister
SYS_ERR_INT_FLG
sysctl.h SysCtl_getInterruptStatus
SYS_ERR_INT_CLR
sysctl.h SysCtl_clearInterruptStatus
SYS_ERR_INT_SET
sysctl.h SysCtl_setInterruptStatus
SYS_ERR_MASK
sysctl.h SysCtl_getInterruptStatusMask
sysctl.h SysCtl_setInterruptStatusMask

3.15.2 CPUTIMER Registers to Driverlib Functions

Table 3-20. CPUTIMER Registers to Driverlib Functions
File Driverlib Function
TIM
cputimer.h CPUTimer_getTimerCount
PRD
cputimer.h CPUTimer_setPeriod
TCR
cputimer.c CPUTimer_setEmulationMode
cputimer.h CPUTimer_clearOverflowFlag
cputimer.h CPUTimer_disableInterrupt
cputimer.h CPUTimer_enableInterrupt
cputimer.h CPUTimer_reloadTimerCounter
cputimer.h CPUTimer_stopTimer
cputimer.h CPUTimer_resumeTimer
cputimer.h CPUTimer_startTimer
cputimer.h CPUTimer_getTimerOverflowStatus
TPR
cputimer.h CPUTimer_setPreScaler

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Table 3-20. CPUTIMER Registers to Driverlib Functions (continued)

File Driverlib Function
TPRH
cputimer.h CPUTimer_setPreScaler

3.15.3 MEMCFG Registers to Driverlib Functions

Table 3-21. MEMCFG Registers to Driverlib Functions
File Driverlib Function
DXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
DXCOMMIT
memcfg.c MemCfg_commitConfig
DXACCPROT0
memcfg.c MemCfg_setProtection
DXACCPROT1
-
DXTEST
memcfg.c MemCfg_setTestMode
DXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
DXINITDONE
memcfg.c MemCfg_getInitStatus
DXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
LSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
LSXCOMMIT
memcfg.c MemCfg_commitConfig
LSXMSEL
memcfg.c MemCfg_setLSRAMControllerSel
LSXCLAPGM
memcfg.h MemCfg_setCLAMemType
LSXACCPROT0
memcfg.c MemCfg_setProtection
LSXACCPROT1
-
LSXACCPROT2(i)
-
LSXTEST
memcfg.c MemCfg_setTestMode
LSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus

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Table 3-21. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
LSXINITDONE
memcfg.c MemCfg_getInitStatus
LSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
GSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
GSXCOMMIT
memcfg.c MemCfg_commitConfig
GSXACCPROT0
memcfg.c MemCfg_setProtection
GSXTEST
memcfg.c MemCfg_setTestMode
GSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
GSXINITDONE
memcfg.c MemCfg_getInitStatus
GSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
MSGXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
MSGXCOMMIT
memcfg.c MemCfg_commitConfig
MSGXTEST
memcfg.c MemCfg_setTestMode
MSGXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
MSGXINITDONE
memcfg.c MemCfg_getInitStatus
MSGXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_TEST
memcfg.c MemCfg_setTestMode
ROM_FORCE_ERROR
memcfg.c MemCfg_forceMemError
NMAVFLG

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Table 3-21. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.h MemCfg_getViolationInterruptStatus
NMAVSET
memcfg.h MemCfg_forceViolationInterrupt
NMAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
NMAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
NMCPURDAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUWRAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUFAVADDR
-
NMDMAWRAVADDR
-
NMCLA1RDAVADDR
-
NMCLA1WRAVADDR
-
NMCLA1FAVADDR
-
NMDMARDAVADDR
-
MAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
MAVSET
memcfg.h MemCfg_forceViolationInterrupt
MAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
MAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
MCPUFAVADDR
memcfg.c MemCfg_getViolationAddress
MCPUWRAVADDR
-
MDMAWRAVADDR
-
NMTINIERDAVADDR
-
NMTINIEWRAVADDR
-
UCERRFLG
memcfg.h MemCfg_getUncorrErrorStatus

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Table 3-21. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
UCERRSET
memcfg.h MemCfg_forceUncorrErrorStatus
UCERRCLR
memcfg.h MemCfg_clearUncorrErrorStatus
UCCPUREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCDMAREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCCLA1READDR
-
UCTINIEREADDR
-
FLUCERRSTATUS
-
FLCERRSTATUS
-
CERRFLG
memcfg.h MemCfg_getCorrErrorStatus
CERRSET
memcfg.c MemCfg_getCorrErrorAddress
memcfg.h MemCfg_forceCorrErrorStatus
CERRCLR
memcfg.c MemCfg_getCorrErrorAddress
memcfg.h MemCfg_clearCorrErrorStatus
CCPUREADDR
memcfg.c MemCfg_getCorrErrorAddress
CDMAREADDR
-
CCLA1READDR
-
CERRCNT
memcfg.h MemCfg_getCorrErrorCount
CERRTHRES
memcfg.h MemCfg_setCorrErrorThreshold
CEINTFLG
memcfg.h MemCfg_getCorrErrorInterruptStatus
CEINTCLR
memcfg.h MemCfg_clearCorrErrorInterruptStatus
CEINTSET
memcfg.h MemCfg_forceCorrErrorInterrupt
CEINTEN
memcfg.h MemCfg_enableCorrErrorInterrupt
memcfg.h MemCfg_disableCorrErrorInterrupt
CPU_RAM_TEST_ERROR_STS
memcfg.h MemCfg_getDiagErrorStatus

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Table 3-21. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_STS_CLR
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_ADDR
memcfg.h MemCfg_getDiagErrorAddress

3.15.4 PIE Registers to Driverlib Functions

Table 3-22. PIE Registers to Driverlib Functions
File Driverlib Function
CTRL
interrupt.c Interrupt_initModule
interrupt.c Interrupt_defaultHandler
interrupt.h Interrupt_enablePIE
interrupt.h Interrupt_disablePIE
ACK
interrupt.c Interrupt_disable
interrupt.h Interrupt_clearACKGroup
IER1
interrupt.c Interrupt_initModule
interrupt.c Interrupt_enable
interrupt.c Interrupt_disable
IFR1
interrupt.c Interrupt_initModule
IER2
interrupt.c Interrupt_initModule
IFR2
interrupt.c Interrupt_initModule
IER3
interrupt.c Interrupt_initModule
IFR3
interrupt.c Interrupt_initModule
IER4
interrupt.c Interrupt_initModule
IFR4
interrupt.c Interrupt_initModule
IER5
interrupt.c Interrupt_initModule
IFR5
interrupt.c Interrupt_initModule
IER6
interrupt.c Interrupt_initModule
IFR6
interrupt.c Interrupt_initModule
IER7
interrupt.c Interrupt_initModule

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Table 3-22. PIE Registers to Driverlib Functions (continued)

File Driverlib Function
IFR7
interrupt.c Interrupt_initModule
IER8
interrupt.c Interrupt_initModule
IFR8
interrupt.c Interrupt_initModule
IER9
interrupt.c Interrupt_initModule
IFR9
interrupt.c Interrupt_initModule
IER10
interrupt.c Interrupt_initModule
IFR10
interrupt.c Interrupt_initModule
IER11
interrupt.c Interrupt_initModule
IFR11
interrupt.c Interrupt_initModule
IER12
interrupt.c Interrupt_initModule
IFR12
interrupt.c Interrupt_initModule

3.15.5 NMI Registers to Driverlib Functions

Table 3-23. NMI Registers to Driverlib Functions
File Driverlib Function
CFG
sysctl.h SysCtl_enableNMIGlobalInterrupt
FLG
sysctl.h SysCtl_getNMIStatus
sysctl.h SysCtl_getNMIFlagStatus
sysctl.h SysCtl_isNMIFlagSet
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
sysctl.h SysCtl_forceNMIFlags
FLGCLR
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
FLGFRC
sysctl.h SysCtl_forceNMIFlags
WDCNT
sysctl.h SysCtl_getNMIWatchdogCounter
WDPRD
sysctl.h SysCtl_setNMIWatchdogPeriod
sysctl.h SysCtl_getNMIWatchdogPeriod

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Table 3-23. NMI Registers to Driverlib Functions (continued)

File Driverlib Function
SHDFLG
sysctl.h SysCtl_getNMIShadowFlagStatus
sysctl.h SysCtl_isNMIShadowFlagSet
ERRORSTS
sysctl.h SysCtl_isErrorTriggered
sysctl.h SysCtl_getErrorPinStatus
sysctl.h SysCtl_forceError
sysctl.h SysCtl_clearError
ERRORSTSCLR
sysctl.h SysCtl_clearError
ERRORSTSFRC
sysctl.h SysCtl_forceError
ERRORCTL
sysctl.h SysCtl_selectErrPinPolarity
ERRORLOCK
sysctl.h SysCtl_lockErrControl

3.15.6 XINT Registers to Driverlib Functions

Table 3-24. XINT Registers to Driverlib Functions
File Driverlib Function
1CR
gpio.c GPIO_setInterruptPin
gpio.h GPIO_setInterruptType
gpio.h GPIO_getInterruptType
gpio.h GPIO_enableInterrupt
gpio.h GPIO_disableInterrupt
gpio.h GPIO_getInterruptCounter
2CR
- See 1CR
3CR
- See 1CR
4CR
- See 1CR
5CR
- See 1CR
1CTR
gpio.h GPIO_getInterruptCounter
2CTR
-
3CTR
-

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3.15.7 WWD Registers to Driverlib Functions

Table 3-25. WWD Registers to Driverlib Functions
File Driverlib Function
SCSR
sysctl.h SysCtl_setWatchdogMode
sysctl.h SysCtl_isWatchdogInterruptActive
sysctl.h SysCtl_clearWatchdogOverride
WDCNTR
sysctl.h SysCtl_getWatchdogCounterValue
WDKEY
sysctl.h SysCtl_serviceWatchdog
sysctl.h SysCtl_enableWatchdogReset
sysctl.h SysCtl_resetWatchdog
WDCR
sysctl.h SysCtl_resetDevice
sysctl.h SysCtl_disableWatchdog
sysctl.h SysCtl_enableWatchdog
sysctl.h SysCtl_isWatchdogEnabled
sysctl.h SysCtl_setWatchdogPredivider
sysctl.h SysCtl_setWatchdogPrescaler
WDWCR
sysctl.h SysCtl_setWatchdogWindowValue

3.15.8 SYSCTL Examples

NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/sysctl
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.8.1 Missing clock detection (MCD)
FILE: sysctl_ex1_missing_clock_detection.c
This example demonstrates the missing clock detection functionality and the way to handle it. Once the MCD is
simulated by disconnecting the OSCCLK to the MCD module an NMI would be generated. This NMI determines
that an MCD was generated due to a clock failure which is handled in the ISR.
Before an MCD the clock frequency would be as per device initialization (150Mhz). Post MCD the frequency
would move to 10Mhz or INTOSC1.
The example also shows how we can lock the PLL after missing clock, detection, by first explicitly switching the
clock source to INTOSC1, resetting the missing clock detect circuit and then re-locking the PLL. Post a re-lock
the clock frequency would be 150Mhz but using the INTOSC1 as clock source.
External Connections
• None.
Watch Variables
• fail - Indicates that a missing clock was either not detected or was not handled correctly.
• mcd_clkfail_isr - Indicates that the missing clock failure caused an NMI to be triggered and called an the ISR
to handle it.
• mcd_detect - Indicates that a missing clock was detected.
• result - Status of a successful handling of missing clock detection

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3.15.8.2 XCLKOUT (External Clock Output) Configuration

FILE: sysctl_ex2_xclkout_config.c
This example demonstrates how to configure the XCLKOUT pin for observing internal clocks through an external
pin, for debugging and testing purposes.
In this example, we are using INTOSC1 as the XCLKOUT clock source and configuring the divider as 8.
Expected frequency of XCLKOUT = (INTOSC1 freq)/8 = 10/8 = 1.25MHz
View the XCLKOUT on GPIO16 using an oscilloscope.
3.15.9 TIMER Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/timer
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.9.1 CPU Timers
FILE: timer_ex1_cputimers.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt. In order to migrate the project within syscfg to any device, click the swtich button under the device view
and select your
corresponding device to migrate, saving the project will auto-migrate your project settings.
External Connections
• None
Watch Variables
• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.15.9.2 CPU Timers
FILE: timer_ex1_cputimers_sysconfig.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt.
This example project has support for migration across our C2000 device families. If you are wanting to build this
project from launchpad or controlCARD, please specify in the .syscfg file the board you're using. At any time you
can select another device to migrate this example. External Connections
• None
Watch Variables
• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.15.10 MEMCFG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/memcfg
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.10.1 Correctable & Uncorrectable Memory Error Handling
FILE: memcfg_ex1_error_handling.c

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This example demonstrates error handling in case of various erroneous memory read/write operations.
Error handling in case of CPU read/write violations, correctable & uncorrectable memory errors has been
demonstrated. Correctable memory errors & violations can generate SYS_INT interrupt to CPU while
uncorrectable errors lead to NMI generation.
External Connections
• None
Watch Variables
• testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to TEST_FAIL
• errCountGlobal - Error counter
3.15.11 INTERRUPT Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/interrupt
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.11.1 External Interrupts (ExternalInterrupt)
FILE: interrupt_ex1_external.c
This program sets up GPIO0 as XINT1 and GPIO1 as XINT2. Two other GPIO signals are used to trigger the
interrupt (GPIO10 triggers XINT1 and GPIO11 triggers XINT2). The user is required to externally connect these
signals for the program to work properly.
XINT1 input is synced to SYSCLKOUT.
XINT2 has a long qualification - 6 samples at 510*SYSCLKOUT each.
GPIO16 will go high outside of the interrupts and low within the interrupts. This signal can be monitored on a
scope.
Each interrupt is fired in sequence - XINT1 first and then XINT2
External Connections
• Connect GPIO10 to GPIO0. GPIO0 will be assigned to XINT1
• Connect GPIO11 to GPIO1. GPIO1 will be assigned to XINT2
Monitor GPIO16 with an oscilloscope. GPIO16 will be high outside of the ISRs and low within each ISR.
Watch Variables
• xint1Count for the number of times through XINT1 interrupt
• xint2Count for the number of times through XINT2 interrupt
• loopCount for the number of times through the idle loop
3.15.11.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
FILE: interrupt_ex2_with_i2c_sci_spi_loopback.c
This program is used to demonstrate how to handle multiple interrupts when using multiple communication
peripherals like I2C, SCI & SPI Digital Loopback all in a single example. The data transfers would be done with
FIFO Interrupts.
It uses the internal loopback test mode of these modules. Both the TX and RX FIFOs and their interrupts are
used. Other than boot mode pin configuration, no other hardware configuration is required.
A stream of data is sent and then compared to the received stream. The sent data looks like this for I2C and
SCI:
0000 0001
0001 0002
0002 0003

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....
00FE 00FF
00FF 0000
etc..
The sent data looks like this for SPI:
0000 0001
0001 0002
0002 0003
....
FFFE FFFF
FFFF 0000
etc..
This pattern is repeated forever.
External Connections
• None
Watch Variables
• sDatai2cA - Data to send through I2C
• rDatai2cA - Received I2C data
• rDataPoint - Used to keep track of the last position in the receive I2C stream for error checking
• sDataspiA - Data to send through SPI
• rDataspiA - Received SPI data
• rDataPointspiA - Used to keep track of the last position in the receive SPI stream for error checking
• sDatasciA - SCI Data being sent
• rDatasciA - SCI Data received
• rDataPointA - Keep track of where we are in the SCI data stream. This is used to check the incoming data
3.15.11.3 CPU Timer Interrupt Software Prioritization
FILE: interrupt_ex3_sw_prioritization.c
This examples demonstrates the software prioritization of interrupts through CPU Timer Interrupts. Software
prioritization of interrupts is achieved by enabling interrupt nesting.
In this device, hardware priorities for CPU Timer 0, 1 and 2 are set as timer 0 being highest priority and timer 2
being lowest priority. This example configures CPU Timer0, 1, and 2 priority in software with timer 2 priority being
highest and timer 0 being lowest in software and prints a trace for the order of execution.
For most applications, the hardware prioritizing of the interrupts is sufficient. For applications that need custom
prioritizing, this example illustrates how this can be done through software.User specific priorities can be
configured in sw_prioritized_isr_level.h header file.
To enable interrupt nesting, following sequence needs to followed in ISRs. Step 1: Set the global priority: Modify
the IER register to allow CPU interrupts with a higher user priority to be serviced. Note: at this time IER has
already been saved on the stack. Step 2: Set the group priority: (optional) Modify the appropriate PIEIERx
register to allow group interrupts with a higher user set priority to be serviced. Do NOT clear PIEIER register bits
from another group other than that being serviced by this ISR. Doing so can cause erroneous interrupts to occur.
Step 3: Enable interrupts: There are three steps to do this: a. Clear the PIEACK bits b. Wait at least one cycle c.
Clear the INTM bit. Step 4: Run the main part of the ISR Step 5: Set INTM to disable interrupts. Step 6: Restore
PIEIERx (optional depending on step 2) Step 7: Return from ISR
Refer to below link on more details on Interrupt nesting in C28x devices:
<C2000Ware>\docs\c28x_interrupt_nesting\html\index.html
External Connections
• None
Watch Variables

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• traceISR - shows the order in which ISRs are executed.

3.15.11.4 EPWM Real-Time Interrupt
FILE: interrupt_ex4_epwm_realtime_interrupt.c
This example configures the ePWM1 Timer and increments a counter each time the ISR is executed. ePWM
interrupt can be configured as time critical to demonstrate real-time mode functionality and real-time interrupt
capability.
The example uses 2 LEDs - LED1 is toggled in the main loop and LED2 is toggled in the EPWM Timer
Interrupt. FREE_SOFT bits and DBGIER.INT3 bit must be set to enable ePWM1 interrupt to be time critical and
operational in real time mode after halt command
How to run the example?
• Add the watch variables as mentioned below and enable Continuous Refresh.
• Enable real-time mode (Run->Advanced->Enable Silicon Real-time Mode)
• Initially, the DBGIER register is set to 0 and the EPWM emulation mode is set to
EPWM_EMULATION_STOP_AFTER_NEXT_TB (FREE_SOFT = 0)
• When the application is running, you will find both LEDs toggling and the watch variables
EPwm1TimerIntCount, EPwm1Regs.TBCTR getting updated.
• When the application is halted, both LEDs stop toggling and the watch variables remain constant. EPWM
counter is stopped on debugger halt.
• To enable EPWM counter run during debugger halt, set emulation mode as
EPWM_EMULATION_FREE_RUN (FREE_SOFT = 2). You will find EPwm1Regs.TBCTR is running, but
EPwm1TimerIntCount remains constant. This means, the EPWM counter is running, but the ISRs are not
getting serviced.
• To enable real-time interrupts, set DBGIER.INT3 = 1 (EPWM1 interrupt is part of PIE Group 3). You will
find that the EPwm1TimerIntCount is incrementing and the LED starts toggling. The EPWM ISR is getting
serviced even during a debugger halt.
For more details, watch this video : C2000 Real-Time Features
External Connections
• None
Watch Variables
• EPwm1TimerIntCount - EPWM1 ISR counter
• EPwm1Regs.TBCTR.TBCTR - EPWM1 Time Base counter
• EPwm1Regs.TBCTL.FREE_SOFT - Set this to 2 to enable free run
• DBGIER.INT3 - Set to 1 to enable real time interrupt
3.15.12 LPM Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/lpm
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.12.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO
FILE: lpm_ex1_idlewake_gpio.c
This example puts the device into IDLE mode and then wakes up the device from IDLE using XINT1 which
triggers on a falling edge of GPIO0.
The GPIO0 pin must be pulled from high to low by an external agent for wakeup. GPIO0 is configured as an
XINT1 pin to trigger an XINT1 interrupt upon detection of a falling edge.

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Initially, pull GPIO0 high externally. To wake device from IDLE mode by triggering an XINT1 interrupt, pull GPIO0
low (falling edge). The wakeup process begins as soon as GPIO0 is held low for the time indicated in the device
datasheet.
GPIO1 is pulled high before entering the IDLE mode and is pulled low when in the external interrupt ISR.
External Connections
• GPIO0 needs to be pulled low to wake up the device.
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog
FILE: lpm_ex2_idlewake_watchdog.c
This example puts the device into IDLE mode and then wakes up the device from IDLE using watchdog timer.
The device wakes up from the IDLE mode when the watchdog timer overflows, triggering an interrupt. A pre
scalar is set for the watchdog timer to change the counter overflow time.
GPIO1 is pulled high before entering the IDLE mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO
FILE: lpm_ex3_standbywake_gpio.c
This example puts the device into STANDBY mode. If the lowest possible current consumption in STANDBY
mode is desired, the JTAG connector must be removed from the device board while the device is in STANDBY
mode.
This example puts the device into STANDBY mode and then wakes up the device from STANDBY using an LPM
wakeup pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse. Initially, pull GPIO0 high externally. To wake device from STANDBY mode, pull GPIO0 low for at least
(2+QUALSTDBY), OSCLKS, then pull it high again.
The example then wakes up the device from STANDBY using GPIO0. GPIO0 wakes the device from STANDBY
mode when a low pulse (signal goes high->low->high)is detected on the pin. This pin must be pulsed by an
external agent for wakeup.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• GPIO0 needs to be pulled low to wake up the device.
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog
FILE: lpm_ex4_standbywake_watchdog.c
This example puts the device into STANDBY mode. If the lowest possible current consumption in STANDBY
mode is desired, the JTAG connector must be removed from the device board while the device is in STANDBY
mode.
This example puts the device into STANDBY mode then wakes up the device from STANDBY using watchdog
timer.
The device wakes up from the STANDBY mode when the watchdog timer overflows triggering an interrupt. In the
ISR, the GPIO1 is pulled low. the GPIO1 is toggled to indicate the device is out of STANDBY mode. A pre scalar
is set for the watchdog timer to change the counter overflow time.

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GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.5 Low Power Modes: Halt Mode and Wakeup using GPIO
FILE: lpm_ex5_haltwake_gpio.c
This example puts the device into HALT mode. If the lowest possible current consumption in HALT mode is
desired, the JTAG connector must be removed from the device board while the device is in HALT mode.
For applications that require minimal power consumption during HALT mode, application software should power
off the XTAL prior to entering HALT by setting the XTALCR.OSCOFF bit or by using the driverlib function
SysCtl_turnOffOsc(SYSCTL_OSCSRC_XTAL);. If the OSCCLK source is configured to be XTAL, the application
should first switch the OSSCLK source to INTOSC1 or INTOSC2 prior to setting XTALCR.OSCOFF.
This example puts the device into HALT mode and then wakes up the device from HALT using an LPM wakeup
pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse.The GPIO0 pin must be pulled from high to low by an external agent for wakeup.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.12.6 Low Power Modes: Halt Mode and Wakeup
FILE: lpm_ex6_haltwake_gpio_watchdog.c
This example puts the device into HALT mode. If the lowest possible current consumption in HALT mode is
desired, the JTAG connector must be removed from the device board while the device is in HALT mode.
For applications that require minimal power consumption during HALT mode, application software should power
off the XTAL prior to entering HALT by setting the XTALCR.OSCOFF bit or by using the driverlib function
SysCtl_turnOffOsc(SYSCTL_OSCSRC_XTAL);. If the OSCCLK source is configured to be XTAL, the application
should first switch the OSSCLK source to INTOSC1 or INTOSC2 prior to setting XTALCR.OSCOFF.
This example puts the device into HALT mode and then wakes up the device from HALT using an LPM wakeup
pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse.The GPIO0 pin must be pulled from high to low by an external agent for wakeup.
In this example, the watchdog timer is clocked, and is configured to produce watchdog reset as a timeout
mechanism.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.13 WATCHDOG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/watchdog
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.13.1 Watchdog
FILE: watchdog_ex1_service.c

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This example shows how to service the watchdog or generate a wakeup interrupt using the watchdog. By default
the example will generate a Wake interrupt. To service the watchdog and not generate the interrupt, uncomment
the SysCtl_serviceWatchdog() line in the main for loop.
External Connections
• None.
Watch Variables
• wakeCount - The number of times entered into the watchdog ISR
• loopCount - The number of loops performed while not in ISR
3.16 SYSCTRL Registers
This Section describes the SYSCTRL Registers.
3.16.1 SYSCTRL Base Address Table
Table 3-26. SYSCTRL Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1
Instance Structure Protected

CPUTIMER_REG
CpuTimer0Regs CPUTIMER0_BASE 0x0000_0C00 YES - - -
S
CPUTIMER_REG
CpuTimer1Regs CPUTIMER1_BASE 0x0000_0C08 YES - - -
S
CPUTIMER_REG
CpuTimer2Regs CPUTIMER2_BASE 0x0000_0C10 YES - - -
S
PieCtrlRegs PIE_CTRL_REGS PIECTRL_BASE 0x0000_0CE0 YES - - -
PieVectTable PIE_VECT_TABLE PIEVECTTABLE_BASE 0x0000_0D00 YES - - -
WdRegs WD_REGS WD_BASE 0x0000_7000 YES - - YES
NMI_INTRUPT_R
NmiIntruptRegs NMI_BASE 0x0000_7060 YES - - YES
EGS
XintRegs XINT_REGS XINT_BASE 0x0000_7070 YES - - YES
SYNC_SOC_REG
SyncSocRegs SYNCSOC_BASE 0x0000_7940 YES - - YES
S
DmaClaSrcSelReg DMA_CLA_SRC_
DMACLASRCSEL_BASE 0x0000_7980 YES - - YES
s SEL_REGS
LfuRegs LFU_REGS LFU_BASE 0x0000_7FE0 YES - YES YES
DevCfgRegs DEV_CFG_REGS DEVCFG_BASE 0x0005_D000 YES - - YES
ClkCfgRegs CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES - - YES
CpuSysRegs CPU_SYS_REGS CPUSYS_BASE 0x0005_D300 YES - - YES
SYS_STATUS_RE
SysStatusRegs SYSSTAT_BASE 0x0005_D400 YES - - YES
GS
PERIPH_AC_REG
PeriphAcRegs PERIPHAC_BASE 0x0005_D500 YES - - YES
S
MemCfgRegs MEM_CFG_REGS MEMCFG_BASE 0x0005_F400 YES - - YES
AccessProtectionR ACCESS_PROTE ACCESSPROTECTION_BA
0x0005_F500 YES - - YES
egs CTION_REGS SE
MEMORY_ERRO
MemoryErrorRegs MEMORYERROR_BASE 0x0005_F540 YES - - YES
R_REGS
TEST_ERROR_R
TestErrorRegs TESTERROR_BASE 0x0005_F590 YES - - YES
EGS
UidRegs UID_REGS UID_BASE 0x0007_2168 YES - - -

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3.16.2 CPUTIMER_REGS Registers

Table 3-27 lists the memory-mapped registers for the CPUTIMER_REGS registers. All register offset addresses
not listed in Table 3-27 should be considered as reserved locations and the register contents should not be
modified.
Table 3-27. CPUTIMER_REGS Registers
Offset Acronym Register Name Write Protection Section
0h TIM CPU-Timer, Counter Register Go
2h PRD CPU-Timer, Period Register Go
4h TCR CPU-Timer, Control Register Go
6h TPR CPU-Timer, Prescale Register Go
7h TPRH CPU-Timer, Prescale Register High Go

Complex bit access types are encoded to fit into small table cells. Table 3-28 shows the codes that are used for
access types in this section.
Table 3-28. CPUTIMER_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W Write
1C 1 to clear
Reset or Default Value
-n Value after reset or the default
value

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3.16.2.1 TIM Register (Offset = 0h) [Reset = 0000FFFFh]

TIM is shown in Figure 3-21 and described in Table 3-29.
Return to the Summary Table.
CPU-Timer, Counter Register
Figure 3-21. TIM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-29. TIM Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Counter Registers
The TIMH register holds the high 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Counter Registers
The TIM register holds the low 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn

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3.16.2.2 PRD Register (Offset = 2h) [Reset = 0000FFFFh]

PRD is shown in Figure 3-22 and described in Table 3-30.
Return to the Summary Table.
CPU-Timer, Period Register
Figure 3-22. PRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-30. PRD Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Period Registers
The PRDH register holds the high 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Period Registers
The PRD register holds the low 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn

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3.16.2.3 TCR Register (Offset = 4h) [Reset = 0001h]

TCR is shown in Figure 3-23 and described in Table 3-31.
Return to the Summary Table.
CPU-Timer, Control Register
Figure 3-23. TCR Register
15 14 13 12 11 10 9 8
TIF TIE RESERVED FREE SOFT RESERVED
R/W1C-0h R/W-0h R-0h R/W-0h R/W-0h R-0h

7 6 5 4 3 2 1 0
RESERVED TRB TSS RESERVED
R-0h R/W-0h R/W-0h R-1h

Table 3-31. TCR Register Field Descriptions

Bit Field Type Reset Description
15 TIF R/W1C 0h CPU-Timer Overflow Flag.
TIF indicates whether a timer overflow has happened since TIF was
last cleared. TIF is not cleared automatically and does not need to be
cleared to enable the next timer interrupt.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer has not decremented to zero.
Writes of 0 are ignored.
1h (R/W) = This flag gets set when the CPU-timer decrements to
zero.
Writing a 1 to this bit clears the flag.
14 TIE R/W 0h CPU-Timer Interrupt Enable.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer interrupt is disabled.
1h (R/W) = The CPU-Timer interrupt is enabled. If the timer
decrements to zero, and TIE is set, the timer asserts its interrupt
request.
13-12 RESERVED R 0h Reserved
11 FREE R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run. If FREE is 0, then the SOFT bit controls the
emulation behavior.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop)
(SOFT bit controls the emulation behavior)
1h (R/W) = Free Run
(SOFT bit is don't care, counter is free running)
10 SOFT R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run (that is, free runs). In this case, SOFT is a
don't care. But if FREE is 0, then SOFT takes effect.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
1h (R/W) = Stop after the TIMH:TIM decrements to 0 (soft stop)
In the SOFT STOP mode, the timer generates an interrupt before
shutting down (since reaching 0 is the interrupt causing condition).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
9-6 RESERVED R 0h Reserved

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Table 3-31. TCR Register Field Descriptions (continued)

Bit Field Type Reset Description
5 TRB R/W 0h Timer reload
Reset type: SYSRSn
0h (R/W) = The TRB bit is always read as zero. Writes of 0 are
ignored.
1h (R/W) = When you write a 1 to TRB, the TIMH:TIM is loaded with
the value in the PRDH:PRD,
and the prescaler counter (PSCH:PSC) is loaded with the value in
the timer dividedown
register (TDDRH:TDDR).
4 TSS R/W 0h CPU-Timer stop status bit.
TSS is a 1-bit flag that stops or starts the CPU-timer.
Reset type: SYSRSn
0h (R/W) = Reads of 0 indicate the CPU-timer is running.
To start or restart the CPU-timer, set TSS to 0. At reset, TSS is
cleared to 0 and the
CPU-timer immediately starts.
1h (R/W) = Reads of 1 indicate that the CPU-timer is stopped.
To stop the CPU-timer, set TSS to 1.
3-0 RESERVED R 1h Reserved

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3.16.2.4 TPR Register (Offset = 6h) [Reset = 0000h]

TPR is shown in Figure 3-24 and described in Table 3-32.
Return to the Summary Table.
CPU-Timer, Prescale Register
Figure 3-24. TPR Register
15 14 13 12 11 10 9 8
PSC
R-0h

7 6 5 4 3 2 1 0
TDDR
R/W-0h

Table 3-32. TPR Register Field Descriptions

Bit Field Type Reset Description
15-8 PSC R 0h CPU-Timer Prescale Counter.
These bits hold the current prescale count for the timer. For every
timer clock source cycle that the PSCH:PSC value is greater than
0, the PSCH:PSC decrements by one. One timer clock (output
of the timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and
the timer counter register (TIMH:TIM) decrements by one. The
PSCH:PSC is also reloaded whenever the timer reload bit (TRB)
is set by software. The PSCH:PSC can be checked by reading the
register, but it cannot be set directly. It must get its value from the
timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.
Reset type: SYSRSn
7-0 TDDR R/W 0h CPU-Timer Divide-Down.
Every (TDDRH:TDDR + 1) timer clock source cycles, the timer
counter register (TIMH:TIM) decrements by one. At reset, the
TDDRH:TDDR bits are cleared to 0. To increase the overall timer
count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC)
value is 0, one timer clock source cycle later, the contents
of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC
whenever the timer reload bit (TRB) is set by software.
Reset type: SYSRSn

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3.16.2.5 TPRH Register (Offset = 7h) [Reset = 0000h]

TPRH is shown in Figure 3-25 and described in Table 3-33.
Return to the Summary Table.
CPU-Timer, Prescale Register High
Figure 3-25. TPRH Register
15 14 13 12 11 10 9 8
PSCH
R-0h

7 6 5 4 3 2 1 0
TDDRH
R/W-0h

Table 3-33. TPRH Register Field Descriptions

Bit Field Type Reset Description
15-8 PSCH R 0h See description of TIMERxTPR.
Reset type: SYSRSn
7-0 TDDRH R/W 0h See description of TIMERxTPR.
Reset type: SYSRSn

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3.16.3 PIE_CTRL_REGS Registers

Table 3-34 lists the memory-mapped registers for the PIE_CTRL_REGS registers. All register offset addresses
not listed in Table 3-34 should be considered as reserved locations and the register contents should not be
modified.
Table 3-34. PIE_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h PIECTRL ePIE Control Register Go
1h PIEACK Interrupt Acknowledge Register Go
2h PIEIER1 Interrupt Group 1 Enable Register Go
3h PIEIFR1 Interrupt Group 1 Flag Register Go
4h PIEIER2 Interrupt Group 2 Enable Register Go
5h PIEIFR2 Interrupt Group 2 Flag Register Go
6h PIEIER3 Interrupt Group 3 Enable Register Go
7h PIEIFR3 Interrupt Group 3 Flag Register Go
8h PIEIER4 Interrupt Group 4 Enable Register Go
9h PIEIFR4 Interrupt Group 4 Flag Register Go
Ah PIEIER5 Interrupt Group 5 Enable Register Go
Bh PIEIFR5 Interrupt Group 5 Flag Register Go
Ch PIEIER6 Interrupt Group 6 Enable Register Go
Dh PIEIFR6 Interrupt Group 6 Flag Register Go
Eh PIEIER7 Interrupt Group 7 Enable Register Go
Fh PIEIFR7 Interrupt Group 7 Flag Register Go
10h PIEIER8 Interrupt Group 8 Enable Register Go
11h PIEIFR8 Interrupt Group 8 Flag Register Go
12h PIEIER9 Interrupt Group 9 Enable Register Go
13h PIEIFR9 Interrupt Group 9 Flag Register Go
14h PIEIER10 Interrupt Group 10 Enable Register Go
15h PIEIFR10 Interrupt Group 10 Flag Register Go
16h PIEIER11 Interrupt Group 11 Enable Register Go
17h PIEIFR11 Interrupt Group 11 Flag Register Go
18h PIEIER12 Interrupt Group 12 Enable Register Go
19h PIEIFR12 Interrupt Group 12 Flag Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-35 shows the codes that are used for
access types in this section.
Table 3-35. PIE_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value

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Table 3-35. PIE_CTRL_REGS Access Type Codes

(continued)
Access Type Code Description
-n Value after reset or the default
value

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3.16.3.1 PIECTRL Register (Offset = 0h) [Reset = 0000h]

PIECTRL is shown in Figure 3-26 and described in Table 3-36.
Return to the Summary Table.
ePIE Control Register
Figure 3-26. PIECTRL Register
15 14 13 12 11 10 9 8
PIEVECT
R-0h

7 6 5 4 3 2 1 0
PIEVECT ENPIE
R-0h R/W-0h

Table 3-36. PIECTRL Register Field Descriptions

Bit Field Type Reset Description
15-1 PIEVECT R 0h These bits indicate the vector address of the vector fetched from the
ePIE vector table. The least significant bit of the address is ignored
and only bits 1 to 15 of the address are shown. The vector value
can be read by the user to determine which interrupt generated the
vector fetch.
Note: When a NMI is serviced, the PIEVECT bit-field does not reflect
the vector as it does for other interrupts.
Reset type: SYSRSn
0 ENPIE R/W 0h Enable vector fetching from ePIE block. This bit must be set to 1
for peripheral interrupts to work. All ePIE registers (PIEACK, PIEIFR,
PIEIER) can be accessed even when the ePIE block is disabled.
Reset type: SYSRSn

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3.16.3.2 PIEACK Register (Offset = 1h) [Reset = 0000h]

PIEACK is shown in Figure 3-27 and described in Table 3-37.
Return to the Summary Table.
Acknowledge Register
When an interrupt propagates from the ePIE to a CPU interrupt line, the interrupt group's PIEACK bit is set. This
prevents other interrupts in that group from propagating to the CPU while the first interrupt is handled. Writing a
1 to a PIEACK bit clears it and allows another interrupt from the corresponding group to propagate. ISRs for PIE
interrupts should clear the group's PIEACK bit before returning from the interrupt.
Writes of 0 are ignored.
Figure 3-27. PIEACK Register
15 14 13 12 11 10 9 8
RESERVED ACK12 ACK11 ACK10 ACK9
R-0-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

7 6 5 4 3 2 1 0
ACK8 ACK7 ACK6 ACK5 ACK4 ACK3 ACK2 ACK1
R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

Table 3-37. PIEACK Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 ACK12 R/W1S 0h Acknowledge PIE Interrupt Group 12
Reset type: SYSRSn
10 ACK11 R/W1S 0h Acknowledge PIE Interrupt Group 11
Reset type: SYSRSn
9 ACK10 R/W1S 0h Acknowledge PIE Interrupt Group 10
Reset type: SYSRSn
8 ACK9 R/W1S 0h Acknowledge PIE Interrupt Group 9
Reset type: SYSRSn
7 ACK8 R/W1S 0h Acknowledge PIE Interrupt Group 8
Reset type: SYSRSn
6 ACK7 R/W1S 0h Acknowledge PIE Interrupt Group 7
Reset type: SYSRSn
5 ACK6 R/W1S 0h Acknowledge PIE Interrupt Group 6
Reset type: SYSRSn
4 ACK5 R/W1S 0h Acknowledge PIE Interrupt Group 5
Reset type: SYSRSn
3 ACK4 R/W1S 0h Acknowledge PIE Interrupt Group 4
Reset type: SYSRSn
2 ACK3 R/W1S 0h Acknowledge PIE Interrupt Group 3
Reset type: SYSRSn
1 ACK2 R/W1S 0h Acknowledge PIE Interrupt Group 2
Reset type: SYSRSn
0 ACK1 R/W1S 0h Acknowledge PIE Interrupt Group 1
Reset type: SYSRSn

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3.16.3.3 PIEIER1 Register (Offset = 2h) [Reset = 0000h]

PIEIER1 is shown in Figure 3-28 and described in Table 3-38.
Return to the Summary Table.
Interrupt Group 1 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-28. PIEIER1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-38. PIEIER1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 1.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 1.2
Reset type: SYSRSn

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Table 3-38. PIEIER1 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 1.1
Reset type: SYSRSn

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3.16.3.4 PIEIFR1 Register (Offset = 3h) [Reset = 0000h]

PIEIFR1 is shown in Figure 3-29 and described in Table 3-39.
Return to the Summary Table.
Interrupt Group 1 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-29. PIEIFR1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-39. PIEIFR1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 1.4
Reset type: SYSRSn

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Table 3-39. PIEIFR1 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 1.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 1.1
Reset type: SYSRSn

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3.16.3.5 PIEIER2 Register (Offset = 4h) [Reset = 0000h]

PIEIER2 is shown in Figure 3-30 and described in Table 3-40.
Return to the Summary Table.
Interrupt Group 2 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-30. PIEIER2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-40. PIEIER2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 2.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 2.2
Reset type: SYSRSn

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Table 3-40. PIEIER2 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 2.1
Reset type: SYSRSn

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3.16.3.6 PIEIFR2 Register (Offset = 5h) [Reset = 0000h]

PIEIFR2 is shown in Figure 3-31 and described in Table 3-41.
Return to the Summary Table.
Interrupt Group 2 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-31. PIEIFR2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-41. PIEIFR2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 2.4
Reset type: SYSRSn

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Table 3-41. PIEIFR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 2.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 2.1
Reset type: SYSRSn

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3.16.3.7 PIEIER3 Register (Offset = 6h) [Reset = 0000h]

PIEIER3 is shown in Figure 3-32 and described in Table 3-42.
Return to the Summary Table.
Interrupt Group 3 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-32. PIEIER3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-42. PIEIER3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 3.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 3.2
Reset type: SYSRSn

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Table 3-42. PIEIER3 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 3.1
Reset type: SYSRSn

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3.16.3.8 PIEIFR3 Register (Offset = 7h) [Reset = 0000h]

PIEIFR3 is shown in Figure 3-33 and described in Table 3-43.
Return to the Summary Table.
Interrupt Group 3 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-33. PIEIFR3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-43. PIEIFR3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 3.4
Reset type: SYSRSn

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Table 3-43. PIEIFR3 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 3.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 3.1
Reset type: SYSRSn

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3.16.3.9 PIEIER4 Register (Offset = 8h) [Reset = 0000h]

PIEIER4 is shown in Figure 3-34 and described in Table 3-44.
Return to the Summary Table.
Interrupt Group 4 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-34. PIEIER4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-44. PIEIER4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 4.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 4.2
Reset type: SYSRSn

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Table 3-44. PIEIER4 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 4.1
Reset type: SYSRSn

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3.16.3.10 PIEIFR4 Register (Offset = 9h) [Reset = 0000h]

PIEIFR4 is shown in Figure 3-35 and described in Table 3-45.
Return to the Summary Table.
Interrupt Group 4 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-35. PIEIFR4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-45. PIEIFR4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 4.4
Reset type: SYSRSn

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Table 3-45. PIEIFR4 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 4.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 4.1
Reset type: SYSRSn

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3.16.3.11 PIEIER5 Register (Offset = Ah) [Reset = 0000h]

PIEIER5 is shown in Figure 3-36 and described in Table 3-46.
Return to the Summary Table.
Interrupt Group 5 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-36. PIEIER5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-46. PIEIER5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 5.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 5.2
Reset type: SYSRSn

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Table 3-46. PIEIER5 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 5.1
Reset type: SYSRSn

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3.16.3.12 PIEIFR5 Register (Offset = Bh) [Reset = 0000h]

PIEIFR5 is shown in Figure 3-37 and described in Table 3-47.
Return to the Summary Table.
Interrupt Group 5 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-37. PIEIFR5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-47. PIEIFR5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 5.4
Reset type: SYSRSn

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Table 3-47. PIEIFR5 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 5.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 5.1
Reset type: SYSRSn

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3.16.3.13 PIEIER6 Register (Offset = Ch) [Reset = 0000h]

PIEIER6 is shown in Figure 3-38 and described in Table 3-48.
Return to the Summary Table.
Interrupt Group 6 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-38. PIEIER6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-48. PIEIER6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 6.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 6.2
Reset type: SYSRSn

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Table 3-48. PIEIER6 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 6.1
Reset type: SYSRSn

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3.16.3.14 PIEIFR6 Register (Offset = Dh) [Reset = 0000h]

PIEIFR6 is shown in Figure 3-39 and described in Table 3-49.
Return to the Summary Table.
Interrupt Group 6 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-39. PIEIFR6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-49. PIEIFR6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 6.4
Reset type: SYSRSn

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Table 3-49. PIEIFR6 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 6.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 6.1
Reset type: SYSRSn

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3.16.3.15 PIEIER7 Register (Offset = Eh) [Reset = 0000h]

PIEIER7 is shown in Figure 3-40 and described in Table 3-50.
Return to the Summary Table.
Interrupt Group 7 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-40. PIEIER7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-50. PIEIER7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 7.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 7.2
Reset type: SYSRSn

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Table 3-50. PIEIER7 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 7.1
Reset type: SYSRSn

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3.16.3.16 PIEIFR7 Register (Offset = Fh) [Reset = 0000h]

PIEIFR7 is shown in Figure 3-41 and described in Table 3-51.
Return to the Summary Table.
Interrupt Group 7 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-41. PIEIFR7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-51. PIEIFR7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 7.4
Reset type: SYSRSn

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Table 3-51. PIEIFR7 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 7.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 7.1
Reset type: SYSRSn

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3.16.3.17 PIEIER8 Register (Offset = 10h) [Reset = 0000h]

PIEIER8 is shown in Figure 3-42 and described in Table 3-52.
Return to the Summary Table.
Interrupt Group 8 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-42. PIEIER8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-52. PIEIER8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 8.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 8.2
Reset type: SYSRSn

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Table 3-52. PIEIER8 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 8.1
Reset type: SYSRSn

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3.16.3.18 PIEIFR8 Register (Offset = 11h) [Reset = 0000h]

PIEIFR8 is shown in Figure 3-43 and described in Table 3-53.
Return to the Summary Table.
Interrupt Group 8 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-43. PIEIFR8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-53. PIEIFR8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 8.4
Reset type: SYSRSn

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Table 3-53. PIEIFR8 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 8.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 8.1
Reset type: SYSRSn

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3.16.3.19 PIEIER9 Register (Offset = 12h) [Reset = 0000h]

PIEIER9 is shown in Figure 3-44 and described in Table 3-54.
Return to the Summary Table.
Interrupt Group 9 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-44. PIEIER9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-54. PIEIER9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 9.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 9.2
Reset type: SYSRSn

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Table 3-54. PIEIER9 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 9.1
Reset type: SYSRSn

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3.16.3.20 PIEIFR9 Register (Offset = 13h) [Reset = 0000h]

PIEIFR9 is shown in Figure 3-45 and described in Table 3-55.
Return to the Summary Table.
Interrupt Group 9 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-45. PIEIFR9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-55. PIEIFR9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 9.4
Reset type: SYSRSn

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Table 3-55. PIEIFR9 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 9.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 9.1
Reset type: SYSRSn

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3.16.3.21 PIEIER10 Register (Offset = 14h) [Reset = 0000h]

PIEIER10 is shown in Figure 3-46 and described in Table 3-56.
Return to the Summary Table.
Interrupt Group 10 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-46. PIEIER10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-56. PIEIER10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 10.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 10.2
Reset type: SYSRSn

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Table 3-56. PIEIER10 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 10.1
Reset type: SYSRSn

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3.16.3.22 PIEIFR10 Register (Offset = 15h) [Reset = 0000h]

PIEIFR10 is shown in Figure 3-47 and described in Table 3-57.
Return to the Summary Table.
Interrupt Group 10 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-47. PIEIFR10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-57. PIEIFR10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 10.4
Reset type: SYSRSn

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Table 3-57. PIEIFR10 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 10.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 10.1
Reset type: SYSRSn

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3.16.3.23 PIEIER11 Register (Offset = 16h) [Reset = 0000h]

PIEIER11 is shown in Figure 3-48 and described in Table 3-58.
Return to the Summary Table.
Interrupt Group 11 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-48. PIEIER11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-58. PIEIER11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 11.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 11.2
Reset type: SYSRSn

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Table 3-58. PIEIER11 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 11.1
Reset type: SYSRSn

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3.16.3.24 PIEIFR11 Register (Offset = 17h) [Reset = 0000h]

PIEIFR11 is shown in Figure 3-49 and described in Table 3-59.
Return to the Summary Table.
Interrupt Group 11 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-49. PIEIFR11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-59. PIEIFR11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 11.4
Reset type: SYSRSn

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Table 3-59. PIEIFR11 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 11.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 11.1
Reset type: SYSRSn

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3.16.3.25 PIEIER12 Register (Offset = 18h) [Reset = 0000h]

PIEIER12 is shown in Figure 3-50 and described in Table 3-60.
Return to the Summary Table.
Interrupt Group 12 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-50. PIEIER12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-60. PIEIER12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 12.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 12.2
Reset type: SYSRSn

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Table 3-60. PIEIER12 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Enable for Interrupt 12.1
Reset type: SYSRSn

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3.16.3.26 PIEIFR12 Register (Offset = 19h) [Reset = 0000h]

PIEIFR12 is shown in Figure 3-51 and described in Table 3-61.
Return to the Summary Table.
Interrupt Group 12 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-51. PIEIFR12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-61. PIEIFR12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 12.4
Reset type: SYSRSn

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Table 3-61. PIEIFR12 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INTx3 R/W 0h Flag for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 12.2
Reset type: SYSRSn
0 INTx1 R/W 0h Flag for Interrupt 12.1
Reset type: SYSRSn

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3.16.4 NMI_INTRUPT_REGS Registers

Table 3-62 lists the memory-mapped registers for the NMI_INTRUPT_REGS registers. All register offset
addresses not listed in Table 3-62 should be considered as reserved locations and the register contents should
not be modified.
Table 3-62. NMI_INTRUPT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h NMICFG NMI Configuration Register EALLOW Go
1h NMIFLG NMI Flag Register (SYSRsn Clear) Go
2h NMIFLGCLR NMI Flag Clear Register EALLOW Go
3h NMIFLGFRC NMI Flag Force Register EALLOW Go
4h NMIWDCNT NMI Watchdog Counter Register Go
5h NMIWDPRD NMI Watchdog Period Register EALLOW Go
6h NMISHDFLG NMI Shadow Flag Register Go
7h ERRORSTS Error pin status Go
8h ERRORSTSCLR ERRORSTS clear register EALLOW Go
9h ERRORSTSFRC ERRORSTS force register EALLOW Go
Ah ERRORCTL Error pin control register EALLOW Go
Bh ERRORLOCK Lock register to Error pin registers. EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-63 shows the codes that are used for
access types in this section.
Table 3-63. NMI_INTRUPT_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.4.1 NMICFG Register (Offset = 0h) [Reset = 0000h]

NMICFG is shown in Figure 3-52 and described in Table 3-64.
Return to the Summary Table.
NMI Configuration Register
Figure 3-52. NMICFG Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED NMIE
R-0-0h R/W1S-0h

Table 3-64. NMICFG Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 NMIE R/W1S 0h When set to 1 any condition will generate an NMI interrupt to the
C28 CPU and kick off the NMI watchdog counter. As part of boot
sequence this bit should be set after the device security related
initialization is complete.
0 NMI disabled
1 NMI enabled
Reset type: SYSRSn

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3.16.4.2 NMIFLG Register (Offset = 1h) [Reset = 0000h]

NMIFLG is shown in Figure 3-53 and described in Table 3-65.
Return to the Summary Table.
NMI Flag Register (SYSRsn Clear)
Figure 3-53. NMIFLG Register
15 14 13 12 11 10 9 8
RESERVED RESERVED SWERR RESERVED RESERVED RESERVED RESERVED CLBNMI
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED RESERVED RESERVED UNCERR CLOCKFAIL NMIINT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-65. NMIFLG Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R-0 0h Reserved
14 RESERVED R 0h Reserved
13 SWERR R 0h SW Error Force NMI Flag: This bit indicates if an NMI was forced
through the NMIFLGFRC register. This bit can only be cleared by the
user writing to the respective bit in the NMIFLGCLR register or by an
SYSRSn reset:
0 No SW Error force Generated
1 SW Error NMI is forced by SW.
No further NMI pulses are generated until this flag is cleared by the
user.
Reset type: SYSRSn
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 CLBNMI R 0h Reconfigurable Logic NMI Flag: This bit indicates if an NMI was
generated by the Reconfigurable Logic. This bit can only be cleared
by the user writing to the corresponding clear bit in the NMIFLGCLR
register or by SYSRSn reset:
0,No Reconfigurable Logic NMI pending
1,Reconfigurable Logic NMI generated
Reset type: SYSRSn
7 SYSDBGNMI R 0h System Debug Module NMI Flag: This bit indicates if an NMI was
generated by the System Debug Module. This bit can only be
cleared by the user writing to the corresponding clear bit in the
NMIFLGCLR register or by SYSRSn reset:
0,No System Debug NMI pending
1,System Debug NMI generated
Reset type: SYSRSn
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved

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Table 3-65. NMIFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
2 UNCERR R 0h Flash/RAM/ROM Uncorrectable Error NMI Flag: This bit indicates
if an uncorrectable error occurred on a memory access (by any
master) and that condition is latched. This bit can only be cleared
by the user writing to the corresponding clear bit in the NMIFLGCLR
register or by SYSRSn reset:
0,No uncorrectable error condition pending
1, uncorrectable error condition generated
Reset type: SYSRSn
1 CLOCKFAIL R 0h Clock Fail Interrupt Flag: These bits indicates if the CLOCKFAIL
condition is latched. These bits can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by
SYSRSn reset:
0,No CLOCKFAIL Condition Pending
1,CLOCKFAIL Condition Generated
Reset type: SYSRSn
0 NMIINT R 0h NMI Interrupt Flag: This bit indicates if an NMI interrupt was
generated. This bit can only be cleared by the user writing to the
respective bit in the NMIFLGCLR register or by SYSRSn reset:
0 No NMI Interrupt Generated
1 NMI Interrupt Generated
No further NMI interrupts pulses are generated until this flag is
cleared by the user.
Reset type: SYSRSn

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3.16.4.3 NMIFLGCLR Register (Offset = 2h) [Reset = 0000h]

NMIFLGCLR is shown in Figure 3-54 and described in Table 3-66.
Return to the Summary Table.
NMI Flag Clear Register
Figure 3-54. NMIFLGCLR Register
15 14 13 12 11 10 9 8
RESERVED RESERVED SWERR RESERVED RESERVED RESERVED RESERVED CLBNMI
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED RESERVED RESERVED UNCERR CLOCKFAIL NMIINT
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-66. NMIFLGCLR Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R-0 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 SWERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
12 RESERVED R-0/W1S 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 CLBNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
7 SYSDBGNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved

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Table 3-66. NMIFLGCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
2 UNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
0 NMIINT R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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3.16.4.4 NMIFLGFRC Register (Offset = 3h) [Reset = 0000h]

NMIFLGFRC is shown in Figure 3-55 and described in Table 3-67.
Return to the Summary Table.
NMI Flag Force Register
Figure 3-55. NMIFLGFRC Register
15 14 13 12 11 10 9 8
RESERVED RESERVED SWERR RESERVED RESERVED RESERVED RESERVED CLBNMI
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED RESERVED RESERVED UNCERR CLOCKFAIL RESERVED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h

Table 3-67. NMIFLGFRC Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R-0 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 SWERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
12 RESERVED R-0/W1S 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 CLBNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
7 SYSDBGNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 UNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
0 RESERVED R-0 0h Reserved

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3.16.4.5 NMIWDCNT Register (Offset = 4h) [Reset = 0000h]

NMIWDCNT is shown in Figure 3-56 and described in Table 3-68.
Return to the Summary Table.
NMI Watchdog Counter Register
Figure 3-56. NMIWDCNT Register
15 14 13 12 11 10 9 8
NMIWDCNT
R-0h

7 6 5 4 3 2 1 0
NMIWDCNT
R-0h

Table 3-68. NMIWDCNT Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDCNT R 0h NMI Watchdog Counter: This 16-bit incremental counter will start
incrementing whenever any one of the enabled FAIL flags are set.
If the counter reaches the period value, an NMIRSn signal is fired
which will then resets the system. The counter will reset to zero
when it reaches the period value and will then restart counting if any
of the enabled FAIL flags are set.
If no enabled FAIL flag is set, then the counter will reset to zero and
remain at zero until an enabled FAIL flag is set.
Normally, the software would respond to the NMI interrupt generated
and clear the offending FLAG(s) before the NMI watchdog triggers
a reset. In some situations, the software may decide to allow the
watchdog to reset the device anyway.
The counter is clocked at the SYSCLKOUT rate.
Reset type: SYSRSn

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3.16.4.6 NMIWDPRD Register (Offset = 5h) [Reset = FFFFh]

NMIWDPRD is shown in Figure 3-57 and described in Table 3-69.
Return to the Summary Table.
NMI Watchdog Period Register
Figure 3-57. NMIWDPRD Register
15 14 13 12 11 10 9 8
NMIWDPRD
R/W-FFFFh

7 6 5 4 3 2 1 0
NMIWDPRD
R/W-FFFFh

Table 3-69. NMIWDPRD Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDPRD R/W FFFFh NMI Watchdog Period: This 16-bit value contains the period value at
which a reset is generated when the watchdog counter matches. At
reset this value is set at the maximum. The software can decrease
the period value at initialization time.
Writing a PERIOD value that is smaller then the current counter
value will automatically force an NMIRSn and hence reset the
watchdog counter.
Reset type: SYSRSn

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3.16.4.7 NMISHDFLG Register (Offset = 6h) [Reset = 0000h]

NMISHDFLG is shown in Figure 3-58 and described in Table 3-70.
Return to the Summary Table.
NMI Shadow Flag Register
Figure 3-58. NMISHDFLG Register
15 14 13 12 11 10 9 8
RESERVED RESERVED SWERR RESERVED RESERVED RESERVED RESERVED CLBNMI
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED RESERVED RESERVED UNCERR CLOCKFAIL RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0-0h

Table 3-70. NMISHDFLG Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R-0 0h Reserved
14 RESERVED R 0h Reserved
13 SWERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 CLBNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
7 SYSDBGNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved

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Table 3-70. NMISHDFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
2 UNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
1 CLOCKFAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
0 RESERVED R-0 0h Reserved

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3.16.4.8 ERRORSTS Register (Offset = 7h) [Reset = 0000h]

ERRORSTS is shown in Figure 3-59 and described in Table 3-71.
Return to the Summary Table.
Error pin status
Figure 3-59. ERRORSTS Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED PINSTS ERROR
R-0-0h R-0h R-0h

Table 3-71. ERRORSTS Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R-0 0h Reserved
1 PINSTS R 0h 0, Error Pin is 0
1, Error Pin is 1
Reset type: PORESETn
0 ERROR R 0h 0,None of the error sources were triggered.
1, One or more of the error sources triggered, or
ERRORSTS.ERROR was set by a write of 1 to
ERRORSTSFRC.ERROR bit. Once set, the ERROR flag can be
cleared by writing 1 to ERRORSTSCLR.ERROR bit. Following are
the events/triggers which can set this bit:
1. nmi interrupt on C28x
2. Watchdog reset
3. Error on a Pie vector fetch
4. Efuse error
On a read of this bit, the pin Error pin state will be returned.
Reset type: PORESETn

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3.16.4.9 ERRORSTSCLR Register (Offset = 8h) [Reset = 0000h]

ERRORSTSCLR is shown in Figure 3-60 and described in Table 3-72.
Return to the Summary Table.
ERRORSTS clear register
Figure 3-60. ERRORSTSCLR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERROR
R-0-0h R-0/W1S-0h

Table 3-72. ERRORSTSCLR Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is cleared to 0
Reset type: PORESETn

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3.16.4.10 ERRORSTSFRC Register (Offset = 9h) [Reset = 0000h]

ERRORSTSFRC is shown in Figure 3-61 and described in Table 3-73.
Return to the Summary Table.
ERRORSTS force register
Figure 3-61. ERRORSTSFRC Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERROR
R-0-0h R-0/W1S-0h

Table 3-73. ERRORSTSFRC Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is set to 1
Reset type: PORESETn

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3.16.4.11 ERRORCTL Register (Offset = Ah) [Reset = 0000h]

ERRORCTL is shown in Figure 3-62 and described in Table 3-74.
Return to the Summary Table.
Error pin control register
Figure 3-62. ERRORCTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERRORPOLSE
L
R-0-0h R/W-0h

Table 3-74. ERRORCTL Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERRORPOLSEL R/W 0h 0, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
0, else 1.
1, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
1, else 0.
Reset type: PORESETn

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3.16.4.12 ERRORLOCK Register (Offset = Bh) [Reset = 0000h]

ERRORLOCK is shown in Figure 3-63 and described in Table 3-75.
Return to the Summary Table.
Lock register to Error pin registers.
Figure 3-63. ERRORLOCK Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERRORCTL
R-0-0h R/WSonce-0h

Table 3-75. ERRORLOCK Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERRORCTL R/WSonce 0h 0, Writes to ERRORCTL register allowed.
1, Writes to ERRORCTL register is blocked.
Writes of 0 to this bit has no effect. Write of 1 will set this bit, cleared
only on a SYSRSn.
Reset type: SYSRSn

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3.16.5 XINT_REGS Registers

Table 3-76 lists the memory-mapped registers for the XINT_REGS registers. All register offset addresses not
listed in Table 3-76 should be considered as reserved locations and the register contents should not be modified.
Table 3-76. XINT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h XINT1CR XINT1 configuration register Go
1h XINT2CR XINT2 configuration register Go
2h XINT3CR XINT3 configuration register Go
3h XINT4CR XINT4 configuration register Go
4h XINT5CR XINT5 configuration register Go
8h XINT1CTR XINT1 counter register Go
9h XINT2CTR XINT2 counter register Go
Ah XINT3CTR XINT3 counter register Go

Complex bit access types are encoded to fit into small table cells. Table 3-77 shows the codes that are used for
access types in this section.
Table 3-77. XINT_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.5.1 XINT1CR Register (Offset = 0h) [Reset = 0000h]

XINT1CR is shown in Figure 3-64 and described in Table 3-78.
Return to the Summary Table.
XINT1 configuration register
Figure 3-64. XINT1CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-78. XINT1CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.2 XINT2CR Register (Offset = 1h) [Reset = 0000h]

XINT2CR is shown in Figure 3-65 and described in Table 3-79.
Return to the Summary Table.
XINT2 configuration register
Figure 3-65. XINT2CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-79. XINT2CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.3 XINT3CR Register (Offset = 2h) [Reset = 0000h]

XINT3CR is shown in Figure 3-66 and described in Table 3-80.
Return to the Summary Table.
XINT3 configuration register
Figure 3-66. XINT3CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-80. XINT3CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.4 XINT4CR Register (Offset = 3h) [Reset = 0000h]

XINT4CR is shown in Figure 3-67 and described in Table 3-81.
Return to the Summary Table.
XINT4 configuration register
Figure 3-67. XINT4CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-81. XINT4CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.5 XINT5CR Register (Offset = 4h) [Reset = 0000h]

XINT5CR is shown in Figure 3-68 and described in Table 3-82.
Return to the Summary Table.
XINT5 configuration register
Figure 3-68. XINT5CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-82. XINT5CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.5.6 XINT1CTR Register (Offset = 8h) [Reset = 0000h]

XINT1CTR is shown in Figure 3-69 and described in Table 3-83.
Return to the Summary Table.
XINT1 counter register
Figure 3-69. XINT1CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-83. XINT1CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.5.7 XINT2CTR Register (Offset = 9h) [Reset = 0000h]

XINT2CTR is shown in Figure 3-70 and described in Table 3-84.
Return to the Summary Table.
XINT2 counter register
Figure 3-70. XINT2CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-84. XINT2CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.5.8 XINT3CTR Register (Offset = Ah) [Reset = 0000h]

XINT3CTR is shown in Figure 3-71 and described in Table 3-85.
Return to the Summary Table.
XINT3 counter register
Figure 3-71. XINT3CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-85. XINT3CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.6 SYNC_SOC_REGS Registers

Table 3-86 lists the memory-mapped registers for the SYNC_SOC_REGS registers. All register offset addresses
not listed in Table 3-86 should be considered as reserved locations and the register contents should not be
modified.
Table 3-86. SYNC_SOC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h SYNCSELECT Sync Input and Output Select Register EALLOW Go
2h ADCSOCOUTSELECT External ADCSOC Select Register EALLOW Go
4h SYNCSOCLOCK SYNCSEL and EXTADCSOC Select Lock register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-87 shows the codes that are used for
access types in this section.
Table 3-87. SYNC_SOC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.6.1 SYNCSELECT Register (Offset = 0h) [Reset = E003FFFFh]

SYNCSELECT is shown in Figure 3-72 and described in Table 3-88.
Return to the Summary Table.
Sync Input and Output Select Register
Figure 3-72. SYNCSELECT Register
31 30 29 28 27 26 25 24
RESERVED SYNCOUT
R/W-7h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED
R-0-0h R/W-7h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R/W-7h R/W-7h R/W-7h R/W-7h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
R/W-7h R/W-7h R/W-7h

Table 3-88. SYNCSELECT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R/W 7h Reserved

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Table 3-88. SYNCSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
28-24 SYNCOUT R/W 0h Select Syncout Source:
00000: EPWM1SYNCOUT selected to drive the SYNCOUT pin.
00001: EPWM2SYNCOUT selected to drive the SYNCOUT pin.
00010: EPWM3SYNCOUT selected to drive the SYNCOUT pin.
00011: EPWM4SYNCOUT selected to drive the SYNCOUT pin.
00100: EPWM5SYNCOUT selected to drive the SYNCOUT pin.
00101: EPWM6SYNCOUT selected to drive the SYNCOUT pin.
00110: EPWM7SYNCOUT selected to drive the SYNCOUT pin.
00111: EPWM8SYNCOUT selected to drive the SYNCOUT pin.
01000: EPWM9SYNCOUT selected to drive the SYNCOUT pin.
01001: EPWM10SYNCOUT selected to drive the SYNCOUT pin.
01010: EPWM11SYNCOUT selected to drive the SYNCOUT pin.
01011: EPWM12SYNCOUT selected to drive the SYNCOUT pin.
01100: Reserved
01101: Reserved
01110: Reserved
01111: Reserved
10000: Reserved
10001: Reserved
10010: Reserved
10011: Reserved
10100: Reserved
10101: Reserved
10110: Reserved
10111: Reserved
11000: ECAP1SYNCOUT selected to drive the SYNCOUT pin.
11001: ECAP2SYNCOUT selected to drive the SYNCOUT pin.
11010: Reserved
11011: Reserved
11100: Reserved
11101: Reserved
11110: Reserved
11111: Reserved
Notes:
[1] Reserved position defaults to 00 selection
Reset type: SYSRSn
23-18 RESERVED R-0 0h Reserved
17-15 RESERVED R/W 7h Reserved
14-12 RESERVED R/W 7h Reserved
11-9 RESERVED R/W 7h Reserved
8-6 RESERVED R/W 7h Reserved
5-3 RESERVED R/W 7h Reserved
2-0 RESERVED R/W 7h Reserved

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3.16.6.2 ADCSOCOUTSELECT Register (Offset = 2h) [Reset = 00000000h]

ADCSOCOUTSELECT is shown in Figure 3-73 and described in Table 3-89.
Return to the Summary Table.
External ADCSOC Select Register
Figure 3-73. ADCSOCOUTSELECT Register
31 30 29 28 27 26 25 24
RESERVED PWM12SOBAE PWM11SOBAE PWM10SOBAE PWM9SOCBEN
N N N
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
PWM8SOCBEN PWM7SOCBEN PWM6SOCBEN PWM5SOCBEN PWM4SOCBEN PWM3SOCBEN PWM2SOCBEN PWM1SOCBEN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED PWM12SOCAE PWM11SOCAE PWM10SOCAE PWM9SOCAEN
N N N
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
PWM8SOCAEN PWM7SOCAEN PWM6SOCAEN PWM5SOCAEN PWM4SOCAEN PWM3SOCAEN PWM2SOCAEN PWM1SOCAEN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-89. ADCSOCOUTSELECT Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R-0 0h Reserved
27 PWM12SOBAEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
26 PWM11SOBAEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
25 PWM10SOBAEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
24 PWM9SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
23 PWM8SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
22 PWM7SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
21 PWM6SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn

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Table 3-89. ADCSOCOUTSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
20 PWM5SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
19 PWM4SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
18 PWM3SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
17 PWM2SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
16 PWM1SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
15-12 RESERVED R-0 0h Reserved
11 PWM12SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
10 PWM11SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
9 PWM10SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
8 PWM9SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
7 PWM8SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
6 PWM7SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
5 PWM6SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
4 PWM5SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn

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Table 3-89. ADCSOCOUTSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
3 PWM4SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
2 PWM3SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
1 PWM2SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
0 PWM1SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn

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3.16.6.3 SYNCSOCLOCK Register (Offset = 4h) [Reset = 00000000h]

SYNCSOCLOCK is shown in Figure 3-74 and described in Table 3-90.
Return to the Summary Table.
SYNCSEL and EXTADCSOC Select Lock register
Figure 3-74. SYNCSOCLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADCSOCOUTS SYNCSELECT
ELECT
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-90. SYNCSOCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 ADCSOCOUTSELECT R/WSonce 0h ADCSOCOUTSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 SYNCSELECT R/WSonce 0h SYNCSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.16.7 DMA_CLA_SRC_SEL_REGS Registers

Table 3-91 lists the memory-mapped registers for the DMA_CLA_SRC_SEL_REGS registers. All register offset
addresses not listed in Table 3-91 should be considered as reserved locations and the register contents should
not be modified.
Table 3-91. DMA_CLA_SRC_SEL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CLA1TASKSRCSELLOCK CLA1 Task Trigger Source Select Lock Register EALLOW Go
4h DMACHSRCSELLOCK DMA Channel Triger Source Select Lock Register EALLOW Go
6h CLA1TASKSRCSEL1 CLA1 Task Trigger Source Select Register-1 EALLOW Go
8h CLA1TASKSRCSEL2 CLA1 Task Trigger Source Select Register-2 EALLOW Go
16h DMACHSRCSEL1 DMA Channel Trigger Source Select Register-1 EALLOW Go
18h DMACHSRCSEL2 DMA Channel Trigger Source Select Register-2 EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-92 shows the codes that are used for
access types in this section.
Table 3-92. DMA_CLA_SRC_SEL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.7.1 CLA1TASKSRCSELLOCK Register (Offset = 0h) [Reset = 00000000h]

CLA1TASKSRCSELLOCK is shown in Figure 3-75 and described in Table 3-93.
Return to the Summary Table.
CLA1 Task Trigger Source Select Lock Register
Figure 3-75. CLA1TASKSRCSELLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CLA1TASKSRC CLA1TASKSRC
SEL2 SEL1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-93. CLA1TASKSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 CLA1TASKSRCSEL2 R/WSonce 0h CLA1TASKSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 CLA1TASKSRCSEL1 R/WSonce 0h CLA1TASKSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.16.7.2 DMACHSRCSELLOCK Register (Offset = 4h) [Reset = 00000000h]

DMACHSRCSELLOCK is shown in Figure 3-76 and described in Table 3-94.
Return to the Summary Table.
DMA Channel Triger Source Select Lock Register
Figure 3-76. DMACHSRCSELLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMACHSRCSE DMACHSRCSE
L2 L1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-94. DMACHSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 DMACHSRCSEL2 R/WSonce 0h DMACHSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 DMACHSRCSEL1 R/WSonce 0h DMACHSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.16.7.3 CLA1TASKSRCSEL1 Register (Offset = 6h) [Reset = 00000000h]

CLA1TASKSRCSEL1 is shown in Figure 3-77 and described in Table 3-95.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-1
Figure 3-77. CLA1TASKSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-95. CLA1TASKSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK4 R/W 0h Selects the Trigger Source for TASK4 of CLA1
Reset type: SYSRSn
23-16 TASK3 R/W 0h Selects the Trigger Source for TASK3 of CLA1
Reset type: SYSRSn
15-8 TASK2 R/W 0h Selects the Trigger Source for TASK2 of CLA1
Reset type: SYSRSn
7-0 TASK1 R/W 0h Selects the Trigger Source for TASK1 of CLA1
Reset type: SYSRSn

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3.16.7.4 CLA1TASKSRCSEL2 Register (Offset = 8h) [Reset = 00000000h]

CLA1TASKSRCSEL2 is shown in Figure 3-78 and described in Table 3-96.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-2
Figure 3-78. CLA1TASKSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-96. CLA1TASKSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK8 R/W 0h Selects the Trigger Source for TASK8 of CLA1
Reset type: SYSRSn
23-16 TASK7 R/W 0h Selects the Trigger Source for TASK7 of CLA1
Reset type: SYSRSn
15-8 TASK6 R/W 0h Selects the Trigger Source for TASK6 of CLA1
Reset type: SYSRSn
7-0 TASK5 R/W 0h Selects the Trigger Source for TASK5 of CLA1
Reset type: SYSRSn

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3.16.7.5 DMACHSRCSEL1 Register (Offset = 16h) [Reset = 00000000h]

DMACHSRCSEL1 is shown in Figure 3-79 and described in Table 3-97.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-1
Figure 3-79. DMACHSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH4 CH3 CH2 CH1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-97. DMACHSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 CH4 R/W 0h Selects the Trigger and Sync Source CH4 of DMA
Reset type: SYSRSn
23-16 CH3 R/W 0h Selects the Trigger and Sync Source CH3 of DMA
Reset type: SYSRSn
15-8 CH2 R/W 0h Selects the Trigger and Sync Source CH2 of DMA
Reset type: SYSRSn
7-0 CH1 R/W 0h Selects the Trigger and Sync Source CH1 of DMA
Reset type: SYSRSn

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3.16.7.6 DMACHSRCSEL2 Register (Offset = 18h) [Reset = 00000000h]

DMACHSRCSEL2 is shown in Figure 3-80 and described in Table 3-98.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-2
Figure 3-80. DMACHSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CH6 CH5
R-0-0h R/W-0h R/W-0h

Table 3-98. DMACHSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 CH6 R/W 0h Selects the Trigger and Sync Source CH6 of DMA
Reset type: SYSRSn
7-0 CH5 R/W 0h Selects the Trigger and Sync Source CH5 of DMA
Reset type: SYSRSn

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3.16.8 LFU_REGS Registers

Table 3-99 lists the memory-mapped registers for the LFU_REGS registers. All register offset addresses not
listed in Table 3-99 should be considered as reserved locations and the register contents should not be modified.
Table 3-99. LFU_REGS Registers
Offset Acronym Register Name Write Protection Section
0h LFUConfig LFU configuration Register EALLOW Go
2h LFUStatus LFU Configuration Status Register Go
1Ch LFU_LOCK LFU Lock Configuration Go
1Eh LFU_COMMIT LFU Commit Configuration Go

Complex bit access types are encoded to fit into small table cells. Table 3-100 shows the codes that are used for
access types in this section.
Table 3-100. LFU_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.8.1 LFUConfig Register (Offset = 0h) [Reset = 00000000h]

LFUConfig is shown in Figure 3-81 and described in Table 3-101.
Return to the Summary Table.
LFU configuration Register
Figure 3-81. LFUConfig Register
31 30 29 28 27 26 25 24
RESERVED
R-0/W-0h

23 22 21 20 19 18 17 16
RESERVED LS01Swap RESERVED
R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED PieVectorSwap RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED LFU_CLA1 RESERVED LFU_CPU
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-101. LFUConfig Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0/W 0h Reserved
23-21 RESERVED R/W 0h Reserved
20 LS01Swap R/W 0h 0: LS0 and LS1 mapped to the original location
1: Location of LS0 and LS1 is swapped.
Reset type: SYSRSn
19-13 RESERVED R/W 0h Reserved
12 PieVectorSwap R/W 0h 0: PIE vector table is mapped to the original location
1: PIE Vector Table is swapped to alternate location
Reset type: SYSRSn
11-9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7-5 RESERVED R/W 0h Reserved
4 LFU_CLA1 R/W 0h 0: No pending LFU Requests
1: LFU Request in progress
This bit is used by compiler/application code for implementing CLA1
LFU
Reset type: SYSRSn
3-1 RESERVED R/W 0h Reserved
0 LFU_CPU R/W 0h 0: No pending LFU Requests
1: LFU Request in progress
This bit is used by compiler/application code for implementing CPU
LFU
Reset type: SYSRSn

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3.16.8.2 LFUStatus Register (Offset = 2h) [Reset = 00000000h]

LFUStatus is shown in Figure 3-82 and described in Table 3-102.
Return to the Summary Table.
LFU Configuration Status Register
Figure 3-82. LFUStatus Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED LS01Swap RESERVED
R-0-0h R/W-0h R-0-0h

15 14 13 12 11 10 9 8
RESERVED PieVectorSwap RESERVED
R-0-0h R/W-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 3-102. LFUStatus Register Field Descriptions

Bit Field Type Reset Description
31-21 RESERVED R-0 0h Reserved
20 LS01Swap R/W 0h 0: LS0 and LS1 mapped to the original location
1: Location of LS0 and LS1 is swapped.
Note: An initiated LSx swap will become uncessful if the LS0 and
LS1 memories have different security configurations
Reset type: SYSRSn
19-13 RESERVED R-0 0h Reserved
12 PieVectorSwap R/W 0h 0: PIE vector table is mapped to the original location
1: PIE Vector Table is swapped to alternate location
Reset type: SYSRSn
11-0 RESERVED R-0 0h Reserved

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3.16.8.3 LFU_LOCK Register (Offset = 1Ch) [Reset = 00000000h]

LFU_LOCK is shown in Figure 3-83 and described in Table 3-103.
Return to the Summary Table.
LFU Lock Configuration
Figure 3-83. LFU_LOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SWConfig2_PO SWConfig1_PO SWConfig2_XR SWConfig1_XR SWConfig2_SY SWConfig1_SY
RESETn RESETn Sn Sn SRSn SRSn
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED LFUConfig
R-0-0h R/W-0h

Table 3-103. LFU_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R-0 0h Reserved
13 SWConfig2_PORESETn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
12 SWConfig1_PORESETn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
11 SWConfig2_XRSn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
10 SWConfig1_XRSn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
9 SWConfig2_SYSRSn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
8 SWConfig1_SYSRSn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
7-1 RESERVED R-0 0h Reserved
0 LFUConfig R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn

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3.16.8.4 LFU_COMMIT Register (Offset = 1Eh) [Reset = 00000000h]

LFU_COMMIT is shown in Figure 3-84 and described in Table 3-104.
Return to the Summary Table.
LFU Commit Configuration
Figure 3-84. LFU_COMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SWConfig2_PO SWConfig1_PO SWConfig2_XR SWConfig1_XR SWConfig2_SY SWConfig1_SY
RESETn RESETn Sn Sn SRSn SRSn
R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
RESERVED LFUConfig
R-0-0h R/WSonce-0h

Table 3-104. LFU_COMMIT Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R-0 0h Reserved
13 SWConfig2_PORESETn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
12 SWConfig1_PORESETn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
11 SWConfig2_XRSn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
10 SWConfig1_XRSn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
9 SWConfig2_SYSRSn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
8 SWConfig1_SYSRSn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn

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Table 3-104. LFU_COMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
7-1 RESERVED R-0 0h Reserved
0 LFUConfig R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn

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3.16.9 DEV_CFG_REGS Registers

Table 3-105 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses
not listed in Table 3-105 should be considered as reserved locations and the register contents should not be
modified.
Table 3-105. DEV_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
8h PARTIDL Lower 32-bit of Device PART Identification Go
Number
Ah PARTIDH Upper 32-bit of Device PART Identification Go
Number
Ch REVID Device Revision Number Go
74h TRIMERRSTS TRIM Error Status register Go
82h SOFTPRES0 Processing Block Software Reset register EALLOW Go
86h SOFTPRES2 EPWM Software Reset register EALLOW Go
88h SOFTPRES3 ECAP Software Reset register EALLOW Go
8Ah SOFTPRES4 EQEP Software Reset register EALLOW Go
90h SOFTPRES7 SCI Software Reset register EALLOW Go
92h SOFTPRES8 SPI Software Reset register EALLOW Go
94h SOFTPRES9 I2C Software Reset register EALLOW Go
96h SOFTPRES10 CAN Software Reset register EALLOW Go
98h SOFTPRES11 McBSP/USB Software Reset register EALLOW Go
9Ch SOFTPRES13 ADC Software Reset register EALLOW Go
9Eh SOFTPRES14 CMPSS Software Reset register EALLOW Go
A0h SOFTPRES15 PGA Software Reset register EALLOW Go
A2h SOFTPRES16 DAC Software Reset register EALLOW Go
A4h SOFTPRES17 CLB Software Reset register EALLOW Go
A6h SOFTPRES18 FSI Software Reset register EALLOW Go
A8h SOFTPRES19 LIN Software Reset register EALLOW Go
AAh SOFTPRES20 PMBUS Software Reset register EALLOW Go
ACh SOFTPRES21 DCC Software Reset register EALLOW Go
B6h SOFTPRES26 AES Software Reset register EALLOW Go
B8h SOFTPRES27 EPG Software Reset register EALLOW Go
BAh SOFTPRES28 Flash Software Reset register EALLOW Go
BEh SOFTPRES30 NPU Software reset register EALLOW Go
D2h SOFTPRES40 Peripheral Software Reset register EALLOW Go
130h TAP_STATUS Status of JTAG State machine & Debugger Go
Connect
132h TAP_CONTROL Disable TAP control Go
19Ah USBTYPE Configures USB Type for the device EALLOW Go
19Bh ECAPTYPE Configures ECAP Type for the device EALLOW Go
1A6h MCUCNF3 MCU Configuration: ETPWM Go
1B0h MCUCNF8 MCU Configuration: SCI Go
1B6h MCUCNF11 MCU Configuration: CAN Go
1B8h MCUCNF12 MCU Configuration: McBSP_USB Go
1BCh MCUCNF14 MCU Configuration: ADC Go
1C0h MCUCNF16 MCU Configuration: PGA Go
1C4h MCUCNF18 MCU Configuration: Lx.1 SRAM Customization Go

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Table 3-105. DEV_CFG_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
1C8h MCUCNF20 MCU Configuration: GSx SRAM Customization Go
1CAh MCUCNF21 MCU Configuration: CLB Go
1CEh MCUCNF23 MCU Configuration: LIN Go
1DEh MCUCNF31 MCU Configuration: Flash Bank0 Go
1E0h MCUCNF32 MCU Configuration: Flash Bank1 Go
1E2h MCUCNF33 MCU Configuration: Flash Bank2 Go
1E4h MCUCNF34 MCU Configuration: Flash Bank3 Go
1E6h MCUCNF35 MCU Configuration: Flash Bank4 Go
1F8h MCUCNFLOCK Lock bit for MCUCNFx registers EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-106 shows the codes that are used for
access types in this section.
Table 3-106. DEV_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
WOnce W Write
Once Write once
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.9.1 PARTIDL Register (Offset = 8h) [Reset = 00XXXXX0h]

PARTIDL is shown in Figure 3-85 and described in Table 3-107.
Return to the Summary Table.
Lower 32-bit of Device PART Identification Number
Figure 3-85. PARTIDL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED
R-0h R-0h

23 22 21 20 19 18 17 16
FLASH_SIZE
R-XXh

15 14 13 12 11 10 9 8
RESERVED INSTASPIN RESERVED RESERVED PIN_COUNT
R-0h R-Xh R-0h R-Xh R-Xh

7 6 5 4 3 2 1 0
QUAL RESERVED RESERVED RESERVED
R-Xh R-0h R-0h R-0h

Table 3-107. PARTIDL Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-24 RESERVED R 0h Reserved
23-16 FLASH_SIZE R XXh 0x8 - 1088KB
0x7 - 1024KB
0x6 - 576KB
0x5 - 512KB
0x4 - 256KB
0x3 -128KB
0x0-0x2 - Reserved
Reset type: PORESETn
15 RESERVED R 0h Reserved
14-13 INSTASPIN R Xh 1 = InstaSPIN-FOC
2 = NONE
3 = NONE
Reset type: PORESETn
12 RESERVED R 0h Reserved
11 RESERVED R Xh Reserved
10-8 PIN_COUNT R Xh 0 = 56 pin QFN
1 = 64 pin QFP
2 = 80 pin QFP
3 = 100 pin QFP
4 = 128 pin QFP
5 = Reserved
6 = Reserved
7 = Reserved
Reset type: PORESETn
7-6 QUAL R Xh 0 = Engineering sample (TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)
Reset type: PORESETn
5 RESERVED R 0h Reserved

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Table 3-107. PARTIDL Register Field Descriptions (continued)

Bit Field Type Reset Description
4-3 RESERVED R 0h Reserved
2-0 RESERVED R 0h Reserved

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3.16.9.2 PARTIDH Register (Offset = Ah) [Reset = 09XX0500h]

PARTIDH is shown in Figure 3-86 and described in Table 3-108.
Return to the Summary Table.
Upper 32-bit of Device PART Identification Number
Figure 3-86. PARTIDH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEVICE_CLASS_ID PARTNO
R-9h R-XXh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAMILY RESERVED RESERVED
R-5h R-0h R-0h

Table 3-108. PARTIDH Register Field Descriptions

Bit Field Type Reset Description
31-24 DEVICE_CLASS_ID R 9h Device class ID
Reset type: PORESETn
23-16 PARTNO R XXh Refer to Datasheet for Device Part Number
Reset type: PORESETn
15-8 FAMILY R 5h Device Family
Reset type: PORESETn
7-4 RESERVED R 0h Reserved
3-0 RESERVED R 0h Reserved

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3.16.9.3 REVID Register (Offset = Ch) [Reset = 00000000h]

REVID is shown in Figure 3-87 and described in Table 3-109.
Return to the Summary Table.
Device Revision Number
Figure 3-87. REVID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVID_EXT REVID
R-0h R/WOnce-0h

Table 3-109. REVID Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 REVID_EXT R 0h Device Revision ID extension.
Reset type: XRSn
7-0 REVID R/WOnce 0h Device Revision ID. Loaded from flash trim sector by boot rom.
Reset value is die-specific.
Reset type: XRSn

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3.16.9.4 TRIMERRSTS Register (Offset = 74h) [Reset = 00000000h]

TRIMERRSTS is shown in Figure 3-88 and described in Table 3-110.
Return to the Summary Table.
TRIM Error Status register
Figure 3-88. TRIMERRSTS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LERR
R-0-0h R/WSonce-0h

Table 3-110. TRIMERRSTS Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-0 LERR R/WSonce 0h TRIM information load error status. This will include error during
SRAM repair also.
00000: No error during load
Other: Non zero value indicates error during load
Note:
[1] This bit is updated by software. Details will be filled in once the
Boot ROM related requirements are complete. It should have bits to
indicate
(i) Double bit error during trim load
(ii) Single bit error during trim load
(iii) Double bit error during SRAM repair load
(iv) Single bit error error during SRAM repair load
(v) SRAM repair error load (chain is broken)
(vi) PWRUPSTS.TRIMOVER signal is not asserted even after the full
wait time
Reset type: XRSn

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3.16.9.5 SOFTPRES0 Register (Offset = 82h) [Reset = 00000000h]

SOFTPRES0 is shown in Figure 3-89 and described in Table 3-111.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-89. SOFTPRES0 Register
31 30 29 28 27 26 25 24
RESERVED CPU1_ERAD
R-0-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED CPU1_CLA1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-111. SOFTPRES0 Register Field Descriptions

Bit Field Type Reset Description
31-25 RESERVED R-0 0h Reserved
24 CPU1_ERAD R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
23-16 RESERVED R-0 0h Reserved
15 RESERVED R-0 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 CPU1_CLA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.6 SOFTPRES2 Register (Offset = 86h) [Reset = 00000000h]

SOFTPRES2 is shown in Figure 3-90 and described in Table 3-112.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-90. SOFTPRES2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-112. SOFTPRES2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 EPWM12 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
10 EPWM11 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
9 EPWM10 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
8 EPWM9 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
7 EPWM8 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
6 EPWM7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
5 EPWM6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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Table 3-112. SOFTPRES2 Register Field Descriptions (continued)

Bit Field Type Reset Description
4 EPWM5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
3 EPWM4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
2 EPWM3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 EPWM2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 EPWM1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.7 SOFTPRES3 Register (Offset = 88h) [Reset = 00000000h]

SOFTPRES3 is shown in Figure 3-91 and described in Table 3-113.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-91. SOFTPRES3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-113. SOFTPRES3 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 ECAP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 ECAP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.8 SOFTPRES4 Register (Offset = 8Ah) [Reset = 00000000h]

SOFTPRES4 is shown in Figure 3-92 and described in Table 3-114.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-92. SOFTPRES4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-114. SOFTPRES4 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 EQEP3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 EQEP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Note: This bit is applicable only for Topoauto
Reset type: SYSRSn
0 EQEP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.9 SOFTPRES7 Register (Offset = 90h) [Reset = 00000000h]

SOFTPRES7 is shown in Figure 3-93 and described in Table 3-115.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-93. SOFTPRES7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-115. SOFTPRES7 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 SCI_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 SCI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 SCI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.10 SOFTPRES8 Register (Offset = 92h) [Reset = 00000000h]

SOFTPRES8 is shown in Figure 3-94 and described in Table 3-116.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-94. SOFTPRES8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-116. SOFTPRES8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SPI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 SPI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.11 SOFTPRES9 Register (Offset = 94h) [Reset = 00000000h]

SOFTPRES9 is shown in Figure 3-95 and described in Table 3-117.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-95. SOFTPRES9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-117. SOFTPRES9 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 I2C_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.12 SOFTPRES10 Register (Offset = 96h) [Reset = 000000X0h]

SOFTPRES10 is shown in Figure 3-96 and described in Table 3-118.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-96. SOFTPRES10 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED MCAN_B MCAN_A RESERVED RESERVED RESERVED RESERVED
R-Xh R-Xh R-Xh R-Xh R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-118. SOFTPRES10 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R Xh Reserved
6 RESERVED R Xh Reserved
5 MCAN_B R Xh 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
4 MCAN_A R Xh 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Note: This bit is applicable only for Topoauto
Reset type: SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.9.13 SOFTPRES11 Register (Offset = 98h) [Reset = 00000000h]

SOFTPRES11 is shown in Figure 3-97 and described in Table 3-119.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-97. SOFTPRES11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

Table 3-119. SOFTPRES11 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 USB_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
15-2 RESERVED R-0 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.9.14 SOFTPRES13 Register (Offset = 9Ch) [Reset = 00000000h]

SOFTPRES13 is shown in Figure 3-98 and described in Table 3-120.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-98. SOFTPRES13 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_E ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-120. SOFTPRES13 Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R-0 0h Reserved
4 ADC_E R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
3 ADC_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
2 ADC_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 ADC_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 ADC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.15 SOFTPRES14 Register (Offset = 9Eh) [Reset = 00000000h]

SOFTPRES14 is shown in Figure 3-99 and described in Table 3-121.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-99. SOFTPRES14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-121. SOFTPRES14 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 CMPSS4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
2 CMPSS3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 CMPSS2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 CMPSS1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.16 SOFTPRES15 Register (Offset = A0h) [Reset = 00000000h]

SOFTPRES15 is shown in Figure 3-100 and described in Table 3-122.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-100. SOFTPRES15 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED PGA3 PGA2 PGA1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-122. SOFTPRES15 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 PGA3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 PGA2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 PGA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.17 SOFTPRES16 Register (Offset = A2h) [Reset = 00000000h]

SOFTPRES16 is shown in Figure 3-101 and described in Table 3-123.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-101. SOFTPRES16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-123. SOFTPRES16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 DAC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.9.18 SOFTPRES17 Register (Offset = A4h) [Reset = 0000000Xh]

SOFTPRES17 is shown in Figure 3-102 and described in Table 3-124.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-102. SOFTPRES17 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CLB2 CLB1
R-0h R/W-0h R/W-0h R-Xh R-Xh

Table 3-124. SOFTPRES17 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 CLB2 R Xh 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 CLB1 R Xh 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.19 SOFTPRES18 Register (Offset = A6h) [Reset = 0000000Xh]

SOFTPRES18 is shown in Figure 3-103 and described in Table 3-125.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-103. SOFTPRES18 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED FSIRX_A FSITX_A
R-0h R/W-0h R/W-0h R-Xh R-Xh

Table 3-125. SOFTPRES18 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 FSIRX_A R Xh 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 FSITX_A R Xh 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.20 SOFTPRES19 Register (Offset = A8h) [Reset = 00000000h]

SOFTPRES19 is shown in Figure 3-104 and described in Table 3-126.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-104. SOFTPRES19 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED LIN_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-126. SOFTPRES19 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 LIN_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Note: This bit is applicable only for Topoauto
Reset type: SYSRSn

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3.16.9.21 SOFTPRES20 Register (Offset = AAh) [Reset = X0000000h]

SOFTPRES20 is shown in Figure 3-105 and described in Table 3-127.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-105. SOFTPRES20 Register
31 30 29 28 27 26 25 24
RESERVED
R-Xh

23 22 21 20 19 18 17 16
RESERVED
R-Xh

15 14 13 12 11 10 9 8
RESERVED
R-Xh

7 6 5 4 3 2 1 0
RESERVED RESERVED PMBUS_A
R-Xh R-Xh R-Xh

Table 3-127. SOFTPRES20 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R Xh Reserved
1 RESERVED R Xh Reserved
0 PMBUS_A R Xh 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.22 SOFTPRES21 Register (Offset = ACh) [Reset = 00000000h]

SOFTPRES21 is shown in Figure 3-106 and described in Table 3-128.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-106. SOFTPRES21 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DCC1 DCC0
R-0-0h R/W-0h R/W-0h

Table 3-128. SOFTPRES21 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 DCC1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 DCC0 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.23 SOFTPRES26 Register (Offset = B6h) [Reset = 00000000h]

SOFTPRES26 is shown in Figure 3-107 and described in Table 3-129.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-107. SOFTPRES26 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED AESA
R-0-0h R/W-0h

Table 3-129. SOFTPRES26 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 AESA R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.24 SOFTPRES27 Register (Offset = B8h) [Reset = 00000000h]

SOFTPRES27 is shown in Figure 3-108 and described in Table 3-130.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-108. SOFTPRES27 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EPG1
R-0-0h R/W-0h

Table 3-130. SOFTPRES27 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 EPG1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.25 SOFTPRES28 Register (Offset = BAh) [Reset = 00000000h]

SOFTPRES28 is shown in Figure 3-109 and described in Table 3-131.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-109. SOFTPRES28 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED FLASHA
R-0-0h R/W-0h

Table 3-131. SOFTPRES28 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 FLASHA R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Note: Whenever the reset to flash is asserted, it will be internally
stretched to ~15us
Reset type: SYSRSn

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3.16.9.26 SOFTPRES30 Register (Offset = BEh) [Reset = 00000000h]

SOFTPRES30 is shown in Figure 3-110 and described in Table 3-132.
Return to the Summary Table.
NPU Software reset register
Figure 3-110. SOFTPRES30 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NPU
R-0-0h R/W-0h

Table 3-132. SOFTPRES30 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 NPU R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.9.27 SOFTPRES40 Register (Offset = D2h) [Reset = 00000000h]

SOFTPRES40 is shown in Figure 3-111 and described in Table 3-133.
Return to the Summary Table.
Peripheral Software Reset register
The Reset bit in this register needs to be set along with valid Key to ensure that JTAG nTRST is asserted. This is
auto clear register.
Figure 3-111. SOFTPRES40 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JTAG_nTRST_Key
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED JTAG_nTRST
R-0-0h R/W-0h

Table 3-133. SOFTPRES40 Register Field Descriptions

Bit Field Type Reset Description
31-16 JTAG_nTRST_Key R-0/W 0h 0xdcaf : Writing this Key value along with 0xA in JTAG_nTRST field
causes a JTAG nTRST pulse generated to the JTAG state machine.
Any other write does not have impact on the JTAG state machine,
bits are self clear when Reset is asserted to JTAG state machine.
Reset type: SYSRSn, TRSTn
15-4 RESERVED R-0 0h Reserved
3-0 JTAG_nTRST R/W 0h 1010: Writing '1010' along with valid key in JTAG_nTRST_Key takes
JTAG TAP to TLR state. Writing any other value or mismatched key
does not have any effect on the JTAG TAP reset behavior.
Once Reset to JTAG domain is asserted then this field is reset back
to 0.
Reset type: SYSRSn, TRSTn

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3.16.9.28 TAP_STATUS Register (Offset = 130h) [Reset = 00000000h]

TAP_STATUS is shown in Figure 3-112 and described in Table 3-134.
Return to the Summary Table.
Status of JTAG State machine & Debugger Connect
Figure 3-112. TAP_STATUS Register
31 30 29 28 27 26 25 24
DCON RESERVED
R-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
TAP_STATE
R-0h

7 6 5 4 3 2 1 0
TAP_STATE
R-0h

Table 3-134. TAP_STATUS Register Field Descriptions

Bit Field Type Reset Description
31 DCON R 0h DebugConnect indication from IcePick.
Reset type: PORESETn
30-16 RESERVED R-0 0h Reserved
15-0 TAP_STATE R 0h TAP State Vector. With bits representing, Connect coresponding
POTAP* output to the
0x0001:TLR,
0x0002:IDLE,
0x0004:SELECTDR,
0x0008:CAPDR,
0x0010:SHIFTDR,
0x0020:EXIT1DR,
0x0040:PAUSEDR,
0x0080:EXIT2DR,
0x0100:UPDTDR,
0x0200:SLECTIR,
0x0400:CAPIR,
0x0800:SHIFTIR,
0x1000:EXIT1IR,
0x2000:PAUSEIR,
0x4000:EXIT2IR,
0x8000:UPDTIR
Reset type: PORESETn

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3.16.9.29 TAP_CONTROL Register (Offset = 132h) [Reset = 00000000h]

TAP_CONTROL is shown in Figure 3-113 and described in Table 3-135.
Return to the Summary Table.
Disable TAP control
Figure 3-113. TAP_CONTROL Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED BSCAN_DIS
R-0-0h R/W-0h

Table 3-135. TAP_CONTROL Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY
matches). 16-bit writes to the upper or lower half of this register will
be ignored
Reset type: PORESETn
15-1 RESERVED R-0 0h Reserved
0 BSCAN_DIS R/W 0h Disables BSCAN TAP control :
0: BSCAN TAP control enabled
1: BSCAN TAP control disabled
Reset type: PORESETn

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3.16.9.30 USBTYPE Register (Offset = 19Ah) [Reset = 0000h]

USBTYPE is shown in Figure 3-114 and described in Table 3-136.
Return to the Summary Table.
Based on the configuration enables disables features associated with the USB type.
Figure 3-114. USBTYPE Register
15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-136. USBTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: CPU1.SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h '00,10,11' :
1. Global interrupt feature is not enabled, interrupts fired
unconditionally.
'01' :
1.Global interrupt feature is enabled, refer to the spec doc for more
details about global interrupt feature.
Reset type: CPU1.SYSRSn

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3.16.9.31 ECAPTYPE Register (Offset = 19Bh) [Reset = 0000h]

ECAPTYPE is shown in Figure 3-115 and described in Table 3-137.
Return to the Summary Table.
Based on the configuration enables disables features associated with the ECAP type.
Figure 3-115. ECAPTYPE Register
15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-137. ECAPTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h '00,10,11' :
1. No EALLOW protection to ECAP registers.
'01' :
1. ECAP registers are EALLOW protected.
Reset type: SYSRSn

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3.16.9.32 MCUCNF3 Register (Offset = 1A6h) [Reset = 0000XXXXh]

MCUCNF3 is shown in Figure 3-116 and described in Table 3-138.
Return to the Summary Table.
MCU Configuration: ETPWM
Figure 3-116. MCUCNF3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPWM12 EPWM11 EPWM10 EPWM9
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-138. MCUCNF3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R Xh Reserved
14 RESERVED R Xh Reserved
13 RESERVED R Xh Reserved
12 RESERVED R Xh Reserved
11 EPWM12 R Xh EPWM12 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
10 EPWM11 R Xh EPWM11 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
9 EPWM10 R Xh EPWM10 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
8 EPWM9 R Xh EPWM9 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
7 EPWM8 R Xh EPWM8 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
6 EPWM7 R Xh EPWM7 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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Table 3-138. MCUCNF3 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 EPWM6 R Xh EPWM6 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
4 EPWM5 R Xh EPWM5 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
3 EPWM4 R Xh EPWM4 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
2 EPWM3 R Xh EPWM3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
1 EPWM2 R Xh EPWM2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
0 EPWM1 R Xh EPWM1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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3.16.9.33 MCUCNF8 Register (Offset = 1B0h) [Reset = 0000000Xh]

MCUCNF8 is shown in Figure 3-117 and described in Table 3-139.
Return to the Summary Table.
MCU Configuration: SCI
Figure 3-117. MCUCNF8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SCI_C SCI_B SCI_A
R-0-0h R-Xh R-Xh R-Xh R-Xh

Table 3-139. MCUCNF8 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R Xh Reserved
2 SCI_C R Xh SCI_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
1 SCI_B R Xh SCI_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
0 SCI_A R Xh SCI_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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3.16.9.34 MCUCNF11 Register (Offset = 1B6h) [Reset = 000000XXh]

MCUCNF11 is shown in Figure 3-118 and described in Table 3-140.
Return to the Summary Table.
MCU Configuration: CAN
Figure 3-118. MCUCNF11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED MCAN_B MCAN_A RESERVED RESERVED RESERVED RESERVED
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-140. MCUCNF11 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R Xh Reserved
6 RESERVED R Xh Reserved
5 MCAN_B R Xh MCAN_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
4 MCAN_A R Xh MCAN_A :
0: Feature not present on the device
1: Feature present on the device
Note: This bit is applicable only for Topoauto
Reset type: PORESETn
3 RESERVED R Xh Reserved
2 RESERVED R Xh Reserved
1 RESERVED R Xh Reserved
0 RESERVED R Xh Reserved

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3.16.9.35 MCUCNF12 Register (Offset = 1B8h) [Reset = 000X000Xh]

MCUCNF12 is shown in Figure 3-119 and described in Table 3-141.
Return to the Summary Table.
MCU Configuration: McBSP_USB
Figure 3-119. MCUCNF12 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED USB_A
R-0-0h R-Xh R-0-0h R-Xh

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
R-0-0h R-Xh R-Xh

Table 3-141. MCUCNF12 Register Field Descriptions

Bit Field Type Reset Description
31-19 RESERVED R-0 0h Reserved
18 RESERVED R Xh Reserved
17 RESERVED R-0 0h Reserved
16 USB_A R Xh USB_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
15-2 RESERVED R-0 0h Reserved
1 RESERVED R Xh Reserved
0 RESERVED R Xh Reserved

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3.16.9.36 MCUCNF14 Register (Offset = 1BCh) [Reset = 000000XXh]

MCUCNF14 is shown in Figure 3-120 and described in Table 3-142.
Return to the Summary Table.
MCU Configuration: ADC
Figure 3-120. MCUCNF14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_E ADC_D ADC_C ADC_B ADC_A
R-0-0h R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-142. MCUCNF14 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-5 RESERVED R-0 0h Reserved
4 ADC_E R Xh ADC_E :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
3 ADC_D R Xh ADC_D :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
2 ADC_C R Xh ADC_C :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
1 ADC_B R Xh ADC_B :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
0 ADC_A R Xh ADC_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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3.16.9.37 MCUCNF16 Register (Offset = 1C0h) [Reset = 000000XXh]

MCUCNF16 is shown in Figure 3-121 and described in Table 3-143.
Return to the Summary Table.
MCU Configuration: PGA
Figure 3-121. MCUCNF16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED PGA3 PGA2 PGA1
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-143. MCUCNF16 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R Xh Reserved
6 RESERVED R Xh Reserved
5 RESERVED R Xh Reserved
4 RESERVED R Xh Reserved
3 RESERVED R Xh Reserved
2 PGA3 R Xh PGA3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
1 PGA2 R Xh PGA2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
0 PGA1 R Xh PGA1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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3.16.9.38 MCUCNF18 Register (Offset = 1C4h) [Reset = 00000XXXh]

MCUCNF18 is shown in Figure 3-122 and described in Table 3-144.
Return to the Summary Table.
MCU Configuration: Lx.1 SRAM Customization
Figure 3-122. MCUCNF18 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED LS9_1 LS8_1
R-0-0h R-Xh R-Xh

7 6 5 4 3 2 1 0
LS7_1 LS6_1 LS5_1 LS4_1 LS3_1 LS2_1 LS1_1 LS0_1
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-144. MCUCNF18 Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R-0 0h Reserved
9 LS9_1 R Xh LS9_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
8 LS8_1 R Xh LS8_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
7 LS7_1 R Xh LS7_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
6 LS6_1 R Xh LS6_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
5 LS5_1 R Xh LS5_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
4 LS4_1 R Xh LS4_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
3 LS3_1 R Xh LS3_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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Table 3-144. MCUCNF18 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 LS2_1 R Xh LS2_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
1 LS1_1 R Xh LS1_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
0 LS0_1 R Xh LS0_1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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3.16.9.39 MCUCNF20 Register (Offset = 1C8h) [Reset = 0000XXXXh]

MCUCNF20 is shown in Figure 3-123 and described in Table 3-145.
Return to the Summary Table.
MCU Configuration: GSx SRAM Customization
Figure 3-123. MCUCNF20 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED GS3 GS2 GS1 GS0
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-145. MCUCNF20 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R Xh Reserved
14 RESERVED R Xh Reserved
13 RESERVED R Xh Reserved
12 RESERVED R Xh Reserved
11 RESERVED R Xh Reserved
10 RESERVED R Xh Reserved
9 RESERVED R Xh Reserved
8 RESERVED R Xh Reserved
7 RESERVED R Xh Reserved
6 RESERVED R Xh Reserved
5 RESERVED R Xh Reserved
4 RESERVED R Xh Reserved
3 GS3 R Xh GS3 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
2 GS2 R Xh GS2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
1 GS1 R Xh GS1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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Table 3-145. MCUCNF20 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 GS0 R Xh GS0 :
0: Feature not present on the device
1: Feature present on the device
Note: This applies to upper 8KB of GS0 only. Lower 8KB is always
available and not affected by this bit value.
Reset type: PORESETn

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3.16.9.40 MCUCNF21 Register (Offset = 1CAh) [Reset = X0000000h]

MCUCNF21 is shown in Figure 3-124 and described in Table 3-146.
Return to the Summary Table.
MCU Configuration: CLB
Figure 3-124. MCUCNF21 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CLB2 CLB1
R-0h R-Xh R-Xh R-Xh R-Xh

Table 3-146. MCUCNF21 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 RESERVED R Xh Reserved
2 RESERVED R Xh Reserved
1 CLB2 R Xh CLB2 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn
0 CLB1 R Xh CLB1 :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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3.16.9.41 MCUCNF23 Register (Offset = 1CEh) [Reset = X0000000h]

MCUCNF23 is shown in Figure 3-125 and described in Table 3-147.
Return to the Summary Table.
MCU Configuration: LIN
Figure 3-125. MCUCNF23 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED LIN_A
R-0h R-Xh R-Xh R-Xh R-Xh

Table 3-147. MCUCNF23 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 RESERVED R Xh Reserved
2 RESERVED R Xh Reserved
1 RESERVED R Xh Reserved
0 LIN_A R Xh LIN_A :
0: Feature not present on the device
1: Feature present on the device
Reset type: PORESETn

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3.16.9.42 MCUCNF31 Register (Offset = 1DEh) [Reset = 000000XXh]

MCUCNF31 is shown in Figure 3-126 and described in Table 3-148.
Return to the Summary Table.
MCU Configuration: Flash Bank0
Figure 3-126. MCUCNF31 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
SECT127_112 SECT111_96 SECT95_80 SECT79_64 SECT63_48 SECT47_32 SECT31_16 SECT15_0
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-148. MCUCNF31 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 SECT127_112 R Xh Flash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
6 SECT111_96 R Xh Flash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
5 SECT95_80 R Xh Flash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
4 SECT79_64 R Xh Flash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
3 SECT63_48 R Xh Flash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
2 SECT47_32 R Xh Flash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
1 SECT31_16 R Xh Flash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn

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Table 3-148. MCUCNF31 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 SECT15_0 R Xh Flash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn

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3.16.9.43 MCUCNF32 Register (Offset = 1E0h) [Reset = 000000XXh]

MCUCNF32 is shown in Figure 3-127 and described in Table 3-149.
Return to the Summary Table.
MCU Configuration: Flash Bank1
Figure 3-127. MCUCNF32 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
SECT127_112 SECT111_96 SECT95_80 SECT79_64 SECT63_48 SECT47_32 SECT31_16 SECT15_0
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-149. MCUCNF32 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 SECT127_112 R Xh Flash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
6 SECT111_96 R Xh Flash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
5 SECT95_80 R Xh Flash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
4 SECT79_64 R Xh Flash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
3 SECT63_48 R Xh Flash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
2 SECT47_32 R Xh Flash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
1 SECT31_16 R Xh Flash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn

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Table 3-149. MCUCNF32 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 SECT15_0 R Xh Flash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn

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3.16.9.44 MCUCNF33 Register (Offset = 1E2h) [Reset = 000000XXh]

MCUCNF33 is shown in Figure 3-128 and described in Table 3-150.
Return to the Summary Table.
MCU Configuration: Flash Bank2
Figure 3-128. MCUCNF33 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
SECT127_112 SECT111_96 SECT95_80 SECT79_64 SECT63_48 SECT47_32 SECT31_16 SECT15_0
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-150. MCUCNF33 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 SECT127_112 R Xh Flash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
6 SECT111_96 R Xh Flash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
5 SECT95_80 R Xh Flash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
4 SECT79_64 R Xh Flash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
3 SECT63_48 R Xh Flash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
2 SECT47_32 R Xh Flash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
1 SECT31_16 R Xh Flash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn

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Table 3-150. MCUCNF33 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 SECT15_0 R Xh Flash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn

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3.16.9.45 MCUCNF34 Register (Offset = 1E4h) [Reset = 000000XXh]

MCUCNF34 is shown in Figure 3-129 and described in Table 3-151.
Return to the Summary Table.
MCU Configuration: Flash Bank3
Figure 3-129. MCUCNF34 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
SECT127_112 SECT111_96 SECT95_80 SECT79_64 SECT63_48 SECT47_32 SECT31_16 SECT15_0
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-151. MCUCNF34 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 SECT127_112 R Xh Flash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
6 SECT111_96 R Xh Flash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
5 SECT95_80 R Xh Flash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
4 SECT79_64 R Xh Flash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
3 SECT63_48 R Xh Flash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
2 SECT47_32 R Xh Flash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
1 SECT31_16 R Xh Flash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn

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Table 3-151. MCUCNF34 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 SECT15_0 R Xh Flash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn

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3.16.9.46 MCUCNF35 Register (Offset = 1E6h) [Reset = 000000XXh]

MCUCNF35 is shown in Figure 3-130 and described in Table 3-152.
Return to the Summary Table.
MCU Configuration: Flash Bank4
Figure 3-130. MCUCNF35 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SECT31_16 SECT15_0
R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh R-Xh

Table 3-152. MCUCNF35 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R Xh Reserved
6 RESERVED R Xh Reserved
5 RESERVED R Xh Reserved
4 RESERVED R Xh Reserved
3 RESERVED R Xh Reserved
2 RESERVED R Xh Reserved
1 SECT31_16 R Xh Flash Bank-4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn
0 SECT15_0 R Xh Flash Bank-4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device
Reset type: PORESETn

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3.16.9.47 MCUCNFLOCK Register (Offset = 1F8h) [Reset = 00000000h]

MCUCNFLOCK is shown in Figure 3-131 and described in Table 3-153.
Return to the Summary Table.
Lock bit for MCUCNFx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
Figure 3-131. MCUCNFLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED MCUCNFLOCK
R-0-0h R/WSonce-0h

Table 3-153. MCUCNFLOCK Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 MCUCNFLOCK R/WSonce 0h Lock bit for all MCUCNF registers:
0: Registers are not locked
1: Register are locked
Reset type: CPU1.SYSRSn

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3.16.10 CLK_CFG_REGS Registers

Table 3-154 lists the memory-mapped registers for the CLK_CFG_REGS registers. All register offset addresses
not listed in Table 3-154 should be considered as reserved locations and the register contents should not be
modified.
Table 3-154. CLK_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
2h CLKCFGLOCK1 Lock bit for CLKCFG registers EALLOW Go
8h CLKSRCCTL1 Clock Source Control register-1 EALLOW Go
Ah CLKSRCCTL2 Clock Source Control register-2 EALLOW Go
Ch CLKSRCCTL3 Clock Source Control register-3 EALLOW Go
Eh SYSPLLCTL1 SYSPLL Control register-1 EALLOW Go
14h SYSPLLMULT SYSPLL Multiplier register EALLOW Go
16h SYSPLLSTS SYSPLL Status register Go
22h SYSCLKDIVSEL System Clock Divider Select register EALLOW Go
24h AUXCLKDIVSEL Auxillary Clock Divider Select register EALLOW Go
26h PERCLKDIVSEL Peripheral Clock Divider Select register EALLOW Go
28h XCLKOUTDIVSEL XCLKOUT Divider Select register EALLOW Go
2Ah CLBCLKCTL CLB Clocking Control Register EALLOW Go
2Ch LOSPCP Low Speed Clock Source Prescalar EALLOW Go
2Eh MCDCR Missing Clock Detect Control Register EALLOW Go
30h X1CNT 10-bit Counter on X1 Clock Go
32h XTALCR XTAL Control Register EALLOW Go
3Ah XTALCR2 XTAL Control Register for pad init EALLOW Go
3Ch CLKFAILCFG Clock Fail cause Configuration EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-155 shows the codes that are used for
access types in this section.
Table 3-155. CLK_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables

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Table 3-155. CLK_CFG_REGS Access Type Codes (continued)

Access Type Code Description
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.10.1 CLKCFGLOCK1 Register (Offset = 2h) [Reset = 00000000h]

CLKCFGLOCK1 is shown in Figure 3-132 and described in Table 3-156.
Return to the Summary Table.
Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-132. CLKCFGLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED EXTRFLTDET XTALCR
R-0-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
LOSPCP CLBCLKCTL PERCLKDIVSE AUXCLKDIVSE SYSCLKDIVSE RESERVED RESERVED RESERVED
L L L
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R-0-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED SYSPLLMULT RESERVED RESERVED SYSPLLCTL1 CLKSRCCTL3 CLKSRCCTL2 CLKSRCCTL1
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-156. CLKCFGLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 EXTRFLTDET R/WSonce 0h Lock bit for EXTRFLTDET register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
16 XTALCR R/WSonce 0h Common Lock bit for XTALCR & XTAL CR2 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
15 LOSPCP R/WSonce 0h Lock bit for LOSPCP register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
14 CLBCLKCTL R/WSonce 0h Lock bit for CLBCLKCTL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
13 PERCLKDIVSEL R/WSonce 0h Lock bit for PERCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
12 AUXCLKDIVSEL R/WSonce 0h Lock bit for AUXCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-156. CLKCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
11 SYSCLKDIVSEL R/WSonce 0h Lock bit for SYSCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
10 RESERVED R/WSonce 0h Reserved
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 RESERVED R/WSonce 0h Reserved
6 SYSPLLMULT R/WSonce 0h Lock bit for SYSPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
5 RESERVED R/WSonce 0h Reserved
4 RESERVED R/WSonce 0h Reserved
3 SYSPLLCTL1 R/WSonce 0h Lock bit for SYSPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
2 CLKSRCCTL3 R/WSonce 0h Lock bit for CLKSRCCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
1 CLKSRCCTL2 R/WSonce 0h Lock bit for CLKSRCCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
0 CLKSRCCTL1 R/WSonce 0h Lock bit for CLKSRCCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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3.16.10.2 CLKSRCCTL1 Register (Offset = 8h) [Reset = 00000000h]

CLKSRCCTL1 is shown in Figure 3-133 and described in Table 3-157.
Return to the Summary Table.
Clock Source Control register-1
Figure 3-133. CLKSRCCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED
R-0-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED WDHALTI RESERVED RESERVED RESERVED OSCCLKSRCSEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0-0h R/W-0h

Table 3-157. CLKSRCCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-9 RESERVED R-0 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 WDHALTI R/W 0h Watchdog HALT Mode Ignore Bit: This bit determines if WD is
functional in the HALT mode or not.
0 = WD is not functional in the HALT mode. Clock to WD is gated
when system enters HALT mode.
1 = WD is functional in the HALT mode. Clock to WD is not gated
Reset type: XRSn
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R-0 0h Reserved

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Table 3-157. CLKSRCCTL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 OSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
OSCCLK.
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = INTOSC1
11 = reserved (default to INTOSC1)
At power-up or after an XRSn, INTOSC2 is selected by default.
Whenever the user changes the clock source using these bits, the
SYSPLLMULT[13:0] register will be forced to zero and the PLL
will be bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the SYSPLLMULT
register to configure the appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to
SYSPLLMULT or disabling the previous clock source to allow the
change to
complete..
Notes:
[1] INTOSC1 is recommended to be used only after missing clock
detection. If user wants to re-lock the PLL with INTOSC1 (the
back-up clock source) after missing clock is detected, he can do a
MCLKCLR and lock the PLL.
Reset type: XRSn

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3.16.10.3 CLKSRCCTL2 Register (Offset = Ah) [Reset = 00000000h]

CLKSRCCTL2 is shown in Figure 3-134 and described in Table 3-158.
Return to the Summary Table.
Clock Source Control register-2
Figure 3-134. CLKSRCCTL2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED MCANBBCLKSEL MCANABCLKSEL RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-158. CLKSRCCTL2 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 MCANBBCLKSEL R/W 0h MCAN Bit Clock Source Select Bit:
00 = CPU1SYSCLK
01 = AUXPLLCLK (Reserved)
10 = AUXCLKIN
11 = PLLRAWCLK
Missing clock detect circuit doesnt have any impact on these bits.
Note: This bit is applicable only for Topoauto
Reset type: XRSn
11-10 MCANABCLKSEL R/W 0h MCAN Bit Clock Source Select Bit:
00 = CPU1SYSCLK
01 = AUXPLLCLK (Reserved)
10 = AUXCLKIN
11 = PLLRAWCLK
Missing clock detect circuit doesnt have any impact on these bits.
Reset type: XRSn
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 RESERVED R/W 0h Reserved
3-2 RESERVED R/W 0h Reserved
1-0 RESERVED R/W 0h Reserved

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3.16.10.4 CLKSRCCTL3 Register (Offset = Ch) [Reset = 00000000h]

CLKSRCCTL3 is shown in Figure 3-135 and described in Table 3-159.
Return to the Summary Table.
Clock Source Control register-3
Figure 3-135. CLKSRCCTL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XCLKOUTSEL
R-0-0h R/W-0h

Table 3-159. CLKSRCCTL3 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3-0 XCLKOUTSEL R/W 0h XCLKOUT Source Select Bit: This bit selects the source for
XCLKOUT:
0000 = PLLSYSCLK (default on reset)
0001 = PLLCLK
0010 = SYSCLK
0101 = INTOSC1
0110 = INTOSC2
0111 = XTAL OSC o/p clock
1001 = PUMPOSC (from no-wrapper)
1010 = SYSAPLL.CLK_AUX
1100 = SYSPLL.CLKOUT
Rest = Reserved
Reset type: SYSRSn

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3.16.10.5 SYSPLLCTL1 Register (Offset = Eh) [Reset = 00000000h]

SYSPLLCTL1 is shown in Figure 3-136 and described in Table 3-160.
Return to the Summary Table.
SYSPLL Control register-1
Figure 3-136. SYSPLLCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED PLLCLKEN PLLEN
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-160. SYSPLLCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 PLLCLKEN R/W 0h SYSPLL bypassed or included in the PLLSYSCLK path: This bit
decides if the SYSPLL is bypassed when PLLSYSCLK is generated
1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
system.
0 = SYSPLL is bypassed. Clock to system is direct feed from
OSCCLK
Reset type: XRSn
0 PLLEN R/W 0h SYSPLL enabled or disabled: This bit decides if the SYSPLL is
enabled or not
1 = SYSPLL is enabled
0 = SYSPLL is powered off. Clock to system is direct feed from
OSCCLK
Reset type: XRSn

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3.16.10.6 SYSPLLMULT Register (Offset = 14h) [Reset = 00000000h]

SYSPLLMULT is shown in Figure 3-137 and described in Table 3-161.
Return to the Summary Table.
SYSPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
Figure 3-137. SYSPLLMULT Register
31 30 29 28 27 26 25 24
RESERVED REFDIV
R-0-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED ODIV
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R-0-0h R/W-0h

7 6 5 4 3 2 1 0
IMULT
R/W-0h

Table 3-161. SYSPLLMULT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R-0 0h Reserved
28-24 REFDIV R/W 0h SYSPLL Reference Clock Divider
PLL Reference Divider = REFDIV + 1
Reset type: XRSn
23-21 RESERVED R-0 0h Reserved
20-16 ODIV R/W 0h SYSPLL Output Clock Divider
PLL Output Divider = ODIV + 1
Reset type: XRSn
15-14 RESERVED R-0 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 RESERVED R-0 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-0 IMULT R/W 0h SYSPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
Note for APLL Multiplier values from 0-3 are invalid, internally those
will be treated to 4.
Reset type: XRSn

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3.16.10.7 SYSPLLSTS Register (Offset = 16h) [Reset = 00000030h]

SYSPLLSTS is shown in Figure 3-138 and described in Table 3-162.
Return to the Summary Table.
SYSPLL Status register
Figure 3-138. SYSPLLSTS Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED REF_LOSTS RESERVED SLIPS_NOTSU LOCKS
PPORTED
R-0-0h R-1h R-1h W1C-0h R-0h R-0h R-0h

Table 3-162. SYSPLLSTS Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5 RESERVED R 1h Reserved
4 RESERVED R 1h Reserved
3 REF_LOSTS W1C 0h SYSPLL 'Reference Lost' Status Bit: This bit indicates whether the
SYSPLL is out of lock range
0 = 'Reference Lost' event has not occurred.
1 = 'Reference Lost' event has occurred.
Reset type: XRSn
2 RESERVED R 0h Reserved
1 SLIPS_NOTSUPPORTED R 0h RESERVED: This bit is reserved and the value read should be
ignored. TI recommends using DCC to evaluate SYSPLL Slip status.
Refer to InitSysPll() or SysCtl_setClock() functions inside the latest
example software from C2000Ware for checking SYSPLL Slip status
using DCC.
Reset type: XRSn
0 LOCKS R 0h SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is
locked or not
0 = SYSPLL is not yet locked
1 = SYSPLL is locked
Reset type: XRSn

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3.16.10.8 SYSCLKDIVSEL Register (Offset = 22h) [Reset = 00000000h]

SYSCLKDIVSEL is shown in Figure 3-139 and described in Table 3-163.
Return to the Summary Table.
System Clock Divider Select register
Figure 3-139. SYSCLKDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED PLLSYSCLKDI
V_LSB
R-0-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED PLLSYSCLKDIV
R-0-0h R/W-0h

Table 3-163. SYSCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-9 RESERVED R-0 0h Reserved
8 PLLSYSCLKDIV_LSB R/W 0h This bit is LSB of the Divider that when set
allows the ODD divisions such that the divider
value is {PLLSYSCLKDIV,PLLSYSCLKDIV_LSB}. E.g. if
PLLSYSCLKDIV=0x1, and PLLSYSCLKDIV_LSB=0 then divider of
2 is used else in case PLLSYSCLKDIV_LSB=1 then divider value is
3.
Reset type: XRSn
7-6 RESERVED R-0 0h Reserved
5-0 PLLSYSCLKDIV R/W 0h PLLSYSCLK Divide Select: This bit selects the divider setting for the
PLLSYSCLK.
000000 = /1
000001 = /2
000010 = /4
000011 = /6
000100 = /8
......
111111 = /126
The minimum value of this divider is 2 when PLL is enabled.
Reset type: XRSn

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3.16.10.9 AUXCLKDIVSEL Register (Offset = 24h) [Reset = 00027301h]

AUXCLKDIVSEL is shown in Figure 3-140 and described in Table 3-164.
Return to the Summary Table.
Auxillary Clock Divider Select register
Figure 3-140. AUXCLKDIVSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED MCANBCLKDIV
R-0-0h R/W-13h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCANBCLKDIV MCANACLKDIV RESERVED RESERVED
R/W-13h R/W-13h R-0-0h R/W-1h

Table 3-164. AUXCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17-13 MCANBCLKDIV R/W 13h 00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd
Reset type: XRSn
12-8 MCANACLKDIV R/W 13h 00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd
Reset type: XRSn
7-3 RESERVED R-0 0h Reserved
2-0 RESERVED R/W 1h Reserved

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3.16.10.10 PERCLKDIVSEL Register (Offset = 26h) [Reset = 000104D0h]

PERCLKDIVSEL is shown in Figure 3-141 and described in Table 3-165.
Return to the Summary Table.
Peripheral Clock Divider Select register
Figure 3-141. PERCLKDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED NPUCLKDIV
R-0-0h R/W-1h

15 14 13 12 11 10 9 8
LINACLKDIV USBCLKDIV
R/W-1h R/W-1h

7 6 5 4 3 2 1 0
USBCLKDIV RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R-0-0h R/W-1h R/W-0h R/W-0h

Table 3-165. PERCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-17 RESERVED R-0 0h Reserved
16 NPUCLKDIV R/W 1h NPU Clock Divide Select: This bit selects whether the NPU module
run with a /1 or /2 clock.
0: /1 of SYSCLK is selected
1: /2 of SYSCLK is selected
Reset type: SYSRSn
15-10 LINACLKDIV R/W 1h LINA Clock Divide Select: This bit selects whether the LINA module
run with a /1, /2, or /4 clock.
00: /1 of SYSCLK is selected
01: /2 of SYSCLK is selected
10: /4 of SYSCLK is selected
11: Reserved
Reset type: SYSRSn
9-7 USBCLKDIV R/W 1h USB Clock Divide select.
000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Reset type: SYSRSn
6 RESERVED R/W 1h Reserved
5 RESERVED R-0 0h Reserved
4 RESERVED R/W 1h Reserved
3-2 RESERVED R/W 0h Reserved
1-0 RESERVED R/W 0h Reserved

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3.16.10.11 XCLKOUTDIVSEL Register (Offset = 28h) [Reset = 00000003h]

XCLKOUTDIVSEL is shown in Figure 3-142 and described in Table 3-166.
Return to the Summary Table.
XCLKOUT Divider Select register
Figure 3-142. XCLKOUTDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED XCLKOUTDIV
R-0-0h R/W-3h

Table 3-166. XCLKOUTDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1-0 XCLKOUTDIV R/W 3h XCLKOUT Divide Select: This bit selects the divider setting for the
XCLKOUT.
00 = /1
01 = /2
10 = /4
11 = /8 (default on reset)
Reset type: SYSRSn

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3.16.10.12 CLBCLKCTL Register (Offset = 2Ah) [Reset = 00000007h]

CLBCLKCTL is shown in Figure 3-143 and described in Table 3-167.
Return to the Summary Table.
CLB Clocking Control Register
Figure 3-143. CLBCLKCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED CLKMODECLB CLKMODECLB
2 1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED TILECLKDIV RESERVED CLBCLKDIV
R-0-0h R/W-0h R-0-0h R/W-7h

Table 3-167. CLBCLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 CLKMODECLB2 R/W 0h 0 : CLB2 is synchronous to SYSCLK
1 : CLB2 runs of asynchronous clock
Reset type: SYSRSn
16 CLKMODECLB1 R/W 0h 0 : CLB1 is synchronous to SYSCLK
1 : CLB1 runs of asynchronous clock
Reset type: SYSRSn
15-5 RESERVED R-0 0h Reserved
4 TILECLKDIV R/W 0h 0: /1
1: /2
Reset type: SYSRSn
3 RESERVED R-0 0h Reserved
2-0 CLBCLKDIV R/W 7h 000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Reset type: SYSRSn

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3.16.10.13 LOSPCP Register (Offset = 2Ch) [Reset = 00000002h]

LOSPCP is shown in Figure 3-144 and described in Table 3-168.
Return to the Summary Table.
Low Speed Clock Source Prescalar
Figure 3-144. LOSPCP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LSPCLKDIV
R-0-0h R/W-2h

Table 3-168. LOSPCP Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
2-0 LSPCLKDIV R/W 2h These bits configure the low-speed peripheral clock (LSPCLK) rate
000,LSPCLK = / 1
001,LSPCLK = / 2
010,LSPCLK = / 4 (default on reset)
011,LSPCLK = / 6
100,LSPCLK = / 8
101,LSPCLK = / 10
110,LSPCLK = / 12
111,LSPCLK = / 14
Note:
[1] This clock is used as strobe for the SCI and SPI modules.
Reset type: SYSRSn

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3.16.10.14 MCDCR Register (Offset = 2Eh) [Reset = 00006000h]

MCDCR is shown in Figure 3-145 and described in Table 3-169.
Return to the Summary Table.
Missing Clock Detect Control Register
Figure 3-145. MCDCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-1h R/W-1h R/W-0h R-0/W1S-0h R-0h R/W-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED SYSREF_LOST SYSREF_LOST SYSREF_LOST OSCOFF MCLKOFF MCLKCLR MCLKSTS
_MCD_EN SCLR S
R-0h R/W-0h R-0/W1S-0h R-0h R/W-0h R/W-0h R-0/W1S-0h R-0h

Table 3-169. MCDCR Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R-0 0h Reserved
14 RESERVED R/W 1h Reserved
13 RESERVED R/W 1h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R 0h Reserved
6 SYSREF_LOST_MCD_E R/W 0h Control to add 'PLL reference clock lost' as cause for MCD
N 0 = 'PLL reference clock Lost' does not affect MCD.
1 = Upon 'PLL reference clock Lost' MCD is asserted.
Reset type: XRSn
5 SYSREF_LOSTSCLR R-0/W1S 0h Clears the REF_LOST_STS from PLLSTS which is root for MCD
trigger.
0 = No effect on present state of the REF_LOST_STS
1 = Clears the REF_LOST_STS bit to '0'. Bit clears itself after clear
pulse to REF_LOST_STS.
Read always gives '0'.
Reset type: XRSn
4 SYSREF_LOSTS R 0h SYSPLL 'Reference Lost' Status Bit: This bit indicates whether the
SYSPLL is out of lock range
0 = 'Reference Lost' event has not occurred.
1 = 'Reference Lost' event has occurred.
Reset type: XRSn
3 OSCOFF R/W 0h Oscillator Clock Disconnect from MCD Bit:
0 = OSCCLK Connected to OSCCLK Counter in MCD module
1 = OSCCLK Disconnected to OSCCLK Counter in MCD module
Reset type: XRSn

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Table 3-169. MCDCR Register Field Descriptions (continued)

Bit Field Type Reset Description
2 MCLKOFF R/W 0h Missing Clock Detect Off Bit:
0 = Missing Clock Detect Circuit Enabled
1 = Missing Clock Detect Circuit Disabled
Reset type: XRSn
1 MCLKCLR R-0/W1S 0h Missing Clock Clear Bit:
Write 1' to this bit to clear MCLKSTS bit and reset the missing clock
detect circuit.'
Reset type: XRSn
0 MCLKSTS R 0h Missing Clock Status Bit:
0 = OSCCLK Is OK
1 = OSCCLK Detected Missing, CLOCKFAILn Generated
Reset type: XRSn

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3.16.10.15 X1CNT Register (Offset = 30h) [Reset = 00000000h]

X1CNT is shown in Figure 3-146 and described in Table 3-170.
Return to the Summary Table.
10-bit Counter on X1 Clock
Figure 3-146. X1CNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED CLR
R-0-0h R-0/
W1C-0
h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED X1CNT
R-0-0h R-0h

Table 3-170. X1CNT Register Field Descriptions

Bit Field Type Reset Description
31-17 RESERVED R-0 0h Reserved
16 CLR R-0/W1C 0h X1 Counter clear:
A write of '1' to this bit field clears the X1CNT and makes it count
from 0x0 again (provided X1 clock is ticking).
Writes of '0' are ignore to this bit field
Reset type: XRSn
15-11 RESERVED R-0 0h Reserved
10-0 X1CNT R 0h X1 Counter:
- This counter increments on every X1 CLOCKs positive-edge.
- Once it reaches the values of 0x7ff, it freezes
- Before switching from INTOSC2 to X1, application must check this
counter and make sure that it has saturated. This will ensure that the
Crystal connected to X1/X2 is oscillating.
Reset type: XRSn

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3.16.10.16 XTALCR Register (Offset = 32h) [Reset = 00000005h]

XTALCR is shown in Figure 3-147 and described in Table 3-171.
Return to the Summary Table.
XTAL Control Register
Figure 3-147. XTALCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SE OSCOFF
R-0-0h R/W-1h R/W-0h R/W-1h

Table 3-171. XTALCR Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
2 RESERVED R/W 1h Reserved
1 SE R/W 0h Configures XTAL oscillator in single-ended or Crystal mode when
XTAL oscillator is powered up(i.e. OSCOFF = 0)
0 XTAL oscillator in Crystal mode
1 XTAL oscilator in single-ended mode (through X1)
Reset type: XRSn
0 OSCOFF R/W 1h This bit if '1', powers-down the XTAL oscillator macro and hence
doesn't let X2 to be driven by the XTAL oscillator. If a crystal is
connected to X1/X2, user needs to first clear this bit, wait for the
oscillator to power up (using X1CNT) and then only switch the clock
source to X1/X2
Reset type: XRSn

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3.16.10.17 XTALCR2 Register (Offset = 3Ah) [Reset = 00000003h]

XTALCR2 is shown in Figure 3-148 and described in Table 3-172.
Return to the Summary Table.
XTAL Control Register for pad init
Figure 3-148. XTALCR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FEN XOF XIF
R-0-0h R/W-0h R/W-1h R/W-1h

Table 3-172. XTALCR2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R/W 0h Reserved
15-3 RESERVED R-0 0h Reserved
2 FEN R/W 0h Configures XTAL oscillator pad initilisation.
0 : XOSC pads are not driven through GPIO connection.
1 : XOSC pads are driven through connected GPIO as per XIF &
XOF values.
This register has effect only when XOSC is OFF (no SE , no XTAL
mode).
If this register is set during XOSC off state (XOSCOFF=1 & SE=0)
then upon change of these controls this bit gets reset and rearmed.
Reset type: XRSn
1 XOF R/W 1h Polarity selection to initialise XO /X2 pad of the XOSC before start-
up
This value shall be deposited on the pad before XOSC started
(XOSCOFF=1)
If FEN=0 or XOSC is in XTAL or SE mode
then this value will not be applied to the pad.
Reset type: XRSn
0 XIF R/W 1h Polarity selection to initialise XI /X1 pad of the XOSC before start-up
This value shall be deposited on the pad before XOSC started
(XOSCOFF=1)
If FEN=0 or XOSC is in XTAL or SE mode
then this value will not be applied to the pad.
Reset type: XRSn

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3.16.10.18 CLKFAILCFG Register (Offset = 3Ch) [Reset = 00000000h]

CLKFAILCFG is shown in Figure 3-149 and described in Table 3-173.
Return to the Summary Table.
Clock Fail cause Configuration
Figure 3-149. CLKFAILCFG Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DCC1_ERROR DCC0_ERROR
_EN _EN
R-0-0h R/W-0h R/W-0h

Table 3-173. CLKFAILCFG Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 DCC1_ERROR_EN R/W 0h This field enables DCC1 Error to cause the clock-fail NMI to get
asserted.
0 : DCC1 Error does not affect Clock fail NMI
1: Occurrence of DCC1 Error triggers Clock fail NMI assertion and
ERROR pin assertion.
Reset type: XRSn
0 DCC0_ERROR_EN R/W 0h This field enables DCC0 Error to cause the clock-fail NMI to get
asserted.
0 : DCC0 Error does not affect Clock fail NMI
1: Occurrence of DCC0 Error triggers Clock fail NMI assertion and
ERROR pin assertion.
Reset type: XRSn

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3.16.11 CPU_SYS_REGS Registers

Table 3-174 lists the memory-mapped registers for the CPU_SYS_REGS registers. All register offset addresses
not listed in Table 3-174 should be considered as reserved locations and the register contents should not be
modified.
Table 3-174. CPU_SYS_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CPUSYSLOCK1 Lock bit for CPUSYS registers EALLOW Go
2h CPUSYSLOCK2 Lock bit for CPUSYS registers EALLOW Go
Ah PIEVERRADDR PIE Vector Fetch Error Address register EALLOW Go
22h PCLKCR0 Peripheral Clock Gating Registers EALLOW Go
26h PCLKCR2 Peripheral Clock Gating Register - ETPWM EALLOW Go
28h PCLKCR3 Peripheral Clock Gating Register - ECAP EALLOW Go
2Ah PCLKCR4 Peripheral Clock Gating Register - EQEP EALLOW Go
30h PCLKCR7 Peripheral Clock Gating Register - SCI EALLOW Go
32h PCLKCR8 Peripheral Clock Gating Register - SPI EALLOW Go
34h PCLKCR9 Peripheral Clock Gating Register - I2C EALLOW Go
36h PCLKCR10 Peripheral Clock Gating Register - CAN EALLOW Go
38h PCLKCR11 Peripheral Clock Gating Register - McBSP_USB EALLOW Go
3Ah PCLKCR12 Peripheral Clock Gating Register - Upp EALLOW Go
3Ch PCLKCR13 Peripheral Clock Gating Register - ADC EALLOW Go
3Eh PCLKCR14 Peripheral Clock Gating Register - CMPSS EALLOW Go
40h PCLKCR15 Peripheral Clock Gating Register - PGA EALLOW Go
42h PCLKCR16 Peripheral Clock Gating Register Buf_DAC EALLOW Go
44h PCLKCR17 Peripheral Clock Gating Register - CLB EALLOW Go
46h PCLKCR18 Peripheral Clock Gating Register - FSI EALLOW Go
48h PCLKCR19 Peripheral Clock Gating Register - LIN EALLOW Go
4Ah PCLKCR20 Peripheral Clock Gating Register - PMBUS EALLOW Go
4Ch PCLKCR21 Peripheral Clock Gating Register - DCC EALLOW Go
56h PCLKCR26 Peripheral Clock Gating Register - AES EALLOW Go
58h PCLKCR27 Peripheral Clock Gating Register - EPG EALLOW Go
70h SIMRESET Simulated Reset Register Go
76h LPMCR LPM Control Register EALLOW Go
78h GPIOLPMSEL0 GPIO LPM Wakeup select registers EALLOW Go
7Ah GPIOLPMSEL1 GPIO LPM Wakeup select registers EALLOW Go
7Ch TMR2CLKCTL Timer2 Clock Measurement functionality control EALLOW Go
register
7Eh RESCCLR Reset Cause Clear Register Go
80h RESC Reset Cause register Go
84h CMPSSLPMSEL CMPSS LPM Wakeup select registers EALLOW Go
90h MCANRAMACC MCAN RAM access control Register EALLOW Go
98h MCANWAKESTATUS MCAN Wake Status Register Go
9Ah MCANWAKESTATUSCLR MCAN Wake Status Clear Register Go
9Ch CLKSTOPREQ Peripheral Clock Stop Request Register Go
9Eh CLKSTOPACK Peripheral Clock Stop Ackonwledge Register Go
A0h USER_REG1_SYSRSn Software Configurable registers reset by SYSRSn Go
A2h USER_REG2_SYSRSn Software Configurable registers reset by SYSRSn Go
A4h USER_REG1_XRSn Software Configurable registers reset by XRSn Go

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Table 3-174. CPU_SYS_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
A6h USER_REG2_XRSn Software Configurable registers reset by XRSn Go
A8h USER_REG1_PORESETn Software Configurable registers reset by Go
PORESETn
AAh USER_REG2_PORESETn Software Configurable registers reset by Go
PORESETn
ACh USER_REG3_PORESETn Software Configurable registers reset by Go
PORESETn
AEh USER_REG4_PORESETn Software Configurable registers reset by Go
PORESETn
B0h JTAG_MMR_REG Readback of JTAG registers for test purpose Go

Complex bit access types are encoded to fit into small table cells. Table 3-175 shows the codes that are used for
access types in this section.
Table 3-175. CPU_SYS_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.11.1 CPUSYSLOCK1 Register (Offset = 0h) [Reset = 00000000h]

CPUSYSLOCK1 is shown in Figure 3-150 and described in Table 3-176.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-150. CPUSYSLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED PCLKCR22 PCLKCR21 PCLKCR20 PCLKCR19 PCLKCR18 PCLKCR17
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
GPIOLPMSEL1 GPIOLPMSEL0 LPMCR RESERVED PCLKCR16 PCLKCR15 PCLKCR14 PCLKCR13
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
PCLKCR12 PCLKCR11 PCLKCR10 PCLKCR9 PCLKCR8 PCLKCR7 RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
PCLKCR4 PCLKCR3 PCLKCR2 RESERVED PCLKCR0 PIEVERRADDR RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-176. CPUSYSLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/WSonce 0h Reserved
30 RESERVED R/WSonce 0h Reserved
29 PCLKCR22 R/WSonce 0h Lock bit for PCLKCR22 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
28 PCLKCR21 R/WSonce 0h Lock bit for PCLKCR21 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
27 PCLKCR20 R/WSonce 0h Lock bit for PCLKCR20 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
26 PCLKCR19 R/WSonce 0h Lock bit for PCLKCR19 Register:
0: Respective register is not locked
1: Respective register is locked.
Note: This bit is applicable only for Topoauto
Reset type: SYSRSn
25 PCLKCR18 R/WSonce 0h Lock bit for PCLKCR18 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-176. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
24 PCLKCR17 R/WSonce 0h Lock bit for PCLKCR17 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
23 GPIOLPMSEL1 R/WSonce 0h Lock bit for GPIOLPMSEL1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
22 GPIOLPMSEL0 R/WSonce 0h Lock bit for GPIOLPMSEL0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
21 LPMCR R/WSonce 0h Lock bit for LPMCR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
20 RESERVED R/WSonce 0h Reserved
19 PCLKCR16 R/WSonce 0h Lock bit for PCLKCR16 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
18 PCLKCR15 R/WSonce 0h Lock bit for PCLKCR15 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
17 PCLKCR14 R/WSonce 0h Lock bit for PCLKCR14 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
16 PCLKCR13 R/WSonce 0h Lock bit for PCLKCR13 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
15 PCLKCR12 R/WSonce 0h Lock bit for PCLKCR12 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
14 PCLKCR11 R/WSonce 0h Lock bit for PCLKCR11 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
13 PCLKCR10 R/WSonce 0h Lock bit for PCLKCR10 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
12 PCLKCR9 R/WSonce 0h Lock bit for PCLKCR9 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
11 PCLKCR8 R/WSonce 0h Lock bit for PCLKCR8 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-176. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 PCLKCR7 R/WSonce 0h Lock bit for PCLKCR7 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
9 RESERVED R/WSonce 0h Reserved
8 RESERVED R/WSonce 0h Reserved
7 PCLKCR4 R/WSonce 0h Lock bit for PCLKCR4 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
6 PCLKCR3 R/WSonce 0h Lock bit for PCLKCR3 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
5 PCLKCR2 R/WSonce 0h Lock bit for PCLKCR2 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
4 RESERVED R/WSonce 0h Reserved
3 PCLKCR0 R/WSonce 0h Lock bit for PCLKCR0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
2 PIEVERRADDR R/WSonce 0h Lock bit for PIEVERRADDR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
1 RESERVED R/WSonce 0h Reserved
0 RESERVED R/WSonce 0h Reserved

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3.16.11.2 CPUSYSLOCK2 Register (Offset = 2h) [Reset = 00000000h]

CPUSYSLOCK2 is shown in Figure 3-151 and described in Table 3-177.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-151. CPUSYSLOCK2 Register
31 30 29 28 27 26 25 24
USER_REG4_ USER_REG3_ USER_REG2_ USER_REG1_ USER_REG2_ USER_REG1_ USER_REG2_ USER_REG1_
PORESETn PORESETn PORESETn PORESETn XRSn XRSn SYSRSn SYSRSn
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED
R/WSonce-0h R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CMPSSLPMSE LSEN PCLKCR27 PCLKCR26 RESERVED RESERVED
L
R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-177. CPUSYSLOCK2 Register Field Descriptions

Bit Field Type Reset Description
31 USER_REG4_PORESET R/WSonce 0h Lock bit for USER_REG4_PORESETn Register
n 0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
30 USER_REG3_PORESET R/WSonce 0h Lock bit for USER_REG3_PORESETn Register
n 0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
29 USER_REG2_PORESET R/WSonce 0h Lock bit for USER_REG2_PORESETn Register
n 0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
28 USER_REG1_PORESET R/WSonce 0h Lock bit for USER_REG1_PORESETn Register
n 0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
27 USER_REG2_XRSn R/WSonce 0h Lock bit for USER_REG2_XRSn Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
26 USER_REG1_XRSn R/WSonce 0h Lock bit for USER_REG1_XRSn Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-177. CPUSYSLOCK2 Register Field Descriptions (continued)

Bit Field Type Reset Description
25 USER_REG2_SYSRSn R/WSonce 0h Lock bit for USER_REG2_SYSRSn Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
24 USER_REG1_SYSRSn R/WSonce 0h Lock bit for USER_REG1_SYSRSn Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
23 RESERVED R/WSonce 0h Reserved
22-6 RESERVED R-0 0h Reserved
5 CMPSSLPMSEL R/WSonce 0h Lock bit for CMPSSLPMSEL Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
4 LSEN R/WSonce 0h Lock bit for LSEN Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
3 PCLKCR27 R/WSonce 0h Lock bit for PCLKCR27 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
2 PCLKCR26 R/WSonce 0h Lock bit for PCLKCR26 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
1 RESERVED R/WSonce 0h Reserved
0 RESERVED R/WSonce 0h Reserved

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3.16.11.3 PIEVERRADDR Register (Offset = Ah) [Reset = 003FFFFFh]

PIEVERRADDR is shown in Figure 3-152 and described in Table 3-178.
Return to the Summary Table.
PIE Vector Fetch Error Address register
Figure 3-152. PIEVERRADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R-0-0h R/W-003FFFFFh

Table 3-178. PIEVERRADDR Register Field Descriptions

Bit Field Type Reset Description
31-22 RESERVED R-0 0h Reserved
21-0 ADDR R/W 003FFFFFh This register defines the address of the PIE Vector Fetch Error
handler routine. Its the responsibility of user to initialize this register.
If this register is not initialized, a default error handler at address
0x3fffbe will get executed. Refer to the Boot ROM section for more
details on this register.
Reset type: XRSn

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3.16.11.4 PCLKCR0 Register (Offset = 22h) [Reset = 00000038h]

PCLKCR0 is shown in Figure 3-153 and described in Table 3-179.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-153. PCLKCR0 Register
31 30 29 28 27 26 25 24
RESERVED ERAD
R-0-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED TBCLKSYNC RESERVED HRCAL
R-0-0h R/W-0h R/W-0h R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED CPUTIMER2 CPUTIMER1 CPUTIMER0 DMA RESERVED CLA1
R-0-0h R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h

Table 3-179. PCLKCR0 Register Field Descriptions

Bit Field Type Reset Description
31-25 RESERVED R-0 0h Reserved
24 ERAD R/W 0h ERAD Clock Enable Bit: When set, this enables the clock to the
ERAD module
1: ERAD clock is enabled
0: ERAD clock is disabled
Reset type: SYSRSn
23-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 TBCLKSYNC R/W 0h EPWM Time Base Clock sync: When set PWM time bases of
all the PWM modules belonging to the same CPU-Subsystem (as
partitioned using their CPUSEL bits) start counting
Reset type: SYSRSn
17 RESERVED R-0 0h Reserved
16 HRCAL R/W 0h HRCAL Clock Enable Bit: When set, this enables the clock to the
HRCAL module
1: HRCAL clock is enabled
0: HRCAL clock is disabled
Reset type: SYSRSn
15 RESERVED R-0 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12-6 RESERVED R-0 0h Reserved
5 CPUTIMER2 R/W 1h CPUTIMER2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 CPUTIMER1 R/W 1h CPUTIMER1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-179. PCLKCR0 Register Field Descriptions (continued)

Bit Field Type Reset Description
3 CPUTIMER0 R/W 1h CPUTIMER0 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 DMA R/W 0h DMA Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 RESERVED R/W 0h Reserved
0 CLA1 R/W 0h CLA1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.5 PCLKCR2 Register (Offset = 26h) [Reset = 00000000h]

PCLKCR2 is shown in Figure 3-154 and described in Table 3-180.
Return to the Summary Table.
Peripheral Clock Gating Register - ETPWM
Figure 3-154. PCLKCR2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-180. PCLKCR2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 EPWM12 R/W 0h EPWM12 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
10 EPWM11 R/W 0h EPWM11 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
9 EPWM10 R/W 0h EPWM10 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
8 EPWM9 R/W 0h EPWM9 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
7 EPWM8 R/W 0h EPWM8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6 EPWM7 R/W 0h EPWM7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-180. PCLKCR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 EPWM6 R/W 0h EPWM6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 EPWM5 R/W 0h EPWM5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 EPWM4 R/W 0h EPWM4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 EPWM3 R/W 0h EPWM3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 EPWM2 R/W 0h EPWM2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 EPWM1 R/W 0h EPWM1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.6 PCLKCR3 Register (Offset = 28h) [Reset = 00000000h]

PCLKCR3 is shown in Figure 3-155 and described in Table 3-181.
Return to the Summary Table.
Peripheral Clock Gating Register - ECAP
Figure 3-155. PCLKCR3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-181. PCLKCR3 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 ECAP2 R/W 0h ECAP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 ECAP1 R/W 0h ECAP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.7 PCLKCR4 Register (Offset = 2Ah) [Reset = 00000000h]

PCLKCR4 is shown in Figure 3-156 and described in Table 3-182.
Return to the Summary Table.
Peripheral Clock Gating Register - EQEP
Figure 3-156. PCLKCR4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-182. PCLKCR4 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 EQEP3 R/W 0h EQEP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 EQEP2 R/W 0h EQEP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Note: This bit is applicable only for Topoauto
Reset type: SYSRSn
0 EQEP1 R/W 0h EQEP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.8 PCLKCR7 Register (Offset = 30h) [Reset = 00000000h]

PCLKCR7 is shown in Figure 3-157 and described in Table 3-183.
Return to the Summary Table.
Peripheral Clock Gating Register - SCI
Figure 3-157. PCLKCR7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-183. PCLKCR7 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 SCI_C R/W 0h SCI_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 SCI_B R/W 0h SCI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SCI_A R/W 0h SCI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.9 PCLKCR8 Register (Offset = 32h) [Reset = 00000000h]

PCLKCR8 is shown in Figure 3-158 and described in Table 3-184.
Return to the Summary Table.
Peripheral Clock Gating Register - SPI
Figure 3-158. PCLKCR8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-184. PCLKCR8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SPI_B R/W 0h SPI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SPI_A R/W 0h SPI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.10 PCLKCR9 Register (Offset = 34h) [Reset = 00000000h]

PCLKCR9 is shown in Figure 3-159 and described in Table 3-185.
Return to the Summary Table.
Peripheral Clock Gating Register - I2C
Figure 3-159. PCLKCR9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-185. PCLKCR9 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h I2C_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 I2C_A R/W 0h I2C_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.11 PCLKCR10 Register (Offset = 36h) [Reset = 00000000h]

PCLKCR10 is shown in Figure 3-160 and described in Table 3-186.
Return to the Summary Table.
Peripheral Clock Gating Register - CAN
Figure 3-160. PCLKCR10 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED MCAN_B MCAN_A RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-186. PCLKCR10 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 MCAN_B R/W 0h MCAN_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 MCAN_A R/W 0h MCAN_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Note: This bit is applicable only for Topoauto
Reset type: SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.11.12 PCLKCR11 Register (Offset = 38h) [Reset = 00000000h]

PCLKCR11 is shown in Figure 3-161 and described in Table 3-187.
Return to the Summary Table.
Peripheral Clock Gating Register - McBSP_USB
Figure 3-161. PCLKCR11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

Table 3-187. PCLKCR11 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 USB_A R/W 0h USB_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
15-2 RESERVED R-0 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.11.13 PCLKCR12 Register (Offset = 3Ah) [Reset = 00000000h]

PCLKCR12 is shown in Figure 3-162 and described in Table 3-188.
Return to the Summary Table.
Peripheral Clock Gating Register - Upp
Figure 3-162. PCLKCR12 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NPU
R-0-0h R/W-0h

Table 3-188. PCLKCR12 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-1 RESERVED R-0 0h Reserved
0 NPU R/W 0h NPU Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.14 PCLKCR13 Register (Offset = 3Ch) [Reset = 00000000h]

PCLKCR13 is shown in Figure 3-163 and described in Table 3-189.
Return to the Summary Table.
Peripheral Clock Gating Register - ADC
Figure 3-163. PCLKCR13 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_E ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-189. PCLKCR13 Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R-0 0h Reserved
4 ADC_E R/W 0h ADC_E Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 ADC_D R/W 0h ADC_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 ADC_C R/W 0h ADC_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 ADC_B R/W 0h ADC_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 ADC_A R/W 0h ADC_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.15 PCLKCR14 Register (Offset = 3Eh) [Reset = 00000000h]

PCLKCR14 is shown in Figure 3-164 and described in Table 3-190.
Return to the Summary Table.
Peripheral Clock Gating Register - CMPSS
Figure 3-164. PCLKCR14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-190. PCLKCR14 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 CMPSS4 R/W 0h CMPSS4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 CMPSS3 R/W 0h CMPSS3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 CMPSS2 R/W 0h CMPSS2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 CMPSS1 R/W 0h CMPSS1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.16 PCLKCR15 Register (Offset = 40h) [Reset = 00000000h]

PCLKCR15 is shown in Figure 3-165 and described in Table 3-191.
Return to the Summary Table.
Peripheral Clock Gating Register - PGA
Figure 3-165. PCLKCR15 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED PGA3 PGA2 PGA1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-191. PCLKCR15 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 PGA3 R/W 0h PGA3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 PGA2 R/W 0h PGA2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 PGA1 R/W 0h PGA1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.17 PCLKCR16 Register (Offset = 42h) [Reset = 00000000h]

PCLKCR16 is shown in Figure 3-166 and described in Table 3-192.
Return to the Summary Table.
Peripheral Clock Gating Register Buf_DAC
Figure 3-166. PCLKCR16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-192. PCLKCR16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 DAC_A R/W 0h Buffered_DAC_A Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.11.18 PCLKCR17 Register (Offset = 44h) [Reset = 00000000h]

PCLKCR17 is shown in Figure 3-167 and described in Table 3-193.
Return to the Summary Table.
Peripheral Clock Gating Register - CLB
Figure 3-167. PCLKCR17 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CLB2 CLB1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-193. PCLKCR17 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 CLB2 R/W 0h CLB2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 CLB1 R/W 0h CLB1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.19 PCLKCR18 Register (Offset = 46h) [Reset = 00000000h]

PCLKCR18 is shown in Figure 3-168 and described in Table 3-194.
Return to the Summary Table.
Peripheral Clock Gating Register - FSI
Figure 3-168. PCLKCR18 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED FSIRX_A FSITX_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-194. PCLKCR18 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 FSIRX_A R/W 0h FSIRX_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 FSITX_A R/W 0h FSITX_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.20 PCLKCR19 Register (Offset = 48h) [Reset = 00000000h]

PCLKCR19 is shown in Figure 3-169 and described in Table 3-195.
Return to the Summary Table.
Peripheral Clock Gating Register - LIN
Figure 3-169. PCLKCR19 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED LIN_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-195. PCLKCR19 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 LIN_A R/W 0h LIN_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Note: This bit is applicable only for Topoauto
Reset type: SYSRSn

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3.16.11.21 PCLKCR20 Register (Offset = 4Ah) [Reset = 00000000h]

PCLKCR20 is shown in Figure 3-170 and described in Table 3-196.
Return to the Summary Table.
Peripheral Clock Gating Register - PMBUS
Figure 3-170. PCLKCR20 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED PMBUS_A
R-0-0h R/W-0h R/W-0h

Table 3-196. PCLKCR20 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 RESERVED R/W 0h Reserved
0 PMBUS_A R/W 0h PMBUS_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.22 PCLKCR21 Register (Offset = 4Ch) [Reset = 00000000h]

PCLKCR21 is shown in Figure 3-171 and described in Table 3-197.
Return to the Summary Table.
Peripheral Clock Gating Register - DCC
Figure 3-171. PCLKCR21 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DCC1 DCC0
R-0-0h R/W-0h R/W-0h

Table 3-197. PCLKCR21 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 DCC1 R/W 0h DCC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 DCC0 R/W 0h DCC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.23 PCLKCR26 Register (Offset = 56h) [Reset = 00000000h]

PCLKCR26 is shown in Figure 3-172 and described in Table 3-198.
Return to the Summary Table.
Peripheral Clock Gating Register - AES
Figure 3-172. PCLKCR26 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED AESA
R-0-0h R/W-0h

Table 3-198. PCLKCR26 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 AESA R/W 0h AESA Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.24 PCLKCR27 Register (Offset = 58h) [Reset = 00000000h]

PCLKCR27 is shown in Figure 3-173 and described in Table 3-199.
Return to the Summary Table.
Peripheral Clock Gating Register - EPG
Figure 3-173. PCLKCR27 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EPG1
R-0-0h R/W-0h

Table 3-199. PCLKCR27 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 EPG1 R/W 0h EPG1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.11.25 SIMRESET Register (Offset = 70h) [Reset = 00000000h]

SIMRESET is shown in Figure 3-174 and described in Table 3-200.
Return to the Summary Table.
Simulated Reset Register
Note: This register exists only on CPU1
Figure 3-174. SIMRESET Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED XRSn CPU1RSn
R-0-0h R-0/W1S-0h R-0/W1S-0h

Table 3-200. SIMRESET Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY
matches). 16-bit writes to the upper or lower half of this register will
be ignored
Reset type: XRSn
15-2 RESERVED R-0 0h Reserved
1 XRSn R-0/W1S 0h Writing a 1 to this field generates a XRSn like reset.
Writing a 0 has no effect.
Note: Writing to this pin will pull the XRSn pin low for 512 INTOSC1
clock cycles.
Reset type: XRSn
0 CPU1RSn R-0/W1S 0h Writing a 1 to this field generates a reset to to CPU1.
Writing a 0 has no effect.
Reset type: XRSn

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3.16.11.26 LPMCR Register (Offset = 76h) [Reset = 000000FCh]

LPMCR is shown in Figure 3-175 and described in Table 3-201.
Return to the Summary Table.
LPM Control Register
Figure 3-175. LPMCR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED
R/W1S-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
WDINTE RESERVED
R/W-0h R-0-0h

7 6 5 4 3 2 1 0
QUALSTDBY LPM
R/W-3Fh R/W-0h

Table 3-201. LPMCR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W1S 0h Reserved
30-18 RESERVED R-0 0h Reserved
17-16 RESERVED R/W 0h Reserved
15 WDINTE R/W 0h When this bit is set to 1, it enables the watchdog interrupt signal to
wake the device from STANDBY mode.
Note:
[1] To use this signal, the user must also enable the WDINTn signal
using the WDENINT bit in the SCSR register. This signal will not
wake the device from HALT mode because the clock to watchdog
module is turned off
Reset type: SYSRSn
14-8 RESERVED R-0 0h Reserved
7-2 QUALSTDBY R/W 3Fh Select number of OSCCLK clock cycles to qualify the selected inputs
when waking the from STANDBY mode:
000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
......
111111 = 65 OSCCLKs
Note: The LPMCR.QUALSTDBY register should be set to a value
greater than the ratio of INTOSC1/PLLSYSCLK to ensure proper
wake up.
Reset type: SYSRSn
1-0 LPM R/W 0h These bits set the low power mode for the device. Takes effect when
CPU executes the IDLE instruction (when IDLE instruction is out of
EXE Phase of the Pipeline)
00: IDLE Mode
01: STANDBY Mode
1x: HALT Mode
Reset type: SYSRSn

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3.16.11.27 GPIOLPMSEL0 Register (Offset = 78h) [Reset = 00000000h]

GPIOLPMSEL0 is shown in Figure 3-176 and described in Table 3-202.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the
selected pin.
Figure 3-176. GPIOLPMSEL0 Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-202. GPIOLPMSEL0 Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
30 GPIO30 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
29 GPIO29 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
28 GPIO28 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO27 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO26 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO25 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO24 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO23 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-202. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
22 GPIO22 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
21 GPIO21 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
20 GPIO20 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO19 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO18 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO17 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO16 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO15 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO14 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO13 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO12 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO11 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO10 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO9 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO8 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO7 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 GPIO6 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-202. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 GPIO5 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 GPIO4 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
3 GPIO3 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
2 GPIO2 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO1 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 GPIO0 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.16.11.28 GPIOLPMSEL1 Register (Offset = 7Ah) [Reset = 00000000h]

GPIOLPMSEL1 is shown in Figure 3-177 and described in Table 3-203.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the
selected pin.
Figure 3-177. GPIOLPMSEL1 Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-203. GPIOLPMSEL1 Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
30 GPIO62 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
29 GPIO61 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
28 GPIO60 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO59 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO58 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO57 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO56 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO55 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-203. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
22 GPIO54 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
21 GPIO53 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
20 GPIO52 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO51 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO50 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO49 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO48 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO47 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO46 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO45 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO44 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO43 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO42 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO41 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO40 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO39 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 GPIO38 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-203. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 GPIO37 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 GPIO36 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
3 GPIO35 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
2 GPIO34 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO33 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 GPIO32 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.16.11.29 TMR2CLKCTL Register (Offset = 7Ch) [Reset = 00000000h]

TMR2CLKCTL is shown in Figure 3-178 and described in Table 3-204.
Return to the Summary Table.
Timer2 Clock Measurement functionality control register
Figure 3-178. TMR2CLKCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED TMR2CLKPRESCALE TMR2CLKSRCSEL
R-0-0h R/W-0h R/W-0h

Table 3-204. TMR2CLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-3 TMR2CLKPRESCALE R/W 0h CPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale
value for the selected clock source for CPU Timer 2:
0,0,0,/1 (default on reset)
0,0,1,/2,
0,1,0,/4
0,1,1,/8
1,0,0,/16
1,0,1,spare (defaults to /16)
1,1,0,spare (defaults to /16)
1,1,1,spare (defaults to /16)
Note:
[1] The CPU Timer2s Clock sync logic detects an input clock edge
when configured for any clock source other than SYSCLK and
generates an appropriate clock pulse to the CPU timer2. If SYSCLK
is approximately the same or less then the input clock source, then
the user would need to configure the pre-scale value such that
SYSCLK is at least twice as fast as the pre-scaled value.
Reset type: SYSRSn
2-0 TMR2CLKSRCSEL R/W 0h CPU Timer 2 Clock Source Select Bit: This bit selects the source for
CPU Timer 2:
000 =SYSCLK Selected (default on reset, pre-scale is bypassed)
001 = INTOSC1
010 = INTOSC2
011 = XTAL
100 = PUMPOSC (from no-wrapper)
101 = FOSCCLK (Reserved)
110 = AUXPLLCLK (Reserved)
111 = reserved
Reset type: SYSRSn

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3.16.11.30 RESCCLR Register (Offset = 7Eh) [Reset = 00000000h]

RESCCLR is shown in Figure 3-179 and described in Table 3-205.
Return to the Summary Table.
Reset Cause Clear Register
Figure 3-179. RESCCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SIMRESET_XR SIMRESET_CP RESERVED SCCRESETn
Sn U1RSn
R-0-0h W1C-0h W1C-0h R-0-0h W1S-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED NMIWDRSn WDRSn XRSn POR
R-0-0h W1S-0h W1S-0h R-0-0h W1S-0h W1S-0h W1S-0h W1S-0h

Table 3-205. RESCCLR Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R-0 0h Reserved
11 SIMRESET_XRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
10 SIMRESET_CPU1RSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
9 RESERVED R-0 0h Reserved
8 SCCRESETn W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
7 RESERVED R-0 0h Reserved
6 RESERVED W1S 0h Reserved
5 RESERVED W1S 0h Reserved
4 RESERVED R-0 0h Reserved
3 NMIWDRSn W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn

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Table 3-205. RESCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
2 WDRSn W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
1 XRSn W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
0 POR W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn

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3.16.11.31 RESC Register (Offset = 80h) [Reset = X0000003h]

RESC is shown in Figure 3-180 and described in Table 3-206.
Return to the Summary Table.
Reset Cause register
Figure 3-180. RESC Register
31 30 29 28 27 26 25 24
DCON XRSn_pin_statu RESERVED
s
R-0h R-Xh R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SIMRESET_XR SIMRESET_CP RESERVED SCCRESETn
Sn U1RSn
R-0-0h R-0h R-0h R-0-0h R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED NMIWDRSn WDRSn XRSn POR
R-0-0h R-0h R-0h R-0-0h R-0h R-0h R-1h R-1h

Table 3-206. RESC Register Field Descriptions

Bit Field Type Reset Description
31 DCON R 0h Reading this bit provides the status of debugger connection to the
C28x CPU.
0 : Debugger is not connected to the C28x CPU
1 : Debugger is connected to the C28x CPU
Notes:
[1] This bit is connected to the DCON o/p signal of the C28x CPU
Reset type: N/A
30 XRSn_pin_status R Xh Reading this bit provides the current status of the XRSn pin. Reset
value is reflective of the pin status.
Reset type: N/A
29-16 RESERVED R-0 0h Reserved
15-12 RESERVED R-0 0h Reserved
11 SIMRESET_XRSn R 0h If this bit is set, indicates that the device was reset by
SIMRESET_XRSn
Reset type: PORESETn
10 SIMRESET_CPU1RSn R 0h If this bit is set, indicates that the device was reset by
SIMRESET_CPU1RSn
Reset type: PORESETn
9 RESERVED R-0 0h Reserved
8 SCCRESETn R 0h If this bit is set, indicates that the device was reset by SCCRESETn
(fired by DCSM).
Reset type: PORESETn
7 RESERVED R-0 0h Reserved
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R-0 0h Reserved

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Table 3-206. RESC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 NMIWDRSn R 0h If this bit is set, indicates that the device was reset by NMIWDRSn.
Note: To know the exact cause of NMI after the reset, software
needs to read NMISHDFLG registers
Reset type: PORESETn
2 WDRSn R 0h If this bit is set, indicates that the device was reset by WDRSn.
Note:
[1] A bit inside WD module also provides the same information. This
bit is present to keep things consistent. This register is a one-stop
shop for the software to know the reset cause for the C28x core.
Reset type: PORESETn
1 XRSn R 1h If this bit is set, indicates that the device was reset by XRSn.
Reset type: PORESETn
0 POR R 1h If this bit is set, indicates that the device was reset by PORn.
Reset type: PORESETn

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3.16.11.32 CMPSSLPMSEL Register (Offset = 84h) [Reset = 00000000h]

CMPSSLPMSEL is shown in Figure 3-181 and described in Table 3-207.
Return to the Summary Table.
CMPSS LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the
selected pin.
Figure 3-181. CMPSSLPMSEL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
CMPSS4L CMPSS4H CMPSS3L CMPSS3H CMPSS2L CMPSS2H CMPSS1L CMPSS1H
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-207. CMPSSLPMSEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved

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Table 3-207. CMPSSLPMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
8 RESERVED R/W 0h Reserved
7 CMPSS4L R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 CMPSS4H R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
5 CMPSS3L R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 CMPSS3H R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
3 CMPSS2L R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
2 CMPSS2H R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 CMPSS1L R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 CMPSS1H R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.16.11.33 MCANRAMACC Register (Offset = 90h) [Reset = 00000000h]

MCANRAMACC is shown in Figure 3-182 and described in Table 3-208.
Return to the Summary Table.
MCAN RAM access control Register
Figure 3-182. MCANRAMACC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED MCAN_B_RAM MCAN_A_RAM
ACC ACC
R-0-0h R/W-0h R/W-0h

Table 3-208. MCANRAMACC Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 MCAN_B_RAMACC R/W 0h 0 : Message RAM addresses are considered as x8 (default)
1 : Message RAM addresses are considered as x16
Reset type: PORESETn
0 MCAN_A_RAMACC R/W 0h 0 : Message RAM addresses are considered as x8 (default)
1 : Message RAM addresses are considered as x16
Reset type: PORESETn

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3.16.11.34 MCANWAKESTATUS Register (Offset = 98h) [Reset = 00000000h]

MCANWAKESTATUS is shown in Figure 3-183 and described in Table 3-209.
Return to the Summary Table.
MCAN Wake Status Register
Figure 3-183. MCANWAKESTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WAKE_MCANB WAKE_MCANA
R-0h R-0h R-0h

Table 3-209. MCANWAKESTATUS Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 WAKE_MCANB R 0h MCANB
0 : wakeup event has not occured.
1 : wakeup event has occured.
Reset type: SYSRSn
0 WAKE_MCANA R 0h MCANA
0 : wakeup event has not occured.
1 : wakeup event has occured.
Reset type: SYSRSn

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3.16.11.35 MCANWAKESTATUSCLR Register (Offset = 9Ah) [Reset = 00000000h]

MCANWAKESTATUSCLR is shown in Figure 3-184 and described in Table 3-210.
Return to the Summary Table.
MCAN Wake Status Clear Register
Figure 3-184. MCANWAKESTATUSCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WAKE_MCANB WAKE_MCANA
R-0h R-0/W1S-0h R-0/W1S-0h

Table 3-210. MCANWAKESTATUSCLR Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 WAKE_MCANB R-0/W1S 0h MCANB
0 : No effect.
1 : Clears WAKE_MCANB bit of MCANWAKESTATUS register
Reset type: SYSRSn
0 WAKE_MCANA R-0/W1S 0h MCANA
0 : No effect.
1 : Clears WAKE_MCANA bit of MCANWAKESTATUS register
Reset type: SYSRSn

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3.16.11.36 CLKSTOPREQ Register (Offset = 9Ch) [Reset = 00000000h]

CLKSTOPREQ is shown in Figure 3-185 and described in Table 3-211.
Return to the Summary Table.
Peripheral Clock Stop Request Register
Note: This register exists only on CPU1
Figure 3-185. CLKSTOPREQ Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED MCAN_B MCAN_A
R-0-0h R-0-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-211. CLKSTOPREQ Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to any of the bits in this register will succeed only if a value of
0x5634 is written to the KEY field.
Reset type: SYSRSn
15-12 RESERVED R-0 0h Reserved
11-10 RESERVED R-0 0h Reserved
9 MCAN_B R/W 0h MCAN_B Clock Stop Request Bit
0: If clock to MCAN_B is turned off, it will be turned on, else no
effect.
1: Clock stop request toMCAN_B
Note: Once set, this bit is cleared when clock to MCAN_B is turned
on as a result of a wakeup event in hardware
Reset type: SYSRSn
8 MCAN_A R/W 0h MCAN_A Clock Stop Request Bit
0: If clock to MCAN_A is turned off, it will be turned on, else no
effect.
1: Clock stop request toMCAN_A
Note: Once set, this bit is cleared when clock to MCAN_A is turned
on as a result of a wakeup event in hardware
Note: This bit is applicable only for Topoauto
Reset type: SYSRSn
7-6 RESERVED R-0 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R-0 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R-0 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.11.37 CLKSTOPACK Register (Offset = 9Eh) [Reset = 00000000h]

CLKSTOPACK is shown in Figure 3-186 and described in Table 3-212.
Return to the Summary Table.
Peripheral Clock Stop Ackonwledge Register
Note: This register exists only on CPU1
Figure 3-186. CLKSTOPACK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED MCAN_B MCAN_A
R-0-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R-0h R-0h R-0-0h R-0h R-0-0h R-0h

Table 3-212. CLKSTOPACK Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R-0 0h Reserved
9 MCAN_B R 0h MCAN_B Clock Stop Acknowledge Bit
0: Clock stop request not acknowledged
1: Clock stop acknowledged
Reset type: SYSRSn
8 MCAN_A R 0h MCAN_A Clock Stop Acknowledge Bit
0: Clock stop request not acknowledged
1: Clock stop acknowledged
Note: This bit is applicable only for Topoauto
Reset type: SYSRSn
7-6 RESERVED R-0 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R-0 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R-0 0h Reserved
0 RESERVED R 0h Reserved

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3.16.11.38 USER_REG1_SYSRSn Register (Offset = A0h) [Reset = 00000000h]

USER_REG1_SYSRSn is shown in Figure 3-187 and described in Table 3-213.
Return to the Summary Table.
Software Configurable registers reset by SYSRSn
Figure 3-187. USER_REG1_SYSRSn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-213. USER_REG1_SYSRSn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by SYSRSn to be used by the application software
Reset type: SYSRSn

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3.16.11.39 USER_REG2_SYSRSn Register (Offset = A2h) [Reset = 00000000h]

USER_REG2_SYSRSn is shown in Figure 3-188 and described in Table 3-214.
Return to the Summary Table.
Software Configurable registers reset by SYSRSn
Figure 3-188. USER_REG2_SYSRSn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-214. USER_REG2_SYSRSn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by SYSRSn to be used by the application software
Reset type: SYSRSn

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3.16.11.40 USER_REG1_XRSn Register (Offset = A4h) [Reset = 00000000h]

USER_REG1_XRSn is shown in Figure 3-189 and described in Table 3-215.
Return to the Summary Table.
Software Configurable registers reset by XRSn
Figure 3-189. USER_REG1_XRSn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-215. USER_REG1_XRSn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by XRSn to be used by the application software
Reset type: XRSn

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3.16.11.41 USER_REG2_XRSn Register (Offset = A6h) [Reset = 00000000h]

USER_REG2_XRSn is shown in Figure 3-190 and described in Table 3-216.
Return to the Summary Table.
Software Configurable registers reset by XRSn
Figure 3-190. USER_REG2_XRSn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-216. USER_REG2_XRSn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by XRSn to be used by the application software
Reset type: XRSn

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3.16.11.42 USER_REG1_PORESETn Register (Offset = A8h) [Reset = 00000000h]

USER_REG1_PORESETn is shown in Figure 3-191 and described in Table 3-217.
Return to the Summary Table.
Software Configurable registers reset by PORESETn
Figure 3-191. USER_REG1_PORESETn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-217. USER_REG1_PORESETn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by PORESETn to be used by the application software
Reset type: PORESETn

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3.16.11.43 USER_REG2_PORESETn Register (Offset = AAh) [Reset = 00000000h]

USER_REG2_PORESETn is shown in Figure 3-192 and described in Table 3-218.
Return to the Summary Table.
Software Configurable registers reset by PORESETn
Figure 3-192. USER_REG2_PORESETn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-218. USER_REG2_PORESETn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by PORESETn to be used by the application software
Reset type: PORESETn

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3.16.11.44 USER_REG3_PORESETn Register (Offset = ACh) [Reset = 00000000h]

USER_REG3_PORESETn is shown in Figure 3-193 and described in Table 3-219.
Return to the Summary Table.
Software Configurable registers reset by PORESETn
Figure 3-193. USER_REG3_PORESETn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-219. USER_REG3_PORESETn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by PORESETn to be used by the application software
Reset type: PORESETn

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3.16.11.45 USER_REG4_PORESETn Register (Offset = AEh) [Reset = 00000000h]

USER_REG4_PORESETn is shown in Figure 3-194 and described in Table 3-220.
Return to the Summary Table.
Software Configurable registers reset by PORESETn
Figure 3-194. USER_REG4_PORESETn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-220. USER_REG4_PORESETn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by PORESETn to be used by the application software
Reset type: PORESETn

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3.16.11.46 JTAG_MMR_REG Register (Offset = B0h) [Reset = 00000000h]

JTAG_MMR_REG is shown in Figure 3-195 and described in Table 3-221.
Return to the Summary Table.
Readback of JTAG registers for test purpose
Figure 3-195. JTAG_MMR_REG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
R-0h

Table 3-221. JTAG_MMR_REG Register Field Descriptions

Bit Field Type Reset Description
31-0 RESERVED R 0h Reserved

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3.16.12 SYS_STATUS_REGS Registers

Table 3-222 lists the memory-mapped registers for the SYS_STATUS_REGS registers. All register offset
addresses not listed in Table 3-222 should be considered as reserved locations and the register contents should
not be modified.
Table 3-222. SYS_STATUS_REGS Registers
Offset Acronym Register Name Write Protection Section
10h SYS_ERR_INT_FLG Status of interrupts due to multiple different errors Go
in the system.
12h SYS_ERR_INT_CLR SYS_ERR_INT_FLG clear register Go
14h SYS_ERR_INT_SET SYS_ERR_INT_FLG set register EALLOW Go
16h SYS_ERR_MASK SYS_ERR_MASK register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-223 shows the codes that are used for
access types in this section.
Table 3-223. SYS_STATUS_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.12.1 SYS_ERR_INT_FLG Register (Offset = 10h) [Reset = 00000000h]

SYS_ERR_INT_FLG is shown in Figure 3-196 and described in Table 3-224.
Return to the Summary Table.
Status of interrupts due to multiple different errors in the system.
Figure 3-196. SYS_ERR_INT_FLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED CLA_OFLOW CLA_UFLOW FPU_OFLOW FPU_UFLOW
R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPG1_INT AES_BUS_ER RESERVED RESERVED
ROR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RAM_ACC_VIO RESERVED CORRECTABL RESERVED GINT
L E_ERR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-224. SYS_ERR_INT_FLG Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19 CLA_OFLOW R 0h 0: CLA_OFLOW has not fired an interrupt.
1: CLA_OFLOW has fired an interrupt
Reset type: SYSRSn
18 CLA_UFLOW R 0h 0: CLA_UFLOW has not fired an interrupt.
1: CLA_UFLOW has fired an interrupt
Reset type: SYSRSn
17 FPU_OFLOW R 0h 0: FPU_OFLOW has not fired an interrupt.
1: FPU_OFLOW has fired an interrupt
Reset type: SYSRSn
16 FPU_UFLOW R 0h 0: FPU_UFLOW has not fired an interrupt.
1: FPU_UFLOW has fired an interrupt
Reset type: SYSRSn
15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 RESERVED R 0h Reserved
12 RESERVED R 0h Reserved
11 EPG1_INT R 0h 0: EPG1_INT has not fired an interrupt.
1: EPG1_INT has fired an interrupt
Reset type: SYSRSn
10 AES_BUS_ERROR R 0h 0: AES_BUS_ERROR has not fired an interrupt.
1: AES_BUS_ERROR has fired an interrupt
Reset type: SYSRSn
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved

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Table 3-224. SYS_ERR_INT_FLG Register Field Descriptions (continued)

Bit Field Type Reset Description
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RAM_ACC_VIOL R 0h 0: None of the Controllers have violated the set protection rules
1: At least one of the Controller accesses has violated one or more
of the access protection rules
Reset type: SYSRSn
3 RESERVED R 0h Reserved
2 CORRECTABLE_ERR R 0h 0: Number of correctable errors detected has not exceeded the set
threshold for flash/RAM.
1:Number of correctable errors detected has exceeded the set
threshold for flash/RAM.
Reset type: SYSRSn
1 RESERVED R 0h Reserved
0 GINT R 0h Global Interrupt flag:
0: On any of the flags of SYS_ERR_INT_FLG register being set,
SYS_ERR_INT is pulsed and GINT flag would be set
1: No further interrupts would be fired until GINT flag is cleared
Reset type: SYSRSn

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3.16.12.2 SYS_ERR_INT_CLR Register (Offset = 12h) [Reset = 00000000h]

SYS_ERR_INT_CLR is shown in Figure 3-197 and described in Table 3-225.
Return to the Summary Table.
SYS_ERR_INT_FLG clear register
Figure 3-197. SYS_ERR_INT_CLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED CLA_OFLOW CLA_UFLOW FPU_OFLOW FPU_UFLOW
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPG1_INT AES_BUS_ER RESERVED RESERVED
ROR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RAM_ACC_VIO RESERVED CORRECTABL RESERVED GINT
L E_ERR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-225. SYS_ERR_INT_CLR Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19 CLA_OFLOW R-0/W1S 0h 0: No effect
1: CLA_OFLOW flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
18 CLA_UFLOW R-0/W1S 0h 0: No effect
1: CLA_UFLOW flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
17 FPU_OFLOW R-0/W1S 0h 0: No effect
1: FPU_OFLOW flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
16 FPU_UFLOW R-0/W1S 0h 0: No effect
1: FPU_UFLOW flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
15 RESERVED R-0/W1S 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 RESERVED R-0/W1S 0h Reserved
12 RESERVED R-0/W1S 0h Reserved
11 EPG1_INT R-0/W1S 0h 0: No effect
1: EPG1_INT flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
10 AES_BUS_ERROR R-0/W1S 0h 0: No effect
1: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will be
cleared.
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved

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Table 3-225. SYS_ERR_INT_CLR Register Field Descriptions (continued)

Bit Field Type Reset Description
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RAM_ACC_VIOL R-0/W1S 0h 0: No effect
1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be
cleared.
Reset type: SYSRSn
3 RESERVED R-0/W1S 0h Reserved
2 CORRECTABLE_ERR R-0/W1S 0h 0: No effect
1: CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be
cleared.
Reset type: SYSRSn
1 RESERVED R-0/W1S 0h Reserved
0 GINT R-0/W1S 0h 0: No effect
1: GINT flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn

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3.16.12.3 SYS_ERR_INT_SET Register (Offset = 14h) [Reset = 00000000h]

SYS_ERR_INT_SET is shown in Figure 3-198 and described in Table 3-226.
Return to the Summary Table.
SYS_ERR_INT_FLG set register
Figure 3-198. SYS_ERR_INT_SET Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
RESERVED CLA_OFLOW CLA_UFLOW FPU_OFLOW FPU_UFLOW
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPG1_INT AES_BUS_ER RESERVED RESERVED
ROR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RAM_ACC_VIO RESERVED CORRECTABL RESERVED RESERVED
L E_ERR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0h

Table 3-226. SYS_ERR_INT_SET Register Field Descriptions

Bit Field Type Reset Description
31-24 KEY R-0/W 0h A value of 0xa5 to this field would enable write to the other bit fields
of this register. Any other value written to KEY field would block the
write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
23-20 RESERVED R 0h Reserved
19 CLA_OFLOW R-0/W1S 0h 0: No effect
1: CLA_OFLOW flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
18 CLA_UFLOW R-0/W1S 0h 0: No effect
1: CLA_UFLOW flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
17 FPU_OFLOW R-0/W1S 0h 0: No effect
1: FPU_OFLOW flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
16 FPU_UFLOW R-0/W1S 0h 0: No effect
1: FPU_UFLOW flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
15 RESERVED R-0/W1S 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 RESERVED R-0/W1S 0h Reserved
12 RESERVED R-0/W1S 0h Reserved
11 EPG1_INT R-0/W1S 0h 0: No effect
1: EPG1_INT flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn

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Table 3-226. SYS_ERR_INT_SET Register Field Descriptions (continued)

Bit Field Type Reset Description
10 AES_BUS_ERROR R-0/W1S 0h 0: No effect
1: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RAM_ACC_VIOL R-0/W1S 0h 0: No effect
1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
3 RESERVED R-0/W1S 0h Reserved
2 CORRECTABLE_ERR R-0/W1S 0h 0: No effect
1: CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be
set.
Reset type: SYSRSn
1 RESERVED R-0/W1S 0h Reserved
0 RESERVED R 0h Reserved

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3.16.12.4 SYS_ERR_MASK Register (Offset = 16h) [Reset = 00000000h]

SYS_ERR_MASK is shown in Figure 3-199 and described in Table 3-227.
Return to the Summary Table.
SYS_ERR_MASK register
Figure 3-199. SYS_ERR_MASK Register
31 30 29 28 27 26 25 24
KEY
R/W-0h

23 22 21 20 19 18 17 16
RESERVED CLA_OFLOW CLA_UFLOW FPU_OFLOW FPU_UFLOW
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPG1_INT AES_BUS_ER RESERVED RESERVED
ROR
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RAM_ACC_VIO RESERVED CORRECTABL RESERVED RESERVED
L E_ERR
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h

Table 3-227. SYS_ERR_MASK Register Field Descriptions

Bit Field Type Reset Description
31-24 KEY R/W 0h A value of 0xa5 to this field would enable write to the other bit fields
of this register. Any other value written to KEY field would block the
write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
23-20 RESERVED R 0h Reserved
19 CLA_OFLOW R/W 0h 0: CLA_OFLOW flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: CLA_OFLOW flag of SYS_ERR_INT_FLG reister will not be set
on a hardware event.
Reset type: SYSRSn
18 CLA_UFLOW R/W 0h 0: CLA_UFLOW flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: CLA_UFLOW flag of SYS_ERR_INT_FLG reister will not be set on
a hardware event.
Reset type: SYSRSn
17 FPU_OFLOW R/W 0h 0: FPU_OFLOW flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: FPU_OFLOW flag of SYS_ERR_INT_FLG reister will not be set
on a hardware event.
Reset type: SYSRSn
16 FPU_UFLOW R/W 0h 0: FPU_UFLOW flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: FPU_UFLOW flag of SYS_ERR_INT_FLG reister will not be set
on a hardware event.
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved

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Table 3-227. SYS_ERR_MASK Register Field Descriptions (continued)

Bit Field Type Reset Description
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 EPG1_INT R/W 0h 0: EPG1_INT flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: EPG1_INT flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
10 AES_BUS_ERROR R/W 0h 0: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will be set
on a hardware event.
1: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will not be
set on a hardware event.
Reset type: SYSRSn
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RAM_ACC_VIOL R/W 0h 0: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set on
a hardware event.
1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will not be
set on a hardware event.
Reset type: SYSRSn
3 RESERVED R/W 0h Reserved
2 CORRECTABLE_ERR R/W 0h 0: CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be
set on a hardware event.
1: CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will not
be set on a hardware event.
Reset type: SYSRSn
1 RESERVED R/W 0h Reserved
0 RESERVED R 0h Reserved

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3.16.13 PERIPH_AC_REGS Registers

Table 3-228 lists the memory-mapped registers for the PERIPH_AC_REGS registers. All register offset
addresses not listed in Table 3-228 should be considered as reserved locations and the register contents should
not be modified.
Table 3-228. PERIPH_AC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ADCA_AC ADCA Controller Access Control Register EALLOW Go
2h ADCB_AC ADCB Controller Access Control Register EALLOW Go
4h ADCC_AC ADCC Controller Access Control Register EALLOW Go
6h ADCD_AC ADCD Controller Access Control Register EALLOW Go
8h ADCE_AC ADCE Controller Access Control Register EALLOW Go
10h CMPSS1_AC CMPSS1 Controller Access Control Register EALLOW Go
12h CMPSS2_AC CMPSS2 Controller Access Control Register EALLOW Go
14h CMPSS3_AC CMPSS3 Controller Access Control Register EALLOW Go
16h CMPSS4_AC CMPSS4 Controller Access Control Register EALLOW Go
28h DACA_AC DACA Controller Access Control Register EALLOW Go
38h PGA1_AC PGAA Controller Access Control Register EALLOW Go
3Ah PGA2_AC PGAB Controller Access Control Register EALLOW Go
3Ch PGA3_AC PGAC Controller Access Control Register EALLOW Go
48h EPWM1_AC EPWM1 Controller Access Control Register EALLOW Go
4Ah EPWM2_AC EPWM2 Controller Access Control Register EALLOW Go
4Ch EPWM3_AC EPWM3 Controller Access Control Register EALLOW Go
4Eh EPWM4_AC EPWM4 Controller Access Control Register EALLOW Go
50h EPWM5_AC EPWM5 Controller Access Control Register EALLOW Go
52h EPWM6_AC EPWM6 Controller Access Control Register EALLOW Go
54h EPWM7_AC EPWM7 Controller Access Control Register EALLOW Go
56h EPWM8_AC EPWM8 Controller Access Control Register EALLOW Go
58h EPWM9_AC EPWM9 Controller Access Control Register EALLOW Go
5Ah EPWM10_AC EPWM10 Controller Access Control Register EALLOW Go
5Ch EPWM11_AC EPWM11 Controller Access Control Register EALLOW Go
5Eh EPWM12_AC EPWM12 Controller Access Control Register EALLOW Go
70h EQEP1_AC EQEP1 Controller Access Control Register EALLOW Go
72h EQEP2_AC EQEP2 Controller Access Control Register EALLOW Go
74h EQEP3_AC EQEP3 Controller Access Control Register EALLOW Go
80h ECAP1_AC ECAP1 Controller Access Control Register EALLOW Go
82h ECAP2_AC ECAP2 Controller Access Control Register EALLOW Go
B0h CLB1_AC CLB1 Controller Access Control Register EALLOW Go
B2h CLB2_AC CLB2 Controller Access Control Register EALLOW Go
100h SCIA_AC SCIA Controller Access Control Register EALLOW Go
102h SCIB_AC SCIB Controller Access Control Register EALLOW Go
104h SCIC_AC SCIC Controller Access Control Register EALLOW Go
110h SPIA_AC SPIA Controller Access Control Register EALLOW Go
112h SPIB_AC SPIB Controller Access Control Register EALLOW Go
120h I2CA_AC I2CA Controller Access Control Register EALLOW Go
122h I2CB_AC I2CB Controller Access Control Register EALLOW Go
130h PMBUS_A_AC PMBUSA Controller Access Control Register EALLOW Go

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Table 3-228. PERIPH_AC_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
138h LIN_A_AC LINA Controller Access Control Register EALLOW Go
148h MCANA_AC MCANA Controller Access Control Register EALLOW Go
14Ah MCANB_AC MCANB Controller Access Control Register EALLOW Go
158h FSIATX_AC FSIA Controller Access Control Register EALLOW Go
15Ah FSIARX_AC FSIB Controller Access Control Register EALLOW Go
182h USBA_AC USBA Controller Access Control Register EALLOW Go
1AAh HRPWM_A_AC HRPWM Controller Access Control Register EALLOW Go
1AEh AESA_AC AES Controller Access Control Register EALLOW Go
1FEh PERIPH_AC_LOCK Lock Register to stop Write access to peripheral EALLOW Go
Access register.

Complex bit access types are encoded to fit into small table cells. Table 3-229 shows the codes that are used for
access types in this section.
Table 3-229. PERIPH_AC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.13.1 ADCA_AC Register (Offset = 0h) [Reset = 000000FFh]

ADCA_AC is shown in Figure 3-200 and described in Table 3-230.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-200. ADCA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-230. ADCA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.2 ADCB_AC Register (Offset = 2h) [Reset = 000000FFh]

ADCB_AC is shown in Figure 3-201 and described in Table 3-231.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-201. ADCB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-231. ADCB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.3 ADCC_AC Register (Offset = 4h) [Reset = 000000FFh]

ADCC_AC is shown in Figure 3-202 and described in Table 3-232.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-202. ADCC_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-232. ADCC_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.4 ADCD_AC Register (Offset = 6h) [Reset = 000000FFh]

ADCD_AC is shown in Figure 3-203 and described in Table 3-233.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-203. ADCD_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-233. ADCD_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.5 ADCE_AC Register (Offset = 8h) [Reset = 000000FFh]

ADCE_AC is shown in Figure 3-204 and described in Table 3-234.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-204. ADCE_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-234. ADCE_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.6 CMPSS1_AC Register (Offset = 10h) [Reset = 000000FFh]

CMPSS1_AC is shown in Figure 3-205 and described in Table 3-235.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-205. CMPSS1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-235. CMPSS1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.7 CMPSS2_AC Register (Offset = 12h) [Reset = 000000FFh]

CMPSS2_AC is shown in Figure 3-206 and described in Table 3-236.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-206. CMPSS2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-236. CMPSS2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.8 CMPSS3_AC Register (Offset = 14h) [Reset = 000000FFh]

CMPSS3_AC is shown in Figure 3-207 and described in Table 3-237.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-207. CMPSS3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-237. CMPSS3_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.9 CMPSS4_AC Register (Offset = 16h) [Reset = 000000FFh]

CMPSS4_AC is shown in Figure 3-208 and described in Table 3-238.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-208. CMPSS4_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-238. CMPSS4_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.10 DACA_AC Register (Offset = 28h) [Reset = 000000FFh]

DACA_AC is shown in Figure 3-209 and described in Table 3-239.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-209. DACA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-239. DACA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.11 PGA1_AC Register (Offset = 38h) [Reset = 000000FFh]

PGA1_AC is shown in Figure 3-210 and described in Table 3-240.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-210. PGA1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-240. PGA1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.12 PGA2_AC Register (Offset = 3Ah) [Reset = 000000FFh]

PGA2_AC is shown in Figure 3-211 and described in Table 3-241.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-211. PGA2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-241. PGA2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.13 PGA3_AC Register (Offset = 3Ch) [Reset = 000000FFh]

PGA3_AC is shown in Figure 3-212 and described in Table 3-242.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-212. PGA3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-242. PGA3_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.14 EPWM1_AC Register (Offset = 48h) [Reset = 000000FFh]

EPWM1_AC is shown in Figure 3-213 and described in Table 3-243.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-213. EPWM1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-243. EPWM1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.15 EPWM2_AC Register (Offset = 4Ah) [Reset = 000000FFh]

EPWM2_AC is shown in Figure 3-214 and described in Table 3-244.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-214. EPWM2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-244. EPWM2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.16 EPWM3_AC Register (Offset = 4Ch) [Reset = 000000FFh]

EPWM3_AC is shown in Figure 3-215 and described in Table 3-245.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-215. EPWM3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-245. EPWM3_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.17 EPWM4_AC Register (Offset = 4Eh) [Reset = 000000FFh]

EPWM4_AC is shown in Figure 3-216 and described in Table 3-246.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-216. EPWM4_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-246. EPWM4_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.18 EPWM5_AC Register (Offset = 50h) [Reset = 000000FFh]

EPWM5_AC is shown in Figure 3-217 and described in Table 3-247.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-217. EPWM5_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-247. EPWM5_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.19 EPWM6_AC Register (Offset = 52h) [Reset = 000000FFh]

EPWM6_AC is shown in Figure 3-218 and described in Table 3-248.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-218. EPWM6_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-248. EPWM6_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.20 EPWM7_AC Register (Offset = 54h) [Reset = 000000FFh]

EPWM7_AC is shown in Figure 3-219 and described in Table 3-249.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-219. EPWM7_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-249. EPWM7_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.21 EPWM8_AC Register (Offset = 56h) [Reset = 000000FFh]

EPWM8_AC is shown in Figure 3-220 and described in Table 3-250.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-220. EPWM8_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-250. EPWM8_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.22 EPWM9_AC Register (Offset = 58h) [Reset = 000000FFh]

EPWM9_AC is shown in Figure 3-221 and described in Table 3-251.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-221. EPWM9_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-251. EPWM9_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.23 EPWM10_AC Register (Offset = 5Ah) [Reset = 000000FFh]

EPWM10_AC is shown in Figure 3-222 and described in Table 3-252.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-222. EPWM10_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-252. EPWM10_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.24 EPWM11_AC Register (Offset = 5Ch) [Reset = 000000FFh]

EPWM11_AC is shown in Figure 3-223 and described in Table 3-253.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-223. EPWM11_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-253. EPWM11_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.25 EPWM12_AC Register (Offset = 5Eh) [Reset = 000000FFh]

EPWM12_AC is shown in Figure 3-224 and described in Table 3-254.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-224. EPWM12_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-254. EPWM12_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.26 EQEP1_AC Register (Offset = 70h) [Reset = 000000FFh]

EQEP1_AC is shown in Figure 3-225 and described in Table 3-255.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-225. EQEP1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-255. EQEP1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.27 EQEP2_AC Register (Offset = 72h) [Reset = 000000FFh]

EQEP2_AC is shown in Figure 3-226 and described in Table 3-256.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-226. EQEP2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-256. EQEP2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.28 EQEP3_AC Register (Offset = 74h) [Reset = 000000FFh]

EQEP3_AC is shown in Figure 3-227 and described in Table 3-257.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-227. EQEP3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-257. EQEP3_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.29 ECAP1_AC Register (Offset = 80h) [Reset = 000000FFh]

ECAP1_AC is shown in Figure 3-228 and described in Table 3-258.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-228. ECAP1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-258. ECAP1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.30 ECAP2_AC Register (Offset = 82h) [Reset = 000000FFh]

ECAP2_AC is shown in Figure 3-229 and described in Table 3-259.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-229. ECAP2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-259. ECAP2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.31 CLB1_AC Register (Offset = B0h) [Reset = 000000FFh]

CLB1_AC is shown in Figure 3-230 and described in Table 3-260.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-230. CLB1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-260. CLB1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.32 CLB2_AC Register (Offset = B2h) [Reset = 000000FFh]

CLB2_AC is shown in Figure 3-231 and described in Table 3-261.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-231. CLB2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-261. CLB2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.33 SCIA_AC Register (Offset = 100h) [Reset = 000000CFh]

SCIA_AC is shown in Figure 3-232 and described in Table 3-262.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-232. SCIA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CPU1_ACC
R/W-3h R-0-0h R/W-3h R/W-3h

Table 3-262. SCIA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R-0 0h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.34 SCIB_AC Register (Offset = 102h) [Reset = 000000CFh]

SCIB_AC is shown in Figure 3-233 and described in Table 3-263.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-233. SCIB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CPU1_ACC
R/W-3h R-0-0h R/W-3h R/W-3h

Table 3-263. SCIB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R-0 0h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.35 SCIC_AC Register (Offset = 104h) [Reset = 000000CFh]

SCIC_AC is shown in Figure 3-234 and described in Table 3-264.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-234. SCIC_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CPU1_ACC
R/W-3h R-0-0h R/W-3h R/W-3h

Table 3-264. SCIC_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R-0 0h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.36 SPIA_AC Register (Offset = 110h) [Reset = 000000FFh]

SPIA_AC is shown in Figure 3-235 and described in Table 3-265.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-235. SPIA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-265. SPIA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.37 SPIB_AC Register (Offset = 112h) [Reset = 000000FFh]

SPIB_AC is shown in Figure 3-236 and described in Table 3-266.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-236. SPIB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-266. SPIB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.38 I2CA_AC Register (Offset = 120h) [Reset = 000000CFh]

I2CA_AC is shown in Figure 3-237 and described in Table 3-267.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-237. I2CA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CPU1_ACC
R/W-3h R-0-0h R/W-3h R/W-3h

Table 3-267. I2CA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R-0 0h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.39 I2CB_AC Register (Offset = 122h) [Reset = 000000CFh]

I2CB_AC is shown in Figure 3-238 and described in Table 3-268.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-238. I2CB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED CPU1_ACC
R/W-3h R-0-0h R/W-3h R/W-3h

Table 3-268. I2CB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R-0 0h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.40 PMBUS_A_AC Register (Offset = 130h) [Reset = 000000FFh]

PMBUS_A_AC is shown in Figure 3-239 and described in Table 3-269.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-239. PMBUS_A_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-269. PMBUS_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.41 LIN_A_AC Register (Offset = 138h) [Reset = 000000FFh]

LIN_A_AC is shown in Figure 3-240 and described in Table 3-270.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-240. LIN_A_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-270. LIN_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.42 MCANA_AC Register (Offset = 148h) [Reset = 000000FFh]

MCANA_AC is shown in Figure 3-241 and described in Table 3-271.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-241. MCANA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-271. MCANA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.43 MCANB_AC Register (Offset = 14Ah) [Reset = 000000FFh]

MCANB_AC is shown in Figure 3-242 and described in Table 3-272.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-242. MCANB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-272. MCANB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.44 FSIATX_AC Register (Offset = 158h) [Reset = 000000FFh]

FSIATX_AC is shown in Figure 3-243 and described in Table 3-273.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-243. FSIATX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-273. FSIATX_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.45 FSIARX_AC Register (Offset = 15Ah) [Reset = 000000FFh]

FSIARX_AC is shown in Figure 3-244 and described in Table 3-274.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-244. FSIARX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-274. FSIARX_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.46 USBA_AC Register (Offset = 182h) [Reset = 000000FFh]

USBA_AC is shown in Figure 3-245 and described in Table 3-275.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-245. USBA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-275. USBA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.47 HRPWM_A_AC Register (Offset = 1AAh) [Reset = 000000FFh]

HRPWM_A_AC is shown in Figure 3-246 and described in Table 3-276.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-246. HRPWM_A_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-276. HRPWM_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.48 AESA_AC Register (Offset = 1AEh) [Reset = 000000FFh]

AESA_AC is shown in Figure 3-247 and described in Table 3-277.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
Controller.
Figure 3-247. AESA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-277. AESA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.13.49 PERIPH_AC_LOCK Register (Offset = 1FEh) [Reset = 00000000h]

PERIPH_AC_LOCK is shown in Figure 3-248 and described in Table 3-278.
Return to the Summary Table.
Based on status bit control the Access registers are either RD/WR or RD only.
Figure 3-248. PERIPH_AC_LOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_AC_WR
R-0-0h R/WSonce-0h

Table 3-278. PERIPH_AC_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 LOCK_AC_WR R/WSonce 0h Defines Access control definition for the CPU1 as:
1: Access Control registers are Read Only
0: Read/Write Access allowed to Access Control registers.
Writing '1' sets the bit, writing '0' has no effect.
Reset type: SYSRSn

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3.16.14 MEM_CFG_REGS Registers

Table 3-279 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses
not listed in Table 3-279 should be considered as reserved locations and the register contents should not be
modified.
Table 3-279. MEM_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
0h DxLOCK Dedicated RAM Config Lock Register EALLOW Go
2h DxCOMMIT Dedicated RAM Config Lock Commit Register EALLOW Go
8h DxACCPROT0 Dedicated RAM Config Register EALLOW Go
Ah DxACCPROT1 Dedicated RAM Config Register EALLOW Go
10h DxTEST Dedicated RAM TEST Register Go
12h DxINIT Dedicated RAM Init Register EALLOW Go
14h DxINITDONE Dedicated RAM InitDone Status Register Go
16h DxRAMTEST_LOCK Lock register to Dx RAM TEST registers Go
20h LSxLOCK Local Shared RAM Config Lock Register EALLOW Go
22h LSxCOMMIT Local Shared RAM Config Lock Commit Register EALLOW Go
24h LSxMSEL Local Shared RAM Controller Sel Register EALLOW Go
26h LSxCLAPGM Local Shared RAM Prog/Exe control Register EALLOW Go
28h LSxACCPROT0 Local Shared RAM Config Register 0 EALLOW Go
2Ah LSxACCPROT1 Local Shared RAM Config Register 1 EALLOW Go
2Ch + LSxACCPROT2_y Local Shared RAM Config Register 2 EALLOW Go
formula
30h LSxTEST Local Shared RAM TEST Register Go
32h LSxINIT Local Shared RAM Init Register EALLOW Go
34h LSxINITDONE Local Shared RAM InitDone Status Register Go
36h LSxRAMTEST_LOCK Lock register to LSx RAM TEST registers Go
40h GSxLOCK Global Shared RAM Config Lock Register EALLOW Go
42h GSxCOMMIT Global Shared RAM Config Lock Commit EALLOW Go
Register
48h GSxACCPROT0 Global Shared RAM Config Register 0 EALLOW Go
50h GSxTEST Global Shared RAM TEST Register Go
52h GSxINIT Global Shared RAM Init Register EALLOW Go
54h GSxINITDONE Global Shared RAM InitDone Status Register Go
56h GSxRAMTEST_LOCK Lock register to GSx RAM TEST registers Go
60h MSGxLOCK Message RAM Config Lock Register EALLOW Go
62h MSGxCOMMIT Message RAM Config Lock Commit Register EALLOW Go
70h MSGxTEST Message RAM TEST Register Go
72h MSGxINIT Message RAM Init Register EALLOW Go
74h MSGxINITDONE Message RAM InitDone Status Register Go
76h MSGxRAMTEST_LOCK Lock register for MSGx RAM TEST Register Go
A0h ROM_LOCK ROM Config Lock Register Go
A2h ROM_TEST ROM TEST Register Go
A4h ROM_FORCE_ERROR ROM Force Error register Go

Complex bit access types are encoded to fit into small table cells. Table 3-280 shows the codes that are used for
access types in this section.

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Table 3-280. MEM_CFG_REGS Access Type Codes

Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.14.1 DxLOCK Register (Offset = 0h) [Reset = 00000000h]

DxLOCK is shown in Figure 3-249 and described in Table 3-281.
Return to the Summary Table.
Dedicated RAM Config Lock Register
Figure 3-249. DxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_PIEVEC RESERVED RESERVED LOCK_M1 LOCK_M0
T
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-281. DxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R 0h Reserved
4 LOCK_PIEVECT R/W 0h Locks the write to access protection, controller select, initialization
control and test register fields for PIEVECT RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 LOCK_M1 R/W 0h Locks the write to access protection, controller select, initialization
control and test register fields for M1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
0 LOCK_M0 R/W 0h Locks the write to access protection, controller select, initialization
control and test register fields for M0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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3.16.14.2 DxCOMMIT Register (Offset = 2h) [Reset = 00000000h]

DxCOMMIT is shown in Figure 3-250 and described in Table 3-282.
Return to the Summary Table.
Dedicated RAM Config Lock Commit Register
Figure 3-250. DxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED COMMIT_PIEV RESERVED RESERVED COMMIT_M1 COMMIT_M0
ECT
R-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-282. DxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R 0h Reserved
4 COMMIT_PIEVECT R/WSonce 0h Permanently Locks the write to access protection, controller select,
initialization control and test register fields for PIEVECT RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
3 RESERVED R/WSonce 0h Reserved
2 RESERVED R/WSonce 0h Reserved
1 COMMIT_M1 R/WSonce 0h Permanently Locks the write to access protection, controller select,
initialization control and test register fields for M1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_M0 R/WSonce 0h Permanently Locks the write to access protection, controller select,
initialization control and test register fields for M0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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3.16.14.3 DxACCPROT0 Register (Offset = 8h) [Reset = 00000000h]

DxACCPROT0 is shown in Figure 3-251 and described in Table 3-283.
Return to the Summary Table.
Dedicated RAM Config Register
Figure 3-251. DxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_
M1 M1
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_
M0 M0
R-0h R/W-0h R/W-0h

Table 3-283. DxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23-18 RESERVED R 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_M1 R/W 0h CPU WR Protection For M1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
8 FETCHPROT_M1 R/W 0h Fetch Protection For M1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1 CPUWRPROT_M0 R/W 0h CPU WR Protection For M0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
0 FETCHPROT_M0 R/W 0h Fetch Protection For M0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.14.4 DxACCPROT1 Register (Offset = Ah) [Reset = 00000000h]

DxACCPROT1 is shown in Figure 3-252 and described in Table 3-284.
Return to the Summary Table.
Dedicated RAM Config Register
Figure 3-252. DxACCPROT1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ RESERVED
PIEVECT
R-0h R/W-0h R/W-0h

Table 3-284. DxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 CPUWRPROT_PIEVECT R/W 0h CPU Write Protection For PIEVECT RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 RESERVED R/W 0h Reserved

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3.16.14.5 DxTEST Register (Offset = 10h) [Reset = 00000000h]

DxTEST is shown in Figure 3-253 and described in Table 3-285.
Return to the Summary Table.
Dedicated RAM TEST Register
Figure 3-253. DxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED TEST_PIEVECT
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED TEST_M1 TEST_M0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-285. DxTEST Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9-8 TEST_PIEVECT R/W 0h Selects the defferent modes for PIEVECT RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Functional Mode.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
7-6 RESERVED R/W 0h Reserved
5-4 RESERVED R/W 0h Reserved
3-2 TEST_M1 R/W 0h Selects the defferent modes for M1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
1-0 TEST_M0 R/W 0h Selects the defferent modes for M0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.16.14.6 DxINIT Register (Offset = 12h) [Reset = 00000000h]

DxINIT is shown in Figure 3-254 and described in Table 3-286.
Return to the Summary Table.
Dedicated RAM Init Register
Figure 3-254. DxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED INIT_PIEVECT RESERVED RESERVED INIT_M1 INIT_M0
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-286. DxINIT Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R 0h Reserved
4 INIT_PIEVECT R-0/W1S 0h RAM Initialization control for PIEVECT RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
3 RESERVED R-0/W1S 0h Reserved
2 RESERVED R-0/W1S 0h Reserved
1 INIT_M1 R-0/W1S 0h RAM Initialization control for M1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_M0 R-0/W1S 0h RAM Initialization control for M0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.14.7 DxINITDONE Register (Offset = 14h) [Reset = 00000000h]

DxINITDONE is shown in Figure 3-255 and described in Table 3-287.
Return to the Summary Table.
Dedicated RAM InitDone Status Register
Figure 3-255. DxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED INITDONE_PIE RESERVED RESERVED INITDONE_M1 INITDONE_M0
VECT
R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-287. DxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R 0h Reserved
4 INITDONE_PIEVECT R 0h RAM Initialization status for PIEVECT RAM:
0: RAM Initialization has completed.
1: RAM Initialization has completed.
Reset type: SYSRSn
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 INITDONE_M1 R 0h RAM Initialization status for M1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization has completed.
Reset type: SYSRSn
0 INITDONE_M0 R 0h RAM Initialization status for M0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.14.8 DxRAMTEST_LOCK Register (Offset = 16h) [Reset = 00000000h]

DxRAMTEST_LOCK is shown in Figure 3-256 and described in Table 3-288.
Return to the Summary Table.
Lock register to Dx RAM TEST registers
Figure 3-256. DxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED PIEVECT RESERVED RESERVED M1 M0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-288. DxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-5 RESERVED R 0h Reserved
4 PIEVECT R/W 0h 0: Allows writes to DxTEST.TEST_PIEVECT field.
1: Blocks writes to DxTEST.TEST_PIEVECT field
Reset type: SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 M1 R/W 0h 0: Allows writes to DxTEST.TEST_M1 field.
1: Blocks writes to DxTEST.TEST_M1 field
Reset type: SYSRSn
0 M0 R/W 0h 0: Allows writes to DxTEST.TEST_M0 field.
1: Blocks writes to DxTEST.TEST_M0 field
Reset type: SYSRSn

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3.16.14.9 LSxLOCK Register (Offset = 20h) [Reset = 00000000h]

LSxLOCK is shown in Figure 3-257 and described in Table 3-289.
Return to the Summary Table.
Local Shared RAM Config Lock Register
Figure 3-257. LSxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED LOCK_LS9 LOCK_LS8
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
LOCK_LS7 LOCK_LS6 LOCK_LS5 LOCK_LS4 LOCK_LS3 LOCK_LS2 LOCK_LS1 LOCK_LS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-289. LSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 LOCK_LS9 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS9 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
8 LOCK_LS8 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS8 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
7 LOCK_LS7 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS7 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
6 LOCK_LS6 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS6 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
5 LOCK_LS5 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS5 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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Table 3-289. LSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
4 LOCK_LS4 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS4 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
3 LOCK_LS3 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS3 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
2 LOCK_LS2 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS2 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
1 LOCK_LS1 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
0 LOCK_LS0 R/W 0h Locks the write to access protection, controller select, program or
data memory select, initialization control and test register fields for
LS0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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3.16.14.10 LSxCOMMIT Register (Offset = 22h) [Reset = 00000000h]

LSxCOMMIT is shown in Figure 3-258 and described in Table 3-290.
Return to the Summary Table.
Local Shared RAM Config Lock Commit Register
Figure 3-258. LSxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED COMMIT_LS9 COMMIT_LS8
R-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
COMMIT_LS7 COMMIT_LS6 COMMIT_LS5 COMMIT_LS4 COMMIT_LS3 COMMIT_LS2 COMMIT_LS1 COMMIT_LS0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-290. LSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 COMMIT_LS9 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS9 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
8 COMMIT_LS8 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS8 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
7 COMMIT_LS7 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS7 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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Table 3-290. LSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
6 COMMIT_LS6 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS6 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
5 COMMIT_LS5 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS5 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
4 COMMIT_LS4 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS4 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
3 COMMIT_LS3 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS3 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
2 COMMIT_LS2 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS2 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
1 COMMIT_LS1 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_LS0 R/WSonce 0h Permanently Locks the write to access protection, controller select,
program or data memory select, initialization control and test register
fields for LS0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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3.16.14.11 LSxMSEL Register (Offset = 24h) [Reset = 00000000h]

LSxMSEL is shown in Figure 3-259 and described in Table 3-291.
Return to the Summary Table.
Local Shared RAM Controller Sel Register
Figure 3-259. LSxMSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED MSEL_LS9 MSEL_LS8
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
MSEL_LS7 MSEL_LS6 MSEL_LS5 MSEL_LS4
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
MSEL_LS3 MSEL_LS2 MSEL_LS1 MSEL_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-291. LSxMSEL Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 MSEL_LS9 R/W 0h Controller Select for LS9 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
17-16 MSEL_LS8 R/W 0h Controller Select for LS8 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
15-14 MSEL_LS7 R/W 0h Controller Select for LS7 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
13-12 MSEL_LS6 R/W 0h Controller Select for LS6 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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Table 3-291. LSxMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 MSEL_LS5 R/W 0h Controller Select for LS5 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
9-8 MSEL_LS4 R/W 0h Controller Select for LS4 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
7-6 MSEL_LS3 R/W 0h Controller Select for LS3 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
5-4 MSEL_LS2 R/W 0h Controller Select for LS2 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
3-2 MSEL_LS1 R/W 0h Controller Select for LS1 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
1-0 MSEL_LS0 R/W 0h Controller Select for LS0 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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3.16.14.12 LSxCLAPGM Register (Offset = 26h) [Reset = 00000300h]

LSxCLAPGM is shown in Figure 3-260 and described in Table 3-292.
Return to the Summary Table.
Local Shared RAM Prog/Exe control Register
Figure 3-260. LSxCLAPGM Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED CLAPGM_LS9 CLAPGM_LS8
R-0h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
CLAPGM_LS7 CLAPGM_LS6 CLAPGM_LS5 CLAPGM_LS4 CLAPGM_LS3 CLAPGM_LS2 CLAPGM_LS1 CLAPGM_LS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-292. LSxCLAPGM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 CLAPGM_LS9 R/W 1h Selects LS9 RAM as program vs data memory for CLA:
0: Reserved.
1: CLA Program memory.
Reset type: SYSRSn
8 CLAPGM_LS8 R/W 1h Selects LS8 RAM as program vs data memory for CLA:
0: Reserved.
1: CLA Program memory.
Reset type: SYSRSn
7 CLAPGM_LS7 R/W 0h Selects LS7 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
6 CLAPGM_LS6 R/W 0h Selects LS6 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
5 CLAPGM_LS5 R/W 0h Selects LS5 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
4 CLAPGM_LS4 R/W 0h Selects LS4 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
3 CLAPGM_LS3 R/W 0h Selects LS3 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

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Table 3-292. LSxCLAPGM Register Field Descriptions (continued)

Bit Field Type Reset Description
2 CLAPGM_LS2 R/W 0h Selects LS2 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
1 CLAPGM_LS1 R/W 0h Selects LS1 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
0 CLAPGM_LS0 R/W 0h Selects LS0 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

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3.16.14.13 LSxACCPROT0 Register (Offset = 28h) [Reset = 00000000h]

LSxACCPROT0 is shown in Figure 3-261 and described in Table 3-293.
Return to the Summary Table.
Local Shared RAM Config Register 0
Figure 3-261. LSxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_L
LS3 S3
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_L
LS2 S2
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_L
LS1 S1
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_L
LS0 S0
R-0h R/W-0h R/W-0h

Table 3-293. LSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_LS3 R/W 0h CPU WR Protection For LS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_LS3 R/W 0h Fetch Protection For LS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_LS2 R/W 0h CPU WR Protection For LS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_LS2 R/W 0h Fetch Protection For LS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS1 R/W 0h CPU WR Protection For LS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS1 R/W 0h Fetch Protection For LS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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Table 3-293. LSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-2 RESERVED R 0h Reserved
1 CPUWRPROT_LS0 R/W 0h CPU WR Protection For LS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS0 R/W 0h Fetch Protection For LS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.14.14 LSxACCPROT1 Register (Offset = 2Ah) [Reset = 00000000h]

LSxACCPROT1 is shown in Figure 3-262 and described in Table 3-294.
Return to the Summary Table.
Local Shared RAM Config Register 1
Figure 3-262. LSxACCPROT1 Register
31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_L
LS7 S7
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_L
LS6 S6
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_L
LS5 S5
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_L
LS4 S4
R-0h R/W-0h R/W-0h

Table 3-294. LSxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_LS7 R/W 0h CPU WR Protection For LS7 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_LS7 R/W 0h Fetch Protection For LS7 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_LS6 R/W 0h CPU WR Protection For LS6 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_LS6 R/W 0h Fetch Protection For LS6 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS5 R/W 0h CPU WR Protection For LS5 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS5 R/W 0h Fetch Protection For LS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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Table 3-294. LSxACCPROT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-2 RESERVED R 0h Reserved
1 CPUWRPROT_LS4 R/W 0h CPU WR Protection For LS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS4 R/W 0h Fetch Protection For LS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.14.15 LSxACCPROT2_y Register (Offset = 2Ch + formula) [Reset = 00000000h]

LSxACCPROT2_y is shown in Figure 3-263 and described in Table 3-295.
Return to the Summary Table.
Local Shared RAM Config Register 2
Offset = 2Ch + (y * 2h); where y = 0h to 1h
Figure 3-263. LSxACCPROT2_y Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_L
LS9 S9
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_L
LS8 S8
R-0h R/W-0h R/W-0h

Table 3-295. LSxACCPROT2_y Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS9 R/W 0h CPU WR Protection For LS9 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS9 R/W 0h Fetch Protection For LS9 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1 CPUWRPROT_LS8 R/W 0h CPU WR Protection For LS8 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS8 R/W 0h Fetch Protection For LS8 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.14.16 LSxTEST Register (Offset = 30h) [Reset = 00000000h]

LSxTEST is shown in Figure 3-264 and described in Table 3-296.
Return to the Summary Table.
Local Shared RAM TEST Register
Figure 3-264. LSxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED TEST_LS9 TEST_LS8
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
TEST_LS7 TEST_LS6 TEST_LS5 TEST_LS4
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
TEST_LS3 TEST_LS2 TEST_LS1 TEST_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-296. LSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 TEST_LS9 R/W 0h Selects the defferent modes for LS9 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
17-16 TEST_LS8 R/W 0h Selects the defferent modes for LS8 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
15-14 TEST_LS7 R/W 0h Selects the defferent modes for LS7 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-296. LSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 TEST_LS6 R/W 0h Selects the defferent modes for LS6 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
11-10 TEST_LS5 R/W 0h Selects the defferent modes for LS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
9-8 TEST_LS4 R/W 0h Selects the defferent modes for LS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
7-6 TEST_LS3 R/W 0h Selects the defferent modes for LS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
5-4 TEST_LS2 R/W 0h Selects the defferent modes for LS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_LS1 R/W 0h Selects the defferent modes for LS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-296. LSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 TEST_LS0 R/W 0h Selects the defferent modes for LS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.16.14.17 LSxINIT Register (Offset = 32h) [Reset = 00000000h]

LSxINIT is shown in Figure 3-265 and described in Table 3-297.
Return to the Summary Table.
Local Shared RAM Init Register
Figure 3-265. LSxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED INIT_LS9 INIT_LS8
R-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
INIT_LS7 INIT_LS6 INIT_LS5 INIT_LS4 INIT_LS3 INIT_LS2 INIT_LS1 INIT_LS0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-297. LSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 INIT_LS9 R-0/W1S 0h RAM Initialization control for LS9 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
8 INIT_LS8 R-0/W1S 0h RAM Initialization control for LS8 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
7 INIT_LS7 R-0/W1S 0h RAM Initialization control for LS7 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INIT_LS6 R-0/W1S 0h RAM Initialization control for LS6 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_LS5 R-0/W1S 0h RAM Initialization control for LS5 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 INIT_LS4 R-0/W1S 0h RAM Initialization control for LS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
3 INIT_LS3 R-0/W1S 0h RAM Initialization control for LS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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Table 3-297. LSxINIT Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INIT_LS2 R-0/W1S 0h RAM Initialization control for LS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_LS1 R-0/W1S 0h RAM Initialization control for LS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_LS0 R-0/W1S 0h RAM Initialization control for LS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.14.18 LSxINITDONE Register (Offset = 34h) [Reset = 00000000h]

LSxINITDONE is shown in Figure 3-266 and described in Table 3-298.
Return to the Summary Table.
Local Shared RAM InitDone Status Register
Figure 3-266. LSxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED INITDONE_LS9 INITDONE_LS8
R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED INITDONE_LS1 INITDONE_LS0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-298. LSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9 INITDONE_LS9 R 0h RAM Initialization status for LS9 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
8 INITDONE_LS8 R 0h RAM Initialization status for LS8 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
7 RESERVED R 0h Reserved
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 INITDONE_LS1 R 0h RAM Initialization status for LS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 INITDONE_LS0 R 0h RAM Initialization status for LS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.14.19 LSxRAMTEST_LOCK Register (Offset = 36h) [Reset = 00000000h]

LSxRAMTEST_LOCK is shown in Figure 3-267 and described in Table 3-299.
Return to the Summary Table.
Lock register to LSx RAM TEST registers
Figure 3-267. LSxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LS9 LS8 LS7 LS6 LS5 LS4 LS3 LS2 LS1 LS0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-299. LSxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 LS9 R/W 0h 0: Allows writes to LSxTEST.TEST_LS9 field.
1: Blocks writes to LSxTEST.TEST_LS9 field.
Reset type: SYSRSn
8 LS8 R/W 0h 0: Allows writes to LSxTEST.TEST_LS8 field.
1: Blocks writes to LSxTEST.TEST_LS8 field.
Reset type: SYSRSn
7 LS7 R/W 0h 0: Allows writes to LSxTEST.TEST_LS7 field.
1: Blocks writes to LSxTEST.TEST_LS7 field.
Reset type: SYSRSn
6 LS6 R/W 0h 0: Allows writes to LSxTEST.TEST_LS6 field.
1: Blocks writes to LSxTEST.TEST_LS6 field.
Reset type: SYSRSn
5 LS5 R/W 0h 0: Allows writes to LSxTEST.TEST_LS5 field.
1: Blocks writes to LSxTEST.TEST_LS5 field.
Reset type: SYSRSn
4 LS4 R/W 0h 0: Allows writes to LSxTEST.TEST_LS4 field.
1: Blocks writes to LSxTEST.TEST_LS4 field.
Reset type: SYSRSn
3 LS3 R/W 0h 0: Allows writes to LSxTEST.TEST_LS3 field.
1: Blocks writes to LSxTEST.TEST_LS3 field.
Reset type: SYSRSn
2 LS2 R/W 0h 0: Allows writes to LSxTEST.TEST_LS2 field.
1: Blocks writes to LSxTEST.TEST_LS2 field.
Reset type: SYSRSn
1 LS1 R/W 0h 0: Allows writes to LSxTEST.TEST_LS1 field.
1: Blocks writes to LSxTEST.TEST_LS1 field.
Reset type: SYSRSn
0 LS0 R/W 0h 0: Allows writes to LSxTEST.TEST_LS0 field.
1: Blocks writes to LSxTEST.TEST_LS0 field.
Reset type: SYSRSn

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3.16.14.20 GSxLOCK Register (Offset = 40h) [Reset = 00000000h]

GSxLOCK is shown in Figure 3-268 and described in Table 3-300.
Return to the Summary Table.
Global Shared RAM Config Lock Register
Figure 3-268. GSxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED LOCK_GS3 LOCK_GS2 LOCK_GS1 LOCK_GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-300. GSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 LOCK_GS3 R/W 0h Locks the write to access protection, controller select, initialization
control and test register fields for GS3 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
2 LOCK_GS2 R/W 0h Locks the write to access protection, controller select, initialization
control and test register fields for GS2 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn
1 LOCK_GS1 R/W 0h Locks the write to access protection, controller select, initialization
control and test register fields for GS1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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Table 3-300. GSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
0 LOCK_GS0 R/W 0h Locks the write to access protection, controller select, initialization
control and test register fields for GS0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed.
1: Write to ACCPROT, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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3.16.14.21 GSxCOMMIT Register (Offset = 42h) [Reset = 00000000h]

GSxCOMMIT is shown in Figure 3-269 and described in Table 3-301.
Return to the Summary Table.
Global Shared RAM Config Lock Commit Register
Figure 3-269. GSxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED COMMIT_GS3 COMMIT_GS2 COMMIT_GS1 COMMIT_GS0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-301. GSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R/WSonce 0h Reserved
14 RESERVED R/WSonce 0h Reserved
13 RESERVED R/WSonce 0h Reserved
12 RESERVED R/WSonce 0h Reserved
11 RESERVED R/WSonce 0h Reserved
10 RESERVED R/WSonce 0h Reserved
9 RESERVED R/WSonce 0h Reserved
8 RESERVED R/WSonce 0h Reserved
7 RESERVED R/WSonce 0h Reserved
6 RESERVED R/WSonce 0h Reserved
5 RESERVED R/WSonce 0h Reserved
4 RESERVED R/WSonce 0h Reserved
3 COMMIT_GS3 R/WSonce 0h Permanently Locks the write to access protection, controller select,
initialization control and test register fields for GS3 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
2 COMMIT_GS2 R/WSonce 0h Permanently Locks the write to access protection, controller select,
initialization control and test register fields for GS2 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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Table 3-301. GSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
1 COMMIT_GS1 R/WSonce 0h Permanently Locks the write to access protection, controller select,
initialization control and test register fields for GS1 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_GS0 R/WSonce 0h Permanently Locks the write to access protection, controller select,
initialization control and test register fields for GS0 RAM:
0: Write to ACCPROT, INIT and MSEL fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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3.16.14.22 GSxACCPROT0 Register (Offset = 48h) [Reset = 00000000h]

GSxACCPROT0 is shown in Figure 3-270 and described in Table 3-302.
Return to the Summary Table.
Global Shared RAM Config Register 0
Figure 3-270. GSxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED NPU_WRPROT DMAWRPROT_ CPUWRPROT_ FETCHPROT_
_GS3 GS3 GS3 GS3
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED NPU_WRPROT DMAWRPROT_ CPUWRPROT_ FETCHPROT_
_GS2 GS2 GS2 GS2
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED NPU_WRPROT DMAWRPROT_ CPUWRPROT_ FETCHPROT_
_GS1 GS1 GS1 GS1
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED NPU_WRPROT DMAWRPROT_ CPUWRPROT_ FETCHPROT_
_GS0 GS0 GS0 GS0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-302. GSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27 NPU_WRPROT_GS3 R/W 0h NPU WR Protection For GS3 RAM:
0: NPU Writes are allowed.
1: NPU Writes are blocked.
Reset type: SYSRSn
26 DMAWRPROT_GS3 R/W 0h DMA WR Protection For GS3 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS3 R/W 0h CPU WR Protection For GS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS3 R/W 0h Fetch Protection For GS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-20 RESERVED R 0h Reserved
19 NPU_WRPROT_GS2 R/W 0h NPU WR Protection For GS2 RAM:
0: NPU Writes are allowed.
1: NPU Writes are blocked.
Reset type: SYSRSn
18 DMAWRPROT_GS2 R/W 0h DMA WR Protection For GS2 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

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Table 3-302. GSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
17 CPUWRPROT_GS2 R/W 0h CPU WR Protection For GS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS2 R/W 0h Fetch Protection For GS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-12 RESERVED R 0h Reserved
11 NPU_WRPROT_GS1 R/W 0h NPU WR Protection For GS1 RAM:
0: NPU Writes are allowed.
1: NPU Writes are blocked.
Reset type: SYSRSn
10 DMAWRPROT_GS1 R/W 0h DMA WR Protection For GS1 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS1 R/W 0h CPU WR Protection For GS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS1 R/W 0h Fetch Protection For GS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-4 RESERVED R 0h Reserved
3 NPU_WRPROT_GS0 R/W 0h NPU WR Protection For GS0 RAM:
0: NPU Writes are allowed.
1: NPU Writes are blocked.
Reset type: SYSRSn
2 DMAWRPROT_GS0 R/W 0h DMA WR Protection For GS0 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS0 R/W 0h CPU WR Protection For GS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS0 R/W 0h Fetch Protection For GS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.14.23 GSxTEST Register (Offset = 50h) [Reset = 00000000h]

GSxTEST is shown in Figure 3-271 and described in Table 3-303.
Return to the Summary Table.
Global Shared RAM TEST Register
Figure 3-271. GSxTEST Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
TEST_GS3 TEST_GS2 TEST_GS1 TEST_GS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-303. GSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 RESERVED R/W 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-6 TEST_GS3 R/W 0h Selects the defferent modes for GS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-303. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 TEST_GS2 R/W 0h Selects the defferent modes for GS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_GS1 R/W 0h Selects the defferent modes for GS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
1-0 TEST_GS0 R/W 0h Selects the defferent modes for GS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.16.14.24 GSxINIT Register (Offset = 52h) [Reset = 00000000h]

GSxINIT is shown in Figure 3-272 and described in Table 3-304.
Return to the Summary Table.
Global Shared RAM Init Register
Figure 3-272. GSxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED INIT_GS3 INIT_GS2 INIT_GS1 INIT_GS0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-304. GSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R-0/W1S 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 RESERVED R-0/W1S 0h Reserved
12 RESERVED R-0/W1S 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RESERVED R-0/W1S 0h Reserved
3 INIT_GS3 R-0/W1S 0h RAM Initialization control for GS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_GS2 R-0/W1S 0h RAM Initialization control for GS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_GS1 R-0/W1S 0h RAM Initialization control for GS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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Table 3-304. GSxINIT Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INIT_GS0 R-0/W1S 0h RAM Initialization control for GS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.14.25 GSxINITDONE Register (Offset = 54h) [Reset = 00000000h]

GSxINITDONE is shown in Figure 3-273 and described in Table 3-305.
Return to the Summary Table.
Global Shared RAM InitDone Status Register
Figure 3-273. GSxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
3 2 1 0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-305. GSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 RESERVED R 0h Reserved
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 INITDONE_GS3 R 0h RAM Initialization status for GS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_GS2 R 0h RAM Initialization status for GS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_GS1 R 0h RAM Initialization status for GS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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Table 3-305. GSxINITDONE Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INITDONE_GS0 R 0h RAM Initialization status for GS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.14.26 GSxRAMTEST_LOCK Register (Offset = 56h) [Reset = 00000000h]

GSxRAMTEST_LOCK is shown in Figure 3-274 and described in Table 3-306.
Return to the Summary Table.
Lock register to GSx RAM TEST registers
Figure 3-274. GSxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED GS3 GS2 GS1 GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-306. GSxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 GS3 R/W 0h 0: Allows writes to GSxTEST.TEST_GS3 field.
1: Blocks writes to GSxTEST.TEST_GS3 field.
Reset type: SYSRSn
2 GS2 R/W 0h 0: Allows writes to GSxTEST.TEST_GS2 field.
1: Blocks writes to GSxTEST.TEST_GS2 field.
Reset type: SYSRSn
1 GS1 R/W 0h 0: Allows writes to GSxTEST.TEST_GS1 field.
1: Blocks writes to GSxTEST.TEST_GS1 field.
Reset type: SYSRSn
0 GS0 R/W 0h 0: Allows writes to GSxTEST.TEST_GS0 field.
1: Blocks writes to GSxTEST.TEST_GS0 field.
Reset type: SYSRSn

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3.16.14.27 MSGxLOCK Register (Offset = 60h) [Reset = 00000000h]

MSGxLOCK is shown in Figure 3-275 and described in Table 3-307.
Return to the Summary Table.
Message RAM Config Lock Register
Figure 3-275. MSGxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_DMATO LOCK_CLA1TO RESERVED RESERVED LOCK_CLA1TO LOCK_CPUTO RESERVED
CLA1 DMA CPU CLA1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-307. MSGxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 LOCK_DMATOCLA1 R/W 0h Locks the write to access protection, controller select, initialization
control and test for DMATOCLA1 RAM:
0: Write to TEST, INIT fields are allowed.
1: Write to TEST, INIT fields are blocked.
Reset type: SYSRSn
5 LOCK_CLA1TODMA R/W 0h Locks the write to access protection, controller select, initialization
control and test for CLA1TODMA RAM:
0: Write to TEST, INIT fields are allowed.
1: Write to TEST, INIT fields are blocked.
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 LOCK_CLA1TOCPU R/W 0h Locks the write to access protection, controller select, initialization
control and test register fields for CLA1TOCPU RAM:
0: Write to TEST, INIT fields are allowed.
1: Write to TEST, INIT fields are blocked.
Reset type: SYSRSn
1 LOCK_CPUTOCLA1 R/W 0h Locks the write to access protection, controller select, initialization
control and test register fields for CPUTOCLA1 RAM:
0: Write to TEST, INIT fields are allowed.
1: Write to TEST, INIT fields are blocked.
Reset type: SYSRSn

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Table 3-307. MSGxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
0 RESERVED R/W 0h Reserved

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3.16.14.28 MSGxCOMMIT Register (Offset = 62h) [Reset = 00000000h]

MSGxCOMMIT is shown in Figure 3-276 and described in Table 3-308.
Return to the Summary Table.
Message RAM Config Lock Commit Register
Figure 3-276. MSGxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
RESERVED COMMIT_DMA COMMIT_CLA1 RESERVED RESERVED COMMIT_CLA1 COMMIT_CPU RESERVED
TOCLA1 TODMA TOCPU TOCLA1
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-308. MSGxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R/WSonce 0h Reserved
10 RESERVED R/WSonce 0h Reserved
9 RESERVED R/WSonce 0h Reserved
8 RESERVED R/WSonce 0h Reserved
7 RESERVED R/WSonce 0h Reserved
6 COMMIT_DMATOCLA1 R/WSonce 0h Locks the write to access protection, controller select, initialization
control and test register fields for DMATOCLA1 RAM:
0: Write to TEST, INIT fields are allowed based on value of
corresponding lock field in MSGxLOCK register.
1: Write to TEST, INIT fields are permanently blocked.
Reset type: SYSRSn
5 COMMIT_CLA1TODMA R/WSonce 0h Locks the write to access protection, controller select, initialization
control and test register fields for CLA1TODMA RAM:
0: Write to TEST, INIT fields are allowed based on value of
corresponding lock field in MSGxLOCK register.
1: Write to TEST, INIT fields are permanently blocked.
Reset type: SYSRSn
4 RESERVED R/WSonce 0h Reserved
3 RESERVED R/WSonce 0h Reserved
2 COMMIT_CLA1TOCPU R/WSonce 0h Locks the write to access protection, controller select, initialization
control and test register fields for CLA1TOCPU RAM:
0: Write to TEST, INIT fields are allowed based on value of
corresponding lock field in MSGxLOCK register.
1: Write to TEST, INIT fields are permanently blocked.
Reset type: SYSRSn

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Table 3-308. MSGxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
1 COMMIT_CPUTOCLA1 R/WSonce 0h Locks the write to access protection, controller select, initialization
control and test register fields for CPUTOCLA1 RAM:
0: Write to TEST, INIT fields are allowed based on value of
corresponding lock field in MSGxLOCK register.
1: Write to TEST, INIT fields are permanently blocked.
Reset type: SYSRSn
0 RESERVED R/WSonce 0h Reserved

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3.16.14.29 MSGxTEST Register (Offset = 70h) [Reset = 00000000h]

MSGxTEST is shown in Figure 3-277 and described in Table 3-309.
Return to the Summary Table.
Message RAM TEST Register
Figure 3-277. MSGxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED TEST_DMATOCLA1 TEST_CLA1TODMA RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED TEST_CLA1TOCPU TEST_CPUTOCLA1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-309. MSGxTEST Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 TEST_DMATOCLA1 R/W 0h Selects the defferent modes for DMATOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
11-10 TEST_CLA1TODMA R/W 0h Selects the defferent modes for CLA1TODMA MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved

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Table 3-309. MSGxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 TEST_CLA1TOCPU R/W 0h Selects the defferent modes for CLA1TOCPU MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_CPUTOCLA1 R/W 0h Selects the defferent modes for CPUTOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
1-0 RESERVED R/W 0h Reserved

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3.16.14.30 MSGxINIT Register (Offset = 72h) [Reset = 00000000h]

MSGxINIT is shown in Figure 3-278 and described in Table 3-310.
Return to the Summary Table.
Message RAM Init Register
Figure 3-278. MSGxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED INIT_DMATOCL INIT_CLA1TOD RESERVED RESERVED INIT_CLA1TOC INIT_CPUTOCL RESERVED
A1 MA PU A1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-310. MSGxINIT Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 INIT_DMATOCLA1 R-0/W1S 0h RAM Initialization control for DMATOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_CLA1TODMA R-0/W1S 0h RAM Initialization control for CLA1TODMA MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 INIT_CLA1TOCPU R-0/W1S 0h RAM Initialization control for CLA1TOCPU MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_CPUTOCLA1 R-0/W1S 0h RAM Initialization control for CPUTOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 RESERVED R-0/W1S 0h Reserved

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3.16.14.31 MSGxINITDONE Register (Offset = 74h) [Reset = 00000000h]

MSGxINITDONE is shown in Figure 3-279 and described in Table 3-311.
Return to the Summary Table.
Message RAM InitDone Status Register
Figure 3-279. MSGxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED INITDONE_DM INITDONE_CL RESERVED RESERVED INITDONE_CL INITDONE_CP RESERVED
ATOCLA1 A1TODMA A1TOCPU UTOCLA1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-311. MSGxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 INITDONE_DMATOCLA1 R 0h RAM Initialization status for DMATOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_CLA1TODMA R 0h RAM Initialization status for CLA1TODMA MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 INITDONE_CLA1TOCPU R 0h RAM Initialization status for CLA1TOCPU MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_CPUTOCLA1 R 0h RAM Initialization status for CPUTOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.16.14.32 MSGxRAMTEST_LOCK Register (Offset = 76h) [Reset = 00000000h]

MSGxRAMTEST_LOCK is shown in Figure 3-280 and described in Table 3-312.
Return to the Summary Table.
Lock register for MSGx RAM TEST Register
Figure 3-280. MSGxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMATOCLA1 CLA1TODMA RESERVED RESERVED CLA1TOCPU CPUTOCLA1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-312. MSGxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 DMATOCLA1 R/W 0h 0: Allows writes to MSGxTEST.TEST_DMATOCLA1 field
1: Blocks writes to MSGxTEST.TEST_DMATOCLA1 field
Reset type: SYSRSn
5 CLA1TODMA R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA1TODMA field
1: Blocks writes to MSGxTEST.TEST_CLA1TODMA field
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 CLA1TOCPU R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA1TOCPU field
1: Blocks writes to MSGxTEST.TEST_CLA1TOCPU field
Reset type: SYSRSn
1 CPUTOCLA1 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCLA1 field
1: Blocks writes to MSGxTEST.TEST_CPUTOCLA1 field
Reset type: SYSRSn
0 RESERVED R/W 0h Reserved

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3.16.14.33 ROM_LOCK Register (Offset = A0h) [Reset = 00000000h]

ROM_LOCK is shown in Figure 3-281 and described in Table 3-313.
Return to the Summary Table.
ROM Config Lock Register
Figure 3-281. ROM_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED LOCK_CLADAT LOCK_SECUR LOCK_BOOTR
AROM EROM OM
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-313. ROM_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-4 RESERVED R 0h Reserved
3 RESERVED R/W 0h Reserved
2 LOCK_CLADATAROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of CLADATAROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn
1 LOCK_SECUREROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of SECUREROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn
0 LOCK_BOOTROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of BOOTROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn

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3.16.14.34 ROM_TEST Register (Offset = A2h) [Reset = 00000000h]

ROM_TEST is shown in Figure 3-282 and described in Table 3-314.
Return to the Summary Table.
ROM TEST Register
Figure 3-282. ROM_TEST Register
31 30 29 28 27 26 25 24
RESERVED
R/W-0h

23 22 21 20 19 18 17 16
RESERVED
R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
RESERVED TEST_CLADATAROM TEST_SECUREROM TEST_BOOTROM
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-314. ROM_TEST Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 TEST_CLADATAROM R/W 0h Selects the different modes for CLADATAROM:
00: Functional Mode.
01: same as '00' but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as '00' but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn
3-2 TEST_SECUREROM R/W 0h Selects the different modes for SECUREROM:
00: Functional Mode.
01: same as '00' but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as '00' but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn
1-0 TEST_BOOTROM R/W 0h Selects the different modes for BOOTROM:
00: Functional Mode.
01: same as '00' but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as '00' but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn

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3.16.14.35 ROM_FORCE_ERROR Register (Offset = A4h) [Reset = 00000000h]

ROM_FORCE_ERROR is shown in Figure 3-283 and described in Table 3-315.
Return to the Summary Table.
ROM Force Error register
Figure 3-283. ROM_FORCE_ERROR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED FORCE_CLAD FORCE_SECU FORCE_BOOT
ATAROM_ERR REROM_ERRO ROM_ERROR
OR R
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-315. ROM_FORCE_ERROR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R/W 0h Reserved
2 FORCE_CLADATAROM_ R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
ERROR logic.
Reset type: SYSRSn
1 FORCE_SECUREROM_E R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
RROR logic.
Reset type: SYSRSn
0 FORCE_BOOTROM_ERR R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
OR logic.
Reset type: SYSRSn

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3.16.15 ACCESS_PROTECTION_REGS Registers

Table 3-316 lists the memory-mapped registers for the ACCESS_PROTECTION_REGS registers. All register
offset addresses not listed in Table 3-316 should be considered as reserved locations and the register contents
should not be modified.
Table 3-316. ACCESS_PROTECTION_REGS Registers
Offset Acronym Register Name Write Protection Section
0h NMAVFLG Non-Controller Access Violation Flag Register Go
2h NMAVSET Non-Controller Access Violation Flag Set Register EALLOW Go
4h NMAVCLR Non-Controller Access Violation Flag Clear EALLOW Go
Register
6h NMAVINTEN Non-Controller Access Violation Interrupt Enable EALLOW Go
Register
8h NMCPURDAVADDR Non-Controller CPU Read Access Violation Go
Address
Ah NMCPUWRAVADDR Non-Controller CPU Write Access Violation Go
Address
Ch NMCPUFAVADDR Non-Controller CPU Fetch Access Violation Go
Address
Eh NMDMAWRAVADDR Non-Controller DMA Write Access Violation Go
Address
10h NMCLA1RDAVADDR Non-Controller CLA1 Read Access Violation Go
Address
12h NMCLA1WRAVADDR Non-Controller CLA1 Write Access Violation Go
Address
14h NMCLA1FAVADDR Non-Controller CLA1 Fetch Access Violation Go
Address
1Ch NMDMARDAVADDR Non-Controller DMA Read Access Violation Go
Address
20h MAVFLG Controller Access Violation Flag Register Go
22h MAVSET Controller Access Violation Flag Set Register EALLOW Go
24h MAVCLR Controller Access Violation Flag Clear Register EALLOW Go
26h MAVINTEN Controller Access Violation Interrupt Enable EALLOW Go
Register
28h MCPUFAVADDR Controller CPU Fetch Access Violation Address Go
2Ah MCPUWRAVADDR Controller CPU Write Access Violation Address Go
2Ch MDMAWRAVADDR Controller DMA Write Access Violation Address Go
3Ah NMNPURDAVADDR Non-Controller NPU Read Access Violation Go
Address
3Ch NMNPUWRAVADDR Non-Controller NPU Write Access Violation Go
Address

Complex bit access types are encoded to fit into small table cells. Table 3-317 shows the codes that are used for
access types in this section.
Table 3-317. ACCESS_PROTECTION_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write

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Table 3-317. ACCESS_PROTECTION_REGS Access Type Codes (continued)

Access Type Code Description
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.15.1 NMAVFLG Register (Offset = 0h) [Reset = 00000000h]

NMAVFLG is shown in Figure 3-284 and described in Table 3-318.
Return to the Summary Table.
Non-Controller Access Violation Flag Register
Figure 3-284. NMAVFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED NPUWRITE NPUREAD DMAREAD RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-318. NMAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-13 RESERVED R 0h Reserved
12 NPUWRITE R 0h Non Controller NPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
11 NPUREAD R 0h Non Controller NPU Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
10 DMAREAD R 0h Non Controller DMA Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 CLA1FETCH R 0h Non Controller CLA1 Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
5 CLA1WRITE R 0h Non Controller CLA1 Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
4 CLA1READ R 0h Non Controller CLA1 Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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Table 3-318. NMAVFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
3 DMAWRITE R 0h Non Controller DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
2 CPUFETCH R 0h Non Controller CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
1 CPUWRITE R 0h Non Controller CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
0 CPUREAD R 0h Non Controller CPU Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.16.15.2 NMAVSET Register (Offset = 2h) [Reset = 00000000h]

NMAVSET is shown in Figure 3-285 and described in Table 3-319.
Return to the Summary Table.
Non-Controller Access Violation Flag Set Register
Figure 3-285. NMAVSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED NPUWRITE NPUREAD DMAREAD RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-319. NMAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-13 RESERVED R 0h Reserved
12 NPUWRITE R-0/W1S 0h 0: No action.
1: NPU Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
11 NPUREAD R-0/W1S 0h 0: No action.
1: NPU Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
10 DMAREAD R-0/W1S 0h 0: No action.
1: DMA Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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Table 3-319. NMAVSET Register Field Descriptions (continued)

Bit Field Type Reset Description
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.16.15.3 NMAVCLR Register (Offset = 4h) [Reset = 00000000h]

NMAVCLR is shown in Figure 3-286 and described in Table 3-320.
Return to the Summary Table.
Non-Controller Access Violation Flag Clear Register
Figure 3-286. NMAVCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED NPUWRITE NPUREAD DMAREAD RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-320. NMAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-13 RESERVED R 0h Reserved
12 NPUWRITE R-0/W1S 0h 0: No action.
1: NPU Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
11 NPUREAD R-0/W1S 0h 0: No action.
1: NPU Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
10 DMAREAD R-0/W1S 0h 0: No action.
1: DMA Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

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Table 3-320. NMAVCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

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3.16.15.4 NMAVINTEN Register (Offset = 6h) [Reset = 00000000h]

NMAVINTEN is shown in Figure 3-287 and described in Table 3-321.
Return to the Summary Table.
Non-Controller Access Violation Interrupt Enable Register
Figure 3-287. NMAVINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED NPUWRITE NPUREAD DMAREAD RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-321. NMAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-13 RESERVED R 0h Reserved
12 NPUWRITE R/W 0h 0: NPU Non Controller Write Access Violation Interrupt is disabled.
1: NPU Non Controller Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
11 NPUREAD R/W 0h 0: NPU Non Controller Read Access Violation Interrupt is disabled.
1: NPU Non Controller Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
10 DMAREAD R/W 0h 0: DMA Non Controller Read Access Violation Interrupt is disabled.
1: DMA Non Controller Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 CLA1FETCH R/W 0h 0: CLA1 Non Controller Fetch Access Violation Interrupt is disabled.
1: CLA1 Non Controller Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn
5 CLA1WRITE R/W 0h 0: CLA1 Non Controller Write Access Violation Interrupt is disabled.
1: CLA1 Non Controller Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
4 CLA1READ R/W 0h 0: CLA1 Non Controller Read Access Violation Interrupt is disabled.
1: CLA1 Non Controller Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
3 DMAWRITE R/W 0h 0: DMA Non Controller Write Access Violation Interrupt is disabled.
1: DMA Non Controller Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
2 CPUFETCH R/W 0h 0: CPU Non Controller Fetch Access Violation Interrupt is disabled.
1: CPU Non Controller Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

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Table 3-321. NMAVINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRITE R/W 0h 0: CPU Non Controller Write Access Violation Interrupt is disabled.
1: CPU Non Controller Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUREAD R/W 0h 0: CPU Non Controller Read Access Violation Interrupt is disabled.
1: CPU Non Controller Read Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.16.15.5 NMCPURDAVADDR Register (Offset = 8h) [Reset = 00000000h]

NMCPURDAVADDR is shown in Figure 3-288 and described in Table 3-322.
Return to the Summary Table.
Non-Controller CPU Read Access Violation Address
Figure 3-288. NMCPURDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPURDAVADDR
R-0h

Table 3-322. NMCPURDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPURDAVADDR R 0h This register captures the address location for which non controller
CPU read access violation occurred.
Reset type: SYSRSn

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3.16.15.6 NMCPUWRAVADDR Register (Offset = Ah) [Reset = 00000000h]

NMCPUWRAVADDR is shown in Figure 3-289 and described in Table 3-323.
Return to the Summary Table.
Non-Controller CPU Write Access Violation Address
Figure 3-289. NMCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUWRAVADDR
R-0h

Table 3-323. NMCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUWRAVADDR R 0h This register captures the address location for which non controller
CPU write access violation occurred.
Reset type: SYSRSn

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3.16.15.7 NMCPUFAVADDR Register (Offset = Ch) [Reset = 00000000h]

NMCPUFAVADDR is shown in Figure 3-290 and described in Table 3-324.
Return to the Summary Table.
Non-Controller CPU Fetch Access Violation Address
Figure 3-290. NMCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUFAVADDR
R-0h

Table 3-324. NMCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUFAVADDR R 0h This register captures the address location for which non controller
CPU fetch access violation occurred.
Reset type: SYSRSn

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3.16.15.8 NMDMAWRAVADDR Register (Offset = Eh) [Reset = 00000000h]

NMDMAWRAVADDR is shown in Figure 3-291 and described in Table 3-325.
Return to the Summary Table.
Non-Controller DMA Write Access Violation Address
Figure 3-291. NMDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMDMAWRAVADDR
R-0h

Table 3-325. NMDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMDMAWRAVADDR R 0h This register captures the address location for which non controller
DMA write access violation occurred.
Reset type: SYSRSn

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3.16.15.9 NMCLA1RDAVADDR Register (Offset = 10h) [Reset = 00000000h]

NMCLA1RDAVADDR is shown in Figure 3-292 and described in Table 3-326.
Return to the Summary Table.
Non-Controller CLA1 Read Access Violation Address
Figure 3-292. NMCLA1RDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1RDAVADDR
R-0h

Table 3-326. NMCLA1RDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1RDAVADDR R 0h This register captures the address location for which non controller
CLA1 read access violation occurred.
Reset type: SYSRSn

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3.16.15.10 NMCLA1WRAVADDR Register (Offset = 12h) [Reset = 00000000h]

NMCLA1WRAVADDR is shown in Figure 3-293 and described in Table 3-327.
Return to the Summary Table.
Non-Controller CLA1 Write Access Violation Address
Figure 3-293. NMCLA1WRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1WRAVADDR
R-0h

Table 3-327. NMCLA1WRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1WRAVADDR R 0h This register captures the address location for which non controller
CLA1 write access violation occurred.
Reset type: SYSRSn

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3.16.15.11 NMCLA1FAVADDR Register (Offset = 14h) [Reset = 00000000h]

NMCLA1FAVADDR is shown in Figure 3-294 and described in Table 3-328.
Return to the Summary Table.
Non-Controller CLA1 Fetch Access Violation Address
Figure 3-294. NMCLA1FAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1FAVADDR
R-0h

Table 3-328. NMCLA1FAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1FAVADDR R 0h This register captures the address location for which non controller
CLA1 fetch access violation occurred.
Reset type: SYSRSn

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3.16.15.12 NMDMARDAVADDR Register (Offset = 1Ch) [Reset = 00000000h]

NMDMARDAVADDR is shown in Figure 3-295 and described in Table 3-329.
Return to the Summary Table.
Non-Controller DMA Read Access Violation Address
Figure 3-295. NMDMARDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMDMARDAVADDR
R-0h

Table 3-329. NMDMARDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMDMARDAVADDR R 0h This register captures the address location for which non controller
DMA read access violation occurred.
Reset type: SYSRSn

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3.16.15.13 MAVFLG Register (Offset = 20h) [Reset = 00000000h]

MAVFLG is shown in Figure 3-296 and described in Table 3-330.
Return to the Summary Table.
Controller Access Violation Flag Register
Figure 3-296. MAVFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0h R-0h R-0h R-0h

Table 3-330. MAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 DMAWRITE R 0h Controller DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
1 CPUWRITE R 0h Controller CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
0 CPUFETCH R 0h Controller CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.16.15.14 MAVSET Register (Offset = 22h) [Reset = 00000000h]

MAVSET is shown in Figure 3-297 and described in Table 3-331.
Return to the Summary Table.
Controller Access Violation Flag Set Register
Figure 3-297. MAVSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-331. MAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.16.15.15 MAVCLR Register (Offset = 24h) [Reset = 00000000h]

MAVCLR is shown in Figure 3-298 and described in Table 3-332.
Return to the Summary Table.
Controller Access Violation Flag Clear Register
Figure 3-298. MAVCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-332. MAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be
cleared .
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn

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3.16.15.16 MAVINTEN Register (Offset = 26h) [Reset = 00000000h]

MAVINTEN is shown in Figure 3-299 and described in Table 3-333.
Return to the Summary Table.
Controller Access Violation Interrupt Enable Register
Figure 3-299. MAVINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-333. MAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R/W 0h Reserved
2 DMAWRITE R/W 0h 0: DMA Write Access Violation Interrupt is disabled.
1: DMA Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
1 CPUWRITE R/W 0h 0: CPU Write Access Violation Interrupt is disabled.
1: CPU Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUFETCH R/W 0h 0: CPU Fetch Access Violation Interrupt is disabled.
1: CPU Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.16.15.17 MCPUFAVADDR Register (Offset = 28h) [Reset = 00000000h]

MCPUFAVADDR is shown in Figure 3-300 and described in Table 3-334.
Return to the Summary Table.
Controller CPU Fetch Access Violation Address
Figure 3-300. MCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUFAVADDR
R-0h

Table 3-334. MCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUFAVADDR R 0h This register captures the address location for which controller CPU
fetch access violation occurred.
Reset type: SYSRSn

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3.16.15.18 MCPUWRAVADDR Register (Offset = 2Ah) [Reset = 00000000h]

MCPUWRAVADDR is shown in Figure 3-301 and described in Table 3-335.
Return to the Summary Table.
Controller CPU Write Access Violation Address
Figure 3-301. MCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUWRAVADDR
R-0h

Table 3-335. MCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUWRAVADDR R 0h This register captures the address location for which controller CPU
write access violation occurred.
Reset type: SYSRSn

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3.16.15.19 MDMAWRAVADDR Register (Offset = 2Ch) [Reset = 00000000h]

MDMAWRAVADDR is shown in Figure 3-302 and described in Table 3-336.
Return to the Summary Table.
Controller DMA Write Access Violation Address
Figure 3-302. MDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAWRAVADDR
R-0h

Table 3-336. MDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MDMAWRAVADDR R 0h This register captures the address location for which controller DMA
write access violation occurred.
Reset type: SYSRSn

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3.16.15.20 NMNPURDAVADDR Register (Offset = 3Ah) [Reset = 00000000h]

NMNPURDAVADDR is shown in Figure 3-303 and described in Table 3-337.
Return to the Summary Table.
Non-Controller NPU Read Access Violation Address
Figure 3-303. NMNPURDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMNPURDAVADDR
R-0h

Table 3-337. NMNPURDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMNPURDAVADDR R 0h This register captures the address location for which non controller
NPU read access violation occurred.
Reset type: SYSRSn

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3.16.15.21 NMNPUWRAVADDR Register (Offset = 3Ch) [Reset = 00000000h]

NMNPUWRAVADDR is shown in Figure 3-304 and described in Table 3-338.
Return to the Summary Table.
Non-Controller NPU Write Access Violation Address
Figure 3-304. NMNPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMNPUWRAVADDR
R-0h

Table 3-338. NMNPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMNPUWRAVADDR R 0h This register captures the address location for which non controller
NPU write access violation occurred.
Reset type: SYSRSn

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3.16.16 MEMORY_ERROR_REGS Registers

Table 3-339 lists the memory-mapped registers for the MEMORY_ERROR_REGS registers. All register offset
addresses not listed in Table 3-339 should be considered as reserved locations and the register contents should
not be modified.
Table 3-339. MEMORY_ERROR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h UCERRFLG Uncorrectable Error Flag Register Go
2h UCERRSET Uncorrectable Error Flag Set Register EALLOW Go
4h UCERRCLR Uncorrectable Error Flag Clear Register EALLOW Go
6h UCCPUREADDR Uncorrectable CPU Read Error Address Go
8h UCDMAREADDR Uncorrectable DMA Read Error Address Go
Ah UCCLA1READDR Uncorrectable CLA1 Read Error Address Go
10h UCNPUREADDR Uncorrectable NPU Read Error Address Go
1Ch FLUCERRSTATUS Flash read uncorrectable ecc err status Go
1Eh FLCERRSTATUS Flash read correctable ecc err status Go
20h CERRFLG Correctable Error Flag Register Go
22h CERRSET Correctable Error Flag Set Register EALLOW Go
24h CERRCLR Correctable Error Flag Clear Register EALLOW Go
26h CCPUREADDR Correctable CPU Read Error Address Go
28h CDMAREADDR Correctable DMA Read Error Address Go
2Ah CCLA1READDR Correctable CLA1 Read Error Address Go
2Eh CERRCNT Correctable Error Count Register Go
30h CERRTHRES Correctable Error Threshold Value Register EALLOW Go
32h CEINTFLG Correctable Error Interrupt Flag Status Register Go
34h CEINTCLR Correctable Error Interrupt Flag Clear Register EALLOW Go
36h CEINTSET Correctable Error Interrupt Flag Set Register EALLOW Go
38h CEINTEN Correctable Error Interrupt Enable Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-340 shows the codes that are used for
access types in this section.
Table 3-340. MEMORY_ERROR_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.

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Table 3-340. MEMORY_ERROR_REGS Access Type Codes (continued)

Access Type Code Description
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.16.1 UCERRFLG Register (Offset = 0h) [Reset = 00000000h]

UCERRFLG is shown in Figure 3-305 and described in Table 3-341.
Return to the Summary Table.
Uncorrectable Error Flag Register
Figure 3-305. UCERRFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED NPURDERR RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-341. UCERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 NPURDERR R 0h NPU Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during NPU read.
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 CLA1RDERR R 0h CLA1 Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CPU read.
Reset type: SYSRSn

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3.16.16.2 UCERRSET Register (Offset = 2h) [Reset = 00000000h]

UCERRSET is shown in Figure 3-306 and described in Table 3-342.
Return to the Summary Table.
Uncorrectable Error Flag Set Register
Figure 3-306. UCERRSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED NPURDERR RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-342. UCERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 NPURDERR R-0/W1S 0h 0: No action.
1: NPU Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.16.16.3 UCERRCLR Register (Offset = 4h) [Reset = 00000000h]

UCERRCLR is shown in Figure 3-307 and described in Table 3-343.
Return to the Summary Table.
Uncorrectable Error Flag Clear Register
Figure 3-307. UCERRCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED NPURDERR RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-343. UCERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 NPURDERR R-0/W1S 0h 0: No action.
1: NPU Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn

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3.16.16.4 UCCPUREADDR Register (Offset = 6h) [Reset = 00000000h]

UCCPUREADDR is shown in Figure 3-308 and described in Table 3-344.
Return to the Summary Table.
Uncorrectable CPU Read Error Address
Figure 3-308. UCCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCPUREADDR
R-0h

Table 3-344. UCCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

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3.16.16.5 UCDMAREADDR Register (Offset = 8h) [Reset = 00000000h]

UCDMAREADDR is shown in Figure 3-309 and described in Table 3-345.
Return to the Summary Table.
Uncorrectable DMA Read Error Address
Figure 3-309. UCDMAREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCDMAREADDR
R-0h

Table 3-345. UCDMAREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCDMAREADDR R 0h This register captures the address location for which DMA read
access resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.16.16.6 UCCLA1READDR Register (Offset = Ah) [Reset = 00000000h]

UCCLA1READDR is shown in Figure 3-310 and described in Table 3-346.
Return to the Summary Table.
Uncorrectable CLA1 Read Error Address
Figure 3-310. UCCLA1READDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCLA1READDR
R-0h

Table 3-346. UCCLA1READDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCLA1READDR R 0h This register captures the address location for which CLA1 read/
fetch access resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.16.16.7 UCNPUREADDR Register (Offset = 10h) [Reset = 00000000h]

UCNPUREADDR is shown in Figure 3-311 and described in Table 3-347.
Return to the Summary Table.
Uncorrectable NPU Read Error Address
Figure 3-311. UCNPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCNPUREADDR
R-0h

Table 3-347. UCNPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCNPUREADDR R 0h This register captures the address location for which NPU read
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

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3.16.16.8 FLUCERRSTATUS Register (Offset = 1Ch) [Reset = 00000000h]

FLUCERRSTATUS is shown in Figure 3-312 and described in Table 3-348.
Return to the Summary Table.
Flash read uncorrectable ecc err status
Figure 3-312. FLUCERRSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED DIAG_H_FAIL UNC_ERR_H
R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED DIAG_L_FAIL UNC_ERR_L
R-0h R-0h R-0h

Table 3-348. FLUCERRSTATUS Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9 DIAG_H_FAIL R 0h Status of redundant and functional ECC logic comparison check.
0 : Status of redundant and functional ECC logic comparison passed.
1 : Status of redundant and functional ECC logic comparison failed.
Note :
* The field gets updated along with UNC_ERR_H
* This flag is cleared by writing a 1 to UCERRCLR.CPURDERR flag
* UCERRSET.CPURDERR has no effect on this flag.
Reset type: SYSRSn
8 UNC_ERR_H R 0h Uncorrectable error. A value of 1 indicates that an un-correctable
error occurred in upper 64bits of a 128-bit aligned address.
Note :
* This flag is cleared by writing a 1 to UCERRCLR.CPURDERR flag
* UCERRSET.CPURDERR has no effect on this flag.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1 DIAG_L_FAIL R 0h Status of redundant and functional ECC logic comparison check.
0 : Status of redundant and functional ECC logic comparison passed.
1 : Status of redundant and functional ECC logic comparison failed.
Note :
* The field gets updated along with UNC_ERR_L
* This flag is cleared by writing a 1 to UCERRCLR.CPURDERR flag
* UCERRSET.CPURDERR has no effect on this flag.
Reset type: SYSRSn
0 UNC_ERR_L R 0h Uncorrectable error. A value of 1 indicates that an un-correctable
error occurred in lower 64bits of a 128-bit aligned address.
Note :
* This flag is cleared by writing a 1 to UCERRCLR.CPURDERR flag
* UCERRSET.CPURDERR has no effect on this flag.
Reset type: SYSRSn

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3.16.16.9 FLCERRSTATUS Register (Offset = 1Eh) [Reset = 00000000h]

FLCERRSTATUS is shown in Figure 3-313 and described in Table 3-349.
Return to the Summary Table.
Flash read correctable ecc err status
Figure 3-313. FLCERRSTATUS Register
31 30 29 28 27 26 25 24
RESERVED ERR_TYPE_H ERR_POS_H
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
ERR_POS_H ERR_TYPE_L ERR_POS_L
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED FAIL_1_H FAIL_0_H RESERVED FAIL_1_L FAIL_0_L
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-349. FLCERRSTATUS Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29 ERR_TYPE_H R 0h Error type
0 Indicates that a single bit error occured in upper 64 data bits of a
128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of upper
64bits of a 128-bit aligned address.
Note :
* This field is cleared by writing a 1 to CERRCLR.CPURDERR flag
* CERRSET.CPURDERR has no effect on this field.
Reset type: SYSRSn
28-23 ERR_POS_H R 0h Error position. Bit position of the single bit error in upper 64bits of
a 128-bit aligned address. The position is interpreted depending on
whether the ERR_TYPE bit indicates a check bit or a data bit. If
ERR_TYPE indicates a check bit error, the error position could range
from 0 to 7, else it could range from 0 to 63.
Note :
* This field is cleared by writing a 1 to CERRCLR.CPURDERR flag
* CERRSET.CPURDERR has no effect on this field.
Reset type: SYSRSn
22 ERR_TYPE_L R 0h Error type
0 Indicates that a single bit error occured in lower 64 data bits of a
128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of lower
64bits of a 128-bit aligned address.
Note :
* This field is cleared by writing a 1 to CERRCLR.CPURDERR flag
* CERRSET.CPURDERR has no effect on this field.
Reset type: SYSRSn

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Table 3-349. FLCERRSTATUS Register Field Descriptions (continued)

Bit Field Type Reset Description
21-16 ERR_POS_L R 0h Error position. Bit position of the single bit error in lower 64bits of
a 128-bit aligned address. The position is interpreted depending on
whether the ERR_TYPE bit indicates a check bit or a data bit. If
ERR_TYPE indicates a check bit error, the error position could range
from 0 to 7, else it could range from 0 to 63.
Note :
* This field is cleared by writing a 1 to CERRCLR.CPURDERR flag
* CERRSET.CPURDERR has no effect on this field.
Reset type: SYSRSn
15-6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 FAIL_1_H R 0h Fail on 1.
0 Fail on 1 single bit error did not occur in upper 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper
64bits of a 128-bit aligned address and the corrected value was 1.
Note :
* This flag is cleared by writing a 1 to CERRCLR.CPURDERR flag
* CERRSET.CPURDERR has no effect on this flag.
Reset type: SYSRSn
3 FAIL_0_H R 0h Fail on 0.
0 Fail on 0 single bit error did not occur in upper 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper
64bits of a 128-bit aligned address and the corrected value was 0.
\Note :
* This flag is cleared by writing a 1 to CERRCLR.CPURDERR flag
* CERRSET.CPURDERR has no effect on this flag.
Reset type: SYSRSn
2 RESERVED R 0h Reserved
1 FAIL_1_L R 0h Fail on 1.
0 Fail on 1 single bit error did not occur in lower 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in lower
64bits of a 128-bit aligned address and the corrected value was 1.
Note :
* This flag is cleared by writing a 1 to CERRCLR.CPURDERR flag
* CERRSET.CPURDERR has no effect on this flag.
Reset type: SYSRSn
0 FAIL_0_L R 0h Fail on 0.
0 Fail on 0 single bit error did not occur in lower 64bits of 128-bit
data.
1 Would indicate that a single bit error occurred in lower 64bits of a
128-bit aligned address and the corrected value was 0.
Note :
* This flag is cleared by writing a 1 to CERRCLR.CPURDERR flag
* CERRSET.CPURDERR has no effect on this flag.
Reset type: SYSRSn

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3.16.16.10 CERRFLG Register (Offset = 20h) [Reset = 00000000h]

CERRFLG is shown in Figure 3-314 and described in Table 3-350.
Return to the Summary Table.
Correctable Error Flag Register
Figure 3-314. CERRFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0h R-0h R-0h R-0h

Table 3-350. CERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 CLA1RDERR R 0h CLA1 Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CPU read.
Reset type: SYSRSn

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3.16.16.11 CERRSET Register (Offset = 22h) [Reset = 00000000h]

CERRSET is shown in Figure 3-315 and described in Table 3-351.
Return to the Summary Table.
Correctable Error Flag Set Register
Figure 3-315. CERRSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-351. CERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.16.16.12 CERRCLR Register (Offset = 24h) [Reset = 00000000h]

CERRCLR is shown in Figure 3-316 and described in Table 3-352.
Return to the Summary Table.
Correctable Error Flag Clear Register
Figure 3-316. CERRCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-352. CERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn

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3.16.16.13 CCPUREADDR Register (Offset = 26h) [Reset = 00000000h]

CCPUREADDR is shown in Figure 3-317 and described in Table 3-353.
Return to the Summary Table.
Correctable CPU Read Error Address
Figure 3-317. CCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCPUREADDR
R-0h

Table 3-353. CCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in correctable ECC error.
Reset type: SYSRSn

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3.16.16.14 CDMAREADDR Register (Offset = 28h) [Reset = 00000000h]

CDMAREADDR is shown in Figure 3-318 and described in Table 3-354.
Return to the Summary Table.
Correctable DMA Read Error Address
Figure 3-318. CDMAREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDMAREADDR
R-0h

Table 3-354. CDMAREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CDMAREADDR R 0h This register captures the address location for which DMA read
access resulted in correctable ECC error.
Reset type: SYSRSn

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3.16.16.15 CCLA1READDR Register (Offset = 2Ah) [Reset = 00000000h]

CCLA1READDR is shown in Figure 3-319 and described in Table 3-355.
Return to the Summary Table.
Correctable CLA1 Read Error Address
Figure 3-319. CCLA1READDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCLA1READDR
R-0h

Table 3-355. CCLA1READDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CCLA1READDR R 0h This register captures the address location for which CLA1 read/
fetch access resulted in correctable ECC error.
Reset type: SYSRSn

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3.16.16.16 CERRCNT Register (Offset = 2Eh) [Reset = 00000000h]

CERRCNT is shown in Figure 3-320 and described in Table 3-356.
Return to the Summary Table.
Correctable Error Count Register
Figure 3-320. CERRCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CERRCNT
R-0h

Table 3-356. CERRCNT Register Field Descriptions

Bit Field Type Reset Description
31-0 CERRCNT R 0h This register holds the count of how many times correctable error
occurred.
Reset type: SYSRSn

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3.16.16.17 CERRTHRES Register (Offset = 30h) [Reset = 00000000h]

CERRTHRES is shown in Figure 3-321 and described in Table 3-357.
Return to the Summary Table.
Correctable Error Threshold Value Register
Figure 3-321. CERRTHRES Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CERRTHRES
R-0h R/W-0h

Table 3-357. CERRTHRES Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CERRTHRES R/W 0h When value in CERRCNT register is greater than value configured in
this register, corretable interrupt gets generated, if enabled.
Reset type: SYSRSn

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3.16.16.18 CEINTFLG Register (Offset = 32h) [Reset = 00000000h]

CEINTFLG is shown in Figure 3-322 and described in Table 3-358.
Return to the Summary Table.
Correctable Error Interrupt Flag Status Register
Figure 3-322. CEINTFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTFLAG
R-0h R-0h

Table 3-358. CEINTFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTFLAG R 0h Total corrected error count exceeded threshold Flag
0: Total correctable errors < Threshold value configured in
CERRTHRES register.
1: Total correctable errors >= Threshold value configured in
CERRTHRES register.
Reset type: SYSRSn

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3.16.16.19 CEINTCLR Register (Offset = 34h) [Reset = 00000000h]

CEINTCLR is shown in Figure 3-323 and described in Table 3-359.
Return to the Summary Table.
Correctable Error Interrupt Flag Clear Register
Figure 3-323. CEINTCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTCLR
R-0h R-0/W1S-0h

Table 3-359. CEINTCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTCLR R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be cleared.
Reset type: SYSRSn

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3.16.16.20 CEINTSET Register (Offset = 36h) [Reset = 00000000h]

CEINTSET is shown in Figure 3-324 and described in Table 3-360.
Return to the Summary Table.
Correctable Error Interrupt Flag Set Register
Figure 3-324. CEINTSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTSET
R-0h R-0/W1S-0h

Table 3-360. CEINTSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTSET R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be set and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.16.16.21 CEINTEN Register (Offset = 38h) [Reset = 00000000h]

CEINTEN is shown in Figure 3-325 and described in Table 3-361.
Return to the Summary Table.
Correctable Error Interrupt Enable Register
Figure 3-325. CEINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTEN
R-0h R/W-0h

Table 3-361. CEINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTEN R/W 0h 0: Correctable Error Interrupt is disabled.
1: Correctable Error Interrupt is enabled.
Reset type: SYSRSn

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3.16.17 TEST_ERROR_REGS Registers

Table 3-362 lists the memory-mapped registers for the TEST_ERROR_REGS registers. All register offset
addresses not listed in Table 3-362 should be considered as reserved locations and the register contents should
not be modified.
Table 3-362. TEST_ERROR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CPU_RAM_TEST_ERROR_STS Ram Test: Error Status Register Go
2h CPU_RAM_TEST_ERROR_STS_C Ram Test: Error Status Clear Register Go
LR
4h CPU_RAM_TEST_ERROR_ADDR Ram Test: Error address register Go

Complex bit access types are encoded to fit into small table cells. Table 3-363 shows the codes that are used for
access types in this section.
Table 3-363. TEST_ERROR_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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3.16.17.1 CPU_RAM_TEST_ERROR_STS Register (Offset = 0h) [Reset = 00000000h]

CPU_RAM_TEST_ERROR_STS is shown in Figure 3-326 and described in Table 3-364.
Return to the Summary Table.
Ram Test: Error Status Register
Figure 3-326. CPU_RAM_TEST_ERROR_STS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERROR COR_ERROR
R-0h R-0h R-0h

Table 3-364. CPU_RAM_TEST_ERROR_STS Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 UNC_ERROR R 0h 0: Indicates that there were no 'un-correctable errors' generated in
the RAM/ROM test mode.
1: Indicates that 'un-correctable errors' wer generated in the
RAM/ROM test mode.
Reset type: SYSRSn
0 COR_ERROR R 0h 0: Indicates that there were no 'correctable errors' generated in the
RAM/ROM test mode.
1: Indicates that 'correctable errors' wer generated in the RAM/ROM
test mode.
Reset type: SYSRSn

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3.16.17.2 CPU_RAM_TEST_ERROR_STS_CLR Register (Offset = 2h) [Reset = 00000000h]

CPU_RAM_TEST_ERROR_STS_CLR is shown in Figure 3-327 and described in Table 3-365.
Return to the Summary Table.
Ram Test: Error Status Clear Register
Figure 3-327. CPU_RAM_TEST_ERROR_STS_CLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERROR COR_ERROR
R-0h R-0/W1S-0h R-0/W1S-0h

Table 3-365. CPU_RAM_TEST_ERROR_STS_CLR Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 UNC_ERROR R-0/W1S 0h 0: No effect.
1: Clears the corresponding bit in CPU_RAM_TEST_ERROR_STS
register.
Reset type: SYSRSn
0 COR_ERROR R-0/W1S 0h 0: No effect.
1: Clears the corresponding bit in CPU_RAM_TEST_ERROR_STS
register.
Reset type: SYSRSn

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3.16.17.3 CPU_RAM_TEST_ERROR_ADDR Register (Offset = 4h) [Reset = 00000000h]

CPU_RAM_TEST_ERROR_ADDR is shown in Figure 3-328 and described in Table 3-366.
Return to the Summary Table.
Ram Test: Error address register
Figure 3-328. CPU_RAM_TEST_ERROR_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R-0h

Table 3-366. CPU_RAM_TEST_ERROR_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDR R 0h Address of the location where error was detected in RAM/ROM test
modes.
Reset type: SYSRSn

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3.16.18 UID_REGS Registers

Table 3-367 lists the memory-mapped registers for the UID_REGS registers. All register offset addresses not
listed in Table 3-367 should be considered as reserved locations and the register contents should not be
modified.
Table 3-367. UID_REGS Registers
Offset Acronym Register Name Write Protection Section
0h UID_PSRAND0 UID Psuedo-random 160 bit number Go
2h UID_PSRAND1 UID Psuedo-random 160 bit number Go
4h UID_PSRAND2 UID Psuedo-random 160 bit number Go
6h UID_PSRAND3 UID Psuedo-random 160 bit number Go
8h UID_PSRAND4 UID Psuedo-random 160 bit number Go
Ah UID_UNIQUE0 UID Unique 64 bit number Go
Ch UID_UNIQUE1 UID Unique 64 bit number Go
Eh UID_CHECKSUM UID Checksum Go

Complex bit access types are encoded to fit into small table cells. Table 3-368 shows the codes that are used for
access types in this section.
Table 3-368. UID_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value

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3.16.18.1 UID_PSRAND0 Register (Offset = 0h) [Reset = X0000000h]

UID_PSRAND0 is shown in Figure 3-329 and described in Table 3-369.
Return to the Summary Table.
UID Psuedo-random 160 bit number
Figure 3-329. UID_PSRAND0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-Xh

Table 3-369. UID_PSRAND0 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R Xh Psuedorandom portion of the UID
Reset type: N/A

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3.16.18.2 UID_PSRAND1 Register (Offset = 2h) [Reset = X0000000h]

UID_PSRAND1 is shown in Figure 3-330 and described in Table 3-370.
Return to the Summary Table.
UID Psuedo-random 160 bit number
Figure 3-330. UID_PSRAND1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-Xh

Table 3-370. UID_PSRAND1 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R Xh Psuedorandom portion of the UID
Reset type: N/A

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3.16.18.3 UID_PSRAND2 Register (Offset = 4h) [Reset = X0000000h]

UID_PSRAND2 is shown in Figure 3-331 and described in Table 3-371.
Return to the Summary Table.
UID Psuedo-random 160 bit number
Figure 3-331. UID_PSRAND2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-Xh

Table 3-371. UID_PSRAND2 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R Xh Psuedorandom portion of the UID
Reset type: N/A

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3.16.18.4 UID_PSRAND3 Register (Offset = 6h) [Reset = X0000000h]

UID_PSRAND3 is shown in Figure 3-332 and described in Table 3-372.
Return to the Summary Table.
UID Psuedo-random 160 bit number
Figure 3-332. UID_PSRAND3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-Xh

Table 3-372. UID_PSRAND3 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R Xh Psuedorandom portion of the UID
Reset type: N/A

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3.16.18.5 UID_PSRAND4 Register (Offset = 8h) [Reset = X0000000h]

UID_PSRAND4 is shown in Figure 3-333 and described in Table 3-373.
Return to the Summary Table.
UID Psuedo-random 160 bit number
Figure 3-333. UID_PSRAND4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-Xh

Table 3-373. UID_PSRAND4 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R Xh Psuedorandom portion of the UID
Reset type: N/A

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3.16.18.6 UID_UNIQUE0 Register (Offset = Ah) [Reset = X0000000h]

UID_UNIQUE0 is shown in Figure 3-334 and described in Table 3-374.
Return to the Summary Table.
UID Unique 64 bit number
Figure 3-334. UID_UNIQUE0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UniqueID
R-Xh

Table 3-374. UID_UNIQUE0 Register Field Descriptions

Bit Field Type Reset Description
31-0 UniqueID R Xh Unique portion of the UID. This identifier will be unique across all
devices with the same PARTIDH.
Reset type: N/A

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3.16.18.7 UID_UNIQUE1 Register (Offset = Ch) [Reset = X0000000h]

UID_UNIQUE1 is shown in Figure 3-335 and described in Table 3-375.
Return to the Summary Table.
UID Unique 64 bit number
Figure 3-335. UID_UNIQUE1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UniqueID
R-Xh

Table 3-375. UID_UNIQUE1 Register Field Descriptions

Bit Field Type Reset Description
31-0 UniqueID R Xh Unique portion of the UID. This identifier will be unique across all
devices with the same PARTIDH.
Reset type: N/A

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3.16.18.8 UID_CHECKSUM Register (Offset = Eh) [Reset = X0000000h]

UID_CHECKSUM is shown in Figure 3-336 and described in Table 3-376.
Return to the Summary Table.
Fletcher checksum of UID_PSRAND and UID_UNIQUE registers
Figure 3-336. UID_CHECKSUM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Checksum
R-Xh

Table 3-376. UID_CHECKSUM Register Field Descriptions

Bit Field Type Reset Description
31-0 Checksum R Xh Fletcher checksum of UID_PSRANDx and UID_UINIQUE
Reset type: N/A

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www.ti.com ROM Code and Peripheral Booting

Chapter 4
ROM Code and Peripheral Booting

This chapter explains the boot procedure, the available boot modes, and the various details of the ROM code
including memory maps, initializations, reset handling, and status information.

4.1 Introduction...............................................................................................................................................................604
4.2 Device Boot Sequence.............................................................................................................................................605
4.3 Device Boot Modes.................................................................................................................................................. 605
4.4 Device Boot Configurations.................................................................................................................................... 606
4.5 Device Boot Flow Diagrams.....................................................................................................................................611
4.6 Device Reset and Exception Handling................................................................................................................... 615
4.7 Boot ROM Description............................................................................................................................................. 617
4.8 Application Notes for Using the Bootloaders........................................................................................................648
4.9 Software.................................................................................................................................................................... 651

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4.1 Introduction
The purpose of this chapter is to explain the boot read-only memory (ROM) code functionality for the CPU core,
including the boot procedure. This chapter also discusses the functions and features of the boot ROM code, and
provides details about the ROM memory-map contents. On every reset, the device executes a boot sequence
in the ROM depending on the reset type and boot configuration. This sequence initializes the device to run the
application code. For the CPU, the boot ROM also contains peripheral bootloaders that can be used to load an
application into RAM. These bootloaders can be disabled for safety or security purposes.
See Table 4-1 for details on available boot features for the C28x CPU. Additionally, Table 4-2 shows the sizes of
the various ROMs on the device.
For details on the security APIs provided, refer to Section 4.7.10.
Various tables are provided in ROM for use in software library, refer to Section 4.7.7 for more details.
Table 4-1. Boot System Overview
Boot Feature CPU
Initial boot process Device reset
Boot mode selection GPIOs
Boot modes supported Flash boot
Secure Flash boot
Firmware update (FWU) Flash boot
RAM boot
Peripheral boot loaders supported Parallel IO
SCI / Wait
CANFD
I2C
SPI
USB

Table 4-2. ROM Memory

ROM CPU Size
Unsecure boot ROM 80KB
Secure ROM 16KB
CLA data ROM 8KB

4.1.1 ROM Related Collateral

Foundational Materials
• Bootloading 101 (Video)

Getting Started Materials

• Secure BOOT On C2000 Device Application Report

Expert Materials
• C2000 Software Controlled Firmware Update Process Application Report

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4.2 Device Boot Sequence

Table 4-3 describes the general boot ROM procedure each time the CPU core is reset.
During boot, boot ROM code updates a boot status location in RAM that details the actions taken during this
process. Refer to Section 4.7.12 for more details.
Table 4-3. Device Boot ROM Sequence
Step CPU Action
1 Initialize the device C28x CPU and M0/M1 RAM configuration
2 Initialize the device to use stack addressing mode, initialize DP to lower 64k and clear overflow mode bit
3 Trims are loaded from OTP and device configuration registers are programmed
4 On POR, all CPU RAMs (including GSxRAMs) are initialized. Boot continues once the 2KB RAMs are initialized.
5 Non-maskable interrupt (NMI) handling is enabled and DCSM initialization is performed.
6 If enabled, the MPOST POR memory test is run. The original clock frequency is NOT restored post MPOST
execution.
7 Pull-ups are enabled on unbonded IOs
Device calibration is performed, setting the analog trims. Then resets are handled and RAM is checked for
8
initialization completion.
The boot mode GPIO pins are polled to determine the boot mode to run. Boot loader is executed based on boot
9
mode/configurations. Refer to Figure 4-1 for a flow chart of the boot sequences.
10 After the application is loaded, the watchdog is enabled before executing application

4.3 Device Boot Modes

This section explains the default boot modes, as well as all the available boot modes supported on this device.
The boot ROM uses the boot mode select, general purpose input/output (GPIO) pins to determine the boot mode
configuration.
4.3.1 Default Boot Modes
Table 4-4 shows the boot mode options available for selection by the default boot mode select pins. Users have
the option to program the device to customize the boot modes selectable in the boot-up table as well as the boot
mode select pin GPIOs used.
Table 4-4. Device Default Boot Modes
GPIO24 GPIO32
Boot Mode
(Default boot mode select pin 1) (Default boot mode select pin 0)
Parallel IO 0 0
SCI / Wait Boot(1) 0 1
CAN(MCAN-NONFD) 1 0
Flash (USB)(2) 1 1

(1) SCI boot mode is used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock process.
(2) If the default Flash entry address is not programmed, the boot mode switches to USB Boot for those devices that include the USB
peripheral. On devices without a USB, the action is to enter the ITRAP ISR if the default Flash entry address is not programmed. The
switch to USB boot is only supported for the default Flash entry address option and not all entry address options.

Refer to Section 4.7.8.1 for functional details of the boot modes.

Refer to Section 4.7.9 for GPIOs used for selecting the boot modes.
Refer to Section 4.4 for details of boot configurations.

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Note
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA,
SPIA, I2CA, MCANA, and so on). Whenever these boot modes are referred to in this chapter, such as
SCI boot, the boot mode is actually referring to the first module instance, which means the SCI boot
on the SCIA port. The same applies to the other peripheral boot modes.

4.3.2 Custom Boot Modes

Once the user programs a custom boot table in user OTP, an entry in the custom table is used for booting. Users
can customize the boot mode select pins in the end system design by programming the BOOTPIN_CONFIG
location in user OTP. This allows customers to use 0, 1, 2, or 3 boot mode select pins as needed. You can
also customize the boot definition table and indicate which location to boot from by programming the boot mode
definition table in the BOOTDEF location of user OTP. Table 4-5 shows the options for various boot modes.
Table 4-5. Custom Boot Modes
Boot Mode Number Boot Modes
0 Parallel
1 SCI / Wait
2 CAN (MCAN-NONFD)
3 Flash
4 Wait
5 RAM
6 SPI
7 I2C
8 CAN-FD (MCAN-FD)
9 USB(If Applicable)
10 Secure Flash
11 FWU Flash

4.4 Device Boot Configurations

This section details what boot configurations are available and how to configure them. This device supports from
zero boot mode select pins up to three boot mode select pins as well as from one configured boot mode up to
eight configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use the
following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot option of
Flash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary boot
option of SCI boot for debugging)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: Two BMSPs are required to select
between three boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO10, BMSP1 to GPIO51,
and BMSP2 left as default that is disabled). Refer to Section 4.4.1 for all the details on performing these
configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to
the decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 4.4.2 for all the
details on setting up and configuring the custom boot mode table.
Additionally, Section 4.4.3 provides some example use cases on how to configure the BMSPs and custom boot
tables.

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4.4.1 Configuring Boot Mode Pins

This section explains how the boot mode select pins are customized by the user, by programming
the BOOTPIN-CONFIG location (refer to Table 4-6) in the user-configurable dual-zone security module
(DCSM) OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-CONFIG.
When debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-CONFIG/Z2-OTP-
BOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP.
The device can be programmed to use zero, one, two or three boot mode select pins as needed.

Note
When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location take priority
over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to use Z1-OTP-BOOTPIN-
CONFIG first and then if OTP configurations need to be altered, switch to using Z2-OTP-BOOTPIN-
CONFIG.

Table 4-6. BOOTPIN-CONFIG Bit Fields

Bit Name Description
31:24 Key Write 0x5A to these 8-bits to tell the boot ROM code that the bits in this register are
valid.
23:16 Boot Mode Select Pin 2 (BMSP2) Refer to BMSP0 description.
15:8 Boot Mode Select Pin 1 (BMSP1) Refer to BMSP0 description.
7:0 Boot Mode Select Pin 0 (BMSP0) Set to the GPIO pin to be used during boot (up to 255).
0x0 = GPIO0
0x01 = GPIO1, and so on.
Writing 0xFF disables this BMSP and this pin is no longer used to select the boot
mode.

Note
The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM
automatically selects the factory default GPIOs for BMSP0 and BMSP1. Factory default for BMSP2 is
0xFF, which disables the BMSP.
• GPIO36, GPIO38, GPIO39
• GPIO82 to GPIO210, GPIO216 to GPIO223, GPIO225, GPIO229
• GPIO231 to GPIO235, GPIO237 to GPIO241, GPIO243 to GPIO246
• GPIO248 to GPIO252, and GPIO254

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Table 4-7. Standalone Boot Mode Select Pin Decoding

BOOTPIN_CONFIG
BMSP0 BMSP1 BMSP2 Realized Boot Mode
Key
!= 0x5A Don’t Care Don’t Care Don’t Care Boot as defined by the factory default BMSPs
Boot as defined in the boot table for boot mode 0
0xFF 0xFF 0xFF
(All BMSPs disabled)
Boot as defined by the value of BMSP0
Valid GPIO 0xFF 0xFF
(BMSP1 and BMSP2 disabled)
Boot as defined by the value of BMSP1
0xFF Valid GPIO 0xFF
(BMSP0 and BMSP2 disabled)
Boot as defined by the value of BMSP2
0xFF 0xFF Valid GPIO
(BMSP0 and BMSP1 disabled)
Boot as defined by the values of BMSP0 and BMSP1
Valid GPIO Valid GPIO 0xFF
(BMSP2 disabled)
Boot as defined by the values of BMSP0 and BMSP2
Valid GPIO 0xFF Valid GPIO
(BMSP1 disabled)
= 0x5A
Boot as defined by the values of BMSP1 and BMSP2
0xFF Valid GPIO Valid GPIO
(BMSP0 disabled)
Boot as defined by the values of BMSP0, BMSP1, and
Valid GPIO Valid GPIO Valid GPIO
BMSP2
BMSP0 is reset to the factory default BMSP0 GPIO
Invalid GPIO Valid GPIO Valid GPIO Boot as defined by the values of BMSP0, BMSP1, and
BMSP2
BMSP1 is reset to the factory default BMSP1 GPIO
Valid GPIO Invalid GPIO Valid GPIO Boot as defined by the values of BMSP0, BMSP1, and
BMSP2
BMSP2 is reset to the factory default state, which is
Valid GPIO Valid GPIO Invalid GPIO disabled
Boot as defined by the values of BMSP0 and BMSP1

Note
When decoding the boot mode, BMSP0 is the least-significant bit and BMSP2 is the most-significant
bit of the boot table index value. It is recommended when disabling BMSPs to start with disabling
BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled),
then only the boot table indexes of 0 and 4 are selectable. In the instance when using only BMSP0,
then the selectable boot table indexes are 0 and 1.

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4.4.2 Configuring Boot Mode Table Options

This section explains how to configure the boot definition table, BOOTDEF, for the device and the associated
boot options. The 64-bit location is located in user-configurable DCSM OTP in the Z1-OTP-BOOTDEF-LOW and
Z1-OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and EMU-BOOTDEF-HIGH are
the emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH, and can be programmed
to experiment with different boot mode options without writing to OTP. The range of customization to the boot
definition table depends on how many boot mode select pins (BMSP) are being used. For example, 0 BMSPs
equals to 1 table entry, 1 BMSP equals to 2 table entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs
equals to 8 table entries. Refer to Section 4.4.3 for examples on how to setup the BOOTPIN_CONFIG and
BOOTDEF values.

Note
The locations Z2-OTP-BOOTDEF-LOW and Z2-OTP-BOOTDEF-HIGH is used instead of Z1-OTP-
BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations when Z2-OTP-BOOTPIN-CONFIG is
configured. Refer to Section 4.4.1 for more details on BOOTPIN_CONFIG usage.

Table 4-8. BOOTDEF Bit Fields

BOOTDEF Name Byte Position Name Description
Set the boot mode number from Section 4.3.2.
Any unsupported boot mode causes the device
[3:0] BOOT_DEF0 Mode
to either go to wait boot (debugger connected) or
boot to Flash (standalone).
BOOT_DEF0 7:0 Set alternate / additional boot options. This can
include changing the GPIOs for a particular boot
[7:4] BOOT_DEF0 Options peripheral or specifying a different Flash entry
point. Refer to Section 4.7.9 for valid BOOTDEF
values to set in the table.
BOOT_DEF1 15:8 BOOT_DEF1 Mode/Options
BOOT_DEF2 23:16 BOOT_DEF2 Mode/Options
BOOT_DEF3 31:24 BOOT_DEF3 Mode/Options
BOOT_DEF4 39:32 BOOT_DEF4 Mode/Options Refer to BOOT_DEF0 description.
BOOT_DEF5 47:40 BOOT_DEF5 Mode/Options
BOOT_DEF6 55:48 BOOT_DEF6 Mode/Options
BOOT_DEF7 63:56 BOOT_DEF7 Mode/Options

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4.4.3 Boot Mode Example Use Cases

This section demonstrates some use cases for configuring the boot mode select pins and boot modes.
4.4.3.1 Zero Boot Mode Select Pins
This use case demonstrates a scenario for an application that does not use any boot mode select pins and
always has the device boot to Flash.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to 0xFF
• Set BOOTPIN_CONFIG.BMSP1 to 0xFF
• Set BOOTPIN_CONFIG.BMSP2 to 0xFF
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot mode
table. Refer to Section 4.7.9 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x03 for booting to Flash (entry address option 0). This sets Flash boot to
boot table index 0.
• Refer to Section 4.7.2 for the available Flash entry points.
Table 4-9. Zero Boot Pin Boot Table Result
Boot Mode Table Number Boot Mode

0 Flash Boot (0x03)

4.4.3.2 One Boot Mode Select Pin

This use case demonstrates a scenario for an application using one boot mode select pin to select between
booting to Flash or using CAN boot.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to a user specified GPIO, such as 0x0 for GPIO0
• Set BOOTPIN_CONFIG.BMSP1 to 0xFF
• Set BOOTPIN_CONFIG.BMSP2 to 0xFF
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot mode
table. Refer to Section 4.7.9 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x02 for CAN booting. This sets CAN boot to boot table index 0.
• Set BOOTDEF.BOOTDEF1 to 0x03 for booting to Flash (entry address option 0). This sets Flash boot to
boot table index 1.
Table 4-10. One Boot Pin Boot Table Result
Boot Mode Table Number Boot Mode

0 CAN Boot (0x02)

1 Flash Boot (0x03)

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4.4.3.3 Three Boot Mode Select Pins

This use case demonstrates a scenario for an application using three boot mode select pins to select between
various boot modes in the custom boot table.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to a user specified GPIO, such as 0x0 for GPIO0
• Set BOOTPIN_CONFIG.BMSP1 to a user specified GPIO, such as 0x1 for GPIO1
• Set BOOTPIN_CONFIG.BMSP2 to a user specified GPIO, such as 0x2 for GPIO2
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot mode
table. Refer to Section 4.7.9 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x02 for CAN booting. This sets CAN boot to boot table index 0.
• Set BOOTDEF.BOOTDEF1 to 0x03 for booting to Flash (entry address option 0). This sets Flash boot to
boot table index 1.
• Set BOOTDEF.BOOTDEF2 to 0x24 for booting to wait boot (alternate option). This sets wait boot to boot
table index 2.
• Set BOOTDEF.BOOTDEF3 to 0x66 for SPI booting (alternate GPIO option 3). This sets SPI boot to boot
table index 3.
• Set BOOTDEF.BOOTDEF4 to 0x43 for booting to Flash (entry address option 2). This sets Flash boot to
boot table index 4.
Table 4-11. Three Boot Pins Boot Table Result
Boot Mode Table Number Boot Mode

0 CAN Boot (0x02)

1 Flash Boot (0x03)

2 Wait Boot - Alt (0x24)

3 SPI - Alt3 (0x66)

4 Flash Boot - Alt2 (0x43)

5, 6, 7 Not used in this example

4.5 Device Boot Flow Diagrams

This section details the boot flow diagrams for standalone and emulation boot flows.
4.5.1 Boot Flow
Upon reset, the CPU follows the boot flow shown in Figure 4-1. Depending on whether a JTAG debugger is
connected to the device, the CPU either continues booting following the emulation boot flow or the standalone
boot flow.

Note
BOR follows same flow as POR.

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Security (SCC)
NMI Watchdog HWBIST POR XRS Debugger Watchdog
Reset

Note: Any resets that also cause the XRS reset bit to be set (excluding
CPU Boot Start
POR) will follow the flow relating to an XRS reset.

Set CSTCRET value as application Value All other

Read
HWBIST Reset Cause resets
address Set CSTCRET
No

Value
FUSE Single Bit
is Yes
Error? Error?
Branch to Application zero

Yes
Disable wdg No

Configure Flash pump

Initialize subset of M0RAM
Reset Cause POR or XRS Set Clock Divider to /1 wakeup time and wait
boot stack space to zero
states for 15MHz Timeout

HWBIST, SCC, or
Debugger Reset Wait for
Timeout
Device Configuration
- PARTIDH/L Load
Initialize all of boot ROM stack space
XRS Reset Cause - DCX Load Set pump and bank power mode to Flash Powered up/
in M0RAM to zero
- CPUROM DCx Load active Timeout expired
- Package bonding config

Flash powered up
POR

RAM Initialization (all RAMS) Watchdog Config

(enable/disable via TI OTP)
Delay for
2KB RAMs only

Load VREGCTL.ENMASK from TI

OTP (3 NOPS, min 1uS delay
ERROR_STS Pin Config POR /
DCSM Initialization Reset Cause cJTAG Config needed)
(24/28/29) XRSn

Load PMM Trims (75us blanking)

Load INTOSC Trims (12us)

Lock DC configurations
Enable NMI All other Resets Reset Cause Load APLL Trims and APLL analog
config registers

POR

Capture any single bit flash Enable PLL and switch PLL O/P to
error addresses PBIST Enabled drive sysclk (TI OTP flag)
Verify RAM init
Field in
Is complete
GPREG2
=0x5A
Set flash pump wakeup time and wait
states for 120MHz
RAM Init complete
(delay if not complete)
Disabled
Check Z2/Z1 ROM
GPREG2 key integrity check
with BGCRC Run PBIST Memory Test
Adjust PLL clock as Passed (log staus)
configured in OTP
Any other value RAM Initialization (all RAMs)
(Wait for M0 RAM init)
Failed

Enable pull ups on unbonded IOs

Re-initialize local and global variables
lost during RAMINIT

POR/XRS: Switch sysclk

to bypass and turn off PLL

Device
Calibration (ROM Code)

Clear POR/XRS reset

causes

Disable watchdog (if

enabled via TI OTP)

Wait of RAMInit
Completion (give error
status on timeout)

Is Debugger
Standalone Boot No Yes Emulation Boot
Connected?

Figure 4-1. Device Boot Flow

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4.5.2 Emulation Boot Flow

Figure 4-2 shows the emulation boot flow when JTAG debugger is connected.

Emulation Boot Mode Start

Read EMU boot locations:

BOOTPINCONFIG
EMUBOOTDEF

Unsupported
(=0xA5) Check Key
Emulate Wait
EMU_BOOTPIN_CON
Standalone Boot Boot
FIG_KEY

(=0x5A)

Get EMU Configurable user boot

mode options

Read Boot Mode Select Pins from

BOOTPINCONFIG and set GPIO
state

Unsupported
Decode Boot mode
BOOTDEF options for Wait Boot
boot mode

Supported
Boot mode

Is Flash /
Yes
Secure Flash / FWU Flash
Boot?

No

Start the peripheral loader process or

Enable
set address to branch
Watchdog

Enable
Watchdog

Branch to Application Code Branch to Flash Entry Point

Figure 4-2. Emulation Boot Flow

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4.5.3 Standalone Boot Flow

Figure 4-3 shows the standalone boot flow when no JTAG debugger is connected to the device.
Standalone Boot Mode Start

Read OTP loaded registers:

Z2-BOOTPINCONFIG

Any
Check Other
Z2 value Read OTP loaded registers:
OTP_BOOTPIN_C Z1-BOOTPINCONFIG
ONFIG_KEY

Any
Check Other
Z1 value Read factory default two boot
OTP_BOOTPIN_C mode GPIO pins
(=0x5A)
ONFIG_KEY

(=0x5A)
Decode boot mode from pins
Use Z2 registers: Use Z1 registers:
Z2-BOOTPINCONFIG Z1-BOOTPINCONFIG
Z2-BOOTDEF Z1-BOOTDEF

Execute one of the following:

Parallel Boot
SCI Boot
CAN Boot
Flash Boot
Read Boot Mode Select Pins
specified from
BOOTPINCONFIG

Enable
Watchdog

Unsupported
Decode Boot mode
BOOTDEF table Flash Boot
for boot mode Branch to
Parallel Boot Application Code
SPI Boot
SCI Boot
CAN Boot Supported
CAN-FD Boot Boot mode
Flash Boot
Secure Flash Boot (C28x AES)
FWU Flash Boot
Is Flash Yes
Boot?

No

Start the peripheral loader Enable

process or set address to branch Watchdog

Enable
Watchdog

Branch to Application Code Branch to

Flash Entry Point

Figure 4-3. CPU Standalone Boot Flow

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4.6 Device Reset and Exception Handling

4.6.1 Reset Causes and Handling
Table 4-12 explains the actions each boot ROM performs upon reset for a specific reset cause.
Table 4-12. Boot ROM Reset Causes and Actions
Reset Source Boot ROM Action
1. Configure Clock Divider
2. Flash Power Up
3. Device configuration and trimming
Power-On Reset (POR)
4. Lock PLL and use PLL if configured to do so
5. RAM Initialization
6. Continue default boot flow
1. Configure Clock Divider
External Reset (XRS)
2. Flash Power Up
Includes:
• Watchdog Reset (WDRS) 3. Device configuration and trimming
• NMI Watchdog Reset (NMIWDRS) 4. Lock PLL and use PLL if configured to do so
• Simulate External Reset (SIMRESET.XRS) 5. Clear boot stack
6. Continue default boot flow
1. No change to CLK dividers or RAM
Secure Copy Code Reset (SCCRESET) 2. Clear boot stack
3. Continue default boot flow
1. No change to CLK dividers or RAM
Simulate CPU Reset (SIMRESET) 2. Clear boot stack
3. Continue default boot flow
1. No change to CLK dividers or RAM
Debugger Reset (SYSRS) 2. Clear boot stack
3. Continue default boot flow

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4.6.2 Exceptions and Interrupts Handling

Table 4-13 explains the actions boot ROM performs if any exceptions occur during boot. The exception handling
philosophy in most cases, is to log the error and continue booting to reach the application.
Table 4-13. Boot ROM Exceptions and Actions
Exception Event Source Boot ROM Action Event Logged
Clock Fail Clear the NMI flag and continue to boot Yes
RAM Uncorrectable Error Perform RAM initialization and reset the device Yes(1)
ROM Parity Error
Flash Uncorrectable Error Reset the device Yes
System Debug (ERAD) NMI Clear the NMI flag and continue to boot Yes
RL NMI (CLB) Clear the NMI flag and continue to boot Yes
ITRAP Exception Record memory address of where the illegal instruction was Yes
executed and let device reset
Unsupported PIE Interrupts Ignore and continue to boot No
OVF (Over Voltage Fault) Not in the scope of boot code, let the device reset No
Software Error Software Self-test Error (SW writes to the NMI FLAG). Not in the No
scope of the boot code, let the device reset

(1) A RAM uncorrectable error or ROM parity error clears the boot status information stored in RAM because a RAM initialization is
performed to attempt to correct the error. Since the boot status information is erased, this exception can be identified in that a NMIWD
reset occurred and all the RAMs are erased.

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4.7 Boot ROM Description

This section explains the details regarding the device boot ROMs.
4.7.1 Boot ROM Configuration Registers
The boot ROM code involves several memory addresses and registers used during execution. There are two
sets of configurations; one for emulation and one for standalone boot flow. The emulation locations located in
RAM emulate the OTP configurations and can be written to as many times as needed. The user configurable
DCSM OTP locations used in the standalone boot flow program the device OTP and hence can only be written
once. Table 4-14 details these locations. For bit field configuration details for BOOTPIN-CONFIG and BOOTDEF,
see Section 4.4.1 and Section 4.4.2.
Additionally, the boot ROM supports boot configurations from DCSM zone 1 and zone 2 registers. Zone 2
configurations supercede zone 1 configurations, so it is recommended to use zone 1 configurations and use
zone 2 as a secondary option.
Table 4-14. Boot ROM Registers
Boot Flow Register Name Boot ROM Name Register Address User OTP Address
- EMU-BOOTPIN-CONFIG 0x0000 0D00 -
- EMU-GPREG2 0x0000 0D02 -
Emulation - EMU-BOOTDEF-LOW 0x0000 0D04 -
- EMU-BOOTDEF-HIGH 0x0000 0D06 -
Z1-GPREG1 Z1-OTP-BOOTPIN-CONFIG 0x0005 F008 0x0007 8008

Standalone Z1-GPREG2 Z1-OTP-BOOT-GPREG2 0x0005 F00A 0x0007 800A

(Using Z1) Z1-GPREG3 Z1-OTP-BOOTDEF-LOW 0x0005 F00C 0x0007 800C
Z1-GPREG4 Z1-OTP-BOOTDEF-HIGH 0x0005 F00E 0x0007 800E
Z2-GPREG1 Z2-OTP-BOOTPIN-CONFIG 0x0005 F088 0x0007 8208

Standalone Z2-GPREG2 Z2-OTP-BOOT-GPREG2 0x0005 F08A 0x0007 820A

(Using Z2) Z2-GPREG3 Z2-OTP-BOOTDEF-LOW 0x0005 F08C 0x0007 820C
Z2-GPREG4 Z2-OTP-BOOTDEF-HIGH 0x0005 F08E 0x0007 820E

4.7.1.1 Flash Write Protection

The Z1 GPREG2 register in OTP can selectively enable and disable write protection for selected Flash sectors
in Flash banks 0 and 2. When the selected bits are programmed to a value of 0, the corresponding sectors
can no longer be erased or programmed. This capability allows the user to create immutable Flash regions and
along with the DCSM security module can be used to realize new secure code functions, including authentication
algorithms.
Table 4-15 explains how the bit field values from the user configurable DCSM OTP location, Z1-OTP-BOOT-
GPREG2 or Z2-OTP-BOOT-GPREG2, are decoded by boot ROM.

Note
Z1-GPREG2 shares ECC with Z1-GPREG1, so users must program both these locations at the same
time in User OTP.

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Table 4-15. DCSM Z1 GPREG2 Bit Fields

Bit Name Description Boot ROM Action
31:24 Key Write 0x5A to indicate to the boot ROM code that If user sets to 0x5A, boot ROM uses the values in
the bits in this register are valid. this register. If set to any other value, boot ROM
ignores values in this register.
23(2) WPROT_BANK2_ Write Protect Flash Bank 2 Sectors 28-31 0: Flash sectors cannot be erased or programmed
SEC_28_31 1: Flash sectors can be erased or programmed
22(2) WPROT_BANK2_ Write Protect Flash Bank 2 Sectors 24-27 0: Flash sectors cannot be erased or programmed
SEC_24_27 1: Flash sectors can be erased or programmed
21(2) WPROT_BANK2_ Write Protect Flash Bank 2 Sectors 20-23 0: Flash sectors cannot be erased or programmed
SEC_20_23 1: Flash sectors can be erased or programmed
20(2) WPROT_BANK2_ Write Protect Flash Bank 2 Sectors 16-19 0: Flash sectors cannot be erased or programmed
SEC_16_19 1: Flash sectors can be erased or programmed
19(2) WPROT_BANK2_ Write Protect Flash Bank 2 Sectors 12-15 0: Flash sectors cannot be erased or programmed
SEC_12_15 1: Flash sectors can be erased or programmed
18(2) WPROT_BANK2_ Write Protect Flash Bank 2 Sectors 8-11 0: Flash sectors cannot be erased or programmed
SEC_8_11 1: Flash sectors can be erased or programmed
17(2) WPROT_BANK2_ Write Protect Flash Bank 2 Sectors 0-7 0: Flash sectors cannot be erased or programmed
SEC_0_7 1: Flash sectors can be erased or programmed
16(2) Reserved Reserved No Action
15(2) WPROT_BANK0_ Write Protect Flash Bank 0 Sectors 28-31 0: Flash sectors cannot be erased or programmed
SEC_28_31 1: Flash sectors can be erased or programmed
14(2) WPROT_BANK0_ Write Protect Flash Bank 0 Sectors 24-27 0: Flash sectors cannot be erased or programmed
SEC_24_27 1: Flash sectors can be erased or programmed
13(2) WPROT_BANK0_ Write Protect Flash Bank 0 Sectors 20-23 0: Flash sectors cannot be erased or programmed
SEC_20_23 1: Flash sectors can be erased or programmed
12(2) WPROT_BANK0_ Write Protect Flash Bank 0 Sectors 16-19 0: Flash sectors cannot be erased or programmed
SEC_16_19 1: Flash sectors can be erased or programmed
11(2) WPROT_BANK0_ Write Protect Flash Bank 0 Sectors 12-15 0: Flash sectors cannot be erased or programmed
SEC_12_15 1: Flash sectors can be erased or programmed
10(2) WPROT_BANK0_ Write Protect Flash Bank 0 Sectors 8-11 0: Flash sectors cannot be erased or programmed
SEC_8_11 1: Flash sectors can be erased or programmed
9(2) WPROT_BANK0_ Write Protect Flash Bank 0 Sectors 0-7 0: Flash sectors cannot be erased or programmed
SEC_0_7 1: Flash sectors can be erased or programmed
8:7 MPOST(1) 0x0 = Run MPOST with PLL disabled When configured to a valid value, MPOST POR
(10MHz internal oscillator) memory self-test runs on all device memories
0x1 = Run MPOST with PLL enabled for 150MHz
0x2 = Run MPOST with PLL enabled for 75MHz
0x3 = Disable MPOST
6:4 ERROR_ 0x0 – GPIO24, MUX Option 13 This indicates which GPIO pin is supposed to be
STS_PIN used as ERROR_PIN and boot ROM configures
0x1 – GPIO28, MUX Option 13
configuration the mux the pin. The ERROR_STS pin mux
0x2 – GPIO29, MUX Option 13 configuration is locked by the boot ROM, but is not
0x3 – ERROR_STS function disabled committed.

0x4 – GPIO55, MUX Option 9

0x5 – GPIO64, MUX Option 13
0x6 – GPIO73, MUX Option 13
0x7 – ERROR_STS function disabled (default)
3:0 CJTAGNODEID CJTAGNODEID[3:0] Boot ROM takes this values and programs the
lower 4 bits of the CJTAGNODEID register.

(1) If MPOST is configured to run with PLL enabled and the PLL fails to lock, then the MPOST run is skipped. This does not apply, if
MPOST is configured to use INTOSC2 with PLL disabled.
(2) Bits 23:9 are only present on Z1 GPREG2 and are reserved for Z2 GPREG2

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4.7.1.2 MPOST Configuration

Two separate OTP locations determine if MPOST (Memory Power On Self Test) runs after a Power on Reset
(POR) event. The first is the Z1/Z2 GPREG2 that is part of the Z1/Z2 OTP. The second is the Z1/Z2 DIAG
location that is part of the Zone Select Block of the OTP. While both locations are in the OTP, and are write once
only, the DIAG register is duplicated along with the other locations if the Link-Pointer is incremented.
Table 4-15 explains how the bit field values from the user configurable DCSM OTP location, Z1-OTP-BOOT-
GPREG2 or Z2-OTP-BOOT-GPREG2, are decoded by boot ROM.

Note
Z1-GPREG2 shares ECC with Z1-GPREG1, so users can program both these locations at the same
time in User OTP.

Table 4-16 explains how the bit field values from the user configurable DCSM OTP location, Z1-DIAG or
Z2-DIAG, are decoded by the boot ROM.

Table 4-16. DCSM Z1/Z2 DIAG Bit Fields

Bit Name Description Boot ROM Action
31:6 Reserved Reserved No Action
5:4 MPOST_EN 0x0 - Disable MPOST Value of 1 along with correct value in GPREG2 allows MPOST to run
after POR event. All other values disable MPOST.
0x1 - Enable MPOST
0x2 - Disable MPOST
0x3 - Disable MPOST
3:0 Reserved Reserved No Action

4.7.2 Entry Points

This sections gives details about the entry point addresses for various boot modes. These entry points direct the
boot ROM what address to branch to at the end of booting as per the selected boot mode.
Table 4-17 gives the entry point addresses for Flash boot mode.
Table 4-18 gives the entry point addresses for RAM boot mode.
Table 4-17. Flash Entry Point Addresses
Option BOOTDEFx Value Flash Sector Address Devices Supported
0 0x03 Bank 0 Sector 0 0x0008 0000 All
1 0x23 Bank 0 Sector 32 0x0008 8000 All
2 0x43 Bank 2 Sector 0 0x000C 0000 All
3 0x63 Bank 2 Sector 32 0x000C 8000 All
4 0x83 Bank 4 Sector 0 0x0010 0000 Device Dependent

Table 4-18. RAM Entry Point Address

Option BOOTDEFx Value RAM Entry Point Package Supported
0 0x05 0x0000 0000 All

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4.7.3 Wait Points

The wait mode puts the CPU in a loop in the boot ROM code and does not branch to the user application
code. The device can enter wait boot mode either through manually being set or because of some issue during
boot up. Using wait boot mode is recommended when using a debugger to avoid any JTAG issues. There is an
ESTOP provided for debugging during Wait boot.
Table 4-19. Wait Boot Options
Option BOOTDEFx Value Watchdog Status Device Supported
0 (default) 0x04 Enabled All
1 0x24 Disabled All

During boot ROM execution, there are situations where the CPU can enter a wait loop in the code. This state
can occur for a variety of reasons. Table 4-20 details the address ranges that the CPU PC register value falls
between if the CPU has entered one of these instances.
Following are the actions for entering wait boot mode:
• Wait boot is set by the user as the boot mode.
• Boot mode is unrecognizable and a debugger is connected to the device.
• The emulation BOOTPIN_CONFIG key is not equal to 0xA5 or 0x5A.
• An error occurs during emulation boot and the boot mode pins are decoded with a value not recognized as a
valid boot mode.
Table 4-20. Wait Point Addresses
Address Range Description
0x3F B8B9-0x3F B8C0 In Wait Boot Mode
0x3F C7D0-0x3F C7D8 In SCI Boot waiting on autobaud lock
0x3F EDFE-0x3F EEC8 In NMI Handler
0x3F EEC9-0x3F EEF9 In ITRAP ISR
0x3F CB96-0x3F CB9A In Parallel boot waiting for control signal

4.7.4 Secure Flash Boot

Secure Flash boot mode is similar to Flash boot mode in that the boot flow branches to the configured
memory address in Flash except only after the Flash memory contents have been authenticated. The Flash
authentication uses a Cipher-based Message Authentication Protocol (CMAC) to authenticate 16KB of Flash
starting from the configured Flash entry point address. The CMAC calculation requires a user-defined 128-bit
key programmed in the CPU User OTP Zone 1 Header OTP CMACKEY bit field. Additionally, calculate the
golden CMAC tag based on the 16KB Flash memory range and store the CMAC tag along with the user code
at a hardcoded address in Flash. During secure Flash boot, the calculated CMAC tag is compared to the user
golden CMAC tag in Flash to determine the pass/fail status of the CMAC authentication. When authentication
passes, boot flow continues and branches to Flash to begin executing the application. When authentication fails,
the device is reset.
For the available secure Flash boot entry address options, refer to Section 4.7.2.
For generating the secure Flash golden CMAC tag for CPU, refer to the TMS320C28x Assembly Language
Tools User’s Guide within section “Using Secure Flash Boot on TMS320F2838x Devices” for instructions.

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Note
Both the CMAC golden signature and CMAC key are stored in the most-significant double format, but
each 32-bit section is in little-endian format.
Key: 2B7E 1516 28AE D2A6 ABF7 1588 09CF 4F3C
(MSB is 2B and LSB is 3C)
CMACKEY0 = 0x2B7E 1516
CMACKEY1 = 0x28AE D2A6
CMACKEY2 = 0xABF7 1588
CMACKEY3 = 0x09CF 4F3C
Make sure that the Flash sector that encompasses the configured Flash entry point and the first 16KB
of Flash is assigned to Zone 1 for the core setup for secure Flash boot.
Recommended to use device JTAGLOCK when using secure Flash boot.

APIs for CMAC calculation and authentication is provided as part of ROM. Details are available in Section 4.7.10
Table 4-21. Secure Flash Tag and Key Details
Name Address Details
CMAC Golden Tag CPU: Located in Flash, offset from the entry point address, by 2 words (CPU).
(128-bit) Flash Entry Point Address + 0x2 When CMAC calculations are performed, the golden tag location in memory
is considered all 0xF. Refer to Example 4-1 for an example regarding linker
configuration on CPU.
Lower memory contains the tag most-significant word (MSW) and higher
memory contains the least-significant word (LSW).
Example (on CPU):
Tag = 0x0011 2233 4455 6677 8899 AABB CCDD EEFF
Address 0x0 = 0x0011 2233
Address 0x2 = 0x4455 6677
Address 0x4 = 0x8899 AABB
Address 0x6 = 0xCCDD EEFF
CMAC 128-Bit Key 0x0007 8018 Located in CPU Zone 1 User Header OTP
(CMACKEY0, CMACKEY1, CMACKEY2, CMACKEY3)
CMACKEY0 contains the key MSW and CMACKEY3 contains the LSW.
Example:
Key = 0x0011 2233 4455 6677 8899 AABB CCDD EEFF
CMACKEY0 = 0x0011 2233
CMACKEY1 = 0x4455 6677
CMACKEY2 = 0x8899 AABB
CMACKEY3 = 0xCCDD EEFF
Address Range for Start: Flash Entry Point Address
CMAC Calculation End: Flash Entry Point Address + 16KB

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Table 4-22. Secure Flash Entry Point Addresses

Option BOOTDEFx Value Flash Sector Address Devices Supported
0 0x0A Bank 0 Sector 0 0x0008 0000 All
1 0x2A Bank 0 Sector 32 0x0008 8000 All
2 0x4A Bank 2 Sector 0 0x000C 0000 All
3 0x6A Bank 2 Sector 32 0x000C 8000 All
4 0x83 Bank 4 Sector 0 0x0010 0000 Device Dependent

Table 4-23. Secure Flash Authentication Failure Actions

CPU Action on Failed Authentication
1. Emulation only - Halt debugger (ESTOP)
C28x CPU
2. Wait in endless loop (for device reset due to a watchdog reset)

Table 4-24. Secure Flash on all CPUs Recommended Flow

Step Action
1 Secure Flash boot CPU
Any Flash beyond the first 16KB from the entry point that is planned for use can be authenticated by the user using a
2
different CMAC golden tag embedded at an address somewhere within the already authenticated 16KB of Flash.

Example 4-1. Secure Flash CPU1 Linker File Example

MEMORY
{
/* Code Start branch to _c_int00 */
BEGIN : origin = 0x80000, length = 0x0002
/* User calculated golden CMAC tag for Flash Sector 0 */
GOLDEN_CMAC_TAG : origin = 0x80002, length = 0x0008
/* Flash Sector 0 containing application code */
FLASH_SECTOR_0 : origin = 0x8000A, length = 0x1FF6
.
.
.
}

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4.7.5 Firmware Update (FWU) Flash Boot

Firmware Update (FWU) boot mode is required to handle the FWU feature. In this boot mode, the boot loader
reads the version number from images present in multiple banks and identifies the latest image. The boot ROM
then hands off the execution to the application with the latest version. To support FWU boot mode each Flash
bank containing an application image needs a few fields as shown in Table 4-25.
Table 4-25. FWU Application Image Format
Image Address Offset Content

0x0 Application entry point (32-bit)

0xA Key (32-bit)

Valid Key = 0x5A5A 5A5A

0xC Firmware version number (32-bit)

Application entry point: This is the code execution start address of the image stored in Flash.
Key: This 32-bit field determines if this image is valid. The image in a bank is considered valid only if the location
contains the value 0x5A5A 5A5A. In case all the banks have invalid keys, an error is flagged in the boot_status
variable and the program jumps to a while loop in standalone boot mode (ESTOP in emulation boot mode).
Firmware version number: This 32-bit field is the version number of the firmware or application. 0xFFFF FFFF
is considered as the initial value and this needs to be decremented after every update. The image with the lower
version number is the latest application. If all valid images have the same version number, then bank-0 (or the
lowest numbered bank) is chosen.
For example, if bank-0 has invalid Key and bank-1 and bank-2 have valid keys, then the one having the lowest
Firmware version number is selected for boot. If both are the same, then bank-1 is selected.
Table 4-26 shows the entry points for FWU boot mode.
Table 4-26. FWU Entry Point Addresses
Option BOOTDEFx Value Bank 0 Bank 2
0 0x0B 0x0008 0000 0x000C 0000
1 0x2B 0x0008 8000 0x000C 8000

For example, if Option 0 with Bank 0 has the application image:

[0008 0000-0008 0001] = Application entry point
[0008 000A-0008 000B] = Key
[0008 000C-0008 000D] = Firmware version number

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4.7.6 Memory Maps

4.7.6.1 Boot ROM Memory Maps
Table 4-27 details the ROM memory map.
Table 4-27. Boot ROM Memory Map
Memory Origin Address Length (Words) - TBD
Boot Code 0x0F AC8C 0x4F74
ROM Signature 0x3F 8000 0x0002
Version 0x3F 8002 0x0004
IQmath Tables 0x3F 8006 0x1674
FPU32 Fast Tables 0x3F 967A 0x081A
FPU32 Twiddle Tables 0x3F 9E94 0x0DF8
Interrupt Handlers 0x3F FC00 0x020E
RTS Lib 0x3F FF0E 0x01A8
CRC Table 0x3F FFB6 0x0008
Vector Table 0x3F FFBE 0x0042

Table 4-28 details the secure ROM memory map.

Table 4-28. Secure ROM Memory Map
Memory Origin Address Length
Zone 1 Secure-Copy / CRC Code 0x3F 4C00 0x0600
Zone 1 Secure Flash Boot 0x3F 4000 0x0C00
Zone 2 Secure-Copy / CRC Code 0x3F 5600 0x05F0
Reserved 0x3F 5BF0 0x0010

4.7.6.2 CLA Data ROM Memory Maps

Table 4-29 details the CLA data ROM memory map.

Note
Load refers to the memory addresses where the C28x CPU can view the data. Run refers to the CLA
memory addresses that the CLA uses to access the data.

Table 4-29. CLA Data ROM Memory Map

Memory Origin Address Length (Words)
FFT Tables (Load) 0x0100 1070 0x0800
Data (Load) 0x0100 1870 0x078A
Version (Load) 0x0100 1FFA 0x0006
FFT Tables (Run) 0x0000 F070 0x0800
Data (Run) 0x0000 F870 0x078A
Version (Run) 0x0000 FFFA 0x0006

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4.7.6.3 Reserved RAM Memory Maps

Table 4-30 details memory usage in RAM that is reserved for the boot ROM to use. These memory sections can
be reserved in the user application.
Table 4-30. Reserved RAM Memory Map
Memory Description Origin Address Length (Words)
RAM Boot Status, Boot Mode, MPOST Status, Boot Stack 0x0000 0002 0x01BE

4.7.7 ROM Tables

Table 4-31 details the boot ROM symbol libraries that can be integrated into an application to use the available
ROM functions and tables.
Table 4-31. ROM Symbol Tables
ROM Symbols Library Name Location
ROM Bootloaders and Functions F28P55xCPU_BootROM_Symbols
FPU32 Tables F28P55xCPU_BootROM_Symbols Under /libraries/boot_rom in C2000Ware
IQmath F28P55xCPU_IQMathROM_Symbols

4.7.8 Boot Modes and Loaders

The available boot modes and bootloaders supported on this device are detailed in this section.
4.7.8.1 Boot Modes
Table 4-32 lists the available boot modes that do not involve a peripheral boot loader.
Table 4-32. Boot Mode Availability
Boot Mode CPU Support
Flash Boot C28x CPU
RAM Boot C28x CPU
Wait Boot C28x CPU
Secure Flash Boot C28x CPU
FWU Flash Boot C28x CPU

4.7.8.1.1 Flash Boot

Flash boot mode branches to the configured memory address in Flash. Refer to Section 4.7.2 for all the
available Flash address options.
4.7.8.1.2 RAM Boot
RAM boot mode branches to the configured memory address in RAM. Refer to Section 4.7.2 for all the available
RAM address options.
4.7.8.1.3 Wait Boot
Wait boot mode branches to the memory address as mentioned in Section 4.7.3.
Table 4-33. Wait Boot Options
Option BOOTDEFx Value Watchdog Status Package Supported
0 (default) 0x04 Enabled All
1 0x24 Disabled All

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4.7.8.2 Bootloaders
This section details the available boot modes that use a peripheral boot loader. For more specific details on the
supported data stream structure used by the following bootloaders, refer to Section 4.8.1.
4.7.8.2.1 SCI Boot Mode
The SCI boot mode asynchronously transfers code from SCI-A to internal memory. This boot mode only
supports an incoming 8-bit data stream and follows the data flow as shown in Figure 4-4.

Figure 4-4. Overview of SCI Bootloader Operation

The device communicates with the external host by communication through the SCI-A peripheral. The autobaud
feature of the SCI port is used to lock baud rates with the host. For this reason the SCI loader is very flexible and
you can use a number of different baud rates to communicate with the device.
After each data transfer, the bootloader echoes back the 8-bit character received to the host. This allows the
host to check that each character was received by the bootloader.
At higher baud rates, the slew rate of the incoming data bits can be affected by transceiver and connector
performance. While normal serial communications can work well, this slew rate can limit reliable auto-baud
detection at higher baud rates (typically beyond 100 kbaud) and cause the auto-baud lock feature to fail. To
avoid this, the following is recommended:
1. Achieve a baud-lock between the host and SCI bootloader using a lower baud rate.
2. Load the incoming application or custom loader at this lower baud rate.
3. The host can then handshake with the loaded application to set the SCI baud rate register to the desired
high baud rate.

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Figure 4-5. Overview of SCI Boot Function

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4.7.8.2.2 SPI Boot Mode

The SPI loader expects an SPI-compatible 16-bit or 24-bit addressable serial EEPROM or serial Flash device
to be present on the SPI-A pins as shown in Figure 4-6. The SPI bootloader supports an 8-bit data stream and
does not support a 16-bit data stream.

Figure 4-6. Overview of SPI Bootloader Operation

The SPI boot ROM loader initializes the SPI module to interface to a serial SPI EEPROM or Flash. Devices
of this type include, but are not limited to, the Xicor X25320 (4Kx8) and Xicor X25256 (32Kx8) SPI serial SPI
EEPROMs and the Atmel AT25F1024A serial Flash.
The SPI boot ROM loader initializes the SPI with the following settings: FIFO enabled, 8-bit character, internal
SPICLK controller mode and talk mode, clock phase = 1, polarity = 0, using the slowest baud rate.
If the download is to be performed from an SPI port on another device, then that device must be set up to
operate in the peripheral mode and mimic a serial SPI EEPROM. Immediately after entering the SPI_Boot
function, the pin functions for the SPI pins are set to primary and the SPI is initialized. The initialization is done at
the slowest speed possible. Once the SPI is initialized and the key value read, you can specify a change in baud
rate or low-speed peripheral clock. Table 4-34 shows the 8-bit data stream used by the SPI.
Table 4-34. SPI 8-Bit Data Stream
Byte Contents
1 LSB: AA (KeyValue for memory width = 8 bits)
2 MSB: 08h (KeyValue for memory width = 8 bits)
3 LSB: LOSPCP
4 MSB: SPIBRR
5 LSB: reserved for future use
6 MSB: reserved for future use
... Reserved
17 LSB: reserved for future use
18 MSB: reserved for future use
19 LSB: Upper half (MSW) of Entry point PC[23:16]
20 MSB: Upper half (MSW) of Entry point PC[31:24] (Note: Always 0x00)
21 LSB: Lower half (LSW) of Entry point PC[7:0]
22 MSB: Lower half (LSW) of Entry point PC[15:8]
... ....
... Data for this section.
... Blocks of data in the format size/destination address/data as shown in the generic data stream description
... ...
... Data for this section.
n LSB: 00h
n+1 MSB: 00h - indicates the end of the source

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The data transfer is done in "burst" mode from the serial SPI EEPROM. The transfer is carried out entirely in
byte mode (SPI at 8 bits/character). A step-by-step description of the sequence is:
1. The SPI-A port is initialized.
2. The GPIO pin, as defined by SPI option configured from Table 4-45, is used as a chip-select for the serial
SPI EEPROM or Flash.
3. The SPI-A outputs a read command for the serial SPI EEPROM or Flash.
4. The SPI-A sends the serial SPI EEPROM an address 0x0000; that is, the host requires that the EEPROM or
Flash must have the downloadable packet starting at address 0x0000 in the EEPROM or Flash. The loader
is compatible with both 16-bit addresses and 24-bit addresses.
5. The next word fetched must match the key value for an 8-bit data stream (0x08AA). The least-significant
byte of this word is the byte read first and the most-significant byte is the next byte fetched. This is true of
all word transfers on the SPI. If the key value does not match, then the load is aborted and the bootloader
jumps to Flash.
6. The next two bytes fetched can be used to change the value of the low speed peripheral clock register
(LOSPCP) and the SPI baud rate register (SPIBRR). The first byte read is the LOSPCP value and the
second byte read is the SPIBRR value. The next seven words are reserved for future enhancements. The
SPI bootloader reads these seven words and discards them.
7. The next two words makeup the 32-bit entry point address where execution continues after the boot load
process is complete. This is typically the entry point for the program being downloaded through the SPI port.
8. Multiple blocks of code and data are then copied into memory from the external serial SPI EEPROM through
the SPI port. The blocks of code are organized in the standard data stream structure presented earlier. This
is done until a block size of 0x0000 is encountered. At that point in time the entry point address is returned to
the calling routine that then exits the bootloader and resumes execution at the address specified.

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Figure 4-7. Data Transfer from EEPROM Flow

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4.7.8.2.3 I2C Boot Mode

The I2C bootloader expects an 8-bit wide I2C-compatible EEPROM device to be present at address 0x50 on
the I2C-A bus as shown in Figure 4-8. The EEPROM must adhere to conventional I2C EEPROM protocol, as
described in this section, with a 16-bit base address architecture.

Figure 4-8. EEPROM Device at Address 0x50

If the download is to be performed from a device other than an EEPROM, then that device must be set up to
operate in the peripheral mode and mimic the I2C EEPROM. Immediately after entering the I2C boot function,
the GPIO pins are configured for I2C-A operation and the I2C is initialized. The following requirements must be
met when booting from the I2C module:
• The input frequency to the device must be in the appropriate range.
• The EEPROM must be at peripheral address 0x50.

The bit-period prescalers (I2CCLKH and I2CCLKL) are configured by the bootloader to run the I2C at a
50 percent duty cycle at 100kHz bit rate (standard I2C mode) when the system clock is 10MHz. These registers
can be modified after receiving the first few bytes from the EEPROM. This allows the communication to be
increased up to a 400kHz bit rate (fast I2C mode) during the remaining data reads.
Arbitration, bus busy, and peripheral signals are not checked. Therefore, no other controller is allowed to control
the bus during this initialization phase. If the application requires another controller during I2C boot mode, that
controller must be configured to hold off sending any I2C messages until the application software signals that the
controller is past the bootloader portion of initialization.
The non-acknowledgment bit is checked only during the first message sent to initialize the EEPROM base
address. This is to make sure that an EEPROM is present at address 0x50 before continuing. If an EEPROM is
not present, the non-acknowledgment bit is not checked during the address phase of the data read messages
(I2C_Get Word). If a non-acknowledgment is received during the data read messages, the I2C bus hangs. Table
4-35 shows the 8-bit data stream used by the I2C.
The I2C EEPROM protocol required by the I2C bootloader is shown in Figure 4-10 and Figure 4-11. The first
communication, which sets the EEPROM address pointer to 0x0000 and reads the KeyValue (0x08AA), is shown
in Figure 4-10. All subsequent reads are shown in Figure 4-11 and are read two bytes at a time.

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Figure 4-9. Overview of I2C Boot Function

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Table 4-35. I2C 8-Bit Data Stream

Byte Contents
1 LSB: AA (KeyValue for memory width = 8 bits)
2 MSB: 08h (KeyValue for memory width = 8 bits)
3 LSB: I2CPSC[7:0]
4 Reserved
5 LSB: I2CCLKH[7:0]
6 MSB: I2CCLKH[15:8]
7 LSB: I2CCLKL[7:0]
8 MSB: I2CCLKL[15:8]
... ...
... Data for this section.
... ...
17 LSB: Reserved for future use
18 MSB: Reserved for future use
19 LSB: Upper half of entry point PC
20 MSB: Upper half of entry point PC[22:16] (Note: Always 0x00)
21 LSB: Lower half of entry point PC[15:8]
22 MSB: Lower half of entry point PC[7:0]
... ...
... Data for this section.
... ...
Blocks of data in the format size/destination address/data as shown in the generic data stream description.
... ...
... Data for this section.
n LSB: 00h
n+1 MSB: 00h - indicates the end of the source

Figure 4-10. Random Read

Figure 4-11. Sequential Read

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4.7.8.2.4 Parallel Boot Mode

The parallel general-purpose I/O (GPIO) boot mode asynchronously transfers code from host to C28x internal
memory. Each value is 8-bits long and follows the same data flow as outlined in Figure 4-12.

Figure 4-12. Overview of Parallel GPIO Bootloader Operation

The control subsystem communicates with the external host device by polling/driving the Host Control and C28x
control lines. The handshake protocol shown in Figure 4-13 must be used to successfully transfer each word
using GPIO [D0:D7]. This protocol is very robust and allows for a slower or faster host to communicate with the
controller subsystem.
Two consecutive 8-bit words are read to form a single 16-bit word. The least-significant byte (LSB) is read first
followed by the most-significant byte (MSB). In this case, data is read from GPIO[D0:D7].
The 8-bit data stream is shown in Table 4-36.
Table 4-36. Parallel GPIO Boot 8-Bit Data Stream
Bytes GPIO[D0:D7] GPIO[D0:D7] Description
(Byte 1 of 2) (Byte 2 of 2)
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 8 reserved words (words 2 to 9)
... ... ... ... ...
17 18 00 00 Last reserved word
19 20 BB 00 Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0x00BB CCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of first block Addr[15:0] (Addr = 0xAABB CCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ...
... Data for this section.
... ...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of second block Addr[31:16]
. DD CC Destination address of second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
... …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

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The device first signals the host that the device is ready to begin data transfer by pulling the C28x control pin
low. The host load then initiates the data transfer by pulling the control pin low. The complete protocol is shown
in Figure 4-13.

Figure 4-13. Parallel GPIO Bootloader Handshake Protocol

1. The device indicates the device is ready to start receiving data by pulling the control pin low.
2. The bootloader waits until the host puts data on GPIO [D0:D7]. The host signals to the device that data is
ready by pulling the host control pin low.
3. The device reads the data and signals the host that the read is complete by pulling the control pin high.
4. The bootloader waits until the host acknowledges the device by pulling the host control pin high.
5. The device again indicates the device is ready for more data by pulling the control pin low.
This process is repeated for each data value to be sent.
Figure 4-14 shows an overview of the Parallel GPIO bootloader flow.

Figure 4-14. Overview of Parallel GPIO Boot Function

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Figure 4-15 shows the transfer flow from the host side. The operating speed of the CPU and host are not critical
in this mode as the host waits for the device and the device waits for the host. In this manner, the protocol works
with both a host running faster and a host running slower than the device.

Figure 4-15. Parallel GPIO Mode - Host Transfer Flow

Figure 4-16 shows the flow used to read a single word of data from the parallel port. The 8-bit routine, shown in
Figure 4-16, discards the upper 8 bits of the first read from the port and treats the lower 8 bits masked with D7
in bit position 7 and D6 in bit position 6 as the least-significant byte (LSB) of the word to be fetched. The routine
then performs a second read to fetch the most-significant byte (MSB). The routine then combines the MSB and
LSB into a single 16-bit value to be passed back to the calling routine.

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Figure 4-16. 8-Bit Parallel GetWord Function

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4.7.8.2.5 CAN Boot Mode (MCAN in non-FD mode)

The CAN bootloader asynchronously transfers code from CAN-A to internal memory as shown in Figure 4-17.
The host can be any CAN node. The communication is first done with 11-bit standard identifiers (with a MSGID
of 0x1) using two bytes per data frame. The host can download a kernel to reconfigure the CAN if higher data
throughput is desired.

Figure 4-17. Overview of CAN-A Bootloader Operation

The bit timing registers are programmed in such a way that a 100kbps bit rate is achieved with a 20MHz external
oscillator, as shown in Table 4-37.
Table 4-37. Bit-Rate Value for Internal Oscillators
OSCCLK SYSCLK Bit Rate
20MHz 10MHz 100kbps

The SYSCLKOUT values shown are the reset values with the default PLL setting. The BRP and bit-time values
are hard-coded to 10 and 20, respectively.

Note
The CAN boot loader uses XTAL as the bit clock source and INTOSC2 as the system clock source.

Mailbox 1 is programmed with a standard MSGID of 0x1 for boot-loader communication. The CAN host can
transmit only two bytes at a time, LSB first and MSB next. For example, to transmit the word 0x08AA to
the device, transmit AA first, followed by 08. The program flow of the CAN bootloader is identical to the SCI
bootloader. The data sequence for the CAN bootloader is shown in Table 4-38.

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Table 4-38. CAN 8-Bit Data Stream

Bytes Byte 1 of 2 Byte 2 of 2 Description
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 reserved
5 6 00 00 reserved
7 8 00 00 reserved
9 10 00 00 reserved
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABB CCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of the first block Addr[15:0]
(Addr = 0xAABB CCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
... ...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the second block to load = 0xMMNN words
. BB AA Destination address of the second block Addr[31:16]
. DD CC Destination address of the second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
... …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

4.7.8.2.6 CAN-FD Boot Mode

The CAN-FD bootloader asynchronously transfers code from CAN-FD to internal memory and follows same
bootloader execution flow as Section 4.7.8.2.5. The host can be any CAN-FD node. The communication is first
done with 11-bit standard identifiers (with a MSGID of 0x1) using two bytes per data frame. The bootloader uses
a fixed 64-byte payload size and default bit rate of 1Mbps for nominal phase and 2Mbps for data phase. Bit data
timing can be optionally reconfigured after receiving first data segment. The CAN-FD bootloader supports the
same debug boot mode and GPIO option-0 as CAN bootloader.
Mailbox 1 is programmed with a standard MSGID of 0x1 for boot-loader communication. The CAN-FD host can
transmit only two bytes at a time, LSB first and MSB next. For example, to transmit the word 0x08AA to the
device, transmit AA first, followed by 08. The program flow of the CAN-FD bootloader is identical to the CAN
bootloader. The data sequence for the CAN-FD bootloader is shown in Table 4-39.

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Table 4-39. CAN-FD 8-Bit Data Stream

Bytes Byte 1 of 2 Byte 2 of 2 Description
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 XX XX 0: Ignored
(for example, BB) (for example, AA) Nonzero: Custom nominal bit register timing [31:16]
5 6 XX XX 0: Ignored
(for example, DD) (for example, CC) Nonzero: Custom nominal bit register timing [15:0]
(NBTR = 0xAABB CCDD)
7 8 XX XX 0: Ignored
(for example, BB) (for example, AA) Nonzero: Custom nominal bit register timing [31:16]
9 10 XX XX 0: Ignored
(for example, DD) (for example, CC) Nonzero: Custom nominal bit register timing [15:0]
(DBTR = 0xAABB CCDD)
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABB CCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of the first block Addr[15:0]
(Addr = 0xAABB CCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
... ...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the second block to load = 0xMMNN words
. BB AA Destination address of the second block Addr[31:16]
. DD CC Destination address of the second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
... …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

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4.7.8.2.7 USB Boot Mode

Figure 4-18 illustrates the flow for USB boot mode. In USB boot mode, the device enumerates with vendor ID
0x1CBE and product ID 0x00FF. The device descriptor and interface descriptor both show the class as 0xFF
(vendor-specific), the subclass as 0x00, and the protocol as 0x00. After enumeration, the device waits for data.
Data can be sent using bulk OUT transfers to endpoint 1. The data is interpreted as a series of 8-bit bytes in the
standard data stream format described in Section 4.8.1, shown in Table 4-40. No reserved bytes are used. Once
the data transfer is complete (block size of 0x0000 sent), the device disconnects from the USB bus, allowing
other software to make use of the module if desired.
USB_Boot

Host sends boot

loader data in the
Wait for standard stream
connection format via bulk OUT
transfers to
endpoint 1

Enumerate to host
PC with ID 1cbe:00ff Valid key
Jump to flash
(0x08AA)?

Host PC installs
drivers
MCU loads data into
RAM

MCU waits
for data MCU disconnects
from the USB bus

Return EntryPoint

Figure 4-18. USB Boot Flow

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Table 4-40. USB 8-Bit Data Stream

Bytes First Byte Second Byte Description
(LSB) (MSB)
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 reserved
5 6 00 00 reserved
7 8 00 00 reserved
9 10 00 00 reserved
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABB CCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of the first block Addr[31:16]
27 28 DD CC Destination address of the first block Addr[15:0] (Addr = 0xAABB CCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
... ...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of the second block Addr[31:16]
. DD CC Destination address of the second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
... …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

Implementing PC-side USB software is not trivial. It is recommended to use the TI-provided tools and drivers to
load data in USB boot mode. Hex and binary files for loader tools can be generated from COFF (.out) files using
the hex2000 tool. To produce a plain binary file in the boot loader format, use the following command line:
hex2000 -boot -b Program_to_Load.out -o Binary_Loader_Data.dat
For more information on hex2000, see the TMS320C28x Assembly Language Tools User's Guide.

Note
INTOSC2 must be enabled before invoking the USB boot loader. If INTOSC2 is not enabled, the
boot loader hangs. A debugger reset or SCC reset does not enable INTOSC2, if INTOSC2 has been
disabled by the application.

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4.7.9 GPIO Assignments

This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory
location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/ Z2-OTP-
BOOTDEF-HIGH. Refer to Section 4.4.2 on how to configure BOOT_DEF. When selecting a boot mode option,
make sure to verify that the necessary pins are available in the pin mux options for the specific device package
being used.
Table 4-41. SCI Boot Options
Option BOOTDEF Value SCITXDA GPIO SCIRXDA GPIO Packages Supported
0 (default) 0x01 GPIO29 GPIO28 All
1 0x21 GPIO16 GPIO17 All
2 0x41 GPIO8 GPIO9 64 pin/80 pin/100 pin/
128 pin
3 0x61 GPIO2 GPIO3 All
4 0x81 GPIO16 GPIO3 All

Table 4-42. CAN Boot Options

Option BOOTDEF Value CANTXA GPIO CANRXA GPIO
0 (default) 0x02 GPIO4 GPIO5
1 0x22 GPIO1 GPIO0
2 0x42 GPIO13 GPIO12

Note: CAN boot modes are implemented with the MCAN module in "non-FD" mode.

Table 4-43. CAN-FD Boot Options

Option BOOTDEFx Value CANTXA GPIO CANRXA GPIO
0 0x08 GPIO4 GPIO5
1 0x28 GPIO1 GPIO0
2 0x48 GPIO13 GPIO12

Note: These GPIOs are muxed with analog functions, AGPIO share pins. If the system is using these as analog
pins during normal operation, extra circuitry needs to be used to support the use of these as boot pins.

Table 4-44. I2C Boot Options

Option BOOTDEF Value SDAA GPIO SCLA GPIO
0 0x07 GPIO0 GPIO1
1 0x27 GPIO32 GPIO33
2 0x47 GPIO5 GPIO4

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Table 4-45. SPI Boot Options

Option BOOTDEF Value SPIPICOA SPIPOCIA SPICLKA SPIPTE Packages
Supported
0 0x06 GPIO2 GPIO1 GPIO3 GPIO5 All
1 0x26 GPIO16 GPIO1 GPIO3 GPIO0 All
2 0x46 GPIO8 GPIO10 GPIO9 GPIO11 64 pin/80 pin/
100 pin/128 pin
3 0x66 GPIO8 GPIO17 GPIO9 GPIO11 64 pin/80 pin/
100 pin/128 pin

Table 4-46. Parallel Boot Options

Option BOOTDEF Value D0-D7 GPIO C28x (DSP) Control GPIO Host Control GPIO
0 (default) 0x00 D0 - GPIO0 GPIO16 GPIO29
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
1 0x20 D0 - GPIO0 GPIO12 GPIO13
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7

Table 4-47. USB Boot Options

Options Bootmode Value USB0 DM USB0 DP
0 0x09 GPIO23 GPIO41

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4.7.10 Secure ROM Function APIs

There are a few functions that are available within Secure ROM to be called by the application to perform
EXEONLY Flash/RAM tasks in a secure manner.

Note
The application must disable interrupts before calling one of the EXEONLY function APIs.
If a vector fetch request is given by the CPU (C28x) while the program counter (PC) is within the
EXEONLY function API code of the Secure ROM, a reset fires (RSN if from C28x). The consequence
of this is if an NMI or ITRAP or Bus Fault occurs while the PC is executing one of the EXEONLY API
functions, the NMI/ITRAP/Fault cannot be serviced because a reset is fired to the subsystem.

The secure copy code zone 1 and zone 2 functions allow EXEONLY Flash to be copied to EXEONLY RAM
in a secure manner. The source must be from EXEONLY Flash and the destination to EXEONLY RAM. There is
no support to copy EXEONLY ROM or EXEONLY RAM to RAM. Both Flash and RAM must be set to EXEONLY
and configured for the same zone. Additionally, the copy size must not cross over the Flash sector boundary.
Any violations of these requirements results in a failure status returned. Upon successful copy of the data, the
number of 16-bit words copied is returned.
Table 4-48. Secure Copy Code Function
CPU Function Prototype Function Parameters Function Return Value
uint16_t SecureCopyCodeZ1(uint32_t 0xXXXX : Returns the number of
size, uint16_t *dst, uint16_t *src) size : The number of 16-bit words to 16-bit words copied
copy 0x0000 : Indicates one of the
dst : The destination memory address following: Copy length is zero; Copy
CPU (C28x) size crosses over Flash sector
uint16_t SecureCopyCodeZ2(uint32_t in EXEONLY RAM
boundary; Flash and RAM do not
size, uint16_t *dst, uint16_t *src) src : The source memory address in
belong to the same zone; Flash and/or
EXEONLY Flash RAM are not set to EXEONLY; Error
occurred during data copy

The secure CRC calculation zone 1 and zone 2 functions allow a safety CRC check of EXEONLY memory
in a secure manner. The CRC length provided must be a value from 1 to 8 where 1 represents a CRC size of
32 16-bit words and 8 represents a CRC size of 4096 16-bit words. The source address specifies the starting
address for the CRC and the destination address is the location that the resulting CRC value is stored. The
source and destination memories must be configured for the same zone. Additionally, the CRC length must not
cross over the Flash sector or RAM block boundary. Any violations of these requirements results in a failure
status returned. Upon successful CRC, the number of 16-bit words CRC'd is returned.
Table 4-49. Secure CRC Calculation Function
CPU Function Prototype Function Parameters Function Return Value
uint16_t SecureCRCCalcZ1(uint16_t 0xXXXX : Returns the number of
len_id, uint16_t *dst, uint16_t *src) len_id : A number from 1 to 8 which 16-bit words CRC'd
corresponds to length options of 32, 0x0000 : Indicates one of the
64, 128, 256, 512, 1024, 2048, or following: Invalid length option; Source
4096 16-bit words address is not modulo of length value;
CPU (C28x) dst : The destination memory address Destination address is not within
uint16_t SecureCRCCalcZ2(uint16_t
for resulting CRC secure RAM; CRC size crosses over
size, uint16_t *dst, uint16_t *src)
src : The source memory address to Flash sector or RAM block boundary;
The source and destination memory
begin CRC calculation do not belong to the same zone; On
CM, CRCLOCK is enabled

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The CMAC calculate and compare function allows to calculate CMAC signature of a Flash memory block and
compare against a golden signature. This is used in the secure boot mode to authenticate the boot image.
Table 4-50. Secure CRC Calculation Function
CPU Function Prototype Function Parameters Function Return Value
startAddress: Starting address of 0xFFFF FFFFU: Calculated CMAC
memory for which CMAC has to be signature did not match golden
calculated signature (fail)
uint32_t endAddress: Ending address of 0xA5A5 A5A5U: Memory range
CPU1BROM_calculateCMAC(uint32_t memory for which CMAC has to be provided is not aligned to 128-bit
CPU (C28x)
startAddress, uint32_t endAddress, calculated boundary or length is zero
uint32_t signatureAddress)
signatureAddress: Address of 0xE1E1 E1E1U: AES Engine timed
location where golden CMAC out
signature is stored 0x0000 0000U: No Error

4.7.11 Clock Initializations

During boot-up, the boot ROM initializes the device clocking, depending upon the reset source, to assist in faster
boot time response. Clock configurations are performed by the boot ROM code only for POR and XRS reset
types. For all other resets, the boot ROM starts executing with the clocks that were already set up before reset.

Note
CPU performs clock configurations during boot up. If the PLL is used during the boot process, the PLL
is bypassed by the boot ROM code before branching to the user application.

Table 4-51. CPU Boot Clock Sources

Source Frequency Description
INTOSC2 10MHz Default clock source
INTOSC1 10MHz Set as clock source if missing clock is detected at power up or right after device
reset.
SYSPLL 150MHz, 75MHz Enabled optionally as part of main boot flow or as part of MPOST POR memory test
boot flow. PLL is bypassed and disabled after memory test has completed. See more
details regarding enabling MPOST POR memory test in Section 4.7.1.2.

Table 4-52. CPU Clock State After Boot

Reset Source Clock State
1. Using INTOSC2
POR/XRS
2. System clock divider set to /1
All other Resets Maintain clocks setup before device reset.

4.7.12 Boot Status Information

Boot ROM keeps a record of the various actions and events that occur during boot ROM execution. The
reason for this is because NMI and other exceptions are enabled by default in the device and must be handled
accordingly. Boot ROM stores the boot status information in a RAM location so that the user application can read
this boot status and take the necessary actions per application’s needs to handle these events.

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4.7.12.1 Booting Status

Boot ROM health and booting status is written to a 32-bit address in M0RAM. This status is cleared on a POR
or XRS reset. The previous status is retained on any other reset. For example, you can clear the status before
performing a debugger device reset to view the latest boot ROM actions reflected in the status.
Table 4-53. Boot Status Address
Description Address
Boot ROM Status 0x0000 0002

Table 4-54. Boot Status Bit Fields

Value Description
0x8000 0000 HWBIST reset is handled successfully
0x2000 0000 EFuse Single Bit Error
0x1000 0000 FWU Flash Boot Error
0x0800 0000 Flash Verification Error
0x0400 0000 DCSM initialization LP Error
0x0200 0000 DCSM Initialization Invalid LP
0x0100 0000 SYSPLL enabled successfully
0x0080 0000 HWBIST NMI occurred
0x0040 0000 Missing clock NMI occurred
0x0020 0000 RAM Uncorrectable Error NMI occurred
0x0010 0000 Flash Uncorrectable Error NMI occurred
0x0008 0000 RL NMI occurred
0x0004 0000 ERAD NMI occurred
0x0002 0000 Boot ROM detected a PIE mismatch
0x0001 0000 Boot ROM detected an ITRAP
0x0000 8000 Boot ROM has completed running
0x0000 2000 Boot ROM handled POR
0x0000 1000 Boot ROM handled XRS
0x0000 0800 Boot ROM handled all the resets
0x0000 0400 POR memory test has completed
0x0000 0200 DCSM initialization has completed
0x0000 0100 RAM Initialization Complete
0x0000 000C FWU boot has started
0x0000 000B Wait boot has started
0x0000 000A CAN-FD boot has started
0x0000 0009 CAN boot has started
0x0000 0008 I2C boot has started
0x0000 0007 SPI boot has started
0x0000 0006 SCI boot has started
0x0000 0005 RAM boot has started
0x0000 0004 Parallel boot has started
0x0000 0003 Secure Flash boot has started
0x0000 0002 Flash boot has started
0x0000 0001 Boot ROM has started running

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4.7.12.2 Boot Mode and MPOST (Memory Power On Self-Test) Status

Once the boot mode is decoded during the boot flow, the boot mode value is written to RAM. Additionally when
running the MPOST POR memory test, the test result is written to RAM.
For more information, see the C2000™ Memory Power-On Self-Test (M-POST) Application Report.
Table 4-55. Boot Mode and MPOST Status Addresses
Description Address
Boot Mode 0x0000 0004
MPOST POR Memory Test Result 0x0000 0006

4.7.13 ROM Version

The ROM revision and release date information is stored at the ROM locations specified in Table 4-56. Reading
a revision number value of “0x100” represents version “1.0”, “0x101” represents version “1.1”, and so on.
Reading a revision date value of “0x0119” represents “01/19” or “January 2019”.
Table 4-56. Boot ROM Version Information
Contents Address
Revision Number 0x003F 8044
Revision Date 0x003F 8045
Build Number 0x003F 8046

4.8 Application Notes for Using the Bootloaders

4.8.1 Bootloader Data Stream Structure
This section details the data transfer protocols or stream structures that allow boot data transfer between boot
ROM and host device. This data transfer protocol is compatible to the respective bootloaders on C2000 devices.
Table 4-57 and Example 4-2 show the structure of the data stream incoming to the bootloader. The basic
structure is the same for all the bootloaders and is based on the C54x source data stream generated by
the C54x hex utility. The C28x hex utility (hex2000.exe) has been updated to support this structure. The
hex2000.exe utility is included with the C2000 code generation tools. All values in the data stream structure are
in hex. Refer to Section 4.8.2 for more details on using the C28x hex utility to convert a project to this format.
The first 16-bit word in the data stream is known as the key value. The key value is used to indicate to the
bootloader the width of the incoming stream: 8 or 16 bits. Note that not all bootloaders accept both 8- and 16-bit
streams. Refer to the detailed information on each loader for the valid data stream width. For an 8-bit data
stream, the key value is 0x08AA; for a 16-bit data stream, the key value is 0x10AA. If a bootloader receives an
invalid key value, then the load is aborted.
The next eight words are used to initialize register values or otherwise enhance the bootloader by passing
values to the bootloader. If a bootloader does not use these values, then the values are reserved for future use
and the bootloader simply reads the value and then discards the value. Currently only the SPI and I2C and
parallel bootloaders use these words to initialize registers.
The tenth and eleventh words comprise the 22-bit entry point address. This address is used to initialize the PC
after the boot load is complete. This address is most likely the entry point of the program downloaded by the
bootloader.
The twelfth word in the data stream is the size of the first data block to be transferred. The size of the block is
defined as 8-bit data stream format. For example, to transfer a block of 20 8-bit data values from an 8-bit data
stream, the block size is 0x000A to indicate 10 16-bit words.

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The next two words indicate to the loader the destination address of the block of data. Following the size and
address is the 16-bit words that makeup that block of data.
This pattern of block size/destination address repeats for each block of data to be transferred. Once all the
blocks have been transferred, a block size of 0x0000 signals to the loader that the transfer is complete. At this
point, the loader returns the entry point address to the calling routine, which cleans up and exits. Execution then
continues at the entry point address as determined by the input data stream contents.
Table 4-57. LSB/MSB Loading Sequence in 8-Bit Data Stream
Contents
Byte LSB (First Byte of 2) MSB (Second Byte of 2)
1 2 LSB: AA (KeyValue for memory width = 8 bits) MSB: 08h (KeyValue for memory width = 8 bits)
3 4 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
5 6 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
7 8 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
... ... ... ...
... ... ... ...
17 18 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
19 20 LSB: Upper half of Entry point PC[23:16] MSB: Upper half of entry point PC[31:24] (Always 0x00)
21 22 LSB: Lower half of Entry point PC[7:0] MSB: Lower half of Entry point PC[15:8]
23 24 LSB: Block size in words of the first block to load. If the MSB: block size
block size is 0, this indicates the end of the source program.
Otherwise another block follows. For example, a block size of
0x000A indicates 10 words or 20 bytes in the block.
25 26 LSB: MSW destination address, first block Addr[23:16] MSB: MSW destination address, first block Addr[31:24]
27 28 LSB: LSW destination address, first block Addr[7:0] MSB: LSW destination address, first block Addr[15:8]
29 30 LSB: First word of the first block being loaded MSB: First word of the first block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the first block to load MSB: Last word of the first block to load
. . LSB: Block size of the second block MSB: Block size of the second block
. . LSB: MSW destination address, second block Addr[23:16] MSB: MSW destination address, second block Addr[31:24]
. . LSB: LSW destination address, second block Addr[7:0] MSB: LSW destination address, second block Addr[15:8]
. . LSB: First word of the second block being loaded MSB: First word of the second block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the second block MSB: Last word of the second block
. . LSB: Block size of the last block MSB: Block size of the last block
. . LSB: MSW of destination address of last block Addr[23:16] MSB: MSW destination address, last block Addr[31:24]
. . LSB: LSW destination address, last block Addr[7:0] MSB: LSW destination address, last block Addr[15:8]
. . LSB: First word of the last block being loaded MSB: First word of the last block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the last block MSB: Last word of the last block
n n+1 LSB: 00h MSB: 00h - indicates the end of the source

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Example 4-2. Data Stream Structure 8-bit

AA 08 ; 0x08AA 8bit key value

00 00 00 00 ; 8 reserved words
00 00 00 00
00 00 00 00
00 00 00 00
3F 00 00 80 ; 0x003F8000 EntryAddr, starting point after boot load completes
05 00 ; 0x0005 First block consists of 5 16-bit words
3F 00 10 90 ; 0x003F9010 First block is loaded starting at 0x3F9010
01 00 ; Data loaded = 0x0001 0x0002 0x0003 0x0004 0x0005
02 00
03 00
04 00
05 00
02 00 ; 0x0002 - 2nd block consists of 2 16bit words
3F 00 00 80 ; 0x003F8000 2nd block is loaded starting at 0x3F8000
00 77 ; Data loaded = 0x7700 0x7625
25 76
00 00 ; 0x0000 Size of 0 indicates end of data stream
After load has completed, the following memory values are initialized as follows:
Location Value
0x3F9010 0x0001
0x3F9011 0x0002
0x3F9012 0x0003
0x3F9013 0x0004
0x3F9014 0x0005
0x3F8000 0x7700
0x3F8001 0x7625
PC Begins execution at 0x3F8000

4.8.2 The C2000 Hex Utility

To use the features of the bootloader, you must generate a data stream and boot table as described in Section
4.8.1. The hex conversion utility tool, included with the C28x code generation tools, can generate the required
data stream including the required boot table. This section describes the hex2000 utility. An example of a file
conversion performed by hex2000 is described in Example 4-3.
The hex utility supports creation of the boot table required for the SCI, SPI, I2C, CAN, and parallel I/O loaders.
That is, the hex utility adds the required information to the file such as the key value, reserved bits, entry point,
address, block start address, block length and terminating value. The contents of the boot table vary slightly
depending on the boot mode and the options selected when running the hex conversion utility. The actual file
format required by the host (ASCII, binary, hex, and so on) differs from one specific application to another and
some additional conversion can be required.
To build the boot table, follow these steps:
1. Assemble or compile the code. This creates the object files that is then used by the linker to create a
single output file.
2. Link the file. The linker combines all of the object files into a single output file in common object file format
(ELF). The specified linker command file is used by the linker to allocate the code sections to different
memory blocks. Each block of the boot table data corresponds to an initialized section in the ELF file.
Uninitialized sections are not converted by the hex conversion utility. The following options can be useful:
• The linker -m option can be used to generate a map file. This map file shows all of the sections that were
created, the location in memory, and the length. The map file can be useful to check this file to make sure
that the initialized sections are where you expect them.
• The linker -w option configures the linker to show, if the linker assigned a section to a memory region
automatically. For example, if you have a section in your code called .TI.ramfunc.
3. Run the hex conversion utility. Choose the appropriate options for the desired boot mode and run the hex
conversion utility to convert the ELF file produced by the linker to a boot table.

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See the TMS320C28x Assembly Language Tools User's Guide and the TMS320C28x Optimizing C/C++
Compiler User's Guide for more information on the compiling and linking process.
Table 4-58 summarizes the hex conversion utility options available for the bootloader. See the TMS320C28x
Assembly Language Tools User's Guide for a detailed description of the hex2000 operations used to generate a
boot table. Updates are made to support the I2C boot. See the Codegen release notes for the latest information.
Table 4-58. Boot Loader Options
Option Description
-boot Convert all sections into bootable form (use instead of a SECTIONS directive)
-sci8 Specify the source of the bootloader table as the SCI-A port, 8-bit mode
-spi8 Specify the source of the bootloader table as the SPI-A port, 8-bit mode
-gpio8 Specify the source of the bootloader table as the GPIO port, 8-bit mode
-bootorg value Specify the source address of the bootloader table
-lospcp value Specify the initial value for the LOSPCP register. This value is used only for the spi8 boot table format and
ignored for all other formats. If the value is greater than 0x7F, the value is truncated to 0x7F.
-spibrr value Specify the initial value for the SPIBRR register. This value is used only for the spi8 boot table format and
ignored for all other formats. If the value is greater than 0x7F, the value is truncated to 0x7F.
-e value Specify the entry point at which to begin execution after boot loading. The value can be an address or a global
symbol. This value is optional. The entry point can be defined at compile time using the linker -e option to
assign the entry point to a global symbol. The entry point for a C program is normally _c_int00 unless defined
otherwise by the -e linker option.
-i2c8 Specify the source of the bootloader table as the I2C-A port, 8-bit
-i2cpsc value Specify the value for the I2CPSC register. This value is loaded and takes effect after all I2C options are loaded,
prior to reading data from the EEPROM. This value is truncated to the eight least-significant bits and can be set
to maintain an I2C module clock of 7 to 12MHz.
-i2cclkh value Specify the value for the I2CCLKH register. This value is loaded and takes effect after all I2C options are
loaded, prior to reading data from the EEPROM.
-i2cclkl value Specify the value for the I2CCLKL register. This value is loaded and takes effect after all I2C options are
loaded, prior to reading data from the EEPROM.

Example 4-3. HEX2000.exe Command Syntax

C: HEX2000 GPIO34TOG.OUT -boot -gpio8 -a

Where:
- boot Convert all sections into bootable form.
- gpio8 Use the GPIO in 8-bit mode data format. The eCAN
uses the same data format as the GPIO in 8bit mode.
- a Select ASCII-Hex as the output format.

4.9 Software
4.9.1 BOOT Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/boot
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.

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Chapter 5
Dual Code Security Module (DCSM)

This chapter explains the dual code security module.

5.1 Introduction...............................................................................................................................................................653
5.2 Functional Description.............................................................................................................................................653
5.3 Flash and OTP Erase/Program................................................................................................................................660
5.4 Secure Copy Code....................................................................................................................................................660
5.5 SecureCRC................................................................................................................................................................661
5.6 CSM Impact on Other On-Chip Resources.............................................................................................................662
5.7 Incorporating Code Security in User Applications................................................................................................663
5.8 Software.................................................................................................................................................................... 667
5.9 DCSM Registers........................................................................................................................................................672

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5.1 Introduction
The dual code security module (DCSM) is a security feature incorporated in this device and prevents access
and visibility to on-chip secure memories (and other secure resources) by unauthorized persons. The DCSM
also prevents duplication and reverse-engineering of proprietary code. The term “secure” means that access to
on-chip secure memories and resources is blocked. The term “unsecure” means that access is allowed; that is,
the contents of the memory can be read by any means (for example, through a debugging tool such as Code
Composer Studio™ IDE.
The CSM has dual-zone security, Zone1 (Z1) and Zone2 (Z2).
5.1.1 DCSM Related Collateral

Getting Started Materials

• C2000 DCSM Security Tool Application Report
• C2000 Unique Device Number Application Report
• Enhancing Device Security by Using JTAGLOCK Feature Application Report
• Secure BOOT On C2000 Device Application Report
5.2 Functional Description
The security module restricts the CPU access to on-chip secure memory and resources without interrupting
or stalling CPU execution. When a read occurs to a secure memory location, the read returns a zero value
and CPU execution continues with the next instruction. This, in effect, blocks read and write access to secure
memories through the JTAG port.
The code security mechanism offers protection for two zones, Zone1 (Z1) and Zone2 (Z2). The security
mechanism for both the zones is identical. Each zone has a dedicated secure resource and allocated secure
resource. The following are different secure resources available on this device:
• OTP: Each zone has a dedicated secure OTP (USER OTP). This contains the security configurations for
the individual zone. If a zone is secure, the USER OTP content (including CSM passwords) can be read
(execution not allowed) only if the zone is unlocked using the password match flow (PMF).
• RAM: All LSx RAMs can be secure RAM on this device. These RAMs can be allocated to either zone by
configuring the respective GRABRAM locations in the USER OTP.
• Flash Sectors: Flash sectors of each CPU subsystems can be made secure on this device. Each Flash
sector can be allocated to either zone by configuring the respective GRABSECT locations in the bank's
USER OTP.
• Secure ROM: This device also has secure ROM on each CPU subsystem which is EXEONLY-protected.
These ROM contains specific function for the user, provided by TI.

Table 5-1 shows the status of a RAM block/Flash sector based on the configuration in the GRABRAM/
GRABSECT register.
The security of each zone is provided by a 128-bit (four 32-bit words) password (CSM password). The password
for each zone is stored in USER OTP. A zone can be unsecured by executing the password match flow (PMF),
described in Section 5.7.4.
There are three types of accesses:
• Data/program reads: Data reads to secure memory are always blocked unless the program is executing
from a memory that belongs to the same zone. Data reads to unsecure memory are always allowed. Table
5-2 shows the levels of security.
• JTAG access: JTAG accesses are always blocked when a memory is secure.
• Instruction fetches (calls, jumps, code executions, ISRs): Instruction fetches are never blocked.

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CAUTION
Never program any other values in these fields. Failing any of these conditions for a RAM block/
Flash sector makes that RAM block/Flash sector inaccessible.

Table 5-1. RAM/Flash Status

Zone 1 Zone 2
GRABRAMx/GRABSECTx Bits GRABRAMx/GRABSECT Bits Ownership and Accessibility
01 10 RAM block/Flash Sector belongs to Zone1
01 11(2) RAM block/Flash Sector belongs to Zone1
10 01 RAM block/Flash Sector belongs to Zone2
11(1) 01 RAM block/Flash Sector belongs to Zone2
10 10 RAM block/Flash Sector is unsecure
11(1) 11(2) RAM block/Flash Sector is unsecure
11 11 RAM block/Flash Sector inaccessible if either of the
zone is secure (CSM passwords are programmed). Never
leave these values default (11), if CSM passwords are
programmed for even one zone.

(1) Zone1 must be unsecure. Assumption in this case is that the user is not using Zone1 so none of the fields, including passwords, in
Zone1 USER OTP are programmed by the user, hence, Zone1 is always unsecure.
(2) Zone2 must be unsecure. Assumption in this case is that the user is not using Zone2 so none of the fields, including passwords, in
Zone2 USER OTP are programmed by the user, hence, Zone2 is always unsecure.

Table 5-2. Security Levels

PMF Executed With Operating Mode
Correct Password? of the Zone Program Fetch Location Security Description
No Secure Outside secure memory Only instruction fetches by the CPU are
allowed to secure memory. In other words,
code can still be executed, but not read.
No Secure Inside secure memory CPU has full access (except for EXEONLY
memories where read is not allowed). JTAG
port cannot read the secured memory
contents.
Yes Unsecure Anywhere Full access for CPU and JTAG port to secure
memory of that zone.

5.2.1 CSM Passwords

Unlike earlier C2000™ devices, on this device ALL_1 value (0xFFFF FFFF, 0xFFFF FFFF, 0xFFFF FFFF,
0xFFFF FFFF) for CSM password for a zone does not unsecure the zone. Instead, if for any zone the CSM
password values get loaded as ALL_1 from USER OTP, the device is in BLOCKED state. Due to this reason,
TI programs a few bits in the second 32-bit password value (ZxOTP_CSMPSWD1) in every zone select block of
each zone with value 0. The default value for this password location is chosen in a manner that the respective
ECC value remains ALL_1. Due to this, the CSMPSWD1 value programmed by TI for every zone select block
is different. See Table 5-3 for ZxOTP_CSMPSWD1 value, programmed by TI on every device. Since ECC is not
programmed, the user is able to change this value by flipping the bits that are 1 to 0 but leaving the bits that are
already programmed by TI as 0. BOOTROM code writes the default password value into the KEYx register to
unlock the device as part of device initialization sequence.
If the password locations of a zone have all 128 bits as zeros (ALL_0), that zone becomes permanently secure
(LOCKED state), regardless of the contents of the CSMKEYx registers, which means the zone cannot be
unlocked using PMF, see the password match flow described in Section 5.7.2. Therefore, the user can never use
ALL_0 as password. A password of ALL_0 prevents debug of secure code or reprogramming the Flash sectors.
CSMKEYx registers are user-accessible registers that are used to unsecure the zones.

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Table 5-3. Default Value of ZxOTP (Programmed by TI)

Zone Select Block Zone1 USER OTP Zone2 USER OTP
Address Value Address Value
JLM_ENABLE 0x0007 8006 0xFFFF 000F NA NA
(JTAGLOCK)
PSWDLOCK 0x0007 8010 0xFB7F FFFF 0x0007 8210 0x1F7F FFFF
CRCLOCK 0x0007 8012 0x7FFF FFFF 0x0007 8212 0x3FFF FFFF
JTAGPSWDH0 0x0007 8014 0x4BFF FFFF NA NA
JTAGPSWDH1 0x0007 8016 0x3FFF FFFF NA NA
Zone_Select_Block0 0x0007 8022 (CSMPSWD1) 0x4D7F FFFF 0x0007 8222 (CSMPSWD1) 0x1F7F FFFF
Zone_Select_Block0 0x0007 803E (JTAGPSWDL1) 0x2BFF FFFF NA NA
Zone_Select_Block1 0x0007 8042 (CSMPSWD1) 0x5F7F FFFF 0x0007 8242 (CSMPSWD1) 0xE57F FFFF
Zone_Select_Block1 0x0007 805E (JTAGPSWDL1) 0x27FF FFFF NA NA
Zone_Select_Block2 0x0007 8062 (CSMPSWD1) 0x1DFF FFFF 0x0007 8262 (CSMPSWD1) 0x4FFF FFFF
Zone_Select_Block2 0x0007 807E (JTAGPSWDL1) 0x7B7F FFFF NA NA
Zone_Select_Block3 0x0007 8082 (CSMPSWD1) 0xAF7F FFFF 0x0007 8282 (CSMPSWD1) 0xE37F FFFF
Zone_Select_Block3 0x0007 809E (JTAGPSWDL1) 0xC9FF FFFF NA NA
Zone_Select_Block4 0x0007 80A2 (CSMPSWD1) 0x1BFF FFFF 0x0007 82A2 (CSMPSWD1) 0x57FF FFFF
Zone_Select_Block4 0x0007 80BE (JTAGPSWDL1) 0x7D7F FFFF NA NA
Zone_Select_Block5 0x0007 80C2 (CSMPSWD1) 0x17FF FFFF 0x0007 82C2 (CSMPSWD1) 0x5BFF FFFF
Zone_Select_Block5 0x0007 80DE (JTAGPSWDL1) 0x6F7F FFFF NA NA
Zone_Select_Block6 0x0007 80E2 (CSMPSWD1) 0xBD7F FFFF 0x0007 82E2 (CSMPSWD1) 0xF17F FFFF
Zone_Select_Block6 0x0007 80FE (JTAGPSWDL1) 0x33FF FFFF NA NA
Zone_Select_Block7 0x0007 8102 (CSMPSWD1) 0x9F7F FFFF 0x0007 8302 (CSMPSWD1) 0x3B7F FFFF
Zone_Select_Block7 0x0007 811E (JTAGPSWDL1) 0x0FFF FFFF NA NA
Zone_Select_Block8 0x0007 8122 (CSMPSWD1) 0x2BFF FFFF 0x0007 8322 (CSMPSWD1) 0x8FFF FFFF
Zone_Select_Block8 0x0007 813E (JTAGPSWDL1) 0xBB7F FFFF NA NA
Zone_Select_Block9 0x0007 8142 (CSMPSWD1) 0x27FF FFFF 0x0007 8342 (CSMPSWD1) 0x6BFF FFFF
Zone_Select_Block9 0x0007 815E (JTAGPSWDL1) 0x5F7F FFFF NA NA
Zone_Select_Block10 0x0007 8162 (CSMPSWD1) 0x7B7F FFFF 0x0007 8362 (CSMPSWD1) 0x377F FFFF
Zone_Select_Block10 0x0007 817E (JTAGPSWDL1) 0x1DFF FFFF NA NA
Zone_Select_Block11 0x0007 8182 (CSMPSWD1) 0xC9FF FFFF 0x0007 8382 (CSMPSWD1) 0x9BFF FFFF
Zone_Select_Block11 0x0007 819E (JTAGPSWDL1) 0xAF7F FFFF NA NA
Zone_Select_Block12 0x0007 81A2 (CSMPSWD1) 0x7D7F FFFF 0x0007 83A2 (CSMPSWD1) 0x2F7F FFFF
Zone_Select_Block12 0x0007 81BE (JTAGPSWDL1) 0x1BFF FFFF NA NA
Zone_Select_Block13 0x0007 81C2 (CSMPSWD1) 0x6F7F FFFF 0x0007 83C2 (CSMPSWD1) 0xCB7F FFFF
Zone_Select_Block13 0x0007 81DE (JTAGPSWDL1) 0x17FF FFFF NA NA
Zone_Select_Block14 0x0007 81E2 (CSMPSWD1) 0x33FF FFFF 0x0007 83E2 (CSMPSWD1) 0x97FF FFFF
Zone_Select_Block14 0x0007 81FE (JTAGPSWDL1) 0xBD7F FFFF

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5.2.2 Emulation Code Security Logic (ECSL)

In addition to the CSM, the emulation code security logic (ECSL) has been implemented using a 64-bit
password (part of existing CSM password) for each zone to prevent unauthorized users from stepping through
secure code. A halt in secure code while the emulator is connected trips the ECSL and breaks the emulation
connection. To allow emulation of secure code, while maintaining the CSM protection against secure memory
reads, write the correct 64-bit password into the CSMKEY (0/1) registers, which matches the password value
stored in the USER OTP of that zone. This disables the ECSL for the specific zone.
When initially debugging a device with the password locations in OTP programmed (secured), the emulator
takes some time to take control of the CPU. During this time, the CPU starts running and can execute an
instruction that performs an access to a protected ECSL area and if the CPU is halted when the program counter
(PC) is pointing to a secure location, the ECSL trips and causes the emulator connection to be broken.
The answer to this problem is to use the Wait Boot Mode boot option. In this mode, the CPU is in a loop and
does not jump to the user application code. Using this BOOTMODE, you can connect to CCS and debug the
code.
5.2.3 CPU Secure Logic
The CPU Secure Logic (CPUSL) on this device prevents a hacker from reading the CPU registers in a watch
window while code is running in a secure zone. All accesses to CPU registers when the PC points to a secure
location are blocked by this logic. The only exception to this is read access to the PC. It is highly recommended
not to write into the CPU register in this case, because proper code execution may get affected. If the CSM is
unlocked using the CSM password match flow, the CPUSL logic also gets disabled.
5.2.4 Execute-Only Protection
To achieve a higher level of security on secure Flash sectors and RAM blocks that store critical user code
(instruction opcodes), the Execute-Only protection feature is provided. When the Execute-Only protection is
turned on for any secure Flash sector or RAM block, data reads to that Flash sector or RAM block are disallowed
from any code (even from secure code). Execute-only protection for a Flash sector and RAM block can be
turned on by configuring the bit field associated for that particular sector/RAM block in the zone's (which has
ownership of that sector/RAM block) EXEONLYSECT and EXEONLYRAM register, respectively.
5.2.5 Password Lock
The password locations in USER OTP for each zone can be locked by programming the zone’s PSWDLOCK
field with any value other than 1111 (0xF) at the PSWDLOCK location in OTP. Until the passwords of a zone are
locked, password locations are not secure and can be read from the debugger as well as code running from non-
secure memory. This feature can be used by the user to avoid accidental locking of the zone while programming
the Flash sectors during the software development phase. On a new device, the value for password lock fields
for all zones at the PSWDLOCK location in OTP is 1111, which means the password for all zones is unlocked.

Note
Password unlock only makes password locations non-secure. All other secure memories remains
secure as per security settings. Since password locations are non-secure, anyone can read the
password and make the zone unsecure by running through PMF, user must program PSWDLOCK
locations to lock the password before sending the device in field.

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5.2.6 JTAGLOCK
Sometimes you want to disable the JTAG access on a device to avoid any debug access to the device. This can
be done by using the JTAGLOCK feature on this device. You need to follow a two step process to enable the
JTAGLOCK feature (both steps can be performed at the same time).
1. Program the JTAG passwords. This device has a 128-bit JTAG password that needs to be programmed in
Z1 USER OTP. JTAG passwords are split into two parts, JTAGPSWDH and JTAGPSWDL. JTAGPSWDH is
part of Z1 USER OTP header and JTAGPSWDL is part of Z1 Zone Select Block (ZSB). What this means
is program JTAGPSWDH once and change the JTAGPSWDL multiple times, if needed. Code Composer
Studio has an integrated tool that you need to use to unlock the JTAGLOCK on device.
2. After programming the JTAG passwords, you need to enable the JTAGLOCK module (JLM) by programming
bit [3:0] of Z1OTP_JLM_ENABLE with any value other than 0xF. It is recommended to program all four bits
with a value 0x0.

5.2.7 Link Pointer and Zone Select

For each of the two security zones, a dedicated OTP block exists that holds the configuration related to zone’s
security. The following are user programmable configurations:
• ZxOTP_LINKPOINTER1 • ZxOTP_CSMPSWD1
• ZxOTP_LINKPOINTER2 • ZxOTP_CSMPSWD2
• ZxOTP_LINKPOINTER3 • ZxOTP_CSMPSWD3
• Z1OTP_JLM_ENABLE • ZxOTP_GRABSECT1
• ZxOTP_GPREG1 • ZxOTP_GRABSECT2
• ZxOTP_GPREG2 • ZxOTP_GRABSECT3
• ZxOTP_GPREG3 • ZxOTP_GRABRAM1
• ZxOTP_GPREG4 • ZxOTP_EXEONLYSECT1
• ZxOTP_PSWDLOCK • ZxOTP_EXEONLYSECT2
• ZxOTP_CRCLOCK • ZxOTP_EXEONLYRAM1
• Z1OTP_JTAGPSWDH • Z1OTP_JTAGPSWDL
• Z1OTP_CMACKEY
• ZxOTP_CSMPSWD0

Since OTP cannot be erased, the following configurations are placed in zone select blocks of each zone’s OTP
Flash of both the banks:
• ZxOTP_CSMPSWD0 • ZxOTP_GRABRAM1
• ZxOTP_CSMPSWD1 • ZxOTP_EXEONLYSECT1
• ZxOTP_CSMPSWD2 • ZxOTP_EXEONLYSECT2
• ZxOTP_CSMPSWD3 • ZxOTP_EXEONLYRAM1
• ZxOTP_GRABSECT1 • Z1OTP_JTAGPSWDL
• ZxOTP_GRABSECT2
• ZxOTP_GRABSECT3

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The location of the valid zone select block in OTP is decided based on the value of three 14-bit link pointers
(Zx-LINKPOINTERx) programmed in the OTP of each zone. All OTP locations except link pointers and
Z1OTP_JLM_ENABLE locations are protected with ECC. Since the link pointer locations are not protected with
ECC, three link pointers are provided that need to be programmed with the same value. The final value of the
link pointer is resolved in hardware, when a dummy read is done to all the link pointers, by comparing all the
three values (bit-wise voting logic). Since in OTP, a 1 can be flipped by the user to 0, but 0 can not be flipped to
1 (no erase operation for OTP), the most-significant bit position in the resolved link pointer that is 0, defines the
valid base address for the zone select block. While generating the final link pointer value, if the bit pattern is not
one of those listed in Figure 5-1, the final link pointer value becomes All_1 (0xFFFF_FFFF), which selects the
Zone-Select-Block1 (also known as the default zone select block).

Figure 5-1. Storage of Zone-Select Bits in OTP

Note
Address locations for other security settings that are not part of Zone Select blocks can be
programmed only once; therefore, program the locations towards the end of the development cycle.

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Zone2 OTP Flash

Zone1 OTP Flash
0x78200 Z2OTP_LINKPOINTER1
0x78000 Z1OTP_LINKPOINTER1
0x78202 Z2OTP_LINKPOINTER2
0x78002 Z1OTP_LINKPOINTER2
0x78204 Z2OTP_LINKPOINTER3
0x78004 Z1OTP_LINKPOINTER3
0x78206 Reserved
0x78006 Z1OTP_JLM_ENABLE
0x78208 Z2OTP_GPREG1
0x78008 Z1OTP_GPREG1 Zone Select Block (ZSB)
0x7820A Z2OTP_GPREG2
0x7800A Z1OTP_GPREG2
Address Offset 0x7820C Z2OTP_GPREG3
32-bit Content
0x7800C Z1OTP_GPREG3 (from ZSB Base)
0x7820E Z2OTP_GPREG4
0x7800E Z1OTP_GPREG4 0x0 ZxOTP_CSMPSWD0
0x78210 Z2OTP_PSWDLOCK
0x78010 Z1OTP_PSWDLOCK 0x2 ZxOTP_CSMPSWD1
0x78212 Z2OTP_CRCLOCK
0x78012 Z1OTP_CRCLOCK 0x4 ZxOTP_CSMPSWD2
0x78214 Reserved
0x78014 Z1OTP_JTAGPSWDH0 0x6 ZxOTP_CSMPSWD3
0x78216 Reserved
0x78016 Z1OTP_JTAGPSWDH1 0x8 ZxOTP_GRABSECT1
0x78218 Reserved
0x78018 Z1OTP_CMACKEY0 0xa ZxOTP_GRABSECT2
0x7821A Reserved
0x7801A Z1OTP_CMACKEY1 0xc ZxOTP_GRABSECT3
0x7821C Reserved
0x7801C Z1OTP_CMACKEY2 0xe ZxOTP_GRABRAM1
0x7821E Reserved
0x7801E Z1OTP_CMACKEY3 0x10 ZxOTP_GRABRAM2
Zone Select Block 1
Zone Select Block 1 0x78220
0x78020 0x12 ZxOTP_GRABRAM3 (32x16 Bits)
(32x16 Bits)
Zone Select Block 2
Zone Select Block 2 0x14 ZxOTP_EXEONLYSECT1 0x78240
0x78040 (32x16 Bits)
(32x16 Bits)
0x16 ZxOTP_EXEONLYSECT2

0x18 ZxOTP_EXEONLYRAM1
Zone Select Block 15
Zone Select Block 15 0x783E0
0x781E0 (32x16 Bits)
(32x16 Bits) 0x1a Z1_DIAG

0x1c ZxOTP_JTAGPSWDL0

0x1e ZxOTP_JTAGPSWDL1

Figure 5-2. Location of Zone-Select Block Based on Link-Pointer

CAUTION
USER OTP is ECC protected. Program the ECC value while programming the security setting in
USER OTP. Failing to program the correct ECC value causes the device to be blocked permanently
and replacing the device can be possible.

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5.2.8 C Code Example to Get Zone Select Block Addr for Zone1

unsigned long LinkPointer;

unsigned long *Zone1SelBlockPtr;
int Bitpos = 13;
int ZeroFound = 0;
// Read Z1-Linkpointer register of DCSM module.
LinkPointer = *(unsigned long *)0x5F000;
// Bits 31 to 15 as most-sigificant 0 are reserved LinkPointer options
LinkPointer = LinkPointer << 18;
while ((ZeroFound == 0) && (bitpos > -1))
{
if ((LinkPointer & 0x80000000) == 0)
{
ZeroFound = 1;
Zone1SelBlockPtr = (unsigned long *)(0x78000 + ((bitpos + 2)*32));
}
Else
{
bitpos--;
LinkPointer = LinkPointer << 1;
}
}
if (ZeroFound == 0)
{
//Default in case there is no zero found.
Zone1SelBlockPtr = (unsigned long *)0x78020;
}

5.3 Flash and OTP Erase/Program

On this device, OTP as well as normal Flash, are secure resources. Each zone has a dedicated OTP, whereas
normal Flash sectors can be allocated to any zone based on the value programmed in the GRABSECTx location
in OTP. Each zone has a 128-bit CSM passwords. Read and write accesses are not allowed to resources
assigned to Z1 by code running from memory allocated to Z2 and conversely. Before programming any secure
Flash sector, either unlock the zone to which that particular sector belongs using PMF or execute the Flash
programming code from secure memory that belongs to the same zone. The same is the case for erasing any
secure Flash sector. To program the security settings in OTP Flash, unlock the CSM of the respective zone.
Unless the zone is unlocked, security settings in OTP Flash can not be updated. The OTP content cannot be
erased.
A semaphore mechanism is provided to avoid the program/erase conflict between Z1 and Z2. A zone needs
to grab this semaphore to successfully complete the erase/program operation on the secure Flash sectors
allocated to that zone. A semaphore can be grabbed by a zone by writing the appropriate value in the SEM field
of the FLSEM register. For further details of this field, see the register description.
5.4 Secure Copy Code
In some applications, the user may want to copy the code from secure Flash to secure RAM for better
performance. The user cannot do this for EXEONLY Flash sectors because EXEONLY secure memories cannot
be read from anywhere. TI provides specific “Secure Copy Code” library functions for ZONE1 to enable the
user to copy content from EXEONLY secure Flash sectors to EXEONLY RAM blocks. These functions do the
copy-code operation in a highly secure environment and allow a copy to be performed only when the following
conditions are met:
• The secure RAM block and the secure Flash sector belong to the same zone.
• Both the secure RAM block and the secure Flash sector have EXEONLY protection enabled.
For further usage of these library functions, see the device-specific Boot ROM documentation.

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5.5 SecureCRC
Since reads from EXEONLY memories are not allowed, the user cannot calculate the CRC on content in
EXEONLY memories using the CRC engine available on this device (for example, VCUCRC, GCRC) or
software. In some safety-critical applications, the user can calculate the CRC even on these memories. To
enable this without compromising on security, TI provides specific “SecureCRC” library functions for each zone.
These functions do the CRC calculation in highly secure environment and allow a CRC calculation to be
performed only when the following conditions are met:
• The source address can be modulo the number of words (based on length_id) for which the CRC needs to be
calculated.
• The destination address can belong to the same zone as the source address.
For further usage of these library functions, see the device-specific Boot ROM documentation.

Note
The user must disable all the interrupts before calling the secure functions in ROM. If there is a vector
fetch during secure function execution, the CPU gets reset immediately.

Disclaimer: The Code Security Module (CSM) included on this device was designed to password protect the
data stored in the associated memory and is warranted by Texas Instruments (TI), in accordance with its
standard terms and conditions, to conform to TI's published specifications for the warranty period applicable
for this device. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT
BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES
NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE
OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

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5.6 CSM Impact on Other On-Chip Resources

On this device, some of the memories are not secure. To avoid any potential hacking when the device is
in the default state (post reset), accesses (all types) to all memories (secure as well as non-secure, except
BOOT-ROM and OTP ) are disabled until proper security initialization is done. This means that after reset none
of the memory resources except BOOT_ROM and OTP is accessible to the user.
The following steps are required by CPU after reset (any type of reset) to initialize the security on device.
Security Initialization
• Dummy Read to address location of SECDC (0x703F0, TI-reserved register) in TI OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER1 in Z1 OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER2 in Z1 OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER3 in Z1 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER1 in Z2 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER2 in Z2 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER3 in Z2 OTP
• Dummy Read to address location Z1OTP_JLM_ENABLE in Z1 OTP
• Dummy Read to address location of Z1OTP_GPREG1, Z1OTP_GPREG2, Z1OTP_GPREG3,
Z1OTP_GPREG4 in Z1 OTP
• Dummy Read to address location of Z1OTP_PSWDLOCK in Z1 OTP
• Dummy Read to address location of Z1OTP_CRCLOCK in Z1 OTP
• Dummy Read to address location of Z1OTP_JTAGPSWDH0, Z1OTP_JTAGPSWDH1 in Z1 OTP
• Dummy Read to address location of Z2OTP_GPREG1, Z2OTP_GPREG2, Z2OTP_GPREG3,
Z2OTP_GPREG4 in Z2 OTP
• Dummy Read to address location of Z2OTP_PSWDLOCK in Z2 OTP
• Dummy Read to address location of Z2OTP_CRCLOCK in Z2 OTP
• Read to memory map register of Z1_LINKPOINTER in DCSM module to calculate the address of zone select
block for Z1
• Dummy read to address location of Z1OTP_GRABSECT1, Z1OTP_GRABSECT2, Z1OTP_GRABSECT3 in
Z1 OTP
• Dummy read to address location of Z1OTP_GRABRAM1
• Dummy read to address location of Z1OTP_EXEONLYSECT1, Z1OTP_EXEONLYSECT2 in Z1 OTP
• Dummy read to address location of Z1OTP_EXEONLYRAM1 in Z1 OTP
• Dummy Read to address location of Z1OTP_JTAGPSWDL0, Z1OTP_JTAGPSWDL1 in Z1 OTP
• Read to memory map register of Z2_LINKPOINTER in DCSM module to calculate the address of zone select
block for Z2
• Dummy read to address location of Z2OTP_GRABSECT1, Z2OTP_GRABSECT2, Z2OTP_GRABSECT3 in
Z2 OTP
• Dummy read to address location of Z2OTP_GRABRAM1
• Dummy read to address location of Z2OTP_EXEONLYSECT1, Z2OTP_EXEONLYSECT2 in Z2 OTP
• Dummy read to address location of Z2OTP_EXEONLYRAM1 in Z2 OTP

Note
Security Initialization is done by BOOTROM code on all the resets (as part of device initialization) that
assert SYSRSn. This is not part of user application code.
The order of initialization matters; hence, if a memory watch window with the USER OTP address is
opened in the debugger (CCS IDE), the security initialization can occur in an incorrect order locking
the device down. To avoid this, do not keep a memory window with USER OTP address opened in the
debugger (CCS IDE) when performing a reset.

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5.7 Incorporating Code Security in User Applications

Code security is typically not required in the development phase of a project. However, security is needed
once a robust code is developed for a zone. Before such a code is programmed in the Flash memory, a CSM
password must be chosen to secure the zone. Once a CSM password is in place for a zone, the zone is
secured (programming a password at the appropriate locations and either performing a device reset or setting
the FORCESEC bit (Zx_CR.31) is the action that secures the device). From that time on, access to debug the
contents of secure memory by any means (using JTAG, code running off external/on-chip memory, and so forth)
requires a valid password. A password is not needed to run the code out of secure memory (such as in a typical
end-user usage); however, access to secure memory contents for debug purposes, requires a password.
5.7.1 Environments That Require Security Unlocking
The following are the typical situations under which unsecuring the zone can be required:
• Code development using debuggers (such as Code Composer Studio™ IDE). This is the most common
environment during the design phase of a product.
• Flash programming using TI Flash utilities such as Code Composer Studio On-Chip Flash Programmer
plug-in or the Uniflash tool. Flash programming is common during code development and testing. Once
the user supplies the necessary password, the Flash utilities disable the security logic before attempting to
program the Flash. In custom programming that uses the Flash API supplied by TI, unlocking the CSM can
be avoided by executing the Flash programming algorithms from secure memory.
• Custom environment defined by the application
In addition to the above, access to secure memory contents can be required in situations such as:
– Using the on-chip bootloader to load code or data into secure SRAM or to erase and program the Flash.
– Executing code from on-chip unsecure memory and requiring access to secure memory for the lookup
table. This is not a suggested operating condition as supplying the password from external code can
compromise code security.
The unsecuring sequence is identical in all the above situations. This sequence is referred to as the password
match flow (PMF) for simplicity. Section 5.7.2 explains the sequence of operation that is required every time the
user attempts to unsecure a particular zone. A code example is listed for clarity.
5.7.2 CSM Password Match Flow
Password match flow (PMF) is essentially a sequence of four dummy reads from password locations (PWL)
followed by four writes (32-bit writes) to CSMKEY(0/1/2/3) registers. Figure 5-3 shows how PMF helps to
initialize the security logic registers and disable security logic.

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Figure 5-3. CSM Password Match Flow (PMF)

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5.7.3 C Code Example to Unsecure C28x Zone1

volatile long int *CSM = (volatile long int *)5F090; //CSM register file volatile
long int *CSMPWL = (volatile long int *)0x78020; //CSM Password location (assuming default Zone
select block)
volatile int tmp;
int I;
// Read the 128-bits of the CSM password locations (PWL)
//
for (I=0;I<4; I++) tmp = *CSMPWL++;
// Write the 128-bit password to the CSMKEY registers
// If this password matches that stored in the CSLPWL,
// then the CSM becomes unsecure. If this password does not match,
// then the zone remains secure.
// An example password of: // 0x11112222333344445555666677778888 is used.
*CSM++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F090
*CSM++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F092
*CSM++ = 0x66665555; // Register Z1_CSMKEY2 at 0x5F094
*CSM++ = 0x88887777; // Register Z1_CSMKEY3 at 0x5F096

5.7.4 C Code Example to Resecure C28x Zone1

volatile int *Z1_CR = 0x5F019; //CSMSCR register

//Set FORCESEC bit
*Z1_CR = 0x8000;

5.7.5 Environments That Require ECSL Unlocking

The user develops some main IP, and then outsources peripheral functions to a subcontractor who must be able
to run the user code during debug and can halt while the main IP code is running. If ECSL is not unlocked,
then Code Composer Studio connections get disconnected, which can be inconvenient for the user. Note that
unlocking ECSL does not enable access to secure code but only avoids disconnection of CCS (JTAG).
5.7.6 ECSL Password Match Flow
A password match flow (PMF) is essentially a sequence of eight dummy reads from password locations (PWL)
followed by two writes to KEY registers. Figure 5-4 shows how the PMF helps to initialize the security logic
registers and disable security logic.

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START

Zone’s ECSL LOCK after reset

or runtime

Read Linkpointer and calculate

the address of ZoneSelectBlock

Dummy Read of CSM PWL of

the Secure Zone for which
ECSL needs to be unlocked

Write/Scanin the ECSL YES

Password of that Zone into
CSMKEY(0/1) registers.

NO
Correct Password?

YES

Zone ECSL unlock

Figure 5-4. ECSL Password Match Flow (PMF)

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5.7.7 ECSL Disable Considerations for any Zone

A zone with ECSL enabled can have a predetermined ECSL password stored in the ECSL password locations in
Flash (same as lower 64 bits of CSM passwords). The following are steps to disable the ECSL for any particular
zone:
1. Perform a dummy read of CSM password locations of that Zone.
2. Write the password into the CSMKEY0/1 registers, corresponding to that Zone.
3. If the password is correct, the ECSL gets disabled; otherwise, the ECSL stays enabled.

5.7.7.1 C Code Example to Disable ECSL for C28x Zone1

volatile long int *ECSL = (volatile int *)0x5F090; //ECSL register file
volatile long int *ECSLPWL = (volatile int *)0x78028; //ECSL Password location (assuming default
Zone sel block)
volatile int tmp;
int I;
// Read the 64-bits of the password locations (PWL).
for (I=0;I<2; I++) tmp = *ECSLPWL++;
// Write the 64-bit password to the CSMKEYx registers
// If this password matches that stored in the CSMPWL,
// then ECSL gets disabled. If this password does not match,
// then the zone remains secure.
// An example password of: // 0x1111222233334444 is used.
*ECSL++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F090
*ECSL++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F092

5.7.8 Device Unique ID

TI OTP contains a 256-bit value that is made up of both random and sequential parts. This value can be used as
a seed for code encryption. The starting address of the value is 0x72168. The first 192 bits are random, the next
32 bits are sequential, and the last 32 bits are a checksum value.
5.8 Software
5.8.1 DCSM Registers to Driverlib Functions
Table 5-4. DCSM Registers to Driverlib Functions
File Driverlib Function
Z1OTP_LINKPOINTER1
-
Z1OTP_LINKPOINTER2
-
Z1OTP_LINKPOINTER3
-
Z1OTP_JLM_ENABLE
-
Z1OTP_GPREG1
-
Z1OTP_GPREG2
-
Z1OTP_GPREG3
-
Z1OTP_GPREG4
-
Z1OTP_PSWDLOCK
-
Z1OTP_CRCLOCK

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Table 5-4. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
-
Z1OTP_JTAGPSWDH0
-
Z1OTP_JTAGPSWDH1
-
Z1OTP_CMACKEY0
-
Z1OTP_CMACKEY1
-
Z1OTP_CMACKEY2
-
Z1OTP_CMACKEY3
-
Z2OTP_LINKPOINTER1
-
Z2OTP_LINKPOINTER2
-
Z2OTP_LINKPOINTER3
-
Z2OTP_GPREG1
-
Z2OTP_GPREG2
-
Z2OTP_GPREG3
-
Z2OTP_GPREG4
-
Z2OTP_PSWDLOCK
-
Z2OTP_CRCLOCK
-
Z1_LINKPOINTER
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_readZone1CSMPwd
dcsm.h DCSM_getZone1LinkPointerError
Z1_OTPSECLOCK
dcsm.h DCSM_getZone1OTPSecureLockStatus
Z1_JLM_ENABLE
-
Z1_LINKPOINTERERR
dcsm.h DCSM_getZone1LinkPointerError
Z1_GPREG1
-
Z1_GPREG2
-

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Table 5-4. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
Z1_GPREG3
-
Z1_GPREG4
-
Z1_CSMKEY0
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY1
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY2
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY3
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CR
dcsm.h DCSM_secureZone1
dcsm.h DCSM_getZone1CSMSecurityStatus
dcsm.h DCSM_getZone1ControlStatus
Z1_GRABSECT1R
-
Z1_GRABSECT2R
-
Z1_GRABSECT3R
-
Z1_GRABRAM1R
-
Z1_EXEONLYSECT1R
dcsm.c DCSM_getZone1FlashEXEStatus
Z1_EXEONLYSECT2R
dcsm.c DCSM_getZone1FlashEXEStatus
Z1_EXEONLYRAM1R
dcsm.c DCSM_getZone1RAMEXEStatus
Z1_JTAGKEY0
-
Z1_JTAGKEY1
-
Z1_JTAGKEY2
-
Z1_JTAGKEY3
-
Z1_CMACKEY0
-
Z1_CMACKEY1

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Table 5-4. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
-
Z1_CMACKEY2
-
Z1_CMACKEY3
-
Z1_DIAG
-
Z2_LINKPOINTER
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_readZone2CSMPwd
dcsm.h DCSM_getZone2LinkPointerError
Z2_OTPSECLOCK
dcsm.h DCSM_getZone2OTPSecureLockStatus
Z2_LINKPOINTERERR
dcsm.h DCSM_getZone2LinkPointerError
Z2_GPREG1
-
Z2_GPREG2
-
Z2_GPREG3
-
Z2_GPREG4
-
Z2_CSMKEY0
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY1
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY2
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY3
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CR
dcsm.h DCSM_secureZone2
dcsm.h DCSM_getZone2CSMSecurityStatus
dcsm.h DCSM_getZone2ControlStatus
Z2_GRABSECT1R
-
Z2_GRABSECT2R
-
Z2_GRABSECT3R
-

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Table 5-4. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
Z2_GRABRAM1R
-
Z2_EXEONLYSECT1R
dcsm.c DCSM_getZone2FlashEXEStatus
Z2_EXEONLYSECT2R
dcsm.c DCSM_getZone2FlashEXEStatus
Z2_EXEONLYRAM1R
dcsm.c DCSM_getZone2RAMEXEStatus
FLSEM
dcsm.c DCSM_claimZoneSemaphore
dcsm.c DCSM_releaseZoneSemaphore
SECTSTAT1
dcsm.h DCSM_getFlashSectorZone
SECTSTAT2
dcsm.h DCSM_getFlashSectorZone
SECTSTAT3
dcsm.h DCSM_getFlashSectorZone
RAMSTAT1
dcsm.h DCSM_getRAMZone
SECERRSTAT
dcsm.h DCSM_getFlashErrorStatus
SECERRCLR
dcsm.h DCSM_clearFlashErrorStatus
SECERRFRC
dcsm.h DCSM_forceFlashErrorStatus
DENYCODE
dcsm.h DCSM_getFlashDenyCodeStatus
UID_UNIQUE_31_0
dcsm.h DCSM_getDeviceUIDLow
UID_UNIQUE_63_32
dcsm.h DCSM_getDeviceUIDHigh
PARTIDH
dcsm.h DCSM_getDevicePartID
PERSEM1
dcsm.h DCSM_getPerSemStatus
dcsm.h DCSM_forcePerSemStatus

5.8.2 DCSM Examples

NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/dcsm
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
5.8.2.1 Empty DCSM Tool Example
FILE: dcsm_security_tool.c

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This example is an empty project setup for DCSM Tool and Driverlib development. For guidance refer to: C2000
DCSM Security Tool
5.9 DCSM Registers
This Section describes the DCSM Registers.
5.9.1 DCSM Base Address Table
Table 5-5. DCSM Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1
Instance Structure Protected

DcsmZ1Regs DCSM_Z1_REGS DCSM_Z1_BASE 0x0005_F000 YES - - YES

DcsmZ2Regs DCSM_Z2_REGS DCSM_Z2_BASE 0x0005_F080 YES - - YES
DcsmCommonR DCSM_COMMON DCSMCOMMON_B
0x0005_F0C0 YES - - YES
egs _REGS ASE
DCSM_Z1OTP_BAS
DcsmZ1OtpRegs DCSM_Z1_OTP 0x0007_8000 YES - - -
E
DCSM_Z2OTP_BAS
DcsmZ2OtpRegs DCSM_Z2_OTP 0x0007_8200 YES - - -
E

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5.9.2 DCSM_Z1_REGS Registers

Table 5-6 lists the memory-mapped registers for the DCSM_Z1_REGS registers. All register offset addresses not
listed in Table 5-6 should be considered as reserved locations and the register contents should not be modified.
Table 5-6. DCSM_Z1_REGS Registers
Offset Acronym Register Name Write Protection Section
0h Z1_LINKPOINTER Zone 1 Link Pointer Go
2h Z1_OTPSECLOCK Zone 1 OTP Secure Lock Go
4h Z1_JLM_ENABLE Zone 1 JTAGLOCK Enable Register Go
6h Z1_LINKPOINTERERR Link Pointer Error Go
8h Z1_GPREG1 Zone 1 General Purpose Register-1 Go
Ah Z1_GPREG2 Zone 1 General Purpose Register-2 Go
Ch Z1_GPREG3 Zone 1 General Purpose Register-3 Go
Eh Z1_GPREG4 Zone 1 General Purpose Register-4 Go
10h Z1_CSMKEY0 Zone 1 CSM Key 0 Go
12h Z1_CSMKEY1 Zone 1 CSM Key 1 Go
14h Z1_CSMKEY2 Zone 1 CSM Key 2 Go
16h Z1_CSMKEY3 Zone 1 CSM Key 3 Go
18h Z1_CR Zone 1 CSM Control Register Go
1Ah Z1_GRABSECT1R Zone 1 Grab Flash Status Register 1 Go
1Ch Z1_GRABSECT2R Zone 1 Grab Flash Status Register 2 Go
1Eh Z1_GRABSECT3R Zone 1 Grab Flash Status Register 3 Go
20h Z1_GRABRAM1R Zone 1 Grab RAM Status Register 1 Go
26h Z1_EXEONLYSECT1R Zone 1 Execute Only Flash Status Register 1 Go
28h Z1_EXEONLYSECT2R Zone 1 Execute Only Flash Status Register 2 Go
2Ah Z1_EXEONLYRAM1R Zone 1 Execute Only RAM Status Register 1 Go
2Eh Z1_JTAGKEY0 JTAG Unlock Key Register 0 Go
30h Z1_JTAGKEY1 JTAG Unlock Key Register 1 Go
32h Z1_JTAGKEY2 JTAG Unlock Key Register 2 Go
34h Z1_JTAGKEY3 JTAG Unlock Key Register 3 Go
36h Z1_CMACKEY0 Secure Boot CMAC Key Status Register 0 Go
38h Z1_CMACKEY1 Secure Boot CMAC Key Status Register 1 Go
3Ah Z1_CMACKEY2 Secure Boot CMAC Key Status Register 2 Go
3Ch Z1_CMACKEY3 Secure Boot CMAC Key Status Register 3 Go
3Eh Z1_DIAG Diagnostics Configuration Register Go

Complex bit access types are encoded to fit into small table cells. Table 5-7 shows the codes that are used for
access types in this section.
Table 5-7. DCSM_Z1_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value

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Table 5-7. DCSM_Z1_REGS Access Type Codes

(continued)
Access Type Code Description
-n Value after reset or the default
value

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5.9.2.1 Z1_LINKPOINTER Register (Offset = 0h) [Reset = FFFFC000h]

Z1_LINKPOINTER is shown in Figure 5-5 and described in Table 5-8.
Return to the Summary Table.
Zone 1 Link Pointer
Figure 5-5. Z1_LINKPOINTER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LINKPOINTER
R-0003FFFFh R-0h

Table 5-8. Z1_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0003FFFFh Reserved
13-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP
Reset type: SYSRSn

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5.9.2.2 Z1_OTPSECLOCK Register (Offset = 2h) [Reset = 00000001h]

Z1_OTPSECLOCK is shown in Figure 5-6 and described in Table 5-9.
Return to the Summary Table.
Zone 1 OTP Secure Lock
Figure 5-6. Z1_OTPSECLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED CRCLOCK
R-0h R-0h

7 6 5 4 3 2 1 0
PSWDLOCK RESERVED JTAGLOCK
R-0h R-0h R-1h

Table 5-9. Z1_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R 0h Value in this field gets loaded from Z1_CRCLOCK[3:0] when a read
is issued to address location of Z1_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: XRSn
7-4 PSWDLOCK R 0h Value in this field gets loaded from Z1_PSWDLOCK[3:0] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can be
read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: XRSn
3-1 RESERVED R 0h Reserved
0 JTAGLOCK R 1h Reflects the state of the JTAGLOCK feature.
0 : JTAG is not locked
1 : JTAG is locked
Reset type: PORESETn

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5.9.2.3 Z1_JLM_ENABLE Register (Offset = 4h) [Reset = 0000000Fh]

Z1_JLM_ENABLE is shown in Figure 5-7 and described in Table 5-10.
Return to the Summary Table.
Zone 1 JTAGLOCK Enable Register
Figure 5-7. Z1_JLM_ENABLE Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED Z1_JLM_ENABLE
R-0-0h R-Fh

Table 5-10. Z1_JLM_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3-0 Z1_JLM_ENABLE R Fh Zone1 JLM_ENABLE register. The value in this field gets
loaded from Z1OTP_JLM_ENABLE[3:0] when a read is issued
to address location of Z1OTP_JLM_ENABLE in OTP. If
Z1OTP_JLM_ENABLE[31:0] is equal to all ones during the load,
the JTAGLOCK is not bypassed (is enabled). If the value of
Z1OTP_JLM_ENABLE[31:0] is not all ones during the load, the
JTAGLOCK is governed as follows by the Z1_JLM_ENABLE bits:
1111 : JTAG/Emulation access is allowed (JTAGLOCK is not
enabled)
Other values: JTAGLOCK is governed by the
JTAGKEY==JTAGPSWD match condition
Reset type: PORESETn

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5.9.2.4 Z1_LINKPOINTERERR Register (Offset = 6h) [Reset = 00000000h]

Z1_LINKPOINTERERR is shown in Figure 5-8 and described in Table 5-11.
Return to the Summary Table.
Link Pointer Error
Figure 5-8. Z1_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Z1_LINKPOINTERERR
R-0-0h R-0h

Table 5-11. Z1_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R-0 0h Reserved
13-0 Z1_LINKPOINTERERR R 0h These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP in flash.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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5.9.2.5 Z1_GPREG1 Register (Offset = 8h) [Reset = 00000000h]

Z1_GPREG1 is shown in Figure 5-9 and described in Table 5-12.
Return to the Summary Table.
Zone 1 General Purpose Register-1
Figure 5-9. Z1_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG1
R-0h

Table 5-12. Z1_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG1 R 0h This field gets loaded with the contents of Z1OTP_GPREG1
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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5.9.2.6 Z1_GPREG2 Register (Offset = Ah) [Reset = 00000000h]

Z1_GPREG2 is shown in Figure 5-10 and described in Table 5-13.
Return to the Summary Table.
Zone 1 General Purpose Register-2
Figure 5-10. Z1_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG2
R-0h

Table 5-13. Z1_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG2 R 0h This field gets loaded with the contents of Z1OTP_GPREG2
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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5.9.2.7 Z1_GPREG3 Register (Offset = Ch) [Reset = 00000000h]

Z1_GPREG3 is shown in Figure 5-11 and described in Table 5-14.
Return to the Summary Table.
Zone 1 General Purpose Register-3
Figure 5-11. Z1_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG3
R-0h

Table 5-14. Z1_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG3 R 0h This field gets loaded with the contents of Z1OTP_GPREG3
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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5.9.2.8 Z1_GPREG4 Register (Offset = Eh) [Reset = 00000000h]

Z1_GPREG4 is shown in Figure 5-12 and described in Table 5-15.
Return to the Summary Table.
Zone 1 General Purpose Register-4
Figure 5-12. Z1_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG4
R-0h

Table 5-15. Z1_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG4 R 0h This field gets loaded with the contents of Z1OTP_GPREG4
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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5.9.2.9 Z1_CSMKEY0 Register (Offset = 10h) [Reset = 00000000h]

Z1_CSMKEY0 is shown in Figure 5-13 and described in Table 5-16.
Return to the Summary Table.
Zone 1 CSM Key 0
Figure 5-13. Z1_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY0
R/W-0h

Table 5-16. Z1_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY0 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.2.10 Z1_CSMKEY1 Register (Offset = 12h) [Reset = 00000000h]

Z1_CSMKEY1 is shown in Figure 5-14 and described in Table 5-17.
Return to the Summary Table.
Zone 1 CSM Key 1
Figure 5-14. Z1_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY1
R/W-0h

Table 5-17. Z1_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY1 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.2.11 Z1_CSMKEY2 Register (Offset = 14h) [Reset = 00000000h]

Z1_CSMKEY2 is shown in Figure 5-15 and described in Table 5-18.
Return to the Summary Table.
Zone 1 CSM Key 2
Figure 5-15. Z1_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY2
R/W-0h

Table 5-18. Z1_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY2 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.2.12 Z1_CSMKEY3 Register (Offset = 16h) [Reset = 00000000h]

Z1_CSMKEY3 is shown in Figure 5-16 and described in Table 5-19.
Return to the Summary Table.
Zone 1 CSM Key 3
Figure 5-16. Z1_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY3
R/W-0h

Table 5-19. Z1_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY3 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.2.13 Z1_CR Register (Offset = 18h) [Reset = 00080000h]

Z1_CR is shown in Figure 5-17 and described in Table 5-20.
Return to the Summary Table.
Zone 1 CSM Control Register
Figure 5-17. Z1_CR Register
31 30 29 28 27 26 25 24
FORCESEC RESERVED
R-0/W-0h R-0h

23 22 21 20 19 18 17 16
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-0h R-1h R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R-0h R-0h R-0h R-0h

Table 5-20. Z1_CR Register Field Descriptions

Bit Field Type Reset Description
31 FORCESEC R-0/W 0h A write of '1' to this bit clears the CSMKEYx registers. If writing to this
bit after performing an update of the security passwords, it is advised
to immediately perform a dummy load of the passwords by initiating
a read of the passwords from their flash locations.
Reset type: SYSRSn
30-24 RESERVED R 0h Reserved
23 RESERVED R 0h Reserved
22 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
21 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
20 ALLONE R 0h Indicates the state of CSM passwords.
0 : Zone CSM Passwords are not all ones.
1 : Zone CSM Passwords are all ones.
Reset type: SYSRSn
19 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
18-16 RESERVED R 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R 0h Reserved

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Table 5-20. Z1_CR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 RESERVED R 0h Reserved

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5.9.2.14 Z1_GRABSECT1R Register (Offset = 1Ah) [Reset = 00000000h]

Z1_GRABSECT1R is shown in Figure 5-18 and described in Table 5-21.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 1
Figure 5-18. Z1_GRABSECT1R Register
31 30 29 28 27 26 25 24
GRAB_B1_SECT127_96 GRAB_B1_SECT95_64 GRAB_B1_SECT63_32 GRAB_B1_SECT31_4
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_B1_SECT3 GRAB_B1_SECT2 GRAB_B1_SECT1 GRAB_B1_SECT0
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_B0_SECT127_96 GRAB_B0_SECT95_64 GRAB_B0_SECT63_32 GRAB_B0_SECT31_4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_B0_SECT3 GRAB_B0_SECT2 GRAB_B0_SECT1 GRAB_B0_SECT0
R-0h R-0h R-0h R-0h

Table 5-21. Z1_GRABSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_B1_SECT127_96 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
29-28 GRAB_B1_SECT95_64 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
27-26 GRAB_B1_SECT63_32 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-21. Z1_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_B1_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
23-22 GRAB_B1_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
21-20 GRAB_B1_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
19-18 GRAB_B1_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_B1_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_B0_SECT127_96 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-21. Z1_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_B0_SECT95_64 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_B0_SECT63_32 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_B0_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_B0_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_B0_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_B0_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-21. Z1_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GRAB_B0_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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5.9.2.15 Z1_GRABSECT2R Register (Offset = 1Ch) [Reset = 00000000h]

Z1_GRABSECT2R is shown in Figure 5-19 and described in Table 5-22.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 2
Figure 5-19. Z1_GRABSECT2R Register
31 30 29 28 27 26 25 24
GRAB_B3_SECT127_96 GRAB_B3_SECT95_64 GRAB_B3_SECT63_32 GRAB_B3_SECT31_4
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_B3_SECT3 GRAB_B3_SECT2 GRAB_B3_SECT1 GRAB_B3_SECT0
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_B2_SECT127_96 GRAB_B2_SECT95_64 GRAB_B2_SECT63_32 GRAB_B2_SECT31_4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_B2_SECT3 GRAB_B2_SECT2 GRAB_B2_SECT1 GRAB_B2_SECT0
R-0h R-0h R-0h R-0h

Table 5-22. Z1_GRABSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_B3_SECT127_96 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
29-28 GRAB_B3_SECT95_64 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
27-26 GRAB_B3_SECT63_32 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-22. Z1_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_B3_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
23-22 GRAB_B3_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
21-20 GRAB_B3_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
19-18 GRAB_B3_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_B3_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_B2_SECT127_96 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-22. Z1_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_B2_SECT95_64 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_B2_SECT63_32 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_B2_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_B2_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_B2_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_B2_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-22. Z1_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GRAB_B2_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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5.9.2.16 Z1_GRABSECT3R Register (Offset = 1Eh) [Reset = 00000000h]

Z1_GRABSECT3R is shown in Figure 5-20 and described in Table 5-23.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 3
Figure 5-20. Z1_GRABSECT3R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED GRAB_B4_SECT31_4
R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_B4_SECT3 GRAB_B4_SECT2 GRAB_B4_SECT1 GRAB_B4_SECT0
R-0h R-0h R-0h R-0h

Table 5-23. Z1_GRABSECT3R Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9-8 GRAB_B4_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_B4_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_B4_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-23. Z1_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 GRAB_B4_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_B4_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z1_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone1.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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5.9.2.17 Z1_GRABRAM1R Register (Offset = 20h) [Reset = 00000000h]

Z1_GRABRAM1R is shown in Figure 5-21 and described in Table 5-24.
Return to the Summary Table.
Zone 1 Grab RAM Status Register 1
Figure 5-21. Z1_GRABRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 5-24. Z1_GRABRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 5-24. Z1_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 5-24. Z1_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z1_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone1
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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5.9.2.18 Z1_EXEONLYSECT1R Register (Offset = 26h) [Reset = 00000000h]

Z1_EXEONLYSECT1R is shown in Figure 5-22 and described in Table 5-25.
Return to the Summary Table.
Zone 1 Execute Only Flash Status Register 1
Figure 5-22. Z1_EXEONLYSECT1R Register
31 30 29 28 27 26 25 24
EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_
SECT127_96 SECT95_64 SECT63_32 SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_
SECT127_96 SECT95_64 SECT63_32 SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_
SECT127_96 SECT95_64 SECT63_32 SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_
SECT127_96 SECT95_64 SECT63_32 SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-25. Z1_EXEONLYSECT1R Register Field Descriptions

Bit Field Type Reset Description
31 EXEONLY_B3_SECT127_ R 0h Value in this bit gets loaded from the equivalent bit when a
96 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
30 EXEONLY_B3_SECT95_6 R 0h Value in this bit gets loaded from the equivalent bit when a
4 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
29 EXEONLY_B3_SECT63_3 R 0h Value in this bit gets loaded from the equivalent bit when a
2 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn

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Table 5-25. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
28 EXEONLY_B3_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
27 EXEONLY_B3_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
26 EXEONLY_B3_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
25 EXEONLY_B3_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
24 EXEONLY_B3_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
23 EXEONLY_B2_SECT127_ R 0h Value in this bit gets loaded from the equivalent bit when a
96 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
22 EXEONLY_B2_SECT95_6 R 0h Value in this bit gets loaded from the equivalent bit when a
4 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn

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Table 5-25. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
21 EXEONLY_B2_SECT63_3 R 0h Value in this bit gets loaded from the equivalent bit when a
2 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
20 EXEONLY_B2_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
19 EXEONLY_B2_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
18 EXEONLY_B2_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
17 EXEONLY_B2_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
16 EXEONLY_B2_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
15 EXEONLY_B1_SECT127_ R 0h Value in this bit gets loaded from the equivalent bit when a
96 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn

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Table 5-25. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
14 EXEONLY_B1_SECT95_6 R 0h Value in this bit gets loaded from the equivalent bit when a
4 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
13 EXEONLY_B1_SECT63_3 R 0h Value in this bit gets loaded from the equivalent bit when a
2 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
12 EXEONLY_B1_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
11 EXEONLY_B1_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
10 EXEONLY_B1_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
9 EXEONLY_B1_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_B1_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn

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Table 5-25. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
7 EXEONLY_B0_SECT127_ R 0h Value in this bit gets loaded from the equivalent bit when a
96 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_B0_SECT95_6 R 0h Value in this bit gets loaded from the equivalent bit when a
4 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_B0_SECT63_3 R 0h Value in this bit gets loaded from the equivalent bit when a
2 read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_B0_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_B0_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_B0_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_B0_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn

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Table 5-25. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
0 EXEONLY_B0_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn

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5.9.2.19 Z1_EXEONLYSECT2R Register (Offset = 28h) [Reset = 00000000h]

Z1_EXEONLYSECT2R is shown in Figure 5-23 and described in Table 5-26.
Return to the Summary Table.
Zone 1 Execute Only Flash Status Register 2
Figure 5-23. Z1_EXEONLYSECT2R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED EXEONLY_B4_ EXEONLY_B4_ EXEONLY_B4_ EXEONLY_B4_ EXEONLY_B4_
SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-26. Z1_EXEONLYSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R 0h Reserved
4 EXEONLY_B4_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_B4_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_B4_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn

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Table 5-26. Z1_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EXEONLY_B4_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_B4_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone1)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone1)
Reset type: SYSRSn

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5.9.2.20 Z1_EXEONLYRAM1R Register (Offset = 2Ah) [Reset = 00000000h]

Z1_EXEONLYRAM1R is shown in Figure 5-24 and described in Table 5-27.
Return to the Summary Table.
Zone 1 Execute Only RAM Status Register 1
Figure 5-24. Z1_EXEONLYRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED EXEONLY_RA EXEONLY_RA
M9 M8
R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-27. Z1_EXEONLYRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9 EXEONLY_RAM9 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_RAM8 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_RAM7 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn

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Table 5-27. Z1_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
6 EXEONLY_RAM6 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_RAM3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_RAM1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_RAM0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z1_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone1)
Reset type: SYSRSn

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5.9.2.21 Z1_JTAGKEY0 Register (Offset = 2Eh) [Reset = 00000000h]

Z1_JTAGKEY0 is shown in Figure 5-25 and described in Table 5-28.
Return to the Summary Table.
JTAG Unlock Key Register 0
Figure 5-25. Z1_JTAGKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY0
R-0h

Table 5-28. Z1_JTAGKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY0 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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5.9.2.22 Z1_JTAGKEY1 Register (Offset = 30h) [Reset = 00000000h]

Z1_JTAGKEY1 is shown in Figure 5-26 and described in Table 5-29.
Return to the Summary Table.
JTAG Unlock Key Register 1
Figure 5-26. Z1_JTAGKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1
R-0h

Table 5-29. Z1_JTAGKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY1 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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5.9.2.23 Z1_JTAGKEY2 Register (Offset = 32h) [Reset = 00000000h]

Z1_JTAGKEY2 is shown in Figure 5-27 and described in Table 5-30.
Return to the Summary Table.
JTAG Unlock Key Register 2
Figure 5-27. Z1_JTAGKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY2
R-0h

Table 5-30. Z1_JTAGKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY2 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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5.9.2.24 Z1_JTAGKEY3 Register (Offset = 34h) [Reset = 00000000h]

Z1_JTAGKEY3 is shown in Figure 5-28 and described in Table 5-31.
Return to the Summary Table.
JTAG Unlock Key Register 3
Figure 5-28. Z1_JTAGKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY3
R-0h

Table 5-31. Z1_JTAGKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY3 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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5.9.2.25 Z1_CMACKEY0 Register (Offset = 36h) [Reset = 00000000h]

Z1_CMACKEY0 is shown in Figure 5-29 and described in Table 5-32.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 0
Figure 5-29. Z1_CMACKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY0
R-0h

Table 5-32. Z1_CMACKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY0 R 0h Value in this field gets loaded from CMACKEY0 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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5.9.2.26 Z1_CMACKEY1 Register (Offset = 38h) [Reset = 00000000h]

Z1_CMACKEY1 is shown in Figure 5-30 and described in Table 5-33.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 1
Figure 5-30. Z1_CMACKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1
R-0h

Table 5-33. Z1_CMACKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY1 R 0h Value in this field gets loaded from CMACKEY1 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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5.9.2.27 Z1_CMACKEY2 Register (Offset = 3Ah) [Reset = 00000000h]

Z1_CMACKEY2 is shown in Figure 5-31 and described in Table 5-34.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 2
Figure 5-31. Z1_CMACKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY2
R-0h

Table 5-34. Z1_CMACKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY2 R 0h Value in this field gets loaded from CMACKEY2 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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5.9.2.28 Z1_CMACKEY3 Register (Offset = 3Ch) [Reset = 00000000h]

Z1_CMACKEY3 is shown in Figure 5-32 and described in Table 5-35.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 3
Figure 5-32. Z1_CMACKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY3
R-0h

Table 5-35. Z1_CMACKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY3 R 0h Value in this field gets loaded from CMACKEY3 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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5.9.2.29 Z1_DIAG Register (Offset = 3Eh) [Reset = 00000000h]

Z1_DIAG is shown in Figure 5-33 and described in Table 5-36.
Return to the Summary Table.
Diagnostics Configuration Register
Figure 5-33. Z1_DIAG Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED MPOST_EN RESERVED RESERVED
R-0-0h R-0h R-0h R-0h

Table 5-36. Z1_DIAG Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 MPOST_EN R 0h Value in this bit gets loaded from the equivalent bit when a read is
issued to the Z1_DIAG address location in the SECURITY sector.
MPOST Enable. Indicates whether the boot ROM should run
MPOST or not at boot.
01: Enable MPOST.
10: Disable MPOST.
Reset type: N/A
3-2 RESERVED R 0h Reserved
1-0 RESERVED R 0h Reserved

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5.9.3 DCSM_Z2_REGS Registers

Table 5-37 lists the memory-mapped registers for the DCSM_Z2_REGS registers. All register offset addresses
not listed in Table 5-37 should be considered as reserved locations and the register contents should not be
modified.
Table 5-37. DCSM_Z2_REGS Registers
Offset Acronym Register Name Write Protection Section
0h Z2_LINKPOINTER Zone 2 Link Pointer Go
2h Z2_OTPSECLOCK Zone 2 OTP Secure Lock Go
6h Z2_LINKPOINTERERR Link Pointer Error Go
8h Z2_GPREG1 Zone 2 General Purpose Register-1 Go
Ah Z2_GPREG2 Zone 2 General Purpose Register-2 Go
Ch Z2_GPREG3 Zone 2 General Purpose Register-3 Go
Eh Z2_GPREG4 Zone 2 General Purpose Register-4 Go
10h Z2_CSMKEY0 Zone 2 CSM Key 0 Go
12h Z2_CSMKEY1 Zone 2 CSM Key 1 Go
14h Z2_CSMKEY2 Zone 2 CSM Key 2 Go
16h Z2_CSMKEY3 Zone 2 CSM Key 3 Go
18h Z2_CR Zone 2 CSM Control Register Go
1Ah Z2_GRABSECT1R Zone 2 Grab Flash Status Register 1 Go
1Ch Z2_GRABSECT2R Zone 2 Grab Flash Status Register 2 Go
1Eh Z2_GRABSECT3R Zone 2 Grab Flash Status Register 3 Go
20h Z2_GRABRAM1R Zone 2 Grab RAM Status Register 1 Go
26h Z2_EXEONLYSECT1R Zone 2 Execute Only Flash Status Register 1 Go
28h Z2_EXEONLYSECT2R Zone 2 Execute Only Flash Status Register 2 Go
2Ah Z2_EXEONLYRAM1R Zone 2 Execute Only RAM Status Register 1 Go

Complex bit access types are encoded to fit into small table cells. Table 5-38 shows the codes that are used for
access types in this section.
Table 5-38. DCSM_Z2_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value

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5.9.3.1 Z2_LINKPOINTER Register (Offset = 0h) [Reset = FFFFC000h]

Z2_LINKPOINTER is shown in Figure 5-34 and described in Table 5-39.
Return to the Summary Table.
Zone 2 Link Pointer
Figure 5-34. Z2_LINKPOINTER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LINKPOINTER
R-0003FFFFh R-0h

Table 5-39. Z2_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0003FFFFh Reserved
13-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP
Reset type: SYSRSn

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5.9.3.2 Z2_OTPSECLOCK Register (Offset = 2h) [Reset = 00000001h]

Z2_OTPSECLOCK is shown in Figure 5-35 and described in Table 5-40.
Return to the Summary Table.
Zone 2 OTP Secure Lock
Figure 5-35. Z2_OTPSECLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED CRCLOCK
R-0h R-0h

7 6 5 4 3 2 1 0
PSWDLOCK RESERVED JTAGLOCK
R-0h R-0h R-1h

Table 5-40. Z2_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R 0h Value in this field gets loaded from Z2_CRCLOCK[3:0] when a read
is issued to address location of Z2_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: XRSn
7-4 PSWDLOCK R 0h Value in this field gets loaded from Z2_PSWDLOCK[3:0] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can be
read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: XRSn
3-1 RESERVED R 0h Reserved
0 JTAGLOCK R 1h Reflects the state of the JTAGLOCK feature.
0 : JTAG is not locked
1 : JTAG is locked
This bit is a copy of the Z1_OTPSECLOCK.JTAGLOCK bit.
Reset type: PORESETn

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5.9.3.3 Z2_LINKPOINTERERR Register (Offset = 6h) [Reset = 00000000h]

Z2_LINKPOINTERERR is shown in Figure 5-36 and described in Table 5-41.
Return to the Summary Table.
Link Pointer Error
Figure 5-36. Z2_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Z2_LINKPOINTERERR
R-0-0h R-0h

Table 5-41. Z2_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R-0 0h Reserved
13-0 Z2_LINKPOINTERERR R 0h These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP in flash.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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5.9.3.4 Z2_GPREG1 Register (Offset = 8h) [Reset = 00000000h]

Z2_GPREG1 is shown in Figure 5-37 and described in Table 5-42.
Return to the Summary Table.
Zone 2 General Purpose Register-1
Figure 5-37. Z2_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG1
R-0h

Table 5-42. Z2_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG1 R 0h This field gets loaded with the contents of Z2OTP_GPREG1
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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5.9.3.5 Z2_GPREG2 Register (Offset = Ah) [Reset = 00000000h]

Z2_GPREG2 is shown in Figure 5-38 and described in Table 5-43.
Return to the Summary Table.
Zone 2 General Purpose Register-2
Figure 5-38. Z2_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG2
R-0h

Table 5-43. Z2_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG2 R 0h This field gets loaded with the contents of Z2OTP_GPREG2
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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5.9.3.6 Z2_GPREG3 Register (Offset = Ch) [Reset = 00000000h]

Z2_GPREG3 is shown in Figure 5-39 and described in Table 5-44.
Return to the Summary Table.
Zone 2 General Purpose Register-3
Figure 5-39. Z2_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG3
R-0h

Table 5-44. Z2_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG3 R 0h This field gets loaded with the contents of Z2OTP_GPREG3
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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5.9.3.7 Z2_GPREG4 Register (Offset = Eh) [Reset = 00000000h]

Z2_GPREG4 is shown in Figure 5-40 and described in Table 5-45.
Return to the Summary Table.
Zone 2 General Purpose Register-4
Figure 5-40. Z2_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG4
R-0h

Table 5-45. Z2_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG4 R 0h This field gets loaded with the contents of Z2OTP_GPREG4
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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5.9.3.8 Z2_CSMKEY0 Register (Offset = 10h) [Reset = 00000000h]

Z2_CSMKEY0 is shown in Figure 5-41 and described in Table 5-46.
Return to the Summary Table.
Zone 2 CSM Key 0
Figure 5-41. Z2_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY0
R/W-0h

Table 5-46. Z2_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY0 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.3.9 Z2_CSMKEY1 Register (Offset = 12h) [Reset = 00000000h]

Z2_CSMKEY1 is shown in Figure 5-42 and described in Table 5-47.
Return to the Summary Table.
Zone 2 CSM Key 1
Figure 5-42. Z2_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY1
R/W-0h

Table 5-47. Z2_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY1 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.3.10 Z2_CSMKEY2 Register (Offset = 14h) [Reset = 00000000h]

Z2_CSMKEY2 is shown in Figure 5-43 and described in Table 5-48.
Return to the Summary Table.
Zone 2 CSM Key 2
Figure 5-43. Z2_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY2
R/W-0h

Table 5-48. Z2_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY2 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.3.11 Z2_CSMKEY3 Register (Offset = 16h) [Reset = 00000000h]

Z2_CSMKEY3 is shown in Figure 5-44 and described in Table 5-49.
Return to the Summary Table.
Zone 2 CSM Key 3
Figure 5-44. Z2_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY3
R/W-0h

Table 5-49. Z2_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY3 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.3.12 Z2_CR Register (Offset = 18h) [Reset = 00080000h]

Z2_CR is shown in Figure 5-45 and described in Table 5-50.
Return to the Summary Table.
Zone 2 CSM Control Register
Figure 5-45. Z2_CR Register
31 30 29 28 27 26 25 24
FORCESEC RESERVED
R-0/W-0h R-0h

23 22 21 20 19 18 17 16
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-0h R-1h R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R-0h R-0h R-0h R-0h

Table 5-50. Z2_CR Register Field Descriptions

Bit Field Type Reset Description
31 FORCESEC R-0/W 0h A write of '1' to this bit clears the CSMKEYx registers. If writing to this
bit after performing an update of the security passwords, it is advised
to immediately perform a dummy load of the passwords by initiating
a read of the passwords from their flash locations.
Reset type: SYSRSn
30-24 RESERVED R 0h Reserved
23 RESERVED R 0h Reserved
22 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
21 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
20 ALLONE R 0h Indicates the state of CSM passwords.
0 : Zone CSM Passwords are not all ones.
1 : Zone CSM Passwords are all ones.
Reset type: SYSRSn
19 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
18-16 RESERVED R 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R 0h Reserved

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Table 5-50. Z2_CR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 RESERVED R 0h Reserved

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5.9.3.13 Z2_GRABSECT1R Register (Offset = 1Ah) [Reset = 00000000h]

Z2_GRABSECT1R is shown in Figure 5-46 and described in Table 5-51.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 1
Figure 5-46. Z2_GRABSECT1R Register
31 30 29 28 27 26 25 24
GRAB_B1_SECT127_96 GRAB_B1_SECT95_64 GRAB_B1_SECT63_32 GRAB_B1_SECT31_4
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_B1_SECT3 GRAB_B1_SECT2 GRAB_B1_SECT1 GRAB_B1_SECT0
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_B0_SECT127_96 GRAB_B0_SECT95_64 GRAB_B0_SECT63_32 GRAB_B0_SECT31_4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_B0_SECT3 GRAB_B0_SECT2 GRAB_B0_SECT1 GRAB_B0_SECT0
R-0h R-0h R-0h R-0h

Table 5-51. Z2_GRABSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_B1_SECT127_96 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
29-28 GRAB_B1_SECT95_64 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
27-26 GRAB_B1_SECT63_32 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-51. Z2_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_B1_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
23-22 GRAB_B1_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
21-20 GRAB_B1_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
19-18 GRAB_B1_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_B1_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_B0_SECT127_96 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-51. Z2_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_B0_SECT95_64 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_B0_SECT63_32 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_B0_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_B0_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_B0_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_B0_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-51. Z2_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GRAB_B0_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT1 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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5.9.3.14 Z2_GRABSECT2R Register (Offset = 1Ch) [Reset = 00000000h]

Z2_GRABSECT2R is shown in Figure 5-47 and described in Table 5-52.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 2
Figure 5-47. Z2_GRABSECT2R Register
31 30 29 28 27 26 25 24
GRAB_B3_SECT127_96 GRAB_B3_SECT95_64 GRAB_B3_SECT63_32 GRAB_B3_SECT31_4
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_B3_SECT3 GRAB_B3_SECT2 GRAB_B3_SECT1 GRAB_B3_SECT0
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_B2_SECT127_96 GRAB_B2_SECT95_64 GRAB_B2_SECT63_32 GRAB_B2_SECT31_4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_B2_SECT3 GRAB_B2_SECT2 GRAB_B2_SECT1 GRAB_B2_SECT0
R-0h R-0h R-0h R-0h

Table 5-52. Z2_GRABSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_B3_SECT127_96 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
29-28 GRAB_B3_SECT95_64 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
27-26 GRAB_B3_SECT63_32 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-52. Z2_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_B3_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
23-22 GRAB_B3_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
21-20 GRAB_B3_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
19-18 GRAB_B3_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_B3_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_B2_SECT127_96 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-52. Z2_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_B2_SECT95_64 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_B2_SECT63_32 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_B2_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_B2_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_B2_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_B2_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-52. Z2_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GRAB_B2_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT2 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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5.9.3.15 Z2_GRABSECT3R Register (Offset = 1Eh) [Reset = 00000000h]

Z2_GRABSECT3R is shown in Figure 5-48 and described in Table 5-53.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 3
Figure 5-48. Z2_GRABSECT3R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED GRAB_B4_SECT31_4
R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_B4_SECT3 GRAB_B4_SECT2 GRAB_B4_SECT1 GRAB_B4_SECT0
R-0h R-0h R-0h R-0h

Table 5-53. Z2_GRABSECT3R Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9-8 GRAB_B4_SECT31_4 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_B4_SECT3 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_B4_SECT2 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-53. Z2_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 GRAB_B4_SECT1 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_B4_SECT0 R 0h Value in this field gets loaded from the equivalent bit field
when a read is issued to the active ZSB address location of
Z2_GRABSECT3 in the SECURITY sector.
00 : Invalid. Sectors are inaccessible.
01 : Request to allocate thes sectors to Zone2.
10 : No request for these sectors.
11 : No request for these sectors when this zone is UNLOCKED.
Else these sectors are inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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5.9.3.16 Z2_GRABRAM1R Register (Offset = 20h) [Reset = 00000000h]

Z2_GRABRAM1R is shown in Figure 5-49 and described in Table 5-54.
Return to the Summary Table.
Zone 2 Grab RAM Status Register 1
Figure 5-49. Z2_GRABRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 5-54. Z2_GRABRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 5-54. Z2_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 5-54. Z2_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from the equivalent bit field when a
read is issued to the active ZSB address location of Z2_GRABRAM1
in the SECURITY sector.
00 : Invalid. This section of RAM is inaccessible.
01 : Request to allocate this section of RAM to Zone2
10 : No request for this section of RAM
11 : No request for this section of RAM when this zone is
UNLOCKED. This section of RAM is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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5.9.3.17 Z2_EXEONLYSECT1R Register (Offset = 26h) [Reset = 00000000h]

Z2_EXEONLYSECT1R is shown in Figure 5-50 and described in Table 5-55.
Return to the Summary Table.
Zone 2 Execute Only Flash Status Register 1
Figure 5-50. Z2_EXEONLYSECT1R Register
31 30 29 28 27 26 25 24
EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_ EXEONLY_B3_
SECT127_96 SECT95_64 SECT63_32 SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_ EXEONLY_B2_
SECT127_96 SECT95_64 SECT63_32 SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_ EXEONLY_B1_
SECT127_96 SECT95_64 SECT63_32 SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_ EXEONLY_B0_
SECT127_96 SECT95_64 SECT63_32 SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-55. Z2_EXEONLYSECT1R Register Field Descriptions

Bit Field Type Reset Description
31 EXEONLY_B3_SECT127_ R 0h Value in this bit gets loaded from the equivalent bit when a
96 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
30 EXEONLY_B3_SECT95_6 R 0h Value in this bit gets loaded from the equivalent bit when a
4 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
29 EXEONLY_B3_SECT63_3 R 0h Value in this bit gets loaded from the equivalent bit when a
2 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn

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Table 5-55. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
28 EXEONLY_B3_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
27 EXEONLY_B3_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
26 EXEONLY_B3_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
25 EXEONLY_B3_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
24 EXEONLY_B3_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
23 EXEONLY_B2_SECT127_ R 0h Value in this bit gets loaded from the equivalent bit when a
96 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
22 EXEONLY_B2_SECT95_6 R 0h Value in this bit gets loaded from the equivalent bit when a
4 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn

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Table 5-55. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
21 EXEONLY_B2_SECT63_3 R 0h Value in this bit gets loaded from the equivalent bit when a
2 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
20 EXEONLY_B2_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
19 EXEONLY_B2_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
18 EXEONLY_B2_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
17 EXEONLY_B2_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
16 EXEONLY_B2_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
15 EXEONLY_B1_SECT127_ R 0h Value in this bit gets loaded from the equivalent bit when a
96 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn

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Table 5-55. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
14 EXEONLY_B1_SECT95_6 R 0h Value in this bit gets loaded from the equivalent bit when a
4 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
13 EXEONLY_B1_SECT63_3 R 0h Value in this bit gets loaded from the equivalent bit when a
2 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
12 EXEONLY_B1_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
11 EXEONLY_B1_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
10 EXEONLY_B1_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
9 EXEONLY_B1_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_B1_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn

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Table 5-55. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
7 EXEONLY_B0_SECT127_ R 0h Value in this bit gets loaded from the equivalent bit when a
96 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_B0_SECT95_6 R 0h Value in this bit gets loaded from the equivalent bit when a
4 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_B0_SECT63_3 R 0h Value in this bit gets loaded from the equivalent bit when a
2 read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_B0_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_B0_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_B0_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_B0_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn

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Table 5-55. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
0 EXEONLY_B0_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn

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5.9.3.18 Z2_EXEONLYSECT2R Register (Offset = 28h) [Reset = 00000000h]

Z2_EXEONLYSECT2R is shown in Figure 5-51 and described in Table 5-56.
Return to the Summary Table.
Zone 2 Execute Only Flash Status Register 2
Figure 5-51. Z2_EXEONLYSECT2R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED EXEONLY_B4_ EXEONLY_B4_ EXEONLY_B4_ EXEONLY_B4_ EXEONLY_B4_
SECT31_4 SECT3 SECT2 SECT1 SECT0
R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-56. Z2_EXEONLYSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R 0h Reserved
4 EXEONLY_B4_SECT31_4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_B4_SECT3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_B4_SECT2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn

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Table 5-56. Z2_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EXEONLY_B4_SECT1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_B4_SECT0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYSECT2 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this sector (only if it is
allocated to Zone2)
1 : Execute-Only protection is disabled for this sector (only if it is
allocated to Zone2)
Reset type: SYSRSn

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5.9.3.19 Z2_EXEONLYRAM1R Register (Offset = 2Ah) [Reset = 00000000h]

Z2_EXEONLYRAM1R is shown in Figure 5-52 and described in Table 5-57.
Return to the Summary Table.
Zone 2 Execute Only RAM Status Register 1
Figure 5-52. Z2_EXEONLYRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED EXEONLY_RA EXEONLY_RA
M9 M8
R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-57. Z2_EXEONLYRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9 EXEONLY_RAM9 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_RAM8 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_RAM7 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn

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Table 5-57. Z2_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
6 EXEONLY_RAM6 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_RAM3 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_RAM1 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_RAM0 R 0h Value in this bit gets loaded from the equivalent bit when a
read is issued to the Z2_EXEONLYRAM1 address location in the
SECURITY sector.
0 : Execute-Only protection is enabled for this section of RAM (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for this section of RAM (only
if it's allocated to Zone2)
Reset type: SYSRSn

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5.9.4 DCSM_COMMON_REGS Registers

Table 5-58 lists the memory-mapped registers for the DCSM_COMMON_REGS registers. All register offset
addresses not listed in Table 5-58 should be considered as reserved locations and the register contents should
not be modified.
Table 5-58. DCSM_COMMON_REGS Registers
Offset Acronym Register Name Write Protection Section
0h FLSEM Flash Wrapper Semaphore Register EALLOW Go
8h SECTSTAT1 Flash Sectors Status Register 1 Go
Ah SECTSTAT2 Flash Sectors Status Register 2 Go
Ch SECTSTAT3 Flash Sectors Status Register 3 Go
10h RAMSTAT1 RAM Status Register 1 Go
18h SECERRSTAT Security Error Status Register Go
1Ah SECERRCLR Security Error Clear Register Go
1Ch SECERRFRC Security Error Force Register Go
1Eh DENYCODE Flash Authorization Denial Code Go
28h UID_UNIQUE_31_0 Unique Identification Number Low Go
2Ah UID_UNIQUE_63_32 Unique Identification Number High Go
2Ch PARTIDH Part Identification High Register Go
2Eh PERSEM1 Peripheral Semaphore Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 5-59 shows the codes that are used for
access types in this section.
Table 5-59. DCSM_COMMON_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WOnce W Write
Once Write once
Reset or Default Value
-n Value after reset or the default
value

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5.9.4.1 FLSEM Register (Offset = 0h) [Reset = 00000000h]

FLSEM is shown in Figure 5-53 and described in Table 5-60.
Return to the Summary Table.
Flash Wrapper Semaphore Register
Figure 5-53. FLSEM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED SEM
R-0/W-0h R-0h R/W-0h

Table 5-60. FLSEM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 KEY R-0/W 0h Writing a value 0xA5 into this field will allow the writing of the SEM
bits, else writes are ignored. Reads will return 0.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1-0 SEM R/W 0h 00 : Flash Wrapper registers can be written by code running from
anywhere without any restriction.
01 : Flash Wrapper registers can be written by code running from
Zone1 security zone.
10 : Flash Wrapper registers can be written by code running from
Zone2 security zone
11 : Flash Wrapper registers can be written by code running from
anywhere without any restriction
Allowed State Transitions in this field.
00 TO 11 : Not allowed.
11 TO 00 : Not allowed.
00/11 TO 01 : Code running from Zone1 only can perform this
transition.
01 TO 00/11 : Code running from Zone1 only can perform this
transition.
00/11 TO 10 : Code running from Zone2 only can perform this
transition.
10 TO 00/11 : Code running from Zone2 can perform this transition
10 TO 01 : Not allowed.
01 TO 10 : Not allowed.
Reset type: SYSRSn

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5.9.4.2 SECTSTAT1 Register (Offset = 8h) [Reset = 00000000h]

SECTSTAT1 is shown in Figure 5-54 and described in Table 5-61.
Return to the Summary Table.
Flash Sectors Status Register 1
Figure 5-54. SECTSTAT1 Register
31 30 29 28 27 26 25 24
STATUS_B1_SECT127_96 STATUS_B1_SECT95_64 STATUS_B1_SECT63_32 STATUS_B1_SECT31_4
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_B1_SECT3 STATUS_B1_SECT2 STATUS_B1_SECT1 STATUS_B1_SECT0
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_B0_SECT127_96 STATUS_B0_SECT95_64 STATUS_B0_SECT63_32 STATUS_B0_SECT31_4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_B0_SECT3 STATUS_B0_SECT2 STATUS_B0_SECT1 STATUS_B0_SECT0
R-0h R-0h R-0h R-0h

Table 5-61. SECTSTAT1 Register Field Descriptions

Bit Field Type Reset Description
31-30 STATUS_B1_SECT127_9 R 0h Reflects the status of given flash sector.
6 00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
29-28 STATUS_B1_SECT95_64 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
27-26 STATUS_B1_SECT63_32 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_B1_SECT31_4 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-61. SECTSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
23-22 STATUS_B1_SECT3 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
21-20 STATUS_B1_SECT2 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_B1_SECT1 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_B1_SECT0 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_B0_SECT127_9 R 0h Reflects the status of given flash sector.
6 00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_B0_SECT95_64 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_B0_SECT63_32 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_B0_SECT31_4 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-61. SECTSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 STATUS_B0_SECT3 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_B0_SECT2 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_B0_SECT1 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_B0_SECT0 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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5.9.4.3 SECTSTAT2 Register (Offset = Ah) [Reset = 00000000h]

SECTSTAT2 is shown in Figure 5-55 and described in Table 5-62.
Return to the Summary Table.
Flash Sectors Status Register 2
Figure 5-55. SECTSTAT2 Register
31 30 29 28 27 26 25 24
STATUS_B3_SECT127_96 STATUS_B3_SECT95_64 STATUS_B3_SECT63_32 STATUS_B3_SECT31_4
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_B3_SECT3 STATUS_B3_SECT2 STATUS_B3_SECT1 STATUS_B3_SECT0
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_B2_SECT127_96 STATUS_B2_SECT95_64 STATUS_B2_SECT63_32 STATUS_B2_SECT31_4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_B2_SECT3 STATUS_B2_SECT2 STATUS_B2_SECT1 STATUS_B2_SECT0
R-0h R-0h R-0h R-0h

Table 5-62. SECTSTAT2 Register Field Descriptions

Bit Field Type Reset Description
31-30 STATUS_B3_SECT127_9 R 0h Reflects the status of given flash sector.
6 00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
29-28 STATUS_B3_SECT95_64 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
27-26 STATUS_B3_SECT63_32 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_B3_SECT31_4 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-62. SECTSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
23-22 STATUS_B3_SECT3 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
21-20 STATUS_B3_SECT2 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_B3_SECT1 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_B3_SECT0 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_B2_SECT127_9 R 0h Reflects the status of given flash sector.
6 00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_B2_SECT95_64 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_B2_SECT63_32 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_B2_SECT31_4 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-62. SECTSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 STATUS_B2_SECT3 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_B2_SECT2 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_B2_SECT1 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_B2_SECT0 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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5.9.4.4 SECTSTAT3 Register (Offset = Ch) [Reset = 00000000h]

SECTSTAT3 is shown in Figure 5-56 and described in Table 5-63.
Return to the Summary Table.
Flash Sectors Status Register 3
Figure 5-56. SECTSTAT3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED STATUS_B4_SECT31_4
R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_B4_SECT3 STATUS_B4_SECT2 STATUS_B4_SECT1 STATUS_B4_SECT0
R-0-0h R-0-0h R-0-0h R-0-0h

Table 5-63. SECTSTAT3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-10 RESERVED R 0h Reserved
9-8 STATUS_B4_SECT31_4 R 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_B4_SECT3 R-0 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_B4_SECT2 R-0 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_B4_SECT1 R-0 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-63. SECTSTAT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 STATUS_B4_SECT0 R-0 0h Reflects the status of given flash sector.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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5.9.4.5 RAMSTAT1 Register (Offset = 10h) [Reset = 00000000h]

RAMSTAT1 is shown in Figure 5-57 and described in Table 5-64.
Return to the Summary Table.
RAM Status Register 1
Figure 5-57. RAMSTAT1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED STATUS_RAM9 STATUS_RAM8
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_RAM3 STATUS_RAM2 STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h R-0h

Table 5-64. RAMSTAT1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 STATUS_RAM9 R 0h Reflects the status of LS9 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_RAM8 R 0h Reflects the status of LS8 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_RAM7 R 0h Reflects the status of LS7 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of LS6 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-64. RAMSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 STATUS_RAM5 R 0h Reflects the status of LS5 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_RAM4 R 0h Reflects the status of LS4 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_RAM3 R 0h Reflects the status of LS3 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_RAM2 R 0h Reflects the status of LS2 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_RAM1 R 0h Reflects the status of LS1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_RAM0 R 0h Reflects the status of LS0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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5.9.4.6 SECERRSTAT Register (Offset = 18h) [Reset = 00000000h]

SECERRSTAT is shown in Figure 5-58 and described in Table 5-65.
Return to the Summary Table.
Security Error Status Register
Figure 5-58. SECERRSTAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0-0h R-0h

Table 5-65. SECERRSTAT Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 ERR R 0h This bit indicates if any error has occurred in the load of any security
configuration from USER-OTP.
0: No error has occurred in the load of security information from
USER-OTP
1: Error has occurred in the load of security information from USER-
OTP
Reset type: PORESETn

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5.9.4.7 SECERRCLR Register (Offset = 1Ah) [Reset = 00000000h]

SECERRCLR is shown in Figure 5-59 and described in Table 5-66.
Return to the Summary Table.
Security Error Clear Register
Figure 5-59. SECERRCLR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0-0h R-0/
W1S-0
h

Table 5-66. SECERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 ERR R-0/W1S 0h A write of '1' clears the SECERRSTAT.ERR bit. Write of '0' is ignored.
This bit always reads back '0'.
Reset type: N/A

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5.9.4.8 SECERRFRC Register (Offset = 1Ch) [Reset = 00000000h]

SECERRFRC is shown in Figure 5-60 and described in Table 5-67.
Return to the Summary Table.
Security Error Force Register
Figure 5-60. SECERRFRC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0-0h R-0/
W1S-0
h

Table 5-67. SECERRFRC Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h In order to write to the ERR bits, 0x5a5a must be written to these
key bits at the same time. Otherwise, writes are ignored. The key
is cleared immediately after writing, so it must be written again for
every write to ERR. Reads will return 0.
Reset type: N/A
15-1 RESERVED R-0 0h Reserved
0 ERR R-0/W1S 0h A write of '1', along with the proper KEY, sets the SECERRSTAT.ERR
bit. Write of '0' is ignored. This bit always reads back '0'.
Reset type: N/A

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5.9.4.9 DENYCODE Register (Offset = 1Eh) [Reset = 00000000h]

DENYCODE is shown in Figure 5-61 and described in Table 5-68.
Return to the Summary Table.
Flash Authorization Denial Code
Figure 5-61. DENYCODE Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
ILLSIZE ILLCMD ILLMODECH ILLRDVER ILLERASE ILLPROG ILLADDR BLOCKED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-68. DENYCODE Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 ILLSIZE R 0h This bit indicates the DCSM stopped a Flash Controller operation
because an illegal command size was requested.
This bit is not sticky. It is updated each time a Flash Controller
operation is denied.
0 : Flash operation was not stopped due to an illegal command size
1 : Flash operation was stopped due to an illegal command size
Reset type: SYSRSn
6 ILLCMD R 0h This bit indicates the DCSM stopped a Flash Controller operation
because an illegal command type was requested.
This bit is not sticky. It is updated each time a Flash Controller
operation is denied.
0 : Flash operation was not stopped due to an illegal command type
1 : Flash operation was stopped due to an illegal command type
Reset type: SYSRSn
5 ILLMODECH R 0h This bit indicates the DCSM stopped a Flash Controller operation
because a mode change command tried to move it into a reserved
mode.
This bit is not sticky. It is updated each time a Flash Controller
operation is denied.
0 : Flash operation was not stopped due to an illegal mode change
1 : Flash operation was stopped due to an illegal mode change
Reset type: SYSRSn
4 ILLRDVER R 0h This bit indicates the DCSM stopped a Flash Controller operation
because a read verify command provided an illegal address.
This bit is not sticky. It is updated each time a Flash Controller
operation is denied.
0 : Flash operation was not stopped due to an illegal read verify
address
1 : Flash operation was stopped due to an illegal read verify address
Reset type: SYSRSn

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Table 5-68. DENYCODE Register Field Descriptions (continued)

Bit Field Type Reset Description
3 ILLERASE R 0h This bit indicates the DCSM stopped a Flash Controller operation
because an erase command provided an illegal address.
This bit is not sticky. It is updated each time a Flash Controller
operation is denied.
0 : Flash operation was not stopped due to an illegal erase address
1 : Flash operation was stopped due to an illegal erase address
Reset type: SYSRSn
2 ILLPROG R 0h This bit indicates the DCSM stopped a Flash Controller operation
because a programming command provided an illegal address.
This bit is not sticky. It is updated each time a Flash Controller
operation is denied.
0 : Flash operation was not stopped due to an illegal programming
address
1 : Flash operation was stopped due to an illegal programming
address
Reset type: SYSRSn
1 ILLADDR R 0h This bit indicates the DCSM stopped a Flash Controller operation
because the command provided contained a non-flash address.
This bit is not sticky. It is updated each time a Flash Controller
operation is denied.
0 : Flash operation was not stopped due to a non-flash address
1 : Flash operation was stopped due to a non-flash address
Reset type: SYSRSn
0 BLOCKED R 0h This bit indicates the DCSM stopped a Flash Controller operation
because the DCSM was in the BLOCKED state.
This bit is not sticky. It is updated each time a Flash Controller
operation is denied.
0 : Flash operation was not stopped due to the BLOCKED state
1 : Flash operation was stopped due to the BLOCKED state
Reset type: SYSRSn

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5.9.4.10 UID_UNIQUE_31_0 Register (Offset = 28h) [Reset = 00000000h]

UID_UNIQUE_31_0 is shown in Figure 5-62 and described in Table 5-69.
Return to the Summary Table.
Unique Identification Number Low
Figure 5-62. UID_UNIQUE_31_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UID_L
R/WOnce-0h

Table 5-69. UID_UNIQUE_31_0 Register Field Descriptions

Bit Field Type Reset Description
31-0 UID_L R/WOnce 0h This register contains a copy of the device UID_UNIQUE value bits
31 to 0.
Reset type: PORESETn

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5.9.4.11 UID_UNIQUE_63_32 Register (Offset = 2Ah) [Reset = 00000000h]

UID_UNIQUE_63_32 is shown in Figure 5-63 and described in Table 5-70.
Return to the Summary Table.
Unique Identification Number High
Figure 5-63. UID_UNIQUE_63_32 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UID_H
R/WOnce-0h

Table 5-70. UID_UNIQUE_63_32 Register Field Descriptions

Bit Field Type Reset Description
31-0 UID_H R/WOnce 0h This register contains a copy of the device UID_UNIQUE value bits
63 to 32.
Reset type: PORESETn

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5.9.4.12 PARTIDH Register (Offset = 2Ch) [Reset = 00000000h]

PARTIDH is shown in Figure 5-64 and described in Table 5-71.
Return to the Summary Table.
Part Identification High Register
Figure 5-64. PARTIDH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
R/WOnce-0h

Table 5-71. PARTIDH Register Field Descriptions

Bit Field Type Reset Description
31-0 ID R/WOnce 0h This register contains a copy of the device PARTIDH value.
Reset type: PORESETn

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5.9.4.13 PERSEM1 Register (Offset = 2Eh) [Reset = 00000000h]

PERSEM1 is shown in Figure 5-65 and described in Table 5-72.
Return to the Summary Table.
Peripheral Semaphore Register
Figure 5-65. PERSEM1 Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED GRABRSTCTL
R-0-0h R/W-0h

7 6 5 4 3 2 1 0
GRABCLKCTL GRABTIMER1 GRABNMIWD GRABWD
R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-72. PERSEM1 Register Field Descriptions

Bit Field Type Reset Description
31-24 KEY R-0/W 0h Writing a value 0xA5 into this field will allow the update to any bit
field, else writes are ignored. Reads will return 0.
Reset type: SYSRSn
23-16 RESERVED R-0 0h Reserved
15-10 RESERVED R-0 0h Reserved
9-8 GRABRSTCTL R/W 0h Grab Reset configuration.
Reset type: SYSRSn
7-6 GRABCLKCTL R/W 0h Grab Clock configuration.
Reset type: SYSRSn
5-4 GRABTIMER1 R/W 0h Grab TIMER1 module.
Reset type: SYSRSn
3-2 GRABNMIWD R/W 0h GRAB NMIWD module.
Reset type: SYSRSn

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Table 5-72. PERSEM1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GRABWD R/W 0h Grab Watchdog module
00 : Module configuration registers can be written by code running
from anywhere without any restriction.
01 : Module configuration registers can be written by code running
from Zone1 security zone.
10 : Module configuration registers can be written by code running
from Zone2 security zone
11 : Module configuration registers can be written by code running
from anywhere without any restriction
Allowed State Transitions in this field.
00 TO 11 : Not allowed.
11 TO 00 : Not allowed.
00/11 TO 01 : Code running from Zone1 only can perform this
transition.
01 TO 00/11 : Code running from Zone1 only can perform this
transition.
00/11 TO 10 : Code running from Zone2 only can perform this
transition.
10 TO 00/11 : Code running from Zone2 can perform this transition
10 TO 01 : Not allowed.
01 TO 10 : Not allowed.
Reset type: SYSRSn

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5.9.5 DCSM_Z1_OTP Registers

Table 5-73 lists the memory-mapped registers for the DCSM_Z1_OTP registers. All register offset addresses not
listed in Table 5-73 should be considered as reserved locations and the register contents should not be modified.
Table 5-73. DCSM_Z1_OTP Registers
Offset Acronym Register Name Write Protection Section
0h Z1OTP_LINKPOINTER1 Zone 1 Link Pointer1 Go
2h Z1OTP_LINKPOINTER2 Zone 1 Link Pointer2 Go
4h Z1OTP_LINKPOINTER3 Zone 1 Link Pointer3 Go
6h Z1OTP_JLM_ENABLE Zone 1 JTAGLOCK Enable Register Go
8h Z1OTP_GPREG1 Zone 1 General Purpose Register 1 Go
Ah Z1OTP_GPREG2 Zone 1 General Purpose Register 2 Go
Ch Z1OTP_GPREG3 Zone 1 General Purpose Register 3 Go
Eh Z1OTP_GPREG4 Zone 1 General Purpose Register 4 Go
10h Z1OTP_PSWDLOCK Secure Password Lock Go
12h Z1OTP_CRCLOCK Secure CRC Lock Go
14h Z1OTP_JTAGPSWDH0 JTAG Lock Permanent Password 0 Go
16h Z1OTP_JTAGPSWDH1 JTAG Lock Permanent Password 1 Go
18h Z1OTP_CMACKEY0 Secure Boot CMAC Key 0 Go
1Ah Z1OTP_CMACKEY1 Secure Boot CMAC Key 1 Go
1Ch Z1OTP_CMACKEY2 Secure Boot CMAC Key 2 Go
1Eh Z1OTP_CMACKEY3 Secure Boot CMAC Key 3 Go

Complex bit access types are encoded to fit into small table cells. Table 5-74 shows the codes that are used for
access types in this section.
Table 5-74. DCSM_Z1_OTP Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value

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5.9.5.1 Z1OTP_LINKPOINTER1 Register (Offset = 0h) [Reset = FFFFFFFFh]

Z1OTP_LINKPOINTER1 is shown in Figure 5-66 and described in Table 5-75.
Return to the Summary Table.
Zone 1 Link Pointer1
Figure 5-66. Z1OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER1
R-FFFFFFFFh

Table 5-75. Z1OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER1 R FFFFFFFFh Zone1 Link Pointer 1 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.5.2 Z1OTP_LINKPOINTER2 Register (Offset = 2h) [Reset = FFFFFFFFh]

Z1OTP_LINKPOINTER2 is shown in Figure 5-67 and described in Table 5-76.
Return to the Summary Table.
Zone 1 Link Pointer2
Figure 5-67. Z1OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER2
R-FFFFFFFFh

Table 5-76. Z1OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER2 R FFFFFFFFh Zone1 Link Pointer 2 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.5.3 Z1OTP_LINKPOINTER3 Register (Offset = 4h) [Reset = FFFFFFFFh]

Z1OTP_LINKPOINTER3 is shown in Figure 5-68 and described in Table 5-77.
Return to the Summary Table.
Zone 1 Link Pointer3
Figure 5-68. Z1OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER3
R-FFFFFFFFh

Table 5-77. Z1OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER3 R FFFFFFFFh Zone1 Link Pointer 3 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.5.4 Z1OTP_JLM_ENABLE Register (Offset = 6h) [Reset = FFFFFFFFh]

Z1OTP_JLM_ENABLE is shown in Figure 5-69 and described in Table 5-78.
Return to the Summary Table.
Zone 1 JTAGLOCK Enable Register
Figure 5-69. Z1OTP_JLM_ENABLE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_JLM_ENABLE
R-FFFFFFFFh

Table 5-78. Z1OTP_JLM_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_JLM_ENABLE R FFFFFFFFh Zone1 JLM_ENABLE register location in USER OTP.
Note: When this value is loaded into Z1_JLM_ENABLE, if the value
is 32-bit all-1s, the JTAGLOCK will be enabled. Before shipping parts
to customers, TI will program the default value to 0xFFFF_000F,
which will disable the JTAGLOCK feature. Users should program
0xFFFF_0000 to enable the JTAGLOCK feature.
Reset type: N/A

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5.9.5.5 Z1OTP_GPREG1 Register (Offset = 8h) [Reset = FFFFFFFFh]

Z1OTP_GPREG1 is shown in Figure 5-70 and described in Table 5-79.
Return to the Summary Table.
Zone 1 General Purpose Register 1
Figure 5-70. Z1OTP_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG1
R-FFFFFFFFh

Table 5-79. Z1OTP_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG1 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.5.6 Z1OTP_GPREG2 Register (Offset = Ah) [Reset = FFFFFFFFh]

Z1OTP_GPREG2 is shown in Figure 5-71 and described in Table 5-80.
Return to the Summary Table.
Zone 1 General Purpose Register 2
Figure 5-71. Z1OTP_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG2
R-FFFFFFFFh

Table 5-80. Z1OTP_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG2 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.5.7 Z1OTP_GPREG3 Register (Offset = Ch) [Reset = FFFFFFFFh]

Z1OTP_GPREG3 is shown in Figure 5-72 and described in Table 5-81.
Return to the Summary Table.
Zone 1 General Purpose Register 3
Figure 5-72. Z1OTP_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG3
R-FFFFFFFFh

Table 5-81. Z1OTP_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG3 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.5.8 Z1OTP_GPREG4 Register (Offset = Eh) [Reset = FFFFFFFFh]

Z1OTP_GPREG4 is shown in Figure 5-73 and described in Table 5-82.
Return to the Summary Table.
Zone 1 General Purpose Register 4
Figure 5-73. Z1OTP_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG4
R-FFFFFFFFh

Table 5-82. Z1OTP_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG4 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.5.9 Z1OTP_PSWDLOCK Register (Offset = 10h) [Reset = FFFFFFFFh]

Z1OTP_PSWDLOCK is shown in Figure 5-74 and described in Table 5-83.
Return to the Summary Table.
Secure Password Lock
Figure 5-74. Z1OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_PSWDLOCK
R-FFFFFFFFh

Table 5-83. Z1OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_PSWDLOCK R FFFFFFFFh Zone1 password lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-
bit all-1s, CSMPSWD will remain locked. Before shipping parts to
customers, TI would change the value of this location in such a way
that the ECC field remains all-1s and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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5.9.5.10 Z1OTP_CRCLOCK Register (Offset = 12h) [Reset = FFFFFFFFh]

Z1OTP_CRCLOCK is shown in Figure 5-75 and described in Table 5-84.
Return to the Summary Table.
Secure CRC Lock
Figure 5-75. Z1OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_CRCLOCK
R-FFFFFFFFh

Table 5-84. Z1OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_CRCLOCK R FFFFFFFFh Zone1 CRC lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit
all-1s, VCU will not have ability to calculate CRC on secured memory
content.. Before shipping parts to customers, TI would change the
value of this location in such a way that the ECC field remains all-1s
and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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5.9.5.11 Z1OTP_JTAGPSWDH0 Register (Offset = 14h) [Reset = FFFFFFFFh]

Z1OTP_JTAGPSWDH0 is shown in Figure 5-76 and described in Table 5-85.
Return to the Summary Table.
JTAG Lock Permanent Password 0
Figure 5-76. Z1OTP_JTAGPSWDH0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAGPSWDH0
R-FFFFFFFFh

Table 5-85. Z1OTP_JTAGPSWDH0 Register Field Descriptions

Bit Field Type Reset Description
31-0 JTAGPSWDH0 R FFFFFFFFh JTAG Lock Password High 0 (bits 95:64) location in USER Z1 OTP.
This value is dummy loaded into the non-memory-mapped
JTAGPSWD register, bits 95:64.
TI must program a default value into this location, leaving the ECC
bits all 1's.
Reset type: N/A

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5.9.5.12 Z1OTP_JTAGPSWDH1 Register (Offset = 16h) [Reset = FFFFFFFFh]

Z1OTP_JTAGPSWDH1 is shown in Figure 5-77 and described in Table 5-86.
Return to the Summary Table.
JTAG Lock Permanent Password 1
Figure 5-77. Z1OTP_JTAGPSWDH1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAGPSWDH1
R-FFFFFFFFh

Table 5-86. Z1OTP_JTAGPSWDH1 Register Field Descriptions

Bit Field Type Reset Description
31-0 JTAGPSWDH1 R FFFFFFFFh JTAG Lock Password High 1 (bits 127:96) location in USER Z1 OTP.
This value is dummy loaded into the non-memory-mapped
JTAGPSWD register, bits 127:96.
Reset type: N/A

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5.9.5.13 Z1OTP_CMACKEY0 Register (Offset = 18h) [Reset = FFFFFFFFh]

Z1OTP_CMACKEY0 is shown in Figure 5-78 and described in Table 5-87.
Return to the Summary Table.
Secure Boot CMAC Key 0
Figure 5-78. Z1OTP_CMACKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY0
R-FFFFFFFFh

Table 5-87. Z1OTP_CMACKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY0 R FFFFFFFFh Secure Boot CMAC Key 0 (bits 31:0) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY0 register.
Reset type: N/A

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5.9.5.14 Z1OTP_CMACKEY1 Register (Offset = 1Ah) [Reset = FFFFFFFFh]

Z1OTP_CMACKEY1 is shown in Figure 5-79 and described in Table 5-88.
Return to the Summary Table.
Secure Boot CMAC Key 1
Figure 5-79. Z1OTP_CMACKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY1
R-FFFFFFFFh

Table 5-88. Z1OTP_CMACKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY1 R FFFFFFFFh Secure Boot CMAC Key 1 (bits 63:32) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY1 register.
Reset type: N/A

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5.9.5.15 Z1OTP_CMACKEY2 Register (Offset = 1Ch) [Reset = FFFFFFFFh]

Z1OTP_CMACKEY2 is shown in Figure 5-80 and described in Table 5-89.
Return to the Summary Table.
Secure Boot CMAC Key 2
Figure 5-80. Z1OTP_CMACKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY2
R-FFFFFFFFh

Table 5-89. Z1OTP_CMACKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY2 R FFFFFFFFh Secure Boot CMAC Key 2 (bits 95:64) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY2 register.
Reset type: N/A

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5.9.5.16 Z1OTP_CMACKEY3 Register (Offset = 1Eh) [Reset = FFFFFFFFh]

Z1OTP_CMACKEY3 is shown in Figure 5-81 and described in Table 5-90.
Return to the Summary Table.
Secure Boot CMAC Key 3
Figure 5-81. Z1OTP_CMACKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY3
R-FFFFFFFFh

Table 5-90. Z1OTP_CMACKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY3 R FFFFFFFFh Secure Boot CMAC Key 3 (bits 127:96) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY3 register.
Reset type: N/A

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5.9.6 DCSM_Z2_OTP Registers

Table 5-91 lists the memory-mapped registers for the DCSM_Z2_OTP registers. All register offset addresses not
listed in Table 5-91 should be considered as reserved locations and the register contents should not be modified.
Table 5-91. DCSM_Z2_OTP Registers
Offset Acronym Register Name Write Protection Section
0h Z2OTP_LINKPOINTER1 Zone 2 Link Pointer1 Go
2h Z2OTP_LINKPOINTER2 Zone 2 Link Pointer2 Go
4h Z2OTP_LINKPOINTER3 Zone 2 Link Pointer3 Go
8h Z2OTP_GPREG1 Zone 2 General Purpose Register 1 Go
Ah Z2OTP_GPREG2 Zone 2 General Purpose Register 2 Go
Ch Z2OTP_GPREG3 Zone 2 General Purpose Register 3 Go
Eh Z2OTP_GPREG4 Zone 2 General Purpose Register 4 Go
10h Z2OTP_PSWDLOCK Secure Password Lock Go
12h Z2OTP_CRCLOCK Secure CRC Lock Go

Complex bit access types are encoded to fit into small table cells. Table 5-92 shows the codes that are used for
access types in this section.
Table 5-92. DCSM_Z2_OTP Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value

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5.9.6.1 Z2OTP_LINKPOINTER1 Register (Offset = 0h) [Reset = FFFFFFFFh]

Z2OTP_LINKPOINTER1 is shown in Figure 5-82 and described in Table 5-93.
Return to the Summary Table.
Zone 2 Link Pointer1
Figure 5-82. Z2OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER1
R-FFFFFFFFh

Table 5-93. Z2OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER1 R FFFFFFFFh Zone2 Link Pointer 1 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.6.2 Z2OTP_LINKPOINTER2 Register (Offset = 2h) [Reset = FFFFFFFFh]

Z2OTP_LINKPOINTER2 is shown in Figure 5-83 and described in Table 5-94.
Return to the Summary Table.
Zone 2 Link Pointer2
Figure 5-83. Z2OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER2
R-FFFFFFFFh

Table 5-94. Z2OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER2 R FFFFFFFFh Zone2 Link Pointer 2 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.6.3 Z2OTP_LINKPOINTER3 Register (Offset = 4h) [Reset = FFFFFFFFh]

Z2OTP_LINKPOINTER3 is shown in Figure 5-84 and described in Table 5-95.
Return to the Summary Table.
Zone 2 Link Pointer3
Figure 5-84. Z2OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER3
R-FFFFFFFFh

Table 5-95. Z2OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER3 R FFFFFFFFh Zone2 Link Pointer 3 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.6.4 Z2OTP_GPREG1 Register (Offset = 8h) [Reset = FFFFFFFFh]

Z2OTP_GPREG1 is shown in Figure 5-85 and described in Table 5-96.
Return to the Summary Table.
Zone 2 General Purpose Register 1
Figure 5-85. Z2OTP_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG1
R-FFFFFFFFh

Table 5-96. Z2OTP_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG1 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.6.5 Z2OTP_GPREG2 Register (Offset = Ah) [Reset = FFFFFFFFh]

Z2OTP_GPREG2 is shown in Figure 5-86 and described in Table 5-97.
Return to the Summary Table.
Zone 2 General Purpose Register 2
Figure 5-86. Z2OTP_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG2
R-FFFFFFFFh

Table 5-97. Z2OTP_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG2 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.6.6 Z2OTP_GPREG3 Register (Offset = Ch) [Reset = FFFFFFFFh]

Z2OTP_GPREG3 is shown in Figure 5-87 and described in Table 5-98.
Return to the Summary Table.
Zone 2 General Purpose Register 3
Figure 5-87. Z2OTP_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG3
R-FFFFFFFFh

Table 5-98. Z2OTP_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG3 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.6.7 Z2OTP_GPREG4 Register (Offset = Eh) [Reset = FFFFFFFFh]

Z2OTP_GPREG4 is shown in Figure 5-88 and described in Table 5-99.
Return to the Summary Table.
Zone 2 General Purpose Register 4
Figure 5-88. Z2OTP_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG4
R-FFFFFFFFh

Table 5-99. Z2OTP_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG4 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.6.8 Z2OTP_PSWDLOCK Register (Offset = 10h) [Reset = FFFFFFFFh]

Z2OTP_PSWDLOCK is shown in Figure 5-89 and described in Table 5-100.
Return to the Summary Table.
Secure Password Lock
Figure 5-89. Z2OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_PSWDLOCK
R-FFFFFFFFh

Table 5-100. Z2OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_PSWDLOCK R FFFFFFFFh Zone2 password lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-
bit all-1s, CSMPSWD will remain locked. Before shipping parts to
customers, TI would change the value of this location in such a way
that the ECC field remains all-1s and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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5.9.6.9 Z2OTP_CRCLOCK Register (Offset = 12h) [Reset = FFFFFFFFh]

Z2OTP_CRCLOCK is shown in Figure 5-90 and described in Table 5-101.
Return to the Summary Table.
Secure CRC Lock
Figure 5-90. Z2OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_CRCLOCK
R-FFFFFFFFh

Table 5-101. Z2OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_CRCLOCK R FFFFFFFFh Zone2 CRC lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit
all-1s, VCU will not have ability to calculate CRC on secured memory
content.. Before shipping parts to customers, TI would change the
value of this location in such a way that the ECC field remains all-1s
and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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Chapter 6
Flash Module

This chapter describes the Flash module.

6.1 Introduction to Flash and OTP Memory................................................................................................................. 808

6.2 Flash Bank, OTP, and Pump.................................................................................................................................... 809
6.3 Flash Wrapper ..........................................................................................................................................................810
6.4 Flash and OTP Memory Performance..................................................................................................................... 811
6.5 Flash Read Interface.................................................................................................................................................811
6.6 Flash Erase and Program........................................................................................................................................ 814
6.7 Error Correction Code (ECC) Protection................................................................................................................815
6.8 Reserved Locations Within Flash and OTP........................................................................................................... 819
6.9 Migrating an Application from RAM to Flash.........................................................................................................819
6.10 Procedure to Change the Flash Control Registers............................................................................................. 820
6.11 Software...................................................................................................................................................................820
6.12 FLASH Registers.................................................................................................................................................... 821

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6.1 Introduction to Flash and OTP Memory

Flash is an electrically erasable/programmable nonvolatile memory that can be programmed and erased many
times to ease code development. Flash memory can be used primarily as a program memory for the core, and
secondarily as static data memory.
This section describes the proper sequence to configure the wait states and operating mode of Flash. This
section also includes information on Flash and OTP power modes, how to improve Flash performance by
enabling the Flash prefetch/cache mode, and the SECDED safety feature.
6.1.1 FLASH Related Collateral

Foundational Materials
• C2000 Academy - FLASH
• Embedded Flash Memory (Video)

Getting Started Materials

• Serial Flash Programming of C2000 Microcontrollers Application Report
• [FAQ] FAQ for Flash ECC usage in C2000 devices - Includes ECC test mode, Linker ECC options:
• [FAQ] FAQ on Flash API usage for C2000 devices
• [FAQ] Flash - How to modify an application from RAM configuration to Flash configuration?
• [FAQ] How can we improve the Flash tool performance?
• [FAQ] TI C2000 Device Programming Tools and Services
6.1.2 Features
Features of Flash memory include:
• Up to five Flash banks (refer to device data sheet for the number and size of Flash banks);
• One Flash Wrapper controlling up to five Flash banks (Bank0, 1, 2, 3, 4);
• Program or erase one Flash bank while simultaneously reading another Flash bank;
• 128-bit wide Flash programming;
• Configurable Flash programming options, with ECC support;
• Multiple sectors, with the ability to erase individual/specific sectors while leaving others programmed;
• User-programmable locations in user-configurable DCSM OTP (also referred to as USER OTP), for
configuring security, OTP boot mode and boot mode selection pins (if the user is unable to use factory-default
boot mode select pins);
• Code prefetch mechanism and data cache for enhanced performance;
• Configurable wait states to achieve the best performance at a given clock frequency;
• Safety Features:
– SECDED: Single-error correction and double-error detection is supported;
– Address bits are included in ECC;
– Test mode to check the health of ECC logic;
• Integrated Flash program and erase state machine in the Flash Wrapper:
– Simple Flash API algorithms;
– Fast erase and program times (refer to the device data sheet for details);

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6.1.3 Flash Tools

Texas Instruments provides the following tools for Flash:
• Code Composer Studio™ (CCS) IDE - the development environment with integrated Flash plugin. TI
recommends performing a debug reset and restart after programming the code into Flash using CCS.
• Flash API Library - a set of software peripheral functions to erase/program Flash
• UniFlash - standalone tool to erase/program/verify the Flash content through JTAG. No CCS is required.
• Users must check and install available updates for CCS On-Chip Flash Plugin and UniFlash tools.

6.1.4 Default Flash Configuration

The following are Flash module configuration settings at power-up:
• Flash Bank and Pump are powered up on device reset.
• ECC is enabled
• Wait-states are set to the maximum (0xF)
• Code-prefetch mechanism and data cache are disabled
During the boot process, the boot ROM performs a dummy read of the Code Security Module (CSM) password
locations in the OTP. This read is performed to unlock a new device that has no password stored in the device,
so that Flash programming or loading of code into CSM-protected SRAM can be performed. On devices with a
password, this read has no effect and the device remains locked.
User application software must initialize wait-states using the FRDCNTL register, and configure cache/prefetch
features using the FRD_INTF_CTRL register, to achieve optimum system performance. Software that configures
Flash settings like wait-states, cache/prefetch features, and so on, must be executed only from RAM memory,
not from Flash memory.

Note
Before initializing wait-states, turn off the pre-fetch and data caching in the FRD_INTF_CTRL register.

6.2 Flash Bank, OTP, and Pump

This device includes up to five Flash banks. In addition, there is one-time programmable Flash memory (OTP) in
each Flash bank. Flash and OTP are uniformly mapped in both program and data memory space.
There are two OTP regions. The first OTP region, TI-OTP, contains manufacturing information, trims, Flash
operation settings, and other device data. TI-OTP can be read by the user application, but TI-OTP cannot be
programmed or erased. The second OTP region, USER-OTP, is primarily used for programming device security
(DCSM module) settings. USER-OTP can be programmed only once and cannot be erased afterwards. For
information on the memory-map, Flash bank sizes, TI-OTP, USER-OTP, and corresponding ECC locations, refer
to the device data sheet.
The Location of Zone-Select Block Based on Link-Pointer figure in the Dual Code Security Module (DCSM)
chapter shows the user-programmable OTP locations in CPU1 USER-OTP. For more information on the
functionality of these fields, refer to the ROM Code and Peripheral Booting chapter and the Dual Code Security
Module (DCSM) chapter.

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6.3 Flash Wrapper

The CPU interfaces with the Flash wrapper, which interfaces with the Flash banks and the pump (see Figure
6-1). The Flash wrapper has the following primary features:
• Provides a simple interface for software to program or erase the Flash memory.
• Provides an interface for the CPU to read Flash data, including data caching and prefetch features.
• Performs ECC error checking and correction, and generates interrupts when an error is detected.
• Provides the capability to prevent unwanted bank program or erase operations.

Flash Wrapper

Bank0
256 KB
128 * 2KB
sectors

Bank1
256 KB
128 * 2KB
sectors

C28x Data Read Bus

C28x CPU Flash Bank2

256 KB
CPU
C28x Program Read/ Read Interface 128 * 2KB
Fetch Bus sectors

ePIE/NMI
Bank3
256 KB
128 * 2KB
sectors

Bank4
64 KB
32 * 2KB
sectors

Flash Pump

Figure 6-1. Flash Interface Block Diagram

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6.4 Flash and OTP Memory Performance

Flash read or instruction fetch accesses can be classified either as a Flash access (access to an address
location in Flash), or an OTP access (access to an address location in OTP).
When the CPU performs an access to a Flash memory address, data is returned after (RWAIT+1) SYSCLK
cycles.
For a USER-OTP access, data is returned after 11 SYSCLK cycles.
RWAIT defines the number of random access wait states, and is configured using the RWAIT field in the
FRDCNTL register. At reset, RWAIT defaults to a worst-case wait state count (15), and therefore must be
initialized to the appropriate number of wait states to improve performance, based on the CPU clock frequency
and the access time of the Flash. The Flash supports zero-wait accesses when RWAIT is set to zero, when the
CPU clock frequency is low enough to accommodate the Flash access time.
For a given system clock frequency, configure RWAIT using the following formula:
For C28x Flash Bank: RWAIT = ceiling[(SYSCLK/FCLK)-1]
where SYSCLK is the system operating frequency for CPU1, and FCLK is the clock frequency for Flash.
FCLK must be ≤ FCLKmax, the allowed maximum Flash clock frequency at RWAIT = 0.
If RWAIT results in a fractional value when calculated using the above formula, round up RWAIT to the nearest
integer.

Note
When programming the FRDCNTL register, be sure to avoid writing values to bits other than the
RWAIT field as described in the register description. Overwriting reserved register fields can result in
errors or unpredictable behavior.

6.5 Flash Read Interface

This section provides details about the data read modes to access Flash bank/OTP and the configuration
registers that control the read interface. In addition to a standard read mode, the Flash wrapper has a built-in
prefetch and cache mechanism to allow increased clock speeds and CPU throughput wherever applicable.
6.5.1 C28x-Flash Read Interface
6.5.1.1 Standard Read Mode
Standard read mode is the default Flash read mode after reset. In this mode, the code prefetch mechanism and
data cache are disabled. When standard read mode is active, every read access to Flash is decoded by the
Flash wrapper to fetch the data from the addressed location, and the data is returned after RWAIT+1 cycles
(except User OTP).
Flash data buffers associated with the prefetch mechanism and data cache are bypassed in standard read
mode; therefore, every access to the Flash/OTP is used by the CPU immediately, and every access creates a
unique Flash bank access.
Standard read mode is the recommended mode for lower system frequency operation, where RWAIT can be
set to zero to provide single-cycle access operation. The Flash wrapper can operate at higher frequencies using
standard read mode, at the expense of adding wait states. At higher system frequencies, it is recommended
to enable the data cache and prefetch mechanisms to improve performance. Refer to the device data sheet
to determine the maximum Flash frequency allowed in standard read mode (that is, maximum Flash clock
frequency with RWAIT = 0, FCLKMAX).

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6.5.1.2 Prefetch Mode

Flash memory is typically used to store application code. During code execution, instructions are fetched from
contiguous memory addresses, except when a discontinuity occurs. Usually, the portion of the code that resides
in contiguous address locations makes up the majority of the application code, and is referred to as linear code.
To improve the performance of linear code execution, a Flash prefetch mechanism has been implemented.
Figure 6-2 illustrates how this mode functions.
The prefetch mechanism does a look-ahead prefetch on linear address increments, starting from the address of
the last instruction fetch. The Flash prefetch mechanism is disabled by default. To enable prefetch mode, set the
PREFETCH_EN bit in the FRD_INTF_CTRL register, or call the Flash_enablePrefetch() driverlib function.
Each instruction fetch from the Flash or OTP reads out 128 bits. The starting address of the access from Flash is
automatically aligned to a 128-bit boundary, such that the instruction location is within the 128 bits to be fetched.
When Flash prefetch mode is enabled, the 128 bits read from the instruction fetch are stored in a 128-bit wide
by 2-level deep instruction prefetch buffer. The contents of this prefetch buffer are then sent to the CPU for
processing as required.
Up to four 32-bit or eight 16-bit instructions can reside within a single 128-bit access. The majority of C28x
instructions are 16 bits, so for every 128-bit instruction fetch from the Flash bank there are up to eight
instructions in the prefetch buffer ready to process through the CPU. During the time to process these
instructions, the Flash prefetch mechanism automatically initiates another access to the Flash bank to prefetch
the next 128 bits. The Flash prefetch mechanism works in the background to keep the instruction prefetch
buffers as full as possible. Using this technique, the overall efficiency of sequential code execution from Flash or
OTP is improved significantly.
Flash and OTP
16-bit

Flash prefetch
Instruction buffer

Flash or OTP Read (128-bit)

128-bit 128-bit
buffer buffer

Instruction fetch

128-bit
M Data cache
CPU 32-bit U
X

Data read from data memory

Figure 6-2. Flash Prefetch Mode

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The Flash prefetch is aborted only when there is a code discontinuity caused by executing an instruction such
as a branch, function call, or loop. When this occurs, the prefetch mechanism is aborted, and the contents of the
prefetch buffer are flushed. There are two possible scenarios when this occurs:
1. If the destination address is within the Flash or OTP, the prefetch aborts and then resumes at the destination
address.
2. If the destination address is outside of the Flash and OTP, the prefetch is aborted, and begins again
only when the code branches back into the Flash or OTP. The Flash prefetch mechanism only applies to
instruction fetches from program space. Data reads from data memory and from program memory do not
utilize the prefetch mechanism and thus bypass the prefetch buffer. For example, instructions such as MAC,
DMAC, and PREAD read a data value from program memory. When such a read happens, the prefetch
buffer is bypassed, but the buffer is not flushed. If an instruction prefetch is already in progress when a data
read operation is initiated, then the data read is stalled until the prefetch completes.
Note that the prefetch mechanism gets bypassed when RWAIT is configured as zero.
6.5.1.3 Data Cache
In addition to the prefetch mechanism, a data cache of 128-bits wide has been implemented to improve data
space read performance. This data cache is separate from the instruction prefetch buffer, and is used for data
reads only. Whenever a data read access is performed by the CPU to a Flash bank address, if the data located
at that address is not presently loaded into the data cache, then the Flash wrapper reads 128 bits of data from
the Flash bank and stores the data in the data cache. This data is eventually sent to the CPU for processing.
The starting address of the Flash bank access is automatically aligned to a 128-bit boundary, such that the
requested address location is within the 128 bits to be read from the bank.
The data cache is disabled by default at reset. To enable the data cache, set the DATA_CACHE_EN bit in the
FRD_INTF_CTRL register, or call the Flash_enableCache() driverlib function. Note that the data cache gets
bypassed when RWAIT is set to zero.

Note
The data cache does not get updated on a debugger access, or when a read to the ECC memory-
mapped region is performed.

6.5.1.4 Flash Read Operation

There are a few important points to keep in mind when using Flash or OTP memory:
• Reads of USER OTP locations are hardwired for 9 wait states. The RWAIT bits have no effect on these
locations.
• CPU writes to Flash or OTP memory addresses are ignored, and complete within a single cycle. Flash
memory can only be modified by issuing program or erase commands, using the Flash API.
• When a security zone is in the locked state, and the respective password lock bits are not all ones, then:
– Data reads to Zx-CSMPSWD return zero;
– Program space reads to Zx-CSMPSWD return zero; and
– Program fetches to Zx-CSMPSWD return zero.
• When the Code Security Module (CSM) is secured, reads to Flash or OTP memory addresses from outside
the secure zone take the same number of cycles as a normal access. However, the read operation returns
zero.
• The arbitration scheme in the Flash wrapper prioritizes CPU accesses in the fixed priority order of data space
read (highest priority), program space read, and program fetches/program prefetches (lowest priority).
• When Flash state machine is activated for erase or program operations, the contents of the prefetch buffer
and data cache are automatically flushed.

Note
ECC checks are performed on data read from Flash before the data is stored in the prefetch buffer or
data cache. Once data has entered the cache or buffer, there are no further ECC checks performed.

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6.6 Flash Erase and Program

Flash memory can be programmed either by using the CCS Flash plug-in or by using the UniFlash application.
If these methods are not feasible in an application, the Flash API can be used. The Flash memory can be
programmed, erased, and verified only by using the Flash API library. These functions are written, compiled and
validated by Texas Instruments. The Flash module contains a Flash state machine (FSM) to perform program
and erase operations.
The recommended flow for programming Flash is:
Erase → Program → Verify

6.6.1 Erase
When the target Flash is erased, the Flash reads as all 1s. This state is called 'blank.' The erase function must
be executed before programming. The user cannot skip erase on sectors that read as 'blank' because these
sectors can require additional erasing due to marginally erased bits columns. The FSM provides an Erase Sector
command to erase the target sector. The erase function erases the data and the ECC together. Bank erase is
also supported in this device.
6.6.2 Program
The Flash wrapper provides a command to program the Flash and User OTP. This command is also used to
program ECC check bits.

Note
The main array Flash programming must be aligned to 64-bit address boundaries, and each 64-bit
word can only be programmed once per write/erase cycle.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-bit word
can only be programmed once. The exceptions are:
• The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP can be
programmed together and can be programmed one bit at a time as required by the DCSM
operation.
• The DCSM Zx-LINKPOINTER3 values in the DCSM OTP can be programmed one bit at a time as
required by the DCSM operation.

To avoid exceeding data retention capability limits, do not perform more than 4 program operations
on the same Flash word line before performing an erase operation. Each Flash word line consists
of sixteen 128-bit words (256 bytes). This limit is especially important to observe when writing to
one-time-programmable/non-erasable Flash regions, such as the User OTP.

6.6.3 Verify
After programming, the user must perform verify using API function Fapi_doVerify(). This function verifies the
Flash contents against supplied data.
Application software typically perform a CRC check of the Flash memory contents during power-up and at
regular intervals during runtime (as needed). Apart from this, ECC logic, when enabled (enabled by default),
catches single-bit errors, double-bit errors, and address errors whenever the CPU reads/fetches from a Flash
address.

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6.7 Error Correction Code (ECC) Protection

There are two ECC blocks (ECC64_H and ECC64_L) inside the Flash Read Interface. These ECC blocks
correct single-bit Flash read errors, and can detect uncorrectable errors of two or more bits. The ECC blocks are
also capable of detecting address errors. The ECC blocks operate using eight user-calculated ECC check bits
associated with each 64-bit wide data word and the corresponding 128-bit memory-aligned address. Users must
program these ECC check bits into ECC memory space, along with Flash data during the Flash programming
operation. Refer to the device data sheet for the Flash/OTP ECC memory-map.
The ECC bits for a given Flash address and 64-bit data word can be calculated using the Flash API; however,
TI recommends using the AutoEccGeneration option available in the Flash Plugin or API to auto-calculated and
program ECC bits. The Flash API uses hardware ECC logic in the device to generate the ECC data for the given
Flash data. The Flash Plugin, the Flash programming tool integrated with the Code Composer Studio™ IDE,
uses the Flash API to generate and program ECC data.
Figure 6-3 illustrates the ECC logic inputs and outputs.
During an instruction fetch or a data read operation, the 19 most-significant address bits (the three least-
significant bits of address are not considered), together with the 64-bit data/8-bit ECC read-out of Flash
banks/ECC memory-map area, pass through the ECC logic, and the eight check bits are produced in ECC
block. These eight calculated ECC check bits are then XORed with the stored check bits (user programmed
check bits) associated with the address and the read data. The 8-bit output is decoded inside the ECC block to
determine one of three conditions:
• No error occurred
• A correctable error (single bit data error) occurred
• A non-correctable error (double bit data error or address error) occurred
Flash Read
Interface
FAIL_1_H

Data[127:64] FAIL_0_H

ERR_TYPE_H
ECC_H[7:0]
SINGLE_ERR_H
ECC64_H UNC_ERR_H MEMCONFIG
(Error Logger)
AIN[15:0] ERR_POS_H[5:0]

ECC Enable C_Data[127:64] ERRINT

FLCERRSTATUS
ECC_ENABLE.ENABLE
FLUCERRSTATUS

UCERRFLG

ECC Enable UCCPUREADDR

Prefetch buffers, data
C_Data[63:0] CCPUREADDR
cache etc
CERRINT ERRNMI
Data[63:0]
FAIL_1_L CERRTHRES

CERRFLG
ECC_L[7:0] FAIL_0_L

ECC64_L ERR_TYPE_L

AIN[15:0] SINGLE_ERR_H
UNC_ERR_H

ERR_POS_H[5:0]

Figure 6-3. ECC Logic Inputs and Outputs

A single-bit error in the address field is considered to be a non-correctable error.

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Note
Since ECC is calculated for an entire 64-bit data word, a non 64-bit read such as a byte read or a
half-word read still forces the entire 64-bit data word to be read and calculated, even though only the
byte or half-word is actually used by the CPU.

The ECC feature is enabled by default at reset, and can be enabled or disabled by writing to the ECC_ENABLE
register. ECC logic is automatically bypassed when the 64 data bits and associated ECC bits fetched from the
bank are either all ones or all zeros.
6.7.1 Single-Bit Data Error
This section provides information for both single-bit data errors and single-bit ECC check bit errors. If there is a
single bit flip (0 to 1 or 1 to 0) in Flash data or in ECC data, then the error is considered as a single-bit data error.
The SECDED module detects and corrects single-bit errors, if any, in the 64-bit Flash data or eight ECC check
bits read from the Flash/ECC memory map before the read data is provided to the CPU.
When SECDED finds and corrects single bit data errors, the following information is logged in the ECC registers
if the ECC feature is enabled:
• Address where the error occurred: if the single-bit error occurs in the lower 64 bits of a 128-bit memory-
aligned Flash data word, the address of the lower 64-bit word is captured in the SINGLE_ERR_ADDR_LOW
register. If the single-bit error occurs in the upper 64 bits of the 128-bit data word, then the address of the
upper 64-bit word is captured in the SINGLE_ERR_ADDR_HIGH register.
• Whether the error occurred in data bits or ECC bits: the ERR_TYPE_L and ERR_TYPE_H bit fields in the
ERR_POS register indicate whether the error occurred in data bits or ECC bits of the lower 64 bits, or the
upper 64 bits respectively, of a 128-bit memory-aligned Flash data word.
• Bit position at which the error occurred: the ERR_POS_L and ERR_POS_H bit fields in the ERR_POS
register indicate the bit position of the error in the lower 64 bits/lower 8-bit ECC, or the upper 64 bits/upper
8-bit ECC respectively, of a 128-bit memory-aligned Flash data word.
• Whether the corrected value is 0 (FAIL_0_L, FAIL_0_H flags in ERR_STATUS register).
• Whether the corrected value is 1 (FAIL_1_L, FAIL_1_H flags in ERR_STATUS register).
• A single bit error counter that increments on every single bit error occurrence (ERR_CNT register) until a
user-configurable threshold (see ERR_THRESHOLD) is met.
• A flag that gets set when one or more single-bit errors occurs after ERR_CNT equals ERR_THRESHOLD
(SINGLE_ERR_INT_FLG flag in the ERR_INTFLG register).
When the ERR_CNT value equals ERR_THRESHOLD+1, and a single bit error occurs, the Flash module sets
the SINGLE_ERR_INT flag and generates an interrupt signal. To enable propagation of the generated interrupt
pulse to the CPU, the user application must enable the FLASH_CORRECTABLE_ERROR channel in the C28
Peripheral Interrupt Expansion module (PIE). The interrupt signal remains high until the application clears the
SINGLE_ERR_INTFLG flag by writing to the SINGLE_ERR_INTCLR bit in the ERR_INTCLR register. The Flash
module cannot generate any further FLASH_CORRECTABLE_ERROR interrupt signals to the PIE/CPU until
SINGLE_ERR_INTFLG is cleared, as this is an edge-based interrupt.
When multiple single-bit errors have been detected by ECC logic, the contents of the Flash ECC registers reflect
the most recent ECC error. When multiple single-bit errors have been detected, both FAIL_0_L and FAIL_1_L
(or FAIL_0_H and FAIL_1_H) can be set, indicating that single-bit fail0/fail1 occurred in different 64-bit aligned
addresses.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash data
word causes the single-bit error flag to get set, if there is a single-bit error in both or in either the lower 64 or
upper 64 bits (or corresponding ECC check bits) of that 128-bit data word.

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6.7.2 Uncorrectable Error

Uncorrectable errors include address errors and double-bit errors in data or ECC. When the ECC logic finds
uncorrectable errors, the following information is logged in ECC registers if the ECC feature is enabled:
• Address where the error occurred: if the uncorrectable error occurs in the lower 64 bits of a 128-
bit memory-aligned Flash data word, the lower 64-bit memory-aligned address is captured in the
UNC_ERR_ADDR_LOW register. If the uncorrectable error occurs in the upper 64 bits of a 128-
bit memory-aligned Flash data word, the upper 64-bit memory-aligned address is captured in the
UNC_ERR_ADDR_HIGH register.
• A flag is set indicating that an uncorrectable error occurred – the UNC_ERR_L and UNC_ERR_H flags in the
ERR_STATUS register indicate the uncorrectable error occurrence in the lower 64 bits/lower 8-bit ECC, or the
upper 64 bits/upper 8-bit ECC, respectively, of a 128-bit memory-aligned Flash data word.
• A flag is set indicating that an uncorrectable error interrupt is generated (UNC_ERR_INTFLG in
ERR_INTFLG register).
When an uncorrectable error occurs, the Flash module sets the UNC_ERR_INTFLG bit and generates an
uncorrectable error interrupt. This uncorrectable error interrupt generates a non-maskable interrupt (NMI), if
enabled, in the CPU. If an uncorrectable error interrupt flag is not cleared by writing to the UNC_ERR_INTCLR
bit in the ERR_INTCLR register, the Flash module cannot generate new uncorrectable interrupt signals, as this is
an edge-based interrupt.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash word
causes the uncorrectable error flag to get set, and an uncorrectable error interrupt/NMI to occur, when there is
a uncorrectable error in both or in either the lower 64 bits or upper 64 bits (or corresponding ECC check bits) of
that 128-bit data word.
6.7.3 Mechanism to Check the Correctness of ECC Logic
To make sure the correctness of the ECC logic, a redundant ECC logic block for each of the ECC64_L and
ECC64_H checkers is used. Each 64-bit ECC checker block and the corresponding redundant checker block
receive the same inputs. The output of each 64-bit checker block is bitwise XORed with the output of the
corresponding redudnant checker block; a non-zero output from this comparison generates an uncorrectable
error (UNC_ERR) signal. This redundancy makes sure that any fault in ECC logic circuits can be detected and
trigger an NMI.
A mechanism has been added to enable self-testing of the ECC logic for additional diagnostic coverage.
To use this mechanism, configure the ECC_TEST_EN field in the FECC_CTRL register. A value of 01 in
ECC_TEST_EN injects a single-bit error into the redundant ECC logic upon a Flash read access, and a value
of 11 injects a double-bit error upon a Flash read access. This causes an output comparison failure. In this
mode, the diagnostic outputs of each of the high and low comparators (DIAG_H and DIAG_L) are captured in
the FLUCERRSTATUS Memconfig register.

Note
When ECC self-test is enabled and CPU issues a read access to the Flash, ECC errors are captured
in the data cache and prefetch buffers. TI recommends that application software disables caching
while performing diagnostic checks.

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FAIL_1_H
FAIL_0_H
Data[127:64]
ERR_TYPE_H
ECC_H[7:0] SINGLE_ERR_H
ECC64_H UNC_ERR_H
(func)
AIN[21:0] ERR_POS_H[5:0]
C_Data[127:64]

DIAG_H
Output
Comparator
ERR FAIL_1_H
Inse rtio n FAIL_0_H
ERR_TYPE_H
SINGLE_ERR_H
ECC64_H UNC_ERR_H
(Redun dant)
ERR_POS_H[5:0]
C_Data[127:64]

UNC_ERR_H
FAIL_1_H
FAIL_0_H
FECC_CTRL.ECC_TEST_EN
From ECC64_H ERR_TYPE_H
SINGLE_ERR_H
(func) ERR_POS_H[5:0]
ECC C_Data[127:64]
Enable

FAIL_1_L
FAIL_0_L
Data[63:0]
ERR_TYPE_L
ECC_L[7:0] SINGLE_ERR_L
ECC64_L UNC_ERR_L
(func)
AIN[21:0] ERR_POS_L[5:0]
C_Data[63:0]
DIAG_L
Output
Comparator
ERR FAIL_1_L
Inse rtio n FAIL_0_L
ERR_TYPE_L
SINGLE_ERR_L
ECC64_L UNC_ERR_L
(Redun dant)
ERR_POS_L[5:0]
C_Data[63:0]

UNC_ERR_L
FAIL_1_L
FAIL_0_L
FECC_CTRL.ECC_TEST_EN
From ECC64_L ERR_TYPE_L
SINGLE_ERR_L
(func) ERR_POS_L[5:0]
C_Data[63:0]

Figure 6-4. Testing ECC Logic

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6.8 Reserved Locations Within Flash and OTP

When allocating code and data to Flash and OTP memory, keep the following reserved locations in mind:
• Refer to the ROM Code and Peripheral Booting chapter for reserved locations in Flash for real-time operating
system usage and a boot-to-Flash entry point. A boot-to-Flash entry point is reserved for an entry-into-Flash
branch instruction. When the boot-to-Flash boot option is used, the boot ROM jumps to this address in Flash.
If you program a branch instruction here, that redirects code execution to the entry point of the application.

6.9 Migrating an Application from RAM to Flash

To migrate an existing application that is configured to run from RAM to a Flash-based linker configuration, follow
these steps:
1. Replace the RAM linker command file with a Flash linker command file. For examples of Flash-based linker
command files, see the device_support\<device>\common\cmd directory.
2. When modifying the Flash-based linker command file, be sure to map any initialized sections to Flash
memory regions.
3. Make sure the boot mode pins are configured for Flash boot. This tells the boot ROM to redirect execution to
the application programmed into Flash memory after boot code execution is complete. For more information
on boot mode configuration, see Detailed Description > Device Boot Modes in the device data sheet.
4. When the device is configured for Flash boot, the boot ROM redirects execution to the Flash entry
point location (defined as BEGIN in TI-provided Flash linker command files) at the end of boot code
execution. Make sure there is a branch instruction at the Flash entry point to your code initialization
(for example, _c_int00) function. In the C2000Ware examples, the entry point code is specified in the
codestartbranch.asm file.
5. To achieve best performance for Flash execution, configure the Flash wait states as per the device operating
clock frequency, as specified in the device data sheet. In addition, enable prefetch mode and data cache
mode. Calling the Flash_initModule() driverlib function achieves these steps. Note that code that
initializes the Flash module must execute from a RAM location. This is accomplished by assigning the Flash
initialization function to the .TI.ramfunc section. In the linker command file, map this section to Flash for
load, and RAM for execution. The example cmd files provided in C2000Ware show how to do this correctly.
6. For any functions that require 0- or 1-wait state performance, be sure to map to RAM for execution in the
linker command file, similar to the Flash initialization function. The .TI.ramfunc section in the TI-provided
Flash linker command files accomplishes this purpose.
7. Align all code and data sections to 128-bit address boundaries when mapping to Flash memory, using the
ALIGN directive in the linker command file.
8. For EABI executable formats, define all uninitialized sections mapped to RAM as NOINIT sections (using the
directive "type=NOINIT") in the linker command file.
9. Be sure to program ECC bits correctly for the Flash application image. Keep the AutoEccGeneration option
enabled in the Code Composer Studio Flash Plugin or UniFlash GUI.

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6.10 Procedure to Change the Flash Control Registers

During Flash configuration, no accesses to the Flash or OTP can be in progress. This includes instructions still
in the CPU pipeline, data reads, and instruction prefetch operations. To be sure that no access takes place
during the configuration change, follow the procedure shown below for any code that modifies the Flash control
registers.
1. Start executing application code from RAM/Flash/OTP.
2. Branch to or call the Flash configuration code (that writes to Flash control registers) in RAM. This is required
to properly flush the CPU pipeline before the configuration change. The function that changes the Flash
configuration cannot execute from the Flash or OTP and must reside in RAM.
3. Execute the Flash configuration code (located in RAM) that writes to Flash control registers like FRDCNTL,
FRD_INTF_CTRL, and so on.
4. At the end of the Flash configuration code execution, wait eight cycles to let the write instructions propagate
through the CPU pipeline. This must be done before the return-from-function call is made.
5. Return to the calling function that resides in RAM or Flash/OTP and continue execution.

6.11 Software
6.11.1 FLASH Registers to Driverlib Functions
Table 6-1. FLASH Registers to Driverlib Functions
File Driverlib Function
FRDCNTL
flash.h Flash_setWaitstates
FLPROT
flash.h Flash_setFLWEPROT
FRD_INTF_CTRL
flash.h Flash_enablePrefetch
flash.h Flash_disablePrefetch
flash.h Flash_enableCache
flash.h Flash_disableCache
ECC_ENABLE
flash.h Flash_enableECC
flash.h Flash_disableECC
FECC_CTRL
flash.h Flash_enableSingleBitECCTestMode
flash.h Flash_enableDoubleBitECCTestMode
flash.h Flash_disableSingleBitECCTestMode
flash.h Flash_disableDoubleBitECCTestMode

6.11.2 FLASH Examples

NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/flash
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
6.11.2.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
FILE: flashapi_128bit_programming.c
This example demonstrates how to program Flash using API's following options

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1. AutoEcc generation
2. DataOnly and EccOnly
3. DataAndECC

External Connections
• None.
Watch Variables
• None.
6.11.2.2 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
FILE: flashapi_512bit_programming.c
This example demonstrates how to program Flash using API's following options
1. AutoEcc generation
2. DataOnly and EccOnly
3. DataAndECC
External Connections
• None.
Watch Variables
• None.
6.12 FLASH Registers
This Section describes the FLASH Registers.
6.12.1 FLASH Base Address Table
Table 6-2. FLASH Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1
Instance Structure Protected

FLASH_CTRL_RE FLASH0CTRL_BAS
Flash0CtrlRegs 0x0005_F800 YES - - YES
GS E
FLASH_ECC_RE
Flash0EccRegs FLASH0ECC_BASE 0x0005_FB00 YES - - YES
GS

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6.12.2 FLASH_CTRL_REGS Registers

Table 6-3 lists the memory-mapped registers for the FLASH_CTRL_REGS registers. All register offset
addresses not listed in Table 6-3 should be considered as reserved locations and the register contents should
not be modified.
Table 6-3. FLASH_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h FRDCNTL Flash Read Control Register EALLOW Go
4h FLPROT Flash program/erase protect register EALLOW Go
180h FRD_INTF_CTRL Flash Read Interface Control Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 6-4 shows the codes that are used for
access types in this section.
Table 6-4. FLASH_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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6.12.2.1 FRDCNTL Register (Offset = 0h) [Reset = 0F000F00h]

FRDCNTL is shown in Figure 6-5 and described in Table 6-5.
Return to the Summary Table.
Flash Read Control Register
Figure 6-5. FRDCNTL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED
R-0h R/W-Fh

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RWAIT
R-0h R/W-Fh

7 6 5 4 3 2 1 0
RESERVED
R-0h

Table 6-5. FRDCNTL Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-24 RESERVED R/W Fh Reserved
23-12 RESERVED R 0h Reserved
11-8 RWAIT R/W Fh Random read waitstate
These bits indicate how many waitstates are added to a flash read/
fetch access. The RWAIT value can be set anywhere from 0 to 0xF.
For a flash access, data is returned in RWAIT+1 SYSCLK cycles.
Note: The required wait states for each SYSCLK frequency can be
found in the device data manual.
Reset type: SYSRSn
7-0 RESERVED R 0h Reserved

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6.12.2.2 FLPROT Register (Offset = 4h) [Reset = 00000000h]

FLPROT is shown in Figure 6-6 and described in Table 6-6.
Return to the Summary Table.
Flash program/erase protect register
Figure 6-6. FLPROT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED FLWEPROT
R-0h R/W-0h

Table 6-6. FLPROT Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 FLWEPROT R/W 0h Flash program/erase protect bit.
0 : Program erase operation allowed subject to security settings.
1 : Program erase operation blocked in hardware.
Reset type: SYSRSn

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6.12.2.3 FRD_INTF_CTRL Register (Offset = 180h) [Reset = 00000000h]

FRD_INTF_CTRL is shown in Figure 6-7 and described in Table 6-7.
Return to the Summary Table.
Flash Read Interface Control Register
Figure 6-7. FRD_INTF_CTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DATA_CACHE_ PREFETCH_E
EN N
R-0h R/W-0h R/W-0h

Table 6-7. FRD_INTF_CTRL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-2 RESERVED R 0h Reserved
1 DATA_CACHE_EN R/W 0h Data cache enable.
0 A value of 0 disables the data cache.
1 A value of 1 enables the data cache.
Reset type: SYSRSn
0 PREFETCH_EN R/W 0h Prefetch enable.
0 A value of 0 disables prefetch mechanism.
1 A value of 1 enables pre-fetch mechanism.
Reset type: SYSRSn

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6.12.3 FLASH_ECC_REGS Registers

Table 6-8 lists the memory-mapped registers for the FLASH_ECC_REGS registers. All register offset addresses
not listed in Table 6-8 should be considered as reserved locations and the register contents should not be
modified.
Table 6-8. FLASH_ECC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ECC_ENABLE ECC Enable EALLOW Go
20h FECC_CTRL ECC Control EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 6-9 shows the codes that are used for
access types in this section.
Table 6-9. FLASH_ECC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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6.12.3.1 ECC_ENABLE Register (Offset = 0h) [Reset = 0000000Ah]

ECC_ENABLE is shown in Figure 6-8 and described in Table 6-10.
Return to the Summary Table.
ECC Enable
Figure 6-8. ECC_ENABLE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ENABLE
R-0h R/W-Ah

Table 6-10. ECC_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3-0 ENABLE R/W Ah ECC enable. A value of 0xA would enable ECC. Any other value
would disable ECC.
Reset type: SYSRSn

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6.12.3.2 FECC_CTRL Register (Offset = 20h) [Reset = 00000000h]

FECC_CTRL is shown in Figure 6-9 and described in Table 6-11.
Return to the Summary Table.
ECC Control
Figure 6-9. FECC_CTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ECC_TEST_EN
R-0h R/W-0h

Table 6-11. FECC_CTRL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-2 RESERVED R 0h Reserved
1-0 ECC_TEST_EN R/W 0h ECC test mode enable.
00 ECC test mode disabled
01 ECC test mode enabled, one of the 64 data bits is flipped and fed
to the redundant ECC logic (on both ECC logic low and ECC logc
high blocks).
11 ECC test mode enabled, Two of the 64 data bits are flipped and
fed to the redundant ECC logic (on both ECC logic low and ECC logc
high blocks).
10 Reserved
Reset type: SYSRSn

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Chapter 7
Control Law Accelerator (CLA)

The Control Law Accelerator (CLA) Type-2 is an independent, fully-programmable, 32-bit floating-point math
processor that brings concurrent control-loop execution to the C28x family. The low interrupt latency of the
CLA allows the CLA to read ADC samples "just-in-time." This significantly reduces the ADC sample to output
delay to enable faster system response and higher MHz control loops. By using the CLA to service time-critical
control loops, the main CPU is free to perform other system tasks such as communications and diagnostics. This
chapter provides an overview of the architectural structure and components of the control law accelerator.

7.1 Introduction...............................................................................................................................................................830
7.2 CLA Interface............................................................................................................................................................ 832
7.3 CLA, DMA, and CPU Arbitration..............................................................................................................................838
7.4 CLA Configuration and Debug................................................................................................................................ 841
7.5 Pipeline......................................................................................................................................................................844
7.6 Software.................................................................................................................................................................... 850
7.7 Instruction Set...........................................................................................................................................................857
7.8 CLA Registers...........................................................................................................................................................988

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7.1 Introduction
The Control Law Accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-
critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables
faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks frees up the
main CPU to perform other system and communication functions concurrently.
7.1.1 Features
The following is a list of major features of the CLA:
• C compilers are available for CLA software development.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program Address Bus (PAB) and Program Data Bus (PDB)
• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and
Data Write Data Bus (DWDB)
– Independent eight stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0-MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
• Task trigger mechanisms:
– C28x CPU using the IACK instruction
– Task1 to Task8: trigger sources from peripherals connected to the shared bus on which the CLA assumes
secondary ownership.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.

7.1.2 CLA Related Collateral

Foundational Materials
• C2000 Academy - CLA
• C2000 CLA C Compiler Series (Video)
• CLA Hands On Workshop (Video)
• CLA usage in Valley Switching Boost Power Factor Correction (PFC) Reference Design (Video)
• Enhancing the Computational Performance of the C2000™ Microcontroller Family Application Report

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Getting Started Materials

• CLA Software Development Guide
• Software Examples to Showcase Unique Capabilities of TI's C2000™ CLA Application Report

Expert Materials
• Digital Control of Two Phase Interleaved PFC and Motor Drive Using MCU With CLA Application Report
• Sensorless Field Oriented Control:3-Phase Perm.Magnet Synch. Motors With CLA Application Report
7.1.3 Block Diagram
Figure 7-1 is a block diagram of the CLA.

CLA Control
Register Set

MIFR(16)
MPERINT1 MIOVF(16) CLA_INT1
From Shared to to
Peripherals MPERINT8 MICLR(16) CLA_INT8
MICLROVF(16) C28x
PIE INT11
MIFRC(16) CPU
MIER(16) INT12
MIRUN(16)
LVF
MCTLBGRND(16)
LUF
MSTSBGRND(16)
CLA1SOFTINTEN(16)
CLA1INTFRC(16)
SYSCLK
CLA Clock Enable MVECT1(16)
CPU Read/Write Data Bus
SYSRS MVECT2(16)
MVECT3(16)
MVECT4(16) CLA Program
MVECT5(16) CLA Program Bus Memory (LSx)
MVECT6(16)
MVECT7(16)
MVECT8(16) LSxMSEL[MSEL_LSx]
MVECTBGRND(16) LSxCLAPGM[CLAPGM_LSx]
MVECTBGRNDACTIVE(16)
MPSACTL(16)

CPU Data Bus

MPSA1(32) CLA Data
MPSA2(32) Memory (LSx)

MCTL(16)
CLA Data Bus

CLA Message
CLA Execution
RAMs
Register Set

MPC(16)
MSTF(32)
MR0(32)
MR1(32) Shared
MR2(32) MEALLOW Peripherals
MR3(32)
MAR0(16)
MAR1(16)
CPU Read Data Bus

Figure 7-1. CLA Block Diagram

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7.2 CLA Interface

This section describes how the C28x main CPU can interface to the CLA and conversely.
7.2.1 CLA Memory
The CLA can access three types of memory: program, data and message RAMs. The behavior and arbitration
for each type of memory is described in this chapter.
• CLA Program Memory
The CLA program can be loaded with any of the local shared memories (LSxRAM). At reset, all memory
blocks are mapped to the CPU. While mapped to the CPU space, the CPU can copy the CLA program code
into the memory. During debug, the memory can also be loaded directly by the Code Composer Studio™
IDE.
Once the memory is initialized with CLA code, the CPU maps the memory to the CLA program space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a code block for the CLA by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit.
When a memory block is configured as CLA program memory, debug accesses are allowed only on cycles
where the CLA is not fetching a new instruction. A detailed explanation of the memory configurations and
access arbitration (CPU, CLA, and DEBUG) process can be found in the Memory Controller Module section
of the System Control and Interrupts chapter.
All CLA program fetches are performed as 32-bit read operations and all opcodes must be aligned to an even
address. Since all CLA opcodes are 32-bits, this alignment occurs naturally.

• CLA Data Memory

Any of the device’s LSxRAMs can serve as data memory blocks to the CLA. At reset, all blocks are mapped
to the CPU memory space, whereby the CPU can initialize the memory with data tables, coefficients, and so
on, for the CLA to use.
Once the memory is initialized with CLA data, the CPU maps the memory to the CLA data space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a data block for the CLA by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. The value of this bit at reset is 0.
When a memory block is configured as CLA data memory, CLA read and write accesses are arbitrated along
with CPU accesses. The user has the option of turning on CPU fetch or write protection to the memory by
writing to the appropriate bits of the MemCfgRegs.LSxACCPROTx registers. A detailed explanation of the
memory configurations and access arbitration (CPU, CLA, and DEBUG) process can be found in the Memory
Controller Module section of the System Control and Interrupts chapter.

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• CLA Shared Message RAMs

There are two memory blocks for data sharing and communication between the CLA and the CPU . The
message RAMs are always mapped to both CPU and CLA memory spaces, and only data access is allowed;
no program fetches can be performed.
– CLA to CPU Message RAM: The CLA can use this block to pass data to the CPU. This block is both
readable and writable by the CLA. This block is also readable by the CPU but writes by the CPU are
ignored.
– CPU to CLA Message RAM: The CPU can use this block to pass data and messages to the CLA. This
message RAM is both readable and writable by the CPU. The CLA can perform reads but writes by the
CLA are ignored.

7.2.2 CLA Memory Bus

The CLA has dedicated bus architecture similar to that of the C28x CPU where there are separate program read,
data read, and data write buses. Thus, there can be simultaneous instruction fetch, data read, and data write in
a single cycle. Like the C28x CPU, the CLA expects memory logic to align any 32-bit read or write to an even
address. If the address-generation logic generates an odd address, the CLA can begin reading or writing at the
previous even address. This alignment does not affect the address values generated by the address-generation
logic.
• CLA Program Bus
The CLA program bus has an access range of 32-bit instructions. Since all CLA instructions are 32 bits, this
bus always fetches 32 bits at a time and the opcodes must be even-word aligned. The amount of program
space available for the CLA is limited to the number of blocks. This number is device-dependent and can be
described in the data sheet.

• CLA Data Read Bus

The CLA data read bus has a 64K x 16 address range. The bus can perform 16 or 32-bit reads and can
automatically stall if there are memory access conflicts. The data read bus has access to both the message
RAMs, CLA data memory, and the shared peripherals.

• CLA Data Write Bus

The CLA data write bus has a 64K x 16 address range. This bus can perform 16 or 32-bit writes. The bus can
automatically stall if there are memory access conflicts. The data write bus has access to the CLA to CPU
message RAM, CLA data memory, and the shared peripherals.

7.2.3 Shared Peripherals and EALLOW Protection

Refer to the device data sheet for the list of peripherals connected to the bus.
Several peripheral control registers are protected from spurious 28x CPU writes by the EALLOW protection
mechanism. These same registers are also protected from spurious CLA writes. The EALLOW bit in the CPU
status register 1 (ST1) indicates the state of protection for the CPU. Likewise, the MEALLOW bit in the CLA
status register (MSTF) indicates the state of write protection for the CLA. The MEALLOW CLA instruction
enables write access by the CLA to EALLOW protected registers. Likewise, the MEDIS CLA instruction disables
write access. This way the CLA can enable and disable write access independent of the CPU.
The ADC offers the option to generate an early interrupt pulse at the start of a sample conversion. If this option
is used to start an ADC-triggered CLA task, use the intervening cycles until the completion of the conversion
to perform preliminary calculations or loads and stores before finally reading the ADC value. The CLA pipeline
activity for this scenario is shown in Section 7.5.

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7.2.4 CLA Tasks and Interrupt Vectors

The CLA program code is divided up into tasks or interrupt service routines. Tasks do not have a fixed starting
location or length. The CLA program memory can be divided up as desired. The CLA uses the contents of the
interrupt vectors (MVECT1 to MVECT8) to determine where a task begins; tasks are terminated by the MSTOP
instruction.
The CLA supports eight tasks. Task 1 has the highest priority and task 8 has the lowest priority. The Type-2
CLA offers the option of setting the lowest priority task, for example, task 8, as a background task that, once
triggered, runs continuously until the user either terminates the task or resets the CLA or the device. The
remaining tasks, 1 through 7, maintain the priority levels and interrupt the background task when triggered.
The background task is enabled by setting the BGEN bit in the MCTLBGRND register; this causes the hardware
to disable task 8 in the MIER register. The background task derives the interrupt vector from the MVECTBGRND
register instead of MVECT8.
A task can be requested by a peripheral interrupt or by software:
• Peripheral interrupt trigger
Each task can be triggered by software-selectable interrupt sources. The trigger for each task is defined by
writing an appropriate value to the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field. Each option
specifies an interrupt source from a specific peripheral on the shared bus. The peripheral interrupt triggers
are listed in Table 7-1.
For example, task 1 (MVECT1) can be set to trigger on EPWMINT1 by writing 36 to
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.TASK1. To disable the triggering of a task by a peripheral, set
the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field to 0. Note that a CLA task only triggers on a
level transition (an edge) of the configured interrupt source.
Table 7-1. Configuration Options
Select Value CLA Trigger Source

0 CLA_SOFTWARE_TRIGGER

1 ADCAINT1

2 ADCAINT2

3 ADCAINT3

4 ADCAINT4

5 ADCA_EVT_INT

6 ADCBINT1

7 ADCBINT2

8 ADCBINT3

9 ADCBINT4

10 ADCB_EVT_INT

11 ADCCINT1

12 ADCCINT2

13 ADCCINT3

14 ADCCINT4

15 ADCC_EVT_INT

16 ADCDINT1

17 ADCDINT2

18 ADCDINT3

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Table 7-1. Configuration Options (continued)

Select Value CLA Trigger Source

19 ADCDINT4

20 ADCD_EVT_INT

21-28 Reserved

29 XINT1

30 XINT2

31 XINT3

32 XINT4

33 XINT5

34-35 Reserved

36 EPWM1_INT

37 EPWM2_INT

38 EPWM3_INT

39 EPWM4_INT

40 EPWM5_INT

41 EPWM6_INT

42 EPWM7_INT

43 EPWM8_INT

44 EPWM9_INT

45 EPWM10_INT

46 EPWM11_INT

47 EPWM12_INT

48-51 Reserved

52 MCANA_FEVT0

53 MCANA_FEVT1

54 MCANA_FEVT2

55 MCANB_FEVT0

56 MCANB_FEVT1

57 MCANB_FEVT2

58-67 Reserved

68 CPU_TINT0

69 CPU_TINT1

70 CPU_TINT2

71-74 Reserved

75 ECAP1_INT

76 ECAP2_INT

77-82 Reserved

83 EQEP1_INT

84 EQEP2_INT

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Table 7-1. Configuration Options (continued)

Select Value CLA Trigger Source

85 EQEP3_INT

86-98 Reserved

99 LINA_INT1

100 LINA_INT0

101-104 Reserved

105 PMBUSA_INT

106-108 Reserved

109 SPIA_TXINT

110 SPIA_RXINT

111 SPIB_TXINT

112 SPIB_RXINT

113-122 Reserved

123 FSITXA_INT1

124 FSITXA_INT2

125 FSIRXA_INT1

126 FSIRXA_INT2

127 CLB1_INT

128 CLB2_INT

129-136 Reserved

137 ADCEINT1

138 ADCEINT2

139 ADCEINT3

140 ADCEINT4

141 ADCE_EVT_INT

142-183 Reserved

184 DMA_CH1INT

185 DMA_CH2INT

186 DMA_CH3INT

187 DMA_CH4INT

188 DMA_CH5INT

189 DMA_CH6INT

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• Software Trigger
CPU software can trigger tasks by writing to the MIFRC register or by the IACK instruction. Using the
IACK instruction is more efficient because the instruction does not require the need to issue an EALLOW
to set MIFR bits. Set the MCTL[IACKE] bit to enable the IACK feature. Each bit in the operand of the IACK
instruction corresponds to a task. For example, IACK #0x0001 sets bit 0 in the MIFR register to start task 1.
Likewise, IACK #0x0003 set bits 0 and 1 in the MIFR register to start task 1 and task 2.
• Background Task
The Type-2 CLA allows the use of Task 8 as a background task that runs continuously until Task 8 disables
the task or resets the device (or the CLA using a soft reset). The background task vector is given by the
MVECTBGRND register and the operation is controlled by the MCTLBGRND register; the task is enabled
by setting the BGEN bit to 1. Then start the task through software by writing a 1 to the BGSTART bit
(TRIGEN must be 0), or through a peripheral by setting the TRIGEN bit to 1 and then setting the trigger
source in the bit-field, DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK8. By default, the background task
is interruptible; the highest priority pending task is executed first. When a task completes and there are not
any pending tasks, the execution returns to the background task. The CLA keeps track of the branching point
by saving the return address to the MVECTBGRNDACTIVE register, and then popping this address to the
MPC when execution returns. Choose to make sections of the background task uninterruptible by possibly
doing this with the MSETC BGINTM assembly instruction.
Subsequently, enabling interrupts with the MCLRC BGINTM instruction.
The background interrupt mask bit, BGINTM, can be queried in the MSTSBGRND register. This register also
provides the current status of the background task. If the task is currently executing, the RUN bit is set to 1, if
another trigger for the background task is received while the task has already started, the overflow (BGOVF)
bit is set.
The CLA has a fetch mechanism and can run and execute a task independently of the CPU. Only one task is
serviced at a time; there is no nesting of tasks unless the background task in enabled, then one level of nesting
is possible. The task currently running is indicated in the MIRUN register; if the background task is enabled and
running, the task is reflected in the MSTSBGRND register (the RUN bit).
Interrupts that have been received but not yet serviced are indicated in the flag register (MIFR). If an interrupt
request from a peripheral is received and that same task is already flagged, then the overflow flag bit is set.
Overflow flags remain set until the flags are cleared by the CPU. If the CLA is idle (no task is currently running)
or is executing the background task, then the highest priority interrupt request that is both flagged (MIFR) and
enabled (MIER) starts.
The flow is as follows:
1. The associated RUN register bit is set (MIRUN) and the flag bit (MIFR) is cleared.
2. The CLA begins execution at the location indicated by the associated interrupt vector (MVECTx). MVECT
contains the absolute 16-bit address of the task in the lower 64K memory space. If a task is interrupting
the background task then the current program address is stored in the MVECTBGRNDACTIVE register
before execution jumps to the task; this saved address is restored to the MPC when the task completes and
execution returns to the background task.
3. The CLA executes instructions until the MSTOP instruction is found. This indicates the end of the task.
4. The MIRUN bit is cleared.
5. The task-specific interrupt to the PIE is issued. This informs the main CPU that the task has completed.
6. The CLA returns to idle (or to the background task, if enabled). Once a task completes the next highest-
priority pending task is automatically serviced and this sequence repeats.

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7.3 CLA, DMA, and CPU Arbitration

Typically, CLA activity is independent of the CPU activity. Under the circumstance where the CLA or CPU
attempt to concurrently access memory or a peripheral register within the same interface, an arbitration
procedure occurs. This section describes this arbitration.
The arbitration follows a fixed arbitration scheme with highest priority first:
1. DMA WRITE
2. DMA READ
3. CLA WRITE
4. CLA READ
5. CPU WRITE
6. CPU READ
Refer to the Memory Controller Module section of the System Control and Interrupts chapter.
7.3.1 CLA Message RAM
Message RAMs consist of four blocks:
• CLA to CPU Message RAM
• CPU to CLA Message RAM
• DMA to CLA Message RAM
• CLA to DMA Message RAM
These blocks are useful for passing data between the CLA and CPU or CLA and DMA. No opcode fetches,
from either the CLA or CPU, are allowed from the message RAMs. A write protection violation is not generated
if the CLA attempts to write to the CPU to CLA or DMA to CLA message RAM, but the write is ignored. The
arbitration scheme for the message RAMs are the same as those for the shared memories, described in the
Memory Controller Module section of the System Control and Interrupts chapter.
The message RAMs have the following characteristics:
• CLA to CPU Message RAM:
The following accesses are allowed:
– CPU reads
– CLA data reads and writes
– CPU debug reads and writes
The following accesses are ignored:
– CPU writes
• CPU to CLA Message RAM:
The following accesses are allowed:
– CPU reads and writes
– CLA reads
– CPU debug reads and writes
The following accesses are ignored:
– CLA writes

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7.3.2 CLA Program Memory

The behavior of the program memory depends on the state of the MMEMCFG[PROGE] bit. This bit controls
whether the memory is mapped to CLA space or CPU space.
• MMEMCFG[PROGE] == 0
In this case, the memory is mapped to the CPU. The CLA is halted and no tasks can be incoming.
– Any CLA fetch is treated as an illegal opcode condition as described in Section 7.4.4. This condition does
not occur, if the proper procedure is followed to map the program memory.
– CLA reads and writes cannot occur
– The memory block behaves as any normal RAM block mapped to CPU memory space.

Priority of accesses are (highest priority first):

1. CPU data write, program write, debug write
2. CPU data read, program read, debug read
3. CPU fetch, program read

• MMEMCFG[PROGE] == 1
In this case, the memory block is mapped to CLA space. The CPU can only make debug accesses.
– CLA reads and writes cannot occur
– CLA fetches are allowed
– CPU fetches return 0 that is an illegal opcode and causes an ITRAP interrupt.
– CPU data reads and program reads return 0
– CPU data writes and program writes are ignored

Priority of accesses are (highest priority first):

1. CLA fetch
2. CPU debug write
3. CPU debug read

Note
Because the CLA fetch has higher priority than CPU debug reads, there is a possibility for the CLA
to permanently block debug accesses if the CLA is executing in a loop. This can occur when initially
developing CLA code due to a bug. To avoid this issue, the program memory returns all 0x0000 for
CPU debug reads (ignore writes) when the CLA is running. When the CLA is halted or idle, then
normal CPU debug read and write access can be performed.

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7.3.3 CLA Data Memory

There are independent data memory blocks. The behavior of the data memory depends on the state of the
MMEMCFG[RAM0E] MMEMCFG[RAM1E] bits. These bits determine whether the memory blocks are mapped to
CLA space or CPU space.
• MMEMCFG[RAMxE] == 0
In this case the memory block is mapped to the CPU.
– CLA fetches cannot occur to this block.
– CLA reads return 0.
– CLA writes are ignored.
– The memory block behaves as any normal RAM block mapped to the CPU memory space.

Priority of accesses are (highest priority first):

1. CPU data write/program write/debug access write
2. CPU data read/debug access read
3. CPU fetch/program read

• MMEMCFG[RAMxE] == 1
In this case the memory block is mapped to CLA space. The CPU can make only debug accesses.
– CLA fetches cannot occur to this block.
– CLA read and CLA writes are allowed.
– CPU fetches return 0
– CPU data reads and program reads return 0.
– CPU data writes and program writes are ignored.

Priority of accesses are (highest priority first):

1. CLA data write
2. CPU debug write
3. CPU debug read
4. CLA read

7.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)

Accesses to the registers follow these rules:
• If both the CPU and CLA request access at the same time, then the CLA has priority and the main CPU is
stalled.
• If a CPU access is in-progress and another CPU access is pending, then the CLA has priority over the
pending CPU access. In this case, the CLA access begins when the current CPU access completes.
• While a CPU access is in-progress, any incoming CLA access is stalled.
• While a CLA access is in-progress, any incoming CPU access is stalled.
• A CPU write operation has priority over a CPU read operation.
• A CLA write operation has priority over a CLA read operation.
• If the CPU is performing a read-modify-write operation and the CLA performs a write to the same location, the
CLA write can be lost if the operation occurs in-between the CPU read and write. For this reason, do not mix
CPU and CLA accesses to same location.

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7.4 CLA Configuration and Debug

This section discusses the steps necessary to configure and debug the CLA.
7.4.1 Building a CLA Application
The control law accelerator can be programmed in either CLA assembly code, using the instructions described
in Section 7.7, or a reduced subset of the C language. CLA assembly code resides in the same project with
C28x code. The only restriction is the CLA code must be in the assembly section. This can be easily done
using the .sect assembly directive. This does not prevent CLA and C28x code from being linked into the same
memory region in the linker command file.
System and CLA initialization are performed by the main CPU. This can typically be done in C or C++ but can
also include C28x assembly code. The main CPU also copies the CLA code to the program memory and, if
needed, initialize the CLA data RAMs. Once system initialization is complete and the application begins, the
CLA services the interrupts using the CLA assembly code (or tasks). The main CPU can perform other tasks
concurrently with CLA program execution.
7.4.2 Typical CLA Initialization Sequence
A typical CLA initialization sequence is performed by the main CPU as described in this section.
1. Copy CLA code into the CLA program RAM: The source for the CLA code can initially reside in the Flash
or a data stream from a communications peripheral or anywhere the main CPU can access. The debugger
can also be used to load code directly to the CLA program RAM during development.
2. Initialize CLA data RAM, if necessary: Populate the CLA data RAM with any required data coefficients or
constants.
3. Configure the CLA registers: Configure the CLA registers, but keep interrupts disabled until later (leave
MIER = 0):
• Enable the CLA peripheral clock using the assigned PCLKCRn register: The peripheral clock control
(PCLKCRn) registers are defined in the System Control and Interrupts chapter.
• Populate the CLA task interrupt vectors:
– MVECT1 to MVECT8
• Select the task interrupt sources: For each task select the interrupt source in the CLA1TASKSRCSELx
register. If a task is software triggered, select no interrupt.
• Enable IACK to start a task from software, if desired: To enable the IACK instruction to start a task set
the MCTL[IACKE] bit. Using the IACK instruction avoids having to set and clear the EALLOW bit.
• Map CLA data RAM to CLA space, if necessary:
• Map CLA program RAM to CLA space:
4. Initialize the PIE vector table and registers: When a CLA task completes, the associated interrupt in the
PIE is flagged. The CLA overflow and underflow flags also have associated interrupts within the PIE.
5. Enable CLA tasks/interrupts: Set appropriate bits in the interrupt enable register (MIER) to allow the CLA
to service interrupts. Note that a CLA task only triggers on a level transition (a falling edge) of the configured
interrupt source. If a peripheral is enabled and an interrupt fires before the CLA is configured, then the CLA
does not recognize the interrupt edge and does not respond. To avoid this, configure the CLA before the
peripherals or clear any pending peripheral interrupts before setting bits in the MIER register.
6. Initialize other peripherals: Initialize any peripherals (such as ePWM, ADC, and others) that generate
interrupt triggers for enabled CLA tasks.
The CLA is now ready to service interrupts and the message RAMs can be used to pass data between the
CPU and the CLA. Mapping of the CLA program and data RAMs typically occurs only during the initialization
process. If the RAM mapping needs to be changed after initialization, the CLA interrupts must be disabled
and all tasks must be completed (by checking the MIRUN register) prior to modifying the RAM ownership.

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7.4.3 Debugging CLA Code

Debugging the CLA code is a simple process that occurs independently of the main CPU. The type 2 CLA adds
a true software breakpoint feature.
7.4.3.1 Breakpoint Support (MDEBUGSTOP)
1. Insert a breakpoint in CLA code
Insert a CLA breakpoint (MDEBUGSTOP instruction) into the code where the CLA is to halt, then rebuild
and reload the code. Because the CLA does not flush the pipeline when in single-step, the MDEBUGSTOP
instruction must be inserted as part of the code. The debugger cannot insert the MDEBUGSTOP instruction
as needed.
If CLA breakpoints are not enabled, then the MDEBUGSTOP instruction is ignored and is treated
as a MNOP. The MDEBUGSTOP instruction can be placed anywhere in the CLA code as long as
the MDEBUGSTOP instruction is not within three instructions of a MBCNDD, MCCNDD, or MRCNDD
instruction. When programming in C, the user can use the __mdebugstop() intrinsic instead; the compiler
makes sure that the placement of the MDEBUSTOP instruction in the generated assembly does not violate
any of the pipeline restrictions.
2. Enable CLA breakpoints
Enable the CLA breakpoints in the debugger. In the Code Composer Studio™ IDE, this is done by
connecting to the CLA core (or tap) from the debug perspective. Breakpoints are disabled when the core is
disconnected.
3. Start the task
There are three ways to start the task:
a. The peripheral can assert an interrupt,
b. The main CPU can execute an IACK instruction, or
c. The user can manually write to the MIFRC register in the debugger window
When the task starts, the CLA executes instructions until the MDEBUGSTOP is in the D2 phase of the
pipeline. At this point, the CLA halts and the pipeline is frozen. The MPC register reflects the address of the
MDEBUGSTOP instruction.

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4. Single-step the CLA code

Once halted, the user can single-step the CLA code. The behavior of a CLA single-step is different than the
main C28x. When issuing a CLA single-step, the pipeline is clocked only one cycle and then again frozen.
On the C28x CPU, the pipeline is flushed for each single-step.
Run to the next MDEBUGSTOP or to the end of the task. If another task is pending, the task automatically
starts when run to the end of the task.

Note
A CLA fetch has higher priority than CPU debug reads. For this reason, the CLA to permanently
block CPU debug accesses if the CLA is executing in a loop is possible. This can occur when initially
developing CLA code due to a bug that causes an infinite loop. To avoid locking up the main CPU,
the program memory returns all 0x0000 for CPU debug reads when the CLA is running. When the
CLA is halted or idle, then normal CPU debug read and write access to CLA program memory can be
performed.
If the CLA gets caught in an infinite loop, use a soft or hard reset to exit the condition. A debugger
reset also exits the condition.

There are special cases that can occur when single-stepping a task such that the program counter, MPC,
reaches the MSTOP instruction at the end of the task.
• MPC halts at or after the MSTOP with a task already pending
If single-stepping or halted in "task A" and "task B" comes in before the MPC reaches the MSTOP, then
"task B" starts if continuing to step through the MSTOP instruction. Basically, if "task B" is pending before
the MPC reaches MSTOP in "task A" then there is no issue in "task B" starting and no special action is
required.
• MPC halts at or after the MSTOP with no task pending
In this case, if single-stepped or halted in "task A" and the MPC has reached the MSTOP with no tasks
pending. If "task B" comes in at this point, "task B" is flagged in the MIFR register but "task B" can or
cannot start if continuing to single-step through the MSTOP instruction of "task A."
Depending on exactly when the new task comes in, to reliably start "task B", perform a soft reset and
reconfigure the MIER bits. Once this is done, start single-stepping "task B."
This case can be handled slightly differently if there is control over when "task B" comes in (for example,
using the IACK instruction to start the task). In this case, the task is single-stepped or halted in "task A"
and the MPC has reached the MSTOP with no tasks pending. Before forcing "task B," run free to force
the CLA out of the debug state. Once this is done, force "task B" and continue debugging.
5. Disable CLA breakpoints, if desired
In the Code Composer Studio™ IDE, disable the CLA breakpoints by disconnecting the CLA core in the
debug perspective. Make sure to first issue a run or reset; otherwise, the CLA is halted and no other tasks
start.

7.4.4 CLA Illegal Opcode Behavior

If the CLA fetches an opcode that does not correspond to a legal instruction, the CLA behaves as follows:
• The CLA halts with the illegal opcode in the D2 phase of the pipeline as if a breakpoint. This occurs whether
CLA breakpoints are enabled or not.
• The CLA issues the task-specific interrupt to the PIE.
• The MIRUN bit for the task remains set.
Further single-stepping is ignored once execution halts due to an illegal op-code. To exit this situation, issue
either a soft or hard reset of the CLA as described in Section 7.4.5.

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7.4.5 Resetting the CLA

There are times when resetting the CLA is needed. For example, during code debug the CLA can enter an
infinite loop due to a code bug. The CLA has two types of resets: hard and soft. Both of these resets can be
performed by the debugger or by the main CPU.
• Hard Reset Writing a 1 to the MCTL[HARDRESET] bit performs a hard reset of the CLA. The behavior of a
hard reset is the same as a system reset (using XRS or the debugger). In this case, all CLA configuration and
execution registers can be set to the default state and CLA execution halts.
• Soft Reset Writing a 1 to the MCTL[SOFTRESET] bit performs a soft reset of the CLA. If a task is executing,
the task halts and the associated MIRUN bit is cleared. All bits within the interrupt enable (MIER) register are
also cleared, so that no new tasks start.

7.5 Pipeline
This section describes the CLA pipeline stages and presents cases where pipeline alignment must be
considered.
7.5.1 Pipeline Overview
The CLA pipeline is very similar to the C28x pipeline with eight stages:
1. Fetch 1 (F1): During the F1 stage the program read address is placed on the CLA program address bus.
2. Fetch 2 (F2): During the F2 stage the instruction is read using the CLA program data bus.
3. Decode 1 (D1): During D1 the instruction is decoded.
4. Decode 2 (D2): Generate the data read address. Changes to MAR0 and MAR1 due to post-increment using
indirect addressing takes place in the D2 phase. Conditional branch decisions are also made at this stage
based on the MSTF register flags.
5. Read 1 (R1): Place the data read address on the CLA data-read address bus. If a memory conflict exists,
the R1 stage is stalled.
6. Read 2 (R2): Read the data value using the CLA data read data bus.
7. Execute (EXE): Execute the operation. Changes to MAR0 and MAR1 due to loading an immediate value or
value from memory take place in this stage.
8. Write (W): Place the write address and write data on the CLA write data bus. If a memory conflict exists, the
W stage is stalled.

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7.5.2 CLA Pipeline Alignment

The majority of the CLA instructions do not require any special pipeline considerations. This section lists the few
operations that do require special consideration.
• Write Followed by Read
In both the C28x pipeline and the CLA pipeline, the read operation occurs before the write. This means that
if a read operation immediately follows a write, then the read completes first as shown in Table 7-2. In most
cases this does not cause a problem since the contents of one memory location does not depend on the
state of another. For accesses to peripherals where a write to one location can affect the value in another
location, the code must wait for the write to complete before issuing the read as shown in Table 7-3.
This behavior is different for the C28x CPU. For the C28x CPU, any write followed by read to the same
location is protected by what is called write-followed-by-read protection. This protection automatically stalls
the pipeline so that the write completes before the read. In addition, some peripheral frames are protected
such that a C28x CPU write to one location within the frame always completes before a read to the frame.
The CLA does not have this protection mechanism. Instead, the code must wait to perform the read.
Table 7-2. Write Followed by Read - Read Occurs First
Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 MMOV16 MR2, @Reg2 I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1

Table 7-3. Write Followed by Read - Write Occurs First

Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
I5 MMOV16 MR2, @Reg2 I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3
I5 I4
I5

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• Delayed Conditional instructions: MBCNDD, MCCNDD, and MRCNDD

Referring to Example 7-1, the following applies to delayed conditional instructions:
– I1: I1 is the last instruction that can effect the CNDF flags for the branch, call, or return instruction. The
CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is made whether to branch or
not when MBCNDD, MCCNDD, or MRCNDD is in the D2 phase.
– I2, I3, and I4: The three instructions preceding MBCNDD can change the MSTF flags but have no effect
on whether the MBCNDD instruction branches or not. This is because the flag modification occurs after
the D2 phase of the branch, call, or return instruction. These three instructions must not be a MSTOP,
MDEBUGSTOP, MBCNDD, MCCNDD, or MRCNDD.
– I5, I6, and I7: The three instructions following a branch, call, or return are always executed irrespective of
whether the condition is true or not. These instructions must not be MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
For a more detailed description, refer to the description for MBCNDD, MCCNDD, and MRCNDD.

Example 7-1. Code Fragment For MBCNDD, MCCNDD, or MRCNDD

<Instruction 1> ; I1 Last instruction that can affect flags for

; the branch, call or return operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
<branch/call/ret> ; MBCNDD, MCCNDD or MRCNDD
; I5-I7: Three instructions after are always
; executed whether the branch/call or return is
; taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....

• Stop or Halting a Task: MSTOP and MDEBUGSTOP

The MSTOP and MDEBUGSTOP instructions cannot be placed three instructions before or after a conditional
branch, call or return instruction (MBCNDD, MCCNDD, or MRCNDD). Refer to Example 7-1. To single-step
through a branch/call or return, insert the MDEBUGSTOP at least four instructions back and step from there.

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• Loading MAR0 or MAR1

A load of auxiliary register MAR0 or MAR1 occurs in the EXE phase of the pipeline. Any post increment of
MAR0 or MAR1 using indirect addressing occurs in the D2 phase of the pipeline. Referring to Example 7-2,
the following applies when loading the auxiliary registers:
– I1 and I2: The two instructions following the load instruction use the value in MAR0 or MAR1 before the
update occurs.
– I3: Loading of an auxiliary register occurs in the EXE phase while updates due to post-increment
addressing occur in the D2 phase. Thus I3 cannot use the auxiliary register or there is a conflict. In
the case of a conflict, the update due to address-mode post increment wins and the auxiliary register is
not updated with #_X.
– I4: Starting with the 4th instruction MAR0 or MAR1 has the new value.

Example 7-2. Code Fragment for Loading MAR0 or MAR1

; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)

<Instruction 1> ; I1 uses the old value of MAR0 (50)
<Instruction 2> ; I2 uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 uses the new value of MAR0 (20)
<Instruction 5> ; I5 uses the new value of MAR0 (20)
....

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7.5.2.1 ADC Early Interrupt to CLA Response

The ADC can be configured to generate an early interrupt pulse before the ADC conversion completes. If this
option is used to start a CLA task, the CLA is able to read the result as soon as the conversion result is available
in the ADC result register. This combination of just-in-time sampling along with the low interrupt response of the
CLA enable faster system response and higher frequency control loops. The CLA task trigger to first instruction
fetch interrupt latency is 4 cycles.
Timings for ADC conversions are shown in the timing diagrams of the ADC chapter. If the ADCCLK is a divided
down version of the SYSCLK, the user has to account for the conversion time in SYSCLK cycles.
From a CLA perspective, the pipeline activity is shown in Table 7-4 for an N-cycle (SYSCLK) ADC conversion.
The N-2 instruction arrives in the R2 phase just in time to read the result register. While the prior instructions
enter the R2 phase of the pipeline too soon to read the conversion, the instructions can be efficiently used for
pre-processing calculations needed by the task.
Table 7-4. ADC to CLA Early Interrupt Response
ADC Activity CLA Activity F1 F2 D1 D2 R1 R2 E W
Sample
Sample
...
Sample
Conversion(Cycle 1) Interrupt Received
Conversion(Cycle 2) Task Startup
Conversion(Cycle 3) Task Startup
Conversion(Cycle 4) I(Cycle 4) I(Cycle 4)
Conversion(Cycle 5) I(Cycle 5) I(Cycle 5) I(Cycle 4)
Conversion(...) ... ... ... ... ... ... ...
Conversion(Cycle N-6) I(Cycle N-6) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10) I(Cycle N-11)
Conversion(Cycle N-5) I(Cycle N-5) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10)
Conversion(Cycle N-4) I(Cycle N-4) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9)
Conversion(Cycle N-3) I(Cycle N-3) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8)
Read
Conversion(Cycle N-2) Read RESULT I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7)
RESULT
Read
Conversion(Cycle N-1) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6)
RESULT
Read
Conversion(Cycle N-0) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5)
RESULT
Read
Conversion Complete I(Cycle N-3) I(Cycle N-4)
RESULT
Read
RESULT Latched I(Cycle N-3)
RESULT
Read
RESULT Available
RESULT

The ADCINTCYCLE register of the ADC can be programmed by the application to adjust the generation of the
interrupt pulse to align with the ADC read operation. For example, if the first instruction in the task reads the
ADC and the conversion time is N SYSCLK cycles, then the delay programmed is (N-2) - 4 = N-6.

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7.5.3 Parallel Instructions

Parallel instructions are single opcodes that perform two operations in parallel. The following types of parallel
instructions are available: math operation in parallel with a move operation, or two math operations in parallel.
Both operations complete in a single cycle and there are no special pipeline alignment requirements.
Example 7-3. Math Operation with Parallel Load

; MADDF32 || MMOV32 instruction: 32-bit floating-point add with parallel move

; MADDF32 is a 1 cycle operation
; MMOV32 is a 1 cycle operation
MADDF32 MR0, MR1, #2 ; MR0 = MR1 + 2,
|| MMOV32 MR1, @Val ; MR1 gets the contents of Val
; <-- MMOV32 completes here (MR1 is valid)
; <-- DDF32 completes here (MR0 is valid)
MMPYF32 MR0, MR0, MR1 ; Any instruction, can use MR1 and/or MR0

Example 7-4. Multiply with Parallel Add

; MMPYF32 || MADDF32 instruction: 32-bit floating-point multiply with parallel add

; MMPYF32 is a 1 cycle operation
; MADDF32 is a 1 cycle operation
MMPYF32 MR0, MR1, MR3 ; MR0 = MR1 * MR3
|| MADDF32 MR1, MR2, MR0 ; MR1 = MR2 + MR0 (Uses value of MR0 before MMPYF32)
; <-- MMPYF32 and MADDF32 complete here (MR0 and MR1 are valid)
MMPYF32 MR1, MR1, MR0 ; Any instruction, can use MR1 and/or MR0

7.5.4 CLA Task Execution Latency

The CLA task execution latency depends on the state of the system:
• CLA task trigger of new task (normal or background) without background task active:
Task takes 8 cycles from CLA task trigger to first instruction of task to reach the D2 phase of pipeline.

Note
If background task has been configured in the system, then the compiler during code compilation
adds context save instructions at the start of each regular task and restore instructions at end of each
task so that register content can be saved and restored in case a background task is executing while
the regular task is triggered. When a regular task is entered, this compiler-generated context save
instruction is the first instruction of the task.

• CLA task trigger of normal task when background task is active:

Task takes 9 cycles from CLA task trigger to first instruction of normal task to reach the D2 phase of pipeline.
There is a difference of one clock cycle to force the MSTOP in the D2 phase of the background task before
the task exits as compared to a new task trigger without the background task active.

Note
If the MBCNDD/MCCNDD/MRCNDD instructions in the background task are in the D2 phase of the
pipeline when a new task gets triggered, the task takes a minimum of 3 more cycles to complete these
uninterruptible instructions adding to the delay.

• Returning to background task from normal task:

The task takes 5 cycles to return from a normal task to resume the background task instruction at the D2
phase of the pipeline.

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7.6 Software
7.6.1 CLA Registers to Driverlib Functions
Table 7-5. CLA Registers to Driverlib Functions
File Driverlib Function
MVECT1
cla.h CLA_mapTaskVector
MVECT2
- See MVECT1
MVECT3
- See MVECT1
MVECT4
- See MVECT1
MVECT5
- See MVECT1
MVECT6
- See MVECT1
MVECT7
- See MVECT1
MVECT8
- See MVECT1
MCTL
cla.h CLA_performHardReset
cla.h CLA_performSoftReset
cla.h CLA_enableIACK
cla.h CLA_disableIACK
cla.h CLA_enableBackgroundTask
cla.h CLA_disableBackgroundTask
cla.h CLA_startBackgroundTask
cla.h CLA_enableHardwareTrigger
cla.h CLA_disableHardwareTrigger
MVECTBGRNDACTIVE
cla.h CLA_getBackgroundActiveVector
SOFTINTEN
cla.h CLA_enableSoftwareInterrupt
cla.h CLA_disableSoftwareInterrupt
MSTSBGRND
cla.h CLA_getBackgroundTaskStatus
MCTLBGRND
cla.h CLA_enableBackgroundTask
cla.h CLA_disableBackgroundTask
cla.h CLA_startBackgroundTask
cla.h CLA_enableHardwareTrigger
cla.h CLA_disableHardwareTrigger
MVECTBGRND
cla.h CLA_getBackgroundActiveVector
cla.h CLA_mapBackgroundTaskVector

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Table 7-5. CLA Registers to Driverlib Functions (continued)

File Driverlib Function
MIFR
cla.h CLA_getPendingTaskFlag
cla.h CLA_getAllPendingTaskFlags
cla.h CLA_forceTasks
MIOVF
cla.h CLA_getTaskOverflowFlag
cla.h CLA_getAllTaskOverflowFlags
MIFRC
cla.h CLA_forceTasks
MICLR
cla.h CLA_clearTaskFlags
MICLROVF
-
MIER
cla.h CLA_enableTasks
cla.h CLA_disableTasks
MIRUN
cla.h CLA_getTaskRunStatus
cla.h CLA_getAllTaskRunStatus
MPC
-
MAR0
-
MAR1
-
MSTF
-
MR0
-
MR1
-
MR2
-
MR3
-
MPSACTL
-
MPSA1
-
MPSA2
-
MVECTBGRNDACTIVE
cla.h CLA_getBackgroundActiveVector
MPSACTL
-

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Table 7-5. CLA Registers to Driverlib Functions (continued)

File Driverlib Function
MPSA1
-
MPSA2
-
SOFTINTEN
cla.h CLA_enableSoftwareInterrupt
cla.h CLA_disableSoftwareInterrupt
SOFTINTFRC
cla.h CLA_forceSoftwareInterrupt

7.6.2 CLA Examples

NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/cla
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
7.6.2.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
FILE: cla_asin_ls8_9.c
In this example, Task 1 of the CLA will calculate the arcsine of an input argument in the range (-1.0 to 1.0) using
a lookup table.
Note that since this example does not use background CLA task, the compile flag cla_background_task is
turned off for this project. Set this flag as on to enable background CLA task. The option is available in Project
Properties -> C2000 Build -> C2000 Compiler -> Advanced Options -> Runtime Model Options.
Memory Allocation
• CLA1 Math Tables (RAMLS0)
– CLAasinTable - Lookup table
• CLA1 to CPU Message RAM
– fResult - Result of the lookup algorithm
• CPU to CLA1 Message RAM
– fVal - Sample input to the lookup algorithm
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arcsin(fVal)
7.6.2.2 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
FILE: cla_ex1_asin.c
In this example, Task 1 of the CLA will calculate the arcsine of an input argument in the range (-1.0 to 1.0) using
a lookup table.
Note that since this example does not use background CLA task, the compile flag cla_background_task is
turned off for this project. Set this flag as on to enable background CLA task. The option is available in Project
Properties -> C2000 Build -> C2000 Compiler -> Advanced Options -> Runtime Model Options.
Memory Allocation
• CLA1 Math Tables (RAMLS1)
– CLAasinTable - Lookup table
• CLA1 to CPU Message RAM

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– fResult - Result of the lookup algorithm

• CPU to CLA1 Message RAM
– fVal - Sample input to the lookup algorithm
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arcsin(fVal)
7.6.2.3 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
FILE: cla_ex2_atan.c
In this example, Task 1 of the CLA will calculate the arctangent of an input argument using a lookup table.
Note that since this example does not use background CLA task, the compile flag cla_background_task is
turned off for this project. Set this flag as on to enable background CLA task. The option is available in Project
Properties -> C2000 Build -> C2000 Compiler -> Advanced Options -> Runtime Model Options.
Memory Allocation
• CLA1 Math Tables (RAMLS1)
– CLAatan2Table - Lookup table
• CLA1 to CPU Message RAM
– fResult - Result of the lookup algorithm
• CPU to CLA1 Message RAM
– fNum - Numerator of sample input
– fDen - Denominator of sample input
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arctan(fVal)
7.6.2.4 CLA background nesting task
FILE: cla_ex3_background_nesting_task.c
This example configures CLA task 1 to be triggered by EPWM1 running at 2 Hz (period = 0.5s). A background
task is configured to be triggered by CPU timer running at .5 Hz (period = 2s). CLA task 1 toggles LED1 at the
start and end of the task and the background task toggles LED2 at the start and end of the task. Background
task will be preempted by Task1 and hence LED1 will be toggling even while LED2 is ON.
Note that the compile flag cla_background_task is turned on in this project. Enabling background task adds
additional context save/restore cycles during task switching thus increasing the overall trigger-to-task latency.
If the application does not use the background CLA task, it is recommended to turn this flag off for better
performance. The option is available in Project Properties -> C2000 Build -> C2000 Compiler -> Advanced
Options -> Runtime Model Options.
External Connections
• None
Watch Variables
• None
7.6.2.5 Controlling PWM output using CLA
FILE: cla_ex4_pwm_control.c
This example showcases how to update PWM signal output using CLA. EPWM1 is configured to generate
complementary signals on both of its channels of fixed frequency 100 KHz. EPWM4 is configured to trigger a
periodic CLA control task of frequency 10 KHz. The CLA task implements a very simple logic to vary the duty of
the EPWM1 outputs by increasing it by 0.1 in every iteration and maintaining it in the range of 0.1-0.9. For actual

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use-cases, the control logic could be modified to much more complex depending upon the application. The other
CLA task (CLA task 8) is triggered by software at beginning to initialize the CLA global variables
External Connections
• Observe GPIO0 (EPWM1A) on oscilloscope
• Observe GPIO1 (EPWM1B) on oscilloscope
Watch Variables
• duty
7.6.2.6 Just-in-time ADC sampling with CLA
FILE: cla_ex5_adc_just_in_time.c
This example showcases how to utilize early-interrupt feature of ADC in combination with the low interrupt
response of CLA to enable faster system response and achieve high frequency control loops. EPWM1 is
configured to generate a PWM output signal of frequency 1 MHz and this is also used to trigger the ADC
sampling at each cycle. ADCA is configured to sample the input on Channel 0 and to generate the early interrupt
at the end of S/H + offset cycles. This interrupt is used to trigger the CLA control task. The CLA task implements
the control logic to update the duty of the PWM output based on reading the ADC sample data just-in-time i.e.
as soon as the ADC results gets latched.The early interrupt feature and low interrupt latency of CLA allows
to do some pre-processing as well before reading the ADC data and still completes updating the PWM output
before the next interrupts comes in i.e. data read and PWM update is done within a 1 MHz cycle. For illustration
purposes, 3-point moving average filter is used to simulate some processing and few steps of the filtering code
are done before reading the ADC result which we consider as pre-processing code. The ADC interrupt offset is
programmed based on the cycles consumed by the pre-processing code.
The calculation for interrupt offset value is as follows :- -ADC acquisition cycles programmed = 10 SYSCLKS
-Conversion time for 12-bit data = 10.5 ADCCLKS = N = 42 SYSCLKS -CLA task trigger to first instruction in
Fetch delay = 4 -Let the interrupt offset value be 'x' -The code inside CLA control task before ADC read takes
below cycles : Setting up profiling gpio : 3 cycles Pre-processing : 13 cycles Total = 3 + 13 = 16 cycles
As described in device TRM, in order to read just-in-time the total delay before reading ADC should be (N-2)
cycles = 40 i.e. : x + 4 + 16 = 40 : x = 20
NOTE :- The optimization is off for this project and the cycles quoted above corresponds to that case.
GPIO2 is used for profiling purposes. GPIO2 is set at the beginning of CLA task 1 and is reset at the end of the
task. Thus ON time of GPIO2 indicates the CLA activity. In order to validate the example functionality , observe
the GPIO0 (PWM output) and GPIO2 (profiling GPIO) on CRO. The cycles difference between the rising edge of
the GPIO0 and GPIO2 indicate the total delay from the time of ADC trigger to setting up of profiling GPIO inside
CLA task which should be around 44 cycles (293 ns) based on the above calculation.
External Connections
• Provide constant DC input on ADCA0 for quick validation. GND -> Should observe PWM output duty = 0.1
3.3V -> Should observe PWM output duty = 0.9 Can also provide analog input in range 0 - 3.3V upto fs / 10 =
100 KHz for observing continuous duty variations
• Observe GPIO0 on oscilloscope
• Observe GPIO2 on oscilloscope
Watch Variables
• None
7.6.2.7 Optimal offloading of control algorithms to CLA
FILE: cla_ex6_cpu_offloading.c
This example showcases how to optimally offload the control algorithms from CPU to CLA in order to meet the
system requirements. In this example, two control loops are simulated, the faster one (loop1) running at 200 KHz
and the slower one (loop2) running at 20 KHz. Loop1 senses the first parameter at ADCA Channel 0, runs the

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PI controller to achieve the target and contributes to the duty of EPWM1A output with 80% weightage. Loop2
senses the second parameter at ADCB Channel 2, runs the PI controller and contributes to the duty of EPWM1A
output with 20% weightage. It is important to note that since these are just software simulated control loops but
there is no actual physical process involved and hence updating the duty is not going to have any affect on
sampled inputs. ADCA is configured to oversample the first parameter using SOCs 0-3 to suppress the noise
and similarly ADCB is used to oversample the second parameter. EPWM4 and EPWM5 are configured to trigger
the ADCA and ADCB sampling at loop1 and loop2 frequencies respectively. Once the conversion of all 4 SOCs
complete, a CPU ISR or a CLA task is triggered based on the user-configuration. There is also a background
task running in the main loop which disables the entire system including PWM output and the control loops
when "system_OFF" is set to 1. The system gets enabled again once "system_OFF" is restored back to 0. By
default system_OFF is set to 0 but it's value can be updated dynamically by adding it to expression window and
writing to it. DCL library is included in the project to make use of optimal PI controllers used in both the loops.
User-configurable pre-defined symbol "run_loop1_cla" has been added to the project options in order to specify
whether to run the loop1 on C28x or CLA. GPIO2 and GPIO3 are used to profile the execution of loop1 and
loop2.
For run_loop1_cla == 0 i.e. both loops running on CPU -> Loop1 Utilization = ~77.5% (measured using profiling
GPIO2) -> Loop2 Utilization = ~6% (measured using profiling GPIO3) -> Background task in a while loop ->
Total CPU utilization is greater than Utilization bound (UB) Hence the system is non-schedulable, lower priority
task (Loop2) execution never completes (no toggling observed on GPIO3) and also background task never gets
chance to execute
For run_loop1_cla == 1 i.e. high frequency control loop (loop1) is offloaded to CLA while loop2 runs on CPU ->
Loop1 Utilization (CLA) = ~73% -> Loop2 Utilization (CPU)= ~6% -> Total CPU utilization has come down to just
~6% Hence the system is perfectly schedulable, no miss happens for any of the loops and offloading of loop1 to
CLA saves CPU bandwidth to execute background tasks as well
For quick inspection of the example functionality, constant DC HIGH/LOW inputs can be provided to the analog
channels instead of varying analog voltages. The target value for both the loops are set as some intermediate
value i.e. 3500 corresponds to ~2.8V. Now since the sensed inputs are constant and not same as target so the
controller outputs will get saturated soon to either 1 or 0. Thus the "duty" variable can take only fixed values
based on the equations used in the loops. Infact the duty output would be very intutive, for instance if both inputs
are LOW(GND), the controller will try to produce the maximum duty as the target is higher than sensed value
hence the duty should be 1.0(0.2 + 0.8) but will get saturated to 0.9(the maximum value defined). Similarly if
both inputs are made HIGH, the duty will be 0.1 (the minimum saturation value defined). The final duty table is
shown below :
External Connections
• Observe GPIO2 (Loop1 Profiling) on oscilloscope
• Observe GPIO3 (Loop2 Profiling) on oscilloscope
• Observe GPIO0 (EPWM1A Output) on oscilloscope
• Provide constant HIGH(3.3V)/LOW(0V) on both ADCA Ch0 and ADCB Ch2 for quick validation, the following
duty value should be observable at EPWM1A for various combinations if the system is perfectly schedulable
i.e. both loops gets chance to execute properly :- A0 B2 duty GND GND 0.9 3.3V GND 0.2 GND 3.3V 0.8
3.3V 3.3V 0.1
Note :- The optimization is OFF for this project and all the profiling data quoted above corresponds to this case.
7.6.2.8 Handling shared resources across C28x and CLA
FILE: cla_ex7_shared_resource_handling.c
This example showcases how to handle shared resource challenges across C28x and CLA. As the peripherals
are shared between CLA and the CPU, overlapping read-modify-write to the registers by them can lead to data
race conditions ultimately leading to data violation or incorrect functionality. In this example, CPU ISR and CLA
tasks runs independently. CPU ISR gets triggered by EPWM4 @10KHz and toggles the EPWM1B output via
software by controlling CSFB bits of AQCSFRC. CLA task gets triggered by EPWM5 @100Khz and toggles the
EPWM1A output via software by controlling CSFA bits of AQCSFRC. Thus in this process both CPU and CLA

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do read-modify -write to AQCSFRC register independently at different frequencies so there is chance of race
condition and updates due to one of them can get lost/. overwritten. This can be clearly observed by updating
"phase_shift_ON" to 0U and probing the EPWM1A and 1B outputs on a scope.
This is a standard critical section problem and can be handled by software handshaking mechanism like
mutex etc. But most of the real-time control applications are time-sensitive and cannot afford addition software
overhead hence this example suggests an alternative hardware based technique to avoid shared resource
conflicts between CPU and CLA. The phase shifting mechanism of the EPWM modules is utilized to schedule
the CLA task and CPU ISR as desired. EPWM4 generates a synchronous pulse every ZERO event and provides
a phase shift of 20 cycles to EPWM5. This way both CLA task and C28x ISR runs at original frequencies
i.e. 100KHz and 10KHz but CLA task leads with a phase offset of 20 cycles wrt CPU ISR. Hence concurrent
read-modify-writes to AQCSFRC never happens and the EPWM1A and EPWM1B outputs behave as desired
i.e. consistent 50 KHz PWM output on EPWM1A and 5 KHz PWM output on EPWM1B with a duty ~50% on
both should be generated. In order to utilize this phase shifting mechanism in this example, please make sure
"phase_shift_ON" is set to 1.
External Connections
• Observe GPIO0 (EPWM1A Output) on oscilloscope
• Observe GPIO1 (EPWM1B Output) on oscilloscope
• Observe GPIO2 (CLA Task Profiling) on oscilloscope
• Observe GPIO3 (CPU ISR Profiling) on oscilloscope
Note :- The phase offset value can easily be configured by updating TBPHS register to schedule the CLA task
and C28x ISR as desired depending upon the application need so as to avoid overlapping register writes by
CPU and CLA
Note :- The optimization is on and set to O2 for the project and all the results quoted correspond to this case.

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7.7 Instruction Set

This section describes the assembly language instructions of the control law accelerator. Also described are
parallel operations, conditional operations, resource constraints, and addressing modes. The instructions listed
here are independent from C28x and C28x+FPU instruction sets.
7.7.1 Instruction Descriptions
This section gives detailed information on the instruction set. Each instruction presents the following information:
• Operands
• Opcode
• Description
• Exceptions
• Pipeline
• Examples
• See also
The example INSTRUCTION is shown to familiarize you with the way each instruction is described. The example
describes the kind of information you find in each part of the individual instruction description and where to
obtain more information. CLA instructions follow the same format as the C28x instructions; the source operands
are always on the right and the destination operands are on the left.
The explanations for the syntax of the operands used in the instruction descriptions for the CLA are given in
Table 7-6.
Table 7-6. Operand Nomenclature
Symbol Description
#16FHi 16-bit immediate (hex or float) value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FHiHex 16-bit immediate hex value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits of an IEEE 32-bit floating-point value
#32Fhex 32-bit immediate value that represents an IEEE 32-bit floating-point value
#32F Immediate float value represented in floating-point representation
#0.0 Immediate zero
#SHIFT Immediate value of 1 to 32 used for arithmetic and logical shifts.
addr Opcode field indicating the addressing mode
CNDF Condition to test the flags in the MSTF register
FLAG Selected flags from MSTF register (OR) 8 bit mask indicating which floating-point status flags to change
MAR0 Auxiliary register 0
MAR1 Auxiliary register 1
MARx Either MAR0 or MAR1
mem16 16-bit memory location accessed using direct, indirect, or offset addressing modes
mem32 32-bit memory location accessed using direct, indirect, or offset addressing modes
MRa MR0 to MR3 registers
MRb MR0 to MR3 registers
MRc MR0 to MR3 registers
MRd MR0 to MR3 registers
MRe MR0 to MR3 registers
MRf MR0 to MR3 registers
MSTF CLA Floating-point Status Register
shift Opcode field indicating the number of bits to shift.
VALUE Flag value of 0 or 1 for selected flag (OR) 8 bit mask indicating the flag value; 0 or 1

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Each instruction has a table that gives a list of the operands and a short description. Instructions always have
the destination operands first followed by the source operands.
Table 7-7. INSTRUCTION dest, source1, source2 Short Description
Description
dest1 Description for the 1st operand for the instruction
source1 Description for the 2nd operand for the instruction
source2 Description for the 3rd operand for the instruction
Opcode This section shows the opcode for the instruction
Description Detailed description of the instruction execution is described. Any constraints on the operands imposed by the
processor or the assembler are discussed.
Restrictions Any constraints on the operands or use of the instruction imposed by the processor are discussed.
Pipeline This section describes the instruction in terms of pipeline cycles as described in Section 7.5
Example Examples of instruction execution. If applicable, register and memory values are given before and after instruction
execution. Some examples are code fragments while other examples are full tasks that assume the CLA is correctly
configured and the main CPU has passed the CLA data.
Operands Each instruction has a table that gives a list of the operands and a short description. Instructions always have the
destination operands first followed by the source operands.

7.7.2 Addressing Modes and Encoding

The CLA uses the same address to access data and registers as the main CPU. For example, if the main CPU
accesses an ePWM register at address 0x00 6800, then the CLA accesses the register using address 0x6800.
Since all CLA accessible memory and registers are within the low 64k x 16 of memory, only the low 16-bits of the
address are used by the CLA.
To address the CLA data memory, message RAMs and shared peripherals, the CLA supports two addressing
modes:
• Direct addressing mode: Uses the address of the variable or register directly.
• Indirect addressing with 16-bit post increment. This mode uses either XAR0 or XAR1.
The CLA does not use a data page pointer or a stack pointer. The two addressing modes are encoded as shown
Table 7-8.

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Table 7-8. Addressing Modes

Addressing Mode 'addr' Opcode Description
Field
Encode(1)
@dir 0000 Direct Addressing Mode
Example 1: MMOV32 MR1, @_VarA
Example 2: MMOV32 MR1, @_EPwm1Regs.CMPA.all
In this case, the 'mmmm mmmm mmmm mmmm' opcode field is populated with the 16-bit
address of the variable. This is the low 16-bits of the address to access the variable using the
main CPU.
For example, @_VarA populates the address of the variable VarA. and
@_EPwm1Regs.CMPA.all populates the address of the CMPA register.
*MAR0[#imm16]++ 0001 MAR0 Indirect Addressing with 16-bit Immediate Post Increment
*MAR1[#imm16]++ 0010 MAR1 Indirect Addressing with 16-bit Immediate Post Increment
addr = MAR0 (or MAR1) Access memory using the address stored in MAR0 (or MAR1).
MAR0 (or MAR1) += Then post increment MAR0 (or MAR1) by #imm16.
#imm16
Example 1: MMOV32 MR0, *MAR0[2]++
Example 2: MMOV32 MR1, *MAR1[-2]++
For a post increment of 0, the assembler accepts both *MAR0 and *MAR0[0]++.
The 'mmmm mmmm mmmm mmmm' opcode field is populated with the signed 16-bit pointer
offset. For example, if #imm16 is 2, then the opcode field is 0x0002. Likewise, if #imm16 is -2,
then the opcode field is 0xFFFE.
If addition of the 16-bit immediate causes overflow, then the value wraps around on a 16-bit
boundary.

(1) Values not shown are reserved.

Encoding for the shift fields in the MASR32, MLSR32 and MLSL32 instructions is shown in Table 7-9.
Table 7-9. Shift Field Encoding
Shift Value 'shift' Opcode
Field Encode
1 0000
2 0001
3 0010
.... ....
32 1111

For instructions that use MRx (where x can be 'a' through 'f') as operands, the trailing alphabet appears in the
opcode as a two-bit field. For example:

MMPYF32 MRa, MRb, MRc ||

MADDF32 MRd, MRe, MRf

whose opcode is,

LSW: 0000 ffee ddcc bbaa

MSW: 0111 1010 0000 0000

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The two-bit field specifies one of four working registers according to Table 7-10.
Table 7-10. Operand Encoding
Two-Bit Field Working Register
00 MR0
01 MR1
10 MR2
11 MR3

Table 7-11 shows the condition field encoding for conditional instructions such as MNEGF, MSWAPF, MBCNDD,
MCCNDD, and MRCNDD.
Table 7-11. Condition Field Encoding
Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag modification None

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition allows the ZF and NF flags to be modified when a conditional
operation is executed. All other conditions do not modify these flags.

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7.7.3 Instructions
The instructions are listed alphabetically.

Instruction Set Summary

MABSF32 MRa, MRb — 32-Bit Floating-Point Absolute Value...........................................................................863
MADD32 MRa, MRb, MRc — 32-Bit Integer Add................................................................................................864
MADDF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Addition........................................................................865
MADDF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Addition........................................................................867
MADDF32 MRa, MRb, MRc — 32-Bit Floating-Point Addition............................................................................869
MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa — 32-Bit Floating-Point Addition with Parallel Move...... 870
MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Addition with Parallel Move..... 871
MAND32 MRa, MRb, MRc — Bitwise AND.........................................................................................................873
MASR32 MRa, #SHIFT — Arithmetic Shift Right................................................................................................ 874
MBCNDD 16BitDest {, CNDF} — Branch Conditional Delayed......................................................................... 876
MCCNDD 16BitDest {, CNDF} — Call Conditional Delayed...............................................................................881
MCMP32 MRa, MRb — 32-Bit Integer Compare for Equal, Less Than or Greater Than....................................885
MCMPF32 MRa, MRb — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than.......................887
MCMPF32 MRa, #16FHi — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than...................888
MDEBUGSTOP — Debug Stop Task.................................................................................................................. 890
MEALLOW — Enable CLA Write Access to EALLOW Protected Registers....................................................... 891
MEDIS — Disable CLA Write Access to EALLOW Protected Registers............................................................. 892
MEINVF32 MRa, MRb — 32-Bit Floating-Point Reciprocal Approximation.........................................................893
MEISQRTF32 MRa, MRb — 32-Bit Floating-Point Square-Root Reciprocal Approximation.............................. 895
MF32TOI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer............................................... 897
MF32TOI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round..........................898
MF32TOI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Integer............................................... 899
MF32TOUI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer ............................901
MF32TOUI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round....... 902
MF32TOUI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer ........................... 903
MFRACF32 MRa, MRb — Fractional Portion of a 32-Bit Floating-Point Value................................................... 904
MI16TOF32 MRa, MRb — Convert 16-Bit Integer to 32-Bit Floating-Point Value .............................................. 905
MI16TOF32 MRa, mem16 — Convert 16-Bit Integer to 32-Bit Floating-Point Value ......................................... 906
MI32TOF32 MRa, mem32 — Convert 32-Bit Integer to 32-Bit Floating-Point Value ......................................... 907
MI32TOF32 MRa, MRb — Convert 32-Bit Integer to 32-Bit Floating-Point Value .............................................. 908
MLSL32 MRa, #SHIFT — Logical Shift Left........................................................................................................ 909
MLSR32 MRa, #SHIFT — Logical Shift Right..................................................................................................... 911
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply and
Accumulate with Parallel Move............................................................................................................................ 912
MMAXF32 MRa, MRb — 32-Bit Floating-Point Maximum...................................................................................915
MMAXF32 MRa, #16FHi — 32-Bit Floating-Point Maximum...............................................................................917
MMINF32 MRa, MRb — 32-Bit Floating-Point Minimum..................................................................................... 919
MMINF32 MRa, #16FHi — 32-Bit Floating-Point Minimum................................................................................. 921
MMOV16 MARx, MRa, #16I — Load the Auxiliary Register with MRa + 16-bit Immediate Value...................... 923
MMOV16 MARx, mem16 — Load MAR1 with 16-bit Value................................................................................ 926
MMOV16 mem16, MARx — Move 16-Bit Auxiliary Register Contents to Memory............................................. 929
MMOV16 mem16, MRa — Move 16-Bit Floating-Point Register Contents to Memory....................................... 930
MMOV32 mem32, MRa — Move 32-Bit Floating-Point Register Contents to Memory ...................................... 932
MMOV32 mem32, MSTF — Move 32-Bit MSTF Register to Memory.................................................................934
MMOV32 MRa, mem32 {, CNDF} — Conditional 32-Bit Move........................................................................... 935
MMOV32 MRa, MRb {, CNDF} — Conditional 32-Bit Move................................................................................937
MMOV32 MSTF, mem32 — Move 32-Bit Value from Memory to the MSTF Register.........................................939
MMOVD32 MRa, mem32 — Move 32-Bit Value from Memory with Data Copy..................................................940
MMOVF32 MRa, #32F — Load the 32-Bits of a 32-Bit Floating-Point Register.................................................. 942

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MMOVI16 MARx, #16I — Load the Auxiliary Register with the 16-Bit Immediate Value.................................... 944
MMOVI32 MRa, #32FHex — Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate............. 946
MMOVIZ MRa, #16FHi — Load the Upper 16-Bits of a 32-Bit Floating-Point Register ......................................948
MMOVZ16 MRa, mem16 — Load MRx with 16-Bit Value...................................................................................949
MMOVXI MRa, #16FLoHex — Move Immediate Value to the Lower 16-Bits of a Floating-Point Register.........950
MMPYF32 MRa, MRb, MRc — 32-Bit Floating-Point Multiply.............................................................................951
MMPYF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Multiply ....................................................................... 952
MMPYF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Multiply ....................................................................... 954
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Add...956
MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply with Parallel Move...... 958
MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Multiply with Parallel Move...... 960
MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Subtract
.............................................................................................................................................................................961
MNEGF32 MRa, MRb{, CNDF} — Conditional Negation....................................................................................963
MNOP — No Operation....................................................................................................................................... 965
MOR32 MRa, MRb, MRc — Bitwise OR............................................................................................................. 966
MRCNDD {CNDF} — Return Conditional Delayed..............................................................................................967
MSETFLG FLAG, VALUE — Set or Clear Selected Floating-Point Status Flags............................................... 970
MSTOP — Stop Task...........................................................................................................................................971
MSUB32 MRa, MRb, MRc — 32-Bit Integer Subtraction.................................................................................... 973
MSUBF32 MRa, MRb, MRc — 32-Bit Floating-Point Subtraction.......................................................................974
MSUBF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Subtraction...................................................................975
MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Subtraction with Parallel Move....
977
MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Subtraction with Parallel Move....
978
MSWAPF MRa, MRb {, CNDF} — Conditional Swap......................................................................................... 979
MTESTTF CNDF — Test MSTF Register Flag Condition....................................................................................981
MUI16TOF32 MRa, mem16 — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value........................983
MUI16TOF32 MRa, MRb — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value............................ 984
MUI32TOF32 MRa, mem32 — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value........................985
MUI32TOF32 MRa, MRb — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value............................ 986
MXOR32 MRa, MRb, MRc — Bitwise Exclusive Or............................................................................................ 987

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MABSF32 MRa, MRb

32-Bit Floating-Point Absolute Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0010 0000

Description
The absolute value of MRb is loaded into MRa. Only the sign bit of the operand is
modified by the MABSF32 instruction.

if (MRb < 0) {MRa = -MRb};

else {MRa = MRb};

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = 0;
ZF = 0;
if ( MRa(30:23) == 0) ZF = 1;

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #-2.0 ; MR0 = -2.0 (0xC0000000)
MABSF32 MR0, MR0 ; MR0 = 2.0 (0x40000000), ZF = NF = 0
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MABSF32 MR0, MR0 ; MR0 = 5.0 (0x40A00000), ZF = NF = 0
MMOVIZ MR0, #0.0 ; MR0 = 0.0
MABSF32 MR0, MR0 ; MR0 = 0.0 ZF = 1, NF = 0

See also
MNEGF32 MRa, MRb {, CNDF}

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MADD32 MRa, MRb, MRc

32-Bit Integer Add

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode
LSW: 0000 0000 000cc bbaa
MSW: 0111 1110 1100 0000

Description
32-bit integer addition of MRb and MRc.

MRa(31:0) = MRb(31:0) + MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; };

Pipeline
This is a single-cycle instruction.

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A + B + C
;
_Cla1Task1:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MADD32 MR3, MR0, MR1 ; A + B
MADD32 MR3, MR2, MR3 ; A + B + C = -4 (0xFFFFFFFC)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; end of task

See also
MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MADDF32 MRa, #16FHi, MRb

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description
Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, MRb, #16FHi.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, #2.0, MR1 ; MR0 = 2.0 + MR1
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, #-2.5, MR3 ; MR2 = -2.5 + MR3
; Add to MR3 the value 0x3FC00000 (1.5)
; Store the result in MR3
MADDF32 MR3, #0x3FC0, MR3 ; MR3 = 1.5 + MR3

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MADDF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Addition

See also
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, #16FHi

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description
Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, #16FHi, MRb.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

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MADDF32 MRa, MRb, #16FHi (continued)

32-Bit Floating-Point Addition

Example 1
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrement the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

Example 2
; Show the basic operation of MADDF32
;
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, MR1, #2.0 ; MR0 = MR1 + 2.0
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, MR3, #-2.5 ; MR2 = MR3 + (-2.5)
; Add to MR0 the value 0x3FC00000 (1.5)
; Store the result in MR0
MADDF32 MR0, MR0, #0x3FC0 ; MR0 = MR0 + 1.5

See also
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, MRc

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 000 0000 00cc bbaa
MSW: 0111 1100 0010 0000

Description
Add the contents of MRc to the contents of MRb and load the result into MRa.

MRa = MRb + MRc;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example
; Given M1, X1, and B1 are 32-bit floating-point numbers
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0,@M1 ; Load MR0 with M1
MMOV32 MR1,@X1 ; Load MR1 with X1
MMPYF32 MR1,MR1,MR0 ; Multiply M1*X1
|| MMOV32 MR0,@B1 ; and in parallel load MR0 with B1
MADDF32 MR1,MR1,MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1,MR1 ; Store the result
MSTOP ; end of task

See also
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa

32-Bit Floating-Point Addition with Parallel Move

Operands MRd CLA floating-point destination register for the MADDF32 (MR0 to
MR3)
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the destination of the MMOV32.
MRa CLA floating-point source register for the MMOV32 (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0101 ffee ddaa addr

Description
Perform an MADDF32 and a MMOV32 in parallel. Add MRf to the contents of MRe
and store the result in MRd. In parallel move the contents of MRa to the 32-bit location
mem32.

MRd = MRe + MRf;

[mem32] = MRa;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline
Both MADDF32 and MMOV32 complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) + C
;
_Cla1Task2:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @_C ; and in parallel load MR0 with C
MADDF32 MR1, MR1, MR0 ; Add (A*B) to C
|| MMOV32 @_Y2, MR1 ; and in parallel store A*B
MMOV32 @_Y3, MR1 ; Store the A*B + C
MSTOP ; end of task

See also
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32

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MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Addition with Parallel Move

Operands MRd CLA floating-point destination register for the MADDF32 (MR0 to
MR3).
MRd cannot be the same register as MRa.
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRa CLA floating-point destination register for the MMOV32 (MR0 to
MR3).
MRa cannot be the same register as MRd.
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the source for the MMOV32.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0001 ffee ddaa addr

Description
Perform an MADDF32 and a MMOV32 operation in parallel. Add MRf to the contents
of MRe and store the result in MRd. In parallel move the contents of the 32-bit location
mem32 to MRa.

MRd = MRe + MRf;

MRa = [mem32];

Restrictions
The destination register for the MADDF32 and the MMOV32 must be unique. That is,
MRa and MRd cannot be the same register.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
The MMOV32 Instruction sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; };

Pipeline
The MADDF32 and the MMOV32 both complete in a single cycle.

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MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Addition with Parallel Move

Example 1
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y1 = A + 4B
; Y2 = A + C
;
_Cla1Task1:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, #4.0 ; Multiply 4 * B
|| MMOV32 MR2, @C and in parallel load C
MADDF32 MR3, MR0, MR1 ; Add A + 4B
MADDF32 MR3, MR0, MR2 ; Add A + C
|| MMOV32 @Y1, MR3 ; and in parallel store A+4B
MMOV32 @Y2, MR3 ; store A + C MSTOP
; end of task

Example 2
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y3 = (A + B)
; Y4 = (A + B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MADDF32 MR1, MR1, MR0 ; Add A+B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A+B) by C
|| MMOV32 @Y3, MR1 ; and in parallel store A+B
MMOV32 @Y4, MR1 ; Store the (A+B) * C
MSTOP ; end of task

See also
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MAND32 MRa, MRb, MRc

Bitwise AND

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0110 0000

Description
Bitwise AND of MRb with MRc.

MRa(31:0) = MRb(31:0) AND MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA
MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1, #0xFEDC
; 0101 AND 0101 = 0101 (5)
; 0101 AND 0100 = 0100 (4)
; 0101 AND 0011 = 0001 (1)
; 0101 AND 0010 = 0000 (0)
; 1010 AND 1111 = 1010 (A)
; 1010 AND 1110 = 1010 (A)
; 1010 AND 1101 = 1000 (8)
; 1010 AND 1100 = 1000 (8)
MAND32 MR2, MR1, MR0 ; MR3 = 0x5410AA88

See also
MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MASR32 MRa, #SHIFT

Arithmetic Shift Right

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 0100 0000

Description
Arithmetic shift right of MRa by the number of bits indicated. The number of bits can be 1
to 32.

MARa(31:0) = Arithmetic Shift(MARa(31:0) by #SHIFT bits);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate
; m2 = m2/2
; x2 = x2/4
; b2 = b2/8
;
_Cla1Task2:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MASR32 MR0, #1 ; MR0 = 16 (0x00000010)
MASR32 MR1, #2 ; MR1 = 16 (0x00000010)
MASR32 MR2, #3 ; MR2 = -16 (0xFFFFFFF0)
MMOV32 @_m2, MR0 ; store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

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MASR32 MRa, #SHIFT (continued)

Arithmetic Shift Right

See also
MADD32 MRa, MRb, MRc
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MBCNDD 16BitDest {, CNDF}

Branch Conditional Delayed

Operands 16BitDest 16-bit destination if condition is true

CNDF Optional condition tested

Opcode
LSW: dest dest dest dest
MSW: 0111 1001 1000 cndf

Description
If the specified condition is true, then branch by adding the signed 16BitDest value to the
MPC value. Otherwise, continue without branching. If the address overflows, the address
wraps around. Therefore, a value of "0xFFFE" puts the MPC back to the MBCNDD
instruction.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE) MPC += 16BitDest;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Restrictions
The MBCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more information.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Pipeline
The MBCNDD instruction alone is a single-cycle instruction. As shown in Table 7-12, 6
instruction slots are executed for each branch; 3 slots before the branch instruction (I2-I4)
and 3 slots after the branch instruction (I5-I7). The total number of cycles for a branch
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled. The
effective number of cycles for a branch can, therefore, range from 1 to 7 cycles. The
number of cycles for a branch taken cannot be the same as for a branch not taken.
Referring to Table 7-12 and Table 7-13, the instructions before and after MBCNDD have
the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MBCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to branch or not when MBCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3, and I4
– The three instructions proceeding MBCNDD can change MSTF flags but have no
effect on whether the MBCNDD instruction branches or not. This is because the
flag modification occurs after the D2 phase of the MBCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• I5, I6, and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

<Instruction 1> ; I1 Last instruction that can affect flags for

; the MBCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MBCNDD _Skip, NEQ ; Branch to Skip if not eqal to zero
; Three instructions after MBCNDD are always
; executed whether the branch is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....
_Skip:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
....
....
MSTOP
....

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Table 7-12. Pipeline Activity for MBCNDD, Branch Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
I10 I9 I8 I7 I6 I5
I10 I9 I8 I7 I6
I10 I9 I8 I7
I10 I9 I8
I10 I9
I10

Table 7-13. Pipeline Activity for MBCNDD, Branch Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
d3 d2 d1 I7 I6 I5
d3 d2 d1 I7 I6
d3 d2 d1 I7
d3 d2 d1
d3 d2
d3

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Example 1
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task1:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MNOP
MNOP
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @RampState ; Execute if (A) branch not taken
MMOVXI MR2, #RAMPMASK ; Execute if (A) branch not taken
MOR32 MR1, MR2 ; Execute if (A) branch not taken
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MCMPF32 MR0,#0.01 ; Affects flags for 2nd MBCNDD (B)
MNOP
MNOP
MNOP
MBCNDD Skip2,NEQ ; (B) If State != 0.01, go to Skip2
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @CoastState ; Execute if (B) branch not taken
MMOVXI MR2, #COASTMASK ; Execute if (B) branch not taken
MOR32 MR1, MR2 ; Execute if (B) branch not taken
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP
Skip2:
MMOV32 MR3, @SteadyState ; Executed if (B) branch taken
MMOVXI MR2, #STEADYMASK ; Executed if (B) branch taken
MOR32 MR3, MR2 ; Executed if (B) branch taken
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Example 2
; This example is the same as Example 1, except
; the code is optimized to take advantage of delay slots
;
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MMOV32 MR3, @SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken
Skip2:
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

See also
MCCNDD 16BitDest, CNDF
MRCNDD CNDF

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MCCNDD 16BitDest {, CNDF}

Call Conditional Delayed

Operands 16BitDest 16-bit destination if condition is true

CNDF Optional condition to be tested

Opcode
LSW: dest dest dest dest
MSW: 0111 1001 1001 cndf

Description
If the specified condition is true, then store the return address in the RPC field of MSTF
and make the call by adding the signed 16BitDest value to the MPC value. Otherwise,
continue code execution without making the call. If the address overflows, the address
wraps around. Therefore a value of "0xFFFE" puts the MPC back to the MCCNDD
instruction.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE)
{
RPC = return address;
MPC += 16BitDest;
};

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation if no CNDF field is specified. This condition allows
the ZF and NF flags to be modified when a conditional operation is executed.
All other conditions do not modify these flags.

Restrictions
The MCCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more details.

Flags
This instruction does not modify flags in the MSTF register.

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

Flag TF ZF NF LUF LVF

Modified No No No No No

Pipeline
The MCCNDD instruction alone is a single-cycle instruction. As shown in Table 7-14, 6
instruction slots are executed for each call; 3 before the call instruction (I2-I4) and 3 after
the call instruction (I5-I7). The total number of cycles for a call taken or not taken depends
on the usage of these slots. That is, the number of cycles depends on how many slots are
filled with a MNOP as well as which slots are filled. The effective number of cycles for a
call can, therefore, range from 1 to 7 cycles. The number of cycles for a call taken cannot
be the same as for a call not taken.
Referring to the following code fragment and the pipeline diagrams in Table 7-14 and
Table 7-15, the instructions before and after MCCNDD have the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MCCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to branch or not when MCCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3, and I4
– The three instructions proceeding MCCNDD can change MSTF flags but have no
effect on whether the MCCNDD instruction makes the call or not. This is because
the flag modification occurs after the D2 phase of the MCCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• I5, I6, and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

<Instruction 1> ; I1 Last instruction that can affect flags for

; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return
MRCNDD UNC ; Return to <Instruction 8>, unconditional
; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
....
MSTOP

Table 7-14. Pipeline Activity for MCCNDD, Call Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
I7 I7 I6 I5 MCCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
etc .... I10 I9 I8 I7 I6 I5
.... I10 I9 I8 I7 I6
.... I10 I9 I8 I7
.... I10 I9 I8
I10 I9
I10

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

Table 7-15. Pipeline Activity for MCCNDD, Call Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
I7 (1) I7 I6 I5 MCCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
etc .... d3 d2 d1 I7 I6 I5
.... d3 d2 d1 I7 I6
.... d3 d2 d1 I7
.... d3 d2 d1
d3 d2
d3

(1) The RPC value in the MSTF register points to the instruction following I7 (instruction I8).

See also
MBCNDD #16BitDest, CNDF
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32
MRCNDD CNDF

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MCMP32 MRa, MRb

32-Bit Integer Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0010 0000

Description
Set ZF and NF flags on the result of MRa - MRb where MRa and MRb are 32-bit integers.
For a floating-point compare, refer to MCMPF32.

Note
A known hardware issue exists in the MCMP32 instruction. Signed-integer
comparisons using MCMP32 alone set the status bits in a way that is not useful
for comparison when the difference between the two operands is too large,
such as when the inputs have opposite sign and are near the extreme 32-bit
signed values. This affects both signed and unsigned integer comparisons.
The compiler (version 18.1.5.LTS or higher) has implemented a workaround for
this issue. The compiler checks the upper bits of the operands by performing
a floating point comparison before proceeding to do the integer comparison or
subtraction.
The compiler flag --cla_signed_compare_workaround enables this workaround.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example
; Behavior of ZF and NF flags for different comparisons
;
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MCMP32 MR2, MR2 ; NF = 0, ZF = 1
MCMP32 MR0, MR1 ; NF = 1, ZF = 0
MCMP32 MR1, MR0 ; NF = 0, ZF = 0

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MCMP32 MRa, MRb (continued)

32-Bit Integer Compare for Equal, Less Than or Greater Than

See also
MADD32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MCMPF32 MRa, MRb

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0000 0000

Description
Set ZF and NF flags on the result of MRa - MRb. The MCMPF32 instruction is performed
as a logical compare operation. This is possible because of the IEEE format offsetting the
exponent. Basically the bigger the binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero is treated as positive zero.
• A denormalized value is treated as positive zero.
• Not-a-Number (NaN) is treated as infinity.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example
; Behavior of ZF and NF flags for different comparisons
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, MR0 ; ZF = 0, NF = 1
MCMPF32 MR0, MR1 ; ZF = 0, NF = 0
MCMPF32 MR0, MR0 ; ZF = 1, NF = 0

See also
MCMPF32 MRa, #16FHi
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MCMPF32 MRa, #16FHi

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 1100 00aa

Description
Compare the value in MRa with the floating-point value represented by the immediate
operand. Set the ZF and NF flags on (MRa - #16FHi:0).
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
The MCMPF32 instruction is performed as a logical compare operation. This is possible
because of the IEEE floating-point format offsets the exponent. Basically the bigger the
binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero is treated as positive zero.
• Denormalized value is treated as positive zero.
• Not-a-Number (NaN) is treated as infinity.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == #16FHi:0) {ZF=1, NF=0;}

If(MRa > #16FHi:0) {ZF=0, NF=0;}
If(MRa < #16FHi:0) {ZF=0, NF=1;}

Pipeline
This is a single-cycle instruction

Example 1
; Behavior of ZF and NF flags for different comparisons
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, #-2.2 ; ZF = 0, NF = 0
MCMPF32 MR0, #6.5 ; ZF = 0, NF = 1
MCMPF32 MR0, #5.0 ; ZF = 1, NF = 0

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MCMPF32 MRa, #16FHi (continued)

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Example 2
; X is an array of 32-bit floating-point values
; and has length elements. Find the maximum value in
; the array and store the value in Result
;
; Note: MCMPF32 and MSWAPF can be replaced with MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also
MCMPF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MDEBUGSTOP

Debug Stop Task

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 0110 0000

Description
When CLA breakpoints are enabled, the MDEBUGSTOP instruction is used to halt a task
so that the task can be debugged. That is, MDEBUGSTOP is the CLA breakpoint. If CLA
breakpoints are not enabled, the MDEBUGSTOP instruction behaves like a MNOP. Unlike
the MSTOP, the MIRUN flag is not cleared and an interrupt is not issued. A single-step or
run operation continues execution of the task.

Restrictions
The MDEBUGSTOP instruction cannot be placed 3 instructions before or after a
MBCNDD, MCCNDD, or MRCNDD instruction.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

See also
MSTOP

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MEALLOW

Enable CLA Write Access to EALLOW Protected Registers

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1001 0000

Description
This instruction sets the MEALLOW bit in the CLA status register MSTF. When this bit
is set, the CLA is allowed write access to EALLOW protected registers. To again protect
against CLA writes to protected registers, use the MEDIS instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the CLA
while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden using the JTAG port, allowing full
control of register accesses during debug from Code Composer Studio.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also
MEDIS

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MEDIS

Disable CLA Write Access to EALLOW Protected Registers

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1011 0000

Description
This instruction clears the MEALLOW bit in the CLA status register MSTF. When this bit is
clear, the CLA is not allowed write access to EALLOW-protected registers. To enable CLA
writes to protected registers, use the MEALLOW instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the CLA
while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden using the JTAG port, allowing full
control of register accesses during debug from the Code Composer Studio™ IDE.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also
MEALLOW

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MEINVF32 MRa, MRb

32-Bit Floating-Point Reciprocal Approximation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0000 0000

Description
This operation generates an estimate of 1/X in 32-bit floating-point format accurate to
approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:

Ye = Estimate(1/X);
Ye = Ye*(2.0 - Ye*X);
Ye = Ye*(2.0 - Ye*X);

After two iterations of the Newton-Raphson algorithm, you get an exact answer
accurate to the 32-bit floating-point format. On each iteration, the mantissa bit accuracy
approximately doubles. The MEINVF32 operation does not generate a negative zero,
DeNorm, or NaN value.

MRa = Estimate of 1/MRb;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEINVF32 generates an underflow condition.
• LVF = 1 if MEINVF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

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MEINVF32 MRa, MRb (continued)

32-Bit Floating-Point Reciprocal Approximation

Example
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also
MEISQRTF32 MRa, MRb

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MEISQRTF32 MRa, MRb

32-Bit Floating-Point Square-Root Reciprocal Approximation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0100 0000

Description
This operation generates an estimate of 1/sqrt(X) in 32-bit floating-point format accurate
to approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:

Ye = Estimate(1/sqrt(X));
Ye = Ye*(1.5 - Ye*Ye*X/2.0);
Ye = Ye*(1.5 - Ye*Ye*X/2.0);

After 2 iterations of the Newton-Raphson algorithm, you get an exact answer accurate to
the 32-bit floating-point format. On each iteration, the mantissa bit accuracy approximately
doubles. The MEISQRTF32 operation does not generate a negative zero, DeNorm, or
NaN value.

MRa = Estimate of 1/sqrt (MRb);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEISQRTF32 generates an underflow condition.
• LVF = 1 if MEISQRTF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

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MEISQRTF32 MRa, MRb (continued)

32-Bit Floating-Point Square-Root Reciprocal Approximation

Example
; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

See also
MEINVF32 MRa, MRb

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MF32TOI16 MRa, MRb

Convert 32-Bit Floating-Point Value to 16-Bit Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1110 0000

Description
Convert a 32-bit floating point value in MRb to a 16-bit integer and truncate. The result is
stored in MRa.

MRa(15:0) = F32TOI16(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MF32TOI16 MR1, MR0 ; MR1(15:0) = MF32TOI16(MR0) = 0x0005
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVIZ MR2, #-5.0 ; MR2 = -5.0 (0xC0A00000)
MF32TOI16 MR3, MR2 ; MR3(15:0) = MF32TOI16(MR2) = -5 (0xFFFB)
; MR3(31:16) = Sign extension of MR3(15) = 0xFFFF

See also
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOI16R MRa, MRb

Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0110 0000

Description
Convert the 32-bit floating point value in MRb to a 16-bit integer and round to the nearest
even value. The result is stored in MRa.

MRa(15:0) = F32TOI16round(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x3FD9 ; MR0(31:16) = 0x3FD9
MMOVXI MR0, #0x999A ; MR0(15:0) = 0x999A
; MR0 = 1.7 (0x3FD9999A)
MF32TOI16R MR1, MR0 ; MR1(15:0) = MF32TOI16round (MR0) = 2 (0x0002)
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVF32 MR2, #-1.7 ; MR2 = -1.7 (0xBFD9999A)
MF32TOI16R MR3, MR2 ; MR3(15:0) = MF32TOI16round (MR2) = -2 (0xFFFE)
; MR3(31:16) = Sign extension of MR2(15) = 0xFFFF

See also
MF32TOI16 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOI32 MRa, MRb

Convert 32-Bit Floating-Point Value to 32-Bit Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0110 0000

Description
Convert the 32-bit floating-point value in MRb to a 32-bit integer value and truncate. Store
the result in MRa.

MRa = F32TOI32(MRb);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example 1
MMOVF32 MR2, #11204005.0 ; MR2 = 11204005.0 (0x4B2AF5A5)
MF32TOI32 MR3, MR2 ; MR3 = MF32TOI32(MR2) = 11204005 (0x00AAF5A5)
MMOVF32 MR0, #-11204005.0 ; MR0 = -11204005.0 (0xCB2AF5A5)
MF32TOI32 MR1, MR0 ; MR1 = MF32TOI32(MR0) = -11204005 (0xFF550A5B)

Example 2
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X, and B from IQ24 to float
;
_Cla1Task2:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

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MF32TOI32 MRa, MRb (continued)

Convert 32-Bit Floating-Point Value to 32-Bit Integer

See also
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MF32TOUI16 MRa, MRb

Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1010 0000

Description
Convert the 32-bit floating point value in MRb to an unsigned 16-bit integer value and
truncate to zero. The result is stored in MRa. To instead round the integer to the nearest
even value, use the MF32TOUI16R instruction.

MRa(15:0) = F32TOUI16(MRb);
MRa(31:16) = 0x0000;

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #9.0 ; MR0 = 9.0 (0x41100000)
MF32TOUI16 MR1, MR0 ; MR1(15:0) = MF32TOUI16(MR0) = 9 (0x0009)
; MR1(31:16) = 0x0000
MMOVIZ MR2, #-9.0 ; MR2 = -9.0 (0xC1100000)
MF32TOUI16 MR3, MR2 ; MR3(15:0) = MF32TOUI16(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also
MF32TOI16 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI16R MRa, MRb

Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1100 0000

Description
Convert the 32-bit floating-point value in MRb to an unsigned 16-bit integer and round to
the closest even value. The result is stored in MRa. To instead truncate the converted
value, use the MF32TOUI16 instruction.

MRa(15:0) = MF32TOUI16round(MRb);
MRa(31:16) = 0x0000;

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x412C ; MR0 = 0x412C
MMOVXI MR0, #0xCCCD ; MR0 = 0xCCCD ; MR0 = 10.8 (0x412CCCCD)
MF32TOUI16R MR1, MR0 ; MR1(15:0) = MF32TOUI16round(MR0) = 11 (0x000B)
; MR1(31:16) = 0x0000
MMOVF32 MR2, #-10.8 ; MR2 = -10.8 (0x0xC12CCCCD)
MF32TOUI16R MR3, MR2 ; MR3(15:0) = MF32TOUI16round(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI32 MRa, MRb

Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1010 0000

Description
Convert the 32-bit floating-point value in MRb to an unsigned 32-bit integer and store the
result in MRa.

MRa = F32TOUI32(MRb);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #12.5 ; MR0 = 12.5 (0x41480000)
MF32TOUI32 MR0, MR0 ; MR0 = MF32TOUI32 (MR0) = 12 (0x0000000C)
MMOVIZ MR1, #-6.5 ; MR1 = -6.5 (0xC0D00000)
MF32TOUI32 MR2, MR1 ; MR2 = MF32TOUI32 (MR1) = 0.0 (0x00000000)

See also
MF32TOI32 MRa, MRb
MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MFRACF32 MRa, MRb

Fractional Portion of a 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0000 0000

Description
Returns in MRa the fractional portion of the 32-bit floating-point value in MRb

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR2, #19.625 ; MR2 = 19.625 (0x419D0000)
MFRACF32 MR3, MR2 ; MR3 = MFRACF32(MR2) = 0.625 (0x3F200000)0)

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MI16TOF32 MRa, MRb

Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1000 0000

Description
Convert the 16-bit signed integer in MRb to a 32-bit floating-point value and store the
result in MRa.

MRa = MI16TOF32(MRb);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x0000 ; MR0(31:16) = 0.0 (0x0000)
MMOVXI MR0, #0x0004 ; MR0(15:0) = 4.0 (0x0004)
MI16TOF32 MR1, MR0 ; MR1 = MI16TOF32 (MR0) = 4.0 (0x40800000)
MMOVIZ MR2, #0x0000 ; MR2(31:16) = 0.0 (0x0000)
MMOVXI MR2, #0xFFFC ; MR2(15:0) = -4.0 (0xFFFC)
MI16TOF32 MR3, MR2 ; MR3 = MI16TOF32 (MR2) = -4.0 (0xC0800000)
MSTOP

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI16TOF32 MRa, mem16

Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location to be converted

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 00aa addr

Description
Convert the 16-bit signed integer indicated by the mem16 pointer to a 32-bit floating-point
value and store the result in MRa.

MRa = MI16TOF32[mem16];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction:

Example
; Assume A = 4 (0x0004)
; B = -4 (0xFFFC)
MI16TOF32 MR0, @_A ; MR0 = MI16TOF32(A) = 4.0 (0x40800000)
MI16TOF32 MR1, @_B ; MR1 = MI16TOF32(B) = -4.0 (0xC0800000

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI32TOF32 MRa, mem32

Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory source for the MMOV32 operation.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 01aa addr

Description
Convert the 32-bit signed integer indicated by mem32 to a 32-bit floating-point value and
store the result in MRa.

MRa = MI32TOF32[mem32];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X, and B from IQ24 to float
;
_Cla1Task3:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MI32TOF32 MRa, MRb

Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1000 0000

Description
Convert the signed 32-bit integer in MRb to a 32-bit floating-point value and store the
result in MRa.

MRa = MI32TOF32(MRb);

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR2, #0x1111 ; MR2(31:16) = 4369 (0x1111)
MMOVXI MR2, #0x1111 ; MR2(15:0) = 4369 (0x1111)
; MR2 = +286331153 (0x11111111)
MI32TOF32 MR3, MR2 ; MR3 = MI32TOF32 (MR2) = 286331153.0 (0x4D888888)

See also
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MLSL32 MRa, #SHIFT

Logical Shift Left

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1100 0000

Description
Logical shift-left of MRa by the number of bits indicated. The number of bits can be 1 to
32.

MARa(31:0) = Logical Shift Left(MARa(31:0) by #SHIFT bits);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate:
; m2 = m2*2
; x2 = x2*4
; b2 = b2*8
;
_Cla1Task3:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MLSL32 MR0, #1 ; MR0 = 64 (0x00000040)
MLSL32 MR1, #2 ; MR1 = 256 (0x00000100)
MLSL32 MR2, #3 ; MR2 = -1024 (0xFFFFFC00)
MMOV32 @_m2, MR0 ; Store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

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MLSL32 MRa, #SHIFT (continued)

Logical Shift Left

See also
MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MLSR32 MRa, #SHIFT

Logical Shift Right

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1000 0000

Description
Logical shift-right of MRa by the number of bits indicated. The number of bits can be 1 to
32. Unlike the arithmetic shift (MASR32), the logical shift does not preserve the number's
sign bit. Every bit in the operand is moved the specified number of bit positions, and the
vacant bit positions are filled in with zeros.

MARa(31:0) = Logical Shift Right(MARa(31:0) by #SHIFT bits);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1;}

Pipeline
This is a single-cycle instruction.

Example
; Illustrate the difference between MASR32 and MLSR32
MMOVIZ MR0, #0xAAAA ; MR0 = 0xAAAA5555
MMOVXI MR0, #0x5555
MMOV32 MR1, MR0 ; MR1 = 0xAAAA5555
MMOV32 MR2, MR0 ; MR2 = 0xAAAA5555
MASR32 MR1, #1 ; MR1 = 0xD5552AAA
MLSR32 MR2, #1 ; MR2 = 0x55552AAA
MASR32 MR1, #1 ; MR1 = 0xEAAA9555
MLSR32 MR2, #1 ; MR2 = 0x2AAA9555
MASR32 MR1, #6 ; MR1 = 0xFFAAAA55
MLSR32 MR2, #6 ; MR2 = 0x00AAAA55

See also
MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Operands MR3 floating-point destination/source register MR3 for the add

operation
MR2 CLA floating-point source register MR2 for the add operation
MRd CLA floating-point destination register (MR0 to MR3) for the
multiply operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the multiply
operation
MRf CLA floating-point source register (MR0 to MR3) for the multiply
operation
MRa CLA floating-point destination register for the MMOV32 operation
(MR0 to MR3).
MRa cannot be MR3 or the same register as MRd.
mem32 32-bit source for the MMOV32 operation

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0011 ffee ddaa addr

Description
Multiply and accumulate the contents of floating-point registers and move from register to
memory. The destination register for the MMOV32 cannot be the same as the destination
registers for the MMACF32.

MR3 = MR3 + MR2;

MRd = MRe * MRf;
MRa = [mem32];

Restrictions
The destination registers for the MMACF32 and the MMOV32 must be unique. That is,
MRa cannot be MR3 and MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMACF32 (add or multiply) generates an underflow condition.
• LVF = 1 if MMACF32 (add or multiply) generates an overflow condition.
MMOV32 sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline
MMACF32 and MMOV32 complete in a single cycle.

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Example 1
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3 M
MACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D
MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E
MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Example 2
; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
; X2 = X1
; X1 = X0
; Y2 = Y1 ; Y1 = sum
;
_ClaTask2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0
; MR3 = X1*B1 + X2*B2, MR2 = X0*B0
; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2 M

MOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1
MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1
MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
MMOV32 @_Y1, MR3 ; Y1 = MR3
MSTOP ; end of task

See also
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

914 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024
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MMAXF32 MRa, MRb

32-Bit Floating-Point Maximum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0010 0000

Description
if(MRa < MRb) MRa = MRb;

Special cases for the output from the MMAXF32 operation:

• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == MRb) {ZF=1; NF=0;}

if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example 1
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR2, MR1 ; MR2 = -1.5, ZF = NF = 0
MMAXF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 1
MMAXF32 MR2, MR0 ; MR2 = 5.0, ZF = 0, NF = 1
MAXF32 MR0, MR2 ; MR2 = 5.0, ZF = 1, NF = 0

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MMAXF32 MRa, MRb (continued)

32-Bit Floating-Point Maximum

Example 2
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also
MCMPF32 MRa, MRb
MCMPF32 MRa, #16FHi
MMAXF32 MRa, #16FHi
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMAXF32 MRa, #16FHi

32-Bit Floating-Point Maximum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1001 0000 00aa

Description
Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is larger, then load the value into MRa.

if(MRa < #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMAXF32 operation:
• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == #16FHi:0) {ZF=1; NF=0;}

if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR0, #5.5 ; MR0 = 5.5, ZF = 0, NF = 1
MMAXF32 MR1, #2.5 ; MR1 = 4.0, ZF = 0, NF = 0
MMAXF32 MR2, #-1.0 ; MR2 = -1.0, ZF = 0, NF = 1
MMAXF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 1, NF = 0

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MMAXF32 MRa, #16FHi (continued)

32-Bit Floating-Point Maximum

See also
MMAXF32 MRa, MRb
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMINF32 MRa, MRb

32-Bit Floating-Point Minimum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0100 0000

Description
if(MRa > MRb) MRa = MRb;

Special cases for the output from the MMINF32 operation:

• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == MRb) {ZF=1; NF=0;}

if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example 1
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, MR1 ; MR0 = 4.0, ZF = 0, NF = 0
MMINF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 0
MMINF32 MR2, MR1 ; MR2 = -1.5, ZF = 1, NF = 0
MMINF32 MR1, MR0 ; MR2 = -1.5, ZF = 0, NF = 1

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MMINF32 MRa, MRb (continued)

32-Bit Floating-Point Minimum

Example 2
;
; X is an array of 32-bit floating-point values
; Find the minimum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMINF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also
MMAXF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMINF32 MRa, #16FHi

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MMINF32 MRa, #16FHi

32-Bit Floating-Point Minimum

Operands MRa floating-point source/destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1001 0100 00aa

Description
Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is smaller, then load the value into MRa.

if(MRa > #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMINF32 operation:
• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == #16FHi:0) {ZF=1; NF=0;}

if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, #5.5 ; MR0 = 5.0, ZF = 0, NF = 1
MMINF32 MR1, #2.5 ; MR1 = 2.5, ZF = 0, NF = 0
MMINF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 0, NF = 1
MMINF32 MR2, #-1.5 ; MR2 = -1.5, ZF = 1, NF = 0

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MMINF32 MRa, #16FHi (continued)

32-Bit Floating-Point Minimum

See also
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, MRb

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MMOV16 MARx, MRa, #16I

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Operands MARx Auxiliary register MAR0 or MAR1

MRa CLA Floating-point register (MR0 to MR3)
#16I 16-bit immediate value

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR0, MRa, #16I)
MSW: 0111 1111 1101 00AA
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR1, MRa, #16I)
MSW: 0111 1111 1111 00AA

Description
Load the auxiliary register, MAR0 or MAR1, with MRa(15:0) + 16-bit immediate value.
Refer to the Pipeline section for important information regarding this instruction.

MARx = MRa(15:0) + #16I;

Flags
This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction. The load of MAR0 or MAR1 occurs in the EXE phase
of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing occurs in
the D2 phase of the pipeline. Therefore, the following applies when loading the auxiliary
registers:
• I1 and I2
The two instructions following MMOV16 use MAR0 or MAR1 before the update occurs.
Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment wins and the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOVI16.

; Assume MAR0 is 50, MR0 is 10, and #_X is 20

MMOV16 MAR0, MR0, #_X ; Load MAR0 with address of X (20) + MR0 (10)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (30)
<Instruction 5> ; I5

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MMOV16 MARx, MRa, #16I (continued)

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Table 7-16. Pipeline Activity for MMOV16 MARx, MRa , #16I

Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, MR0,
MMOV16
#_X
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
I6 I6 I5 I4 I3 I2 I1 MMOV16

Example 1
; Calculate an offset into a sin/cos table
;
_Cla1Task1:
MMOV32 MR0,@_rad ; MR0 = rad
MMOV32 MR1,@_TABLE_SIZEDivTwoPi ; MR1 = TABLE_SIZE/(2*Pi)
MMPYF32 MR1,MR0,MR1 ; MR1 = rad* TABLE_SIZE/(2*Pi)
|| MMOV32 MR2,@_TABLE_MASK ; MR2 = TABLE_MASK
MF32TOI32 MR3,MR1 ; MR3 = K=int(rad*TABLE_SIZE/(2*Pi))
MAND32 MR3,MR3,MR2 ; MR3 = K & TABLE_MASK
MLSL32 MR3,#1 ; MR3 = K * 2
MMOV16 MAR0,MR3,#_Cos0 ; MAR0 K*2+addr of table.Cos0
MFRACF32 MR1,MR1 ; I1
MMOV32 MR0,@_TwoPiDivTABLE_SIZE ; I2
MMPYF32 MR1,MR1,MR0 ; I3
|| MMOV32 MR0,@_Coef3
MMOV32 MR2,*MAR0[#-64]++ ; MR2 = *MAR0, MAR0 += (-64)
...
...
MSTOP ; end of task

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MMOV16 MARx, MRa, #16I (continued)

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Example 2
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP ;I1 - I28 Wait till I36 to read
result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

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MMOV16 MARx, mem16

Load MAR1 with 16-bit Value

Operands MARx CLA auxiliary register MAR0 or MAR1

mem16 16-bit destination memory accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR0, mem16)
MSW: 0111 0110 0000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR1, mem16)
MSW: 0111 0110 0100 addr

Description
Load MAR0 or MAR1 with the 16-bit value pointed to by mem16. Refer to the Pipeline
section for important information regarding this instruction.

MAR1 = [mem16];

Flags
No flags MSTF flags are affected.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction. The load of MAR0 or MAR1 occurs in the EXE phase
of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing occurs in
the D2 phase of the pipeline. Therefore, the following applies when loading the auxiliary
registers:
• I1 and I2
The two instructions following MMOV16 use MAR0 or MAR1 before the update occurs.
Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment, the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOV16.

; Assume MAR0 is 50 and @_X is 20

MMOV16 MAR0, @_X ; Load MAR0 with the contents of X (20)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (20)
<Instruction 5> ; I5
....

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MMOV16 MARx, mem16 (continued)

Load MAR1 with 16-bit Value

Table 7-17. Pipeline Activity for MMOV16 MAR0/MAR1, mem16

Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, @_X MMOV16
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
I6 I6 I5 I4 I3 I2 I1 MMOV16

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MMOV16 MARx, mem16 (continued)

Load MAR1 with 16-bit Value

Example
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait until I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

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MMOV16 mem16, MARx

Move 16-Bit Auxiliary Register Contents to Memory

Operands mem16 16-bit destination memory accessed using one of the available
addressing modes
MARx CLA auxiliary register MAR0 or MAR1

Opcode
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR0)
MSW: 0111 0110 1000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR1)
MSW: 0111 0110 1100 addr

Description
Store the contents of MAR0 or MAR1 in the 16-bit memory location pointed to by mem16.

[mem16] = MAR0;

Flags
No flags MSTF flags are affected.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

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MMOV16 mem16, MRa

Move 16-Bit Floating-Point Register Contents to Memory

Operands mem16 16-bit destination memory accessed using one of the available
addressing modes
MRa CLA floating-point source register (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 11aa addr

Description
Move 16-bit value from the lower 16-bits of the floating-point register (MRa(15:0)) to the
location pointed to by mem16.

[mem16] = MRa(15:0);

Flags
No flags MSTF flags are affected.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

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MMOV16 mem16, MRa (continued)

Move 16-Bit Floating-Point Register Contents to Memory

Example
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

See also
MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex

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MMOV32 mem32, MRa

Move 32-Bit Floating-Point Register Contents to Memory

Operands MRa floating-point register (MR0 to MR3)

mem32 32-bit destination memory accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 11aa addr

Description
Move from MRa to 32-bit memory location indicated by mem32.

[mem32] = MRa;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected.

Pipeline
This is a single-cycle instruction.

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MMOV32 mem32, MRa (continued)

Move 32-Bit Floating-Point Register Contents to Memory

Example
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 *
Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D
MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E
MMOV32 @_Result, MR3 ; Store the result MSTOP ; end of task

See also
MMOV32 mem32, MSTF

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MMOV32 mem32, MSTF

Move 32-Bit MSTF Register to Memory

Operands MSTF Floating-point status register

mem32 32-bit destination memory

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0100 addr

Description
Copy the CLA floating-point status register, MSTF, to memory.

[mem32] = MSTF;

Flags
This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.
One of the uses of this instruction is to save off the return PC (RPC) prior to calling a
function. The decision to jump to a function is made when the MCCNDD is in the decode2
(D2) phase of the pipeline; the RPC is also updated in this phase. The actual jump occurs
3 cycles later when MCCNDD enters the execution (E) phase. You must save the old RPC
before MCCNDD updates in the D2 phase; that is, save MSTF 3 instructions prior to the
function call.

Example
The following example illustrates the pipeline flow for the context save (of the flags and
RPC) prior to a function call. The first column in the comments shows the pipeline stages
for the MMOV32 instruction while the second column pertains to the MCCNDD instruction.

MMOV32 @_temp, MSTF ; D2| |

MNOP ; R1|F1| MCCNDD is fetched
MNOP ; R2|F2|
MNOP ; E |D1|
MCCNDD _bar, UNC ; W |D2| old RPC written to memory,
; | | RPC updated with MPC+1
MNOP ; |R1|
MNOP ; |R2|
MNOP ; |E | execution branches to _bar

See also
MMOV32 mem32, MRa

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MMOV32 MRa, mem32 {, CNDF}

Conditional 32-Bit Move

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes
CNDF Optional condition

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 00cn dfaa addr

Description
If the condition is true, then move the 32-bit value referenced by mem32 to the floating-
point register indicated by MRa.

if (CNDF == TRUE) MRa = [mem32];

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }
}
else No flags modified;

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MMOV32 MRa, mem32 {, CNDF} (continued)

Conditional 32-Bit Move

Pipeline
This is a single-cycle instruction.

Example
; Given A, B, X, M1 and M2 are 32-bit floating-point numbers
;
; if(A == B) calculate Y = X*M1
; if(A! = B) calculate Y = X*M2
;
_Cla1Task5:
MMOV32 MR0, @_A
MMOV32 MR1, @_B
MCMPF32 MR0, MR1
MMOV32 MR2, @_M1, EQ ; if A == B, MR2 = M1
; Y = M1*X
MMOV32 MR2, @_M2, NEQ ; if A! = B, MR2 = M2
; Y = M2*X
MMOV32 MR3, @_X
MMPYF32 MR3, MR2, MR3 ; Calculate Y
MMOV32 @_Y, MR3 ; Store Y
MSTOP ; end of task

See also
MMOV32 MRa, MRb {, CNDF}
MMOVD32 MRa, mem32

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MMOV32 MRa, MRb {, CNDF}

Conditional 32-Bit Move

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
CNDF Optional condition

Opcode
LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1100 0000

Description
If the condition is true, then move the 32-bit value in MRb to the floating-point register
indicated by MRa.

if (CNDF == TRUE) MRa = MRb;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF, and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31); ZF = 0;
if(MRa(30:23) == 0) {ZF = 1; NF = 0;}
}
else No flags modified;

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MMOV32 MRa, MRb {, CNDF} (continued)

Conditional 32-Bit Move

Pipeline
This is a single-cycle instruction.

Example
; Given: X = 8.0
; Y = 7.0
; A = 2.0
; B = 5.0
; _ClaTask1
MMOV32 MR3, @_X ; MR3 = X = 8.0
MMOV32 MR0, @_Y ; MR0 = Y = 7.0
MMAXF32 MR3, MR0 ; ZF = 0, NF = 0, MR3 = 8.0
MMOV32 MR1, @_A, GT ; true, MR1 = A = 2.0
MMOV32 MR1, @_B, LT ; false, does not load MR1
MMOV32 MR2, MR1, GT ; true, MR2 = MR1 = 2.0
MMOV32 MR2, MR0, LT ; false, does not load MR2
MSTOP

See also
MMOV32 MRa, mem32 {,CNDF}

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MMOV32 MSTF, mem32

Move 32-Bit Value from Memory to the MSTF Register

Operands MSTF CLA status register

mem32 32-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0000 addr

Description
Move from memory to the CLA's status register MSTF. This instruction is most useful
when nesting function calls (using MCCNDD).

MSTF = [mem32];

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Loading the status register can overwrite all flags and the RPC field. The MEALLOW field
is not affected.

Pipeline
This is a single-cycle instruction.

See also
MMOV32 mem32, MSTF

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MMOVD32 MRa, mem32

Move 32-Bit Value from Memory with Data Copy

Operands MRa CLA floating-point register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 00aa addr

Description
Move the 32-bit value referenced by mem32 to the floating-point register indicated by
MRa.

MRa = [mem32];
[mem32+2] = [mem32];

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0){ ZF = 1; NF = 0; }

Pipeline
This is a single-cycle instruction.

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MMOVD32 MRa, mem32 (continued)

Move 32-Bit Value from Memory with Data Copy

Example
; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
; X2 = X1
; X1 = X0
; Y2 = Y1
; Y1 = sum
;
_Cla1Task2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0
; MR3 = X1*B1 + X2*B2, MR2 = X0*B0
; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2

MMOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1
MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1
MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
MMOV32 @_Y1, MR3 ; Y1 = MR3
MSTOP ; end of task

See also
MMOV32 MRa, mem32 {,CNDF}

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MMOVF32 MRa, #32F

Load the 32-Bits of a 32-Bit Floating-Point Register

Operands
This instruction is an alias for the MMOVIZ and MMOVXI instructions. The second
operand is translated by the assembler such that the instruction becomes:

MMOVIZ MRa, #16FHiHex MMOVXI MRa, #16FLoHex

MRa CLA floating-point destination register (MR0 to MR3)

#32F Immediate float value represented in floating-point representation

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description
This instruction accepts the immediate operand only in floating-point representation. To
specify the immediate value as a hex value (IEEE 32-bit floating- point format), use the
MOVI32 MRa, #32FHex instruction.
Load the 32-bits of MRa with the immediate float value represented by #32F.
#32F is a float value represented in floating-point representation. The assembler only
accepts a float value represented in floating-point representation. That is, 3.0 can only be
represented as #3.0 (#0x40400000 results in an error).

MRa = #32F;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
Depending on #32F, this instruction takes one or two cycles. If all of the lower 16-bits
of the IEEE 32-bit floating-point format of #32F are zeros, then the assembler converts
MMOVF32 into only an MMOVIZ instruction. If the lower 16-bits of the IEEE 32-bit
floating-point format of #32F are not zeros, then the assembler converts MMOVF32 into
MMOVIZ and MMOVXI instructions.

Example
MMOVF32 MR1, #3.0 ; MR1 = 3.0 (0x40400000)
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040
MMOVF32 MR2, #0.0 ; MR2 = 0.0 (0x00000000)
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0
MMOVF32 MR3, #12.265 ; MR3 = 12.625 (0x41443D71)
; Assembler converts this instruction as
; MMOVIZ MR3, #0x4144
; MMOVXI MR3, #0x3D71

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MMOVF32 MRa, #32F (continued)

Load the 32-Bits of a 32-Bit Floating-Point Register

See also
MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex
MMOVI32 MRa, #32FHex

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MMOVI16 MARx, #16I

Load the Auxiliary Register with the 16-Bit Immediate Value

Operands MARx Auxiliary register MAR0 or MAR1

#16I 16-bit immediate value

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR0, #16I)
MSW: 0111 1111 1100 0000
LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR1, #16I)
MSW: 0111 1111 1110 0000

Description
Load the auxiliary register, MAR0 or MAR1, with a 16-bit immediate value. Refer to the
Pipeline section for important information regarding this instruction.

MARx = #16I;

Flags
This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction. The immediate load of MAR0 or MAR1 occurs in
the EXE phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect
addressing occurs in the D2 phase of the pipeline. Therefore, the following applies when
loading the auxiliary registers:
• I1 and I2
The two instructions following MMOVI16 use MAR0 or MAR1 before the update
occurs. Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment, the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOVI16.

; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (20)
<Instruction 5> ; I5
....

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MMOVI16 MARx, #16I (continued)

Load the Auxiliary Register with the 16-Bit Immediate Value

Table 7-18. Pipeline Activity for MMOVI16 MAR0/MAR1, #16I

Instruction F1 F2 D1 D2 R1 R2 E W
MMOVI16 MAR0, #_X MMOVI16
I1 I1 MMOVI16
I2 I2 I1 MMOVI16
I3 I3 I2 I1 MMOVI16
I4 I4 I3 I2 I1 MMOVI16
I5 I5 I4 I3 I2 I1 MMOVI16
I6 I6 I5 I4 I3 I2 I1 MMOVI16

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MMOVI32 MRa, #32FHex

Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate

Operands MRa Floating-point register (MR0 to MR3)

#32FHex A 32-bit immediate value that represents an IEEE 32-bit floating-
point value.

This instruction is an alias for the MMOVIZ and MMOVXI instructions. The second
operand is translated by the assembler such that the instruction becomes:

MMOVIZ MRa, #16FHiHex

MMOVXI MRa, #16FLoHex

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description
This instruction only accepts a hex value as the immediate operand. To specify the
immediate value with a floating-point representation, use the MMOVF32 MRa, #32F
instruction.
Load the 32-bits of MRa with the immediate 32-bit hex value represented by #32FHex.
#32FHex is a 32-bit immediate hex value that represents the IEEE 32-bit floating-point
value of a floating-point number. The assembler only accepts a hex immediate value. That
is, 3.0 can only be represented as #0x40400000 (#3.0 results in an error).

MRa = #32FHex;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
Depending on #32FHex, this instruction takes one or two cycles. If all of the lower 16-bits
of #32FHex are zeros, then the assembler converts MOVI32 to an MMOVIZ instruction.
If the lower 16-bits of #32FHex are not zeros, then the assembler converts MOVI32 to
MMOVIZ and MMOVXI instructions.

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MMOVI32 MRa, #32FHex (continued)

Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate

Example
MOVI32 MR1, #0x40400000 ; MR1 = 0x40400000
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040
MOVI32 MR2, #0x00000000 ; MR2 = 0x00000000
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0
MOVI32 MR3, #0x40004001 ; MR3 = 0x40004001
; Assembler converts this instruction as
; MMOVIZ MR3, #0x4000
; MMOVXI MR3, #0x4001
MOVI32 MR0, #0x00004040 ; MR0 = 0x00004040
; Assembler converts this instruction as
; MMOVIZ MR0, #0x0000
; MMOVXI MR0, #0x4040

See also
MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex
MMOVF32 MRa, #32F

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MMOVIZ MRa, #16FHi

Load the Upper 16-Bits of a 32-Bit Floating-Point Register

Operands MRa Floating-point register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 0100 00aa

Description
Load the upper 16-bits of MRa with the immediate value #16FHi and clear the low 16-bits
of MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE
32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0.
The assembler only accepts a decimal or hex immediate value. That is, -1.5 can be
represented as #-1.5 or #0xBFC0.
MMOVIZ is useful for loading a floating-point register with a constant in which the lowest
16-bits of the mantissa are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000),
0.5 (0x3F000000), and -1.5 (0xBFC00000). If a constant requires all 32-bits of a floating-
point register to be initialized, then use MMOVIZ along with the MMOVXI instruction.

MRa(31:16) = #16FHi;
MRa(15:0) = 0;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; Load MR0 and MR1 with -1.5 (0xBFC00000)
MMOVIZ MR0, #0xBFC0 ; MR0 = 0xBFC00000 (1.5)
MMOVIZ MR1, #-1.5 ; MR1 = -1.5 (0xBFC00000)
; Load MR2 with pi = 3.141593 (0x40490FDB)
MMOVIZ MR2, #0x4049 ; MR2 = 0x40490000
MMOVXI MR2, #0x0FDB ; MR2 = 0x40490FDB

See also
MMOVF32 MRa, #32F
MMOVI32 MRa, #32FHex
MMOVXI MRa, #16FLoHex

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MMOVZ16 MRa, mem16

Load MRx with 16-Bit Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 10aa addr

Description
Move the 16-bit value referenced by mem16 to the floating-point register indicated by
MRa.

MRa(31:16) = 0;
MRa(15:0) = [mem16];

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = 0;
if (MRa(31:0)== 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

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MMOVXI MRa, #16FLoHex

Move Immediate Value to the Lower 16-Bits of a Floating-Point Register

Operands MRa CLA floating-point register (MR0 to MR3)

#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits
of an IEEE 32-bit floating-point value. The upper 16-bits are not
modified.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 1000 00aa

Description
Load the lower 16-bits of MRa with the immediate value #16FLoHex. #16FLoHex
represents the lower 16-bits of an IEEE 32-bit floating-point value. The upper 16-bits of
MRa are not modified. MMOVXI can be combined with the MMOVIZ instruction to initialize
all 32-bits of a MRa register.

MRa(15:0) = #16FLoHex;
MRa(31:16) = Unchanged;

Flags Flag TF ZF NF LUF LVF

Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; Load MR0 with pi = 3.141593 (0x40490FDB)
MMOVIZ MR0,#0x4049 ; MR0 = 0x40490000
MMOVXI MR0,#0x0FDB ; MR0 = 0x40490FDB

See also
MMOVIZ MRa, #16FHi

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MMPYF32 MRa, MRb, MRc

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0000 0000

Description
Multiply the contents of two floating-point registers.

MRa = MRb * MRc;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also
MMPYF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, #16FHi, MRb

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 bbaa

Description
Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The lower 16-bits of the mantissa are assumed to be all 0. #16FHi
is most useful for representing constants where the lowest 16-bits of the mantissa are
0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, MRb, #16FHi.

Flags
This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example 1
; Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #3.0, MR3 ; MR0 = 3.0 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2
; Same as example 1 but #16FHi is represented in Hex
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #0x4040, MR3 ; MR0 = 0x4040 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

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MMPYF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Multiply

Example 3
; Given X, M, and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
;
_Cla1Task2:
;
; Convert M, X, and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also
MMPYF32 MRa, MRb, #16FHi
MMPYF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MMPYF32 MRa, MRb, #16FHi

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 bbaa

Description
Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, #16FHi, MRb.

Flags
This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example 1
;Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #3.0 ; MR0 = MR3 * 3.0 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2
;Same as example 1 but #16FHi is represented in Hex
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #0x4040 ; MR0 = MR3 * 0x4040 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

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MMPYF32 MRa, MRb, #16FHi (continued)

32-Bit Floating-Point Multiply

Example 3
; Given X, M, and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
_Cla1Task2:
;
; Convert M, X, and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, #0x3380, MR0 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, #0x3380, MR1 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, #0x3380, MR2 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, #0x4B80, MR2 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also
MMPYF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc

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MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf

32-Bit Floating-Point Multiply with Parallel Add

Operands MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MADDF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for MADDF32 (MR0 to MR3)

Opcode
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0000 0000

Description
Multiply the contents of two floating-point registers with parallel addition of two registers.

MRa = MRb * MRc;

MRd = MRe + MRf;

Restrictions
The destination register for the MMPYF32 and the MADDF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MADDF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MADDF32 generates an overflow condition.

Pipeline
Both MMPYF32 and MADDF32 complete in a single cycle.

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MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf (continued)

32-Bit Floating-Point Multiply with Parallel Add

Example
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D

MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E

MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

See also
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Multiply with Parallel Move

Operands MRd CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRa CLA floating-point destination register for MMOV32 (MR0 to MR3)
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the source of MMOV32.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0000 ffee ddaa addr

Description
Multiply the contents of two floating-point registers and load another.

MRd = MRe * MRf;

MRa = [mem32];

Restrictions
The destination register for the MMPYF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
The MMOV32 instruction sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline
Both MMPYF32 and MMOV32 complete in a single cycle.

Example 1
; Given M1, X1, and B1 are 32-bit floating point
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0, @M1 ; Load MR0 with M1
MMOV32 MR1, @X1 ; Load MR1 with X1
MMPYF32 MR1, MR1, MR0 ; Multiply M1*X1
|| MMOV32 MR0, @B1 ; and in parallel load MR0 with B1
MADDF32 MR1, MR1, MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1, MR1 ; Store the result
MSTOP ; end of task

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MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply with Parallel Move

Example 2
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also
MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa

32-Bit Floating-Point Multiply with Parallel Move

Operands MRd CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRe CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for MMPYF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the destination of MMOV32.
MRa CLA floating-point source register for MMOV32 (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0100 ffee ddaa addr

Description
Multiply the contents of two floating-point registers and move from memory to register.

MRd = MRe * MRf;

[mem32] = MRa;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline
MMPYF32 and MMOV32 both complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also
MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf

32-Bit Floating-Point Multiply with Parallel Subtract

Operands MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MSUBF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MSUBF32 (MR0 to MR3)
MRf CLA floating-point source register for MSUBF32 (MR0 to MR3)

Opcode
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0100 0000

Description
Multiply the contents of two floating-point registers with parallel subtraction of two
registers.

MRa = MRb * MRc;

MRd = MRe - MRf;

Restrictions
The destination register for the MMPYF32 and the MSUBF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MSUBF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MSUBF32 generates an overflow condition.
Pipeline
MMPYF32 and MSUBF32 both complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A - B)
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR2, MR0, MR1 ; Multiply (A*B)
|| MSUBF32 MR3, MR0, MR1 ; and in parallel Sub (A-B)
MMOV32 @Y2, MR2 ; Store A*B
MMOV32 @Y3, MR3 ; Store A-B
MSTOP ; end of task

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MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf (continued)

32-Bit Floating-Point Multiply with Parallel Subtract

See also
MSUBF32 MRa, MRb, MRc
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa

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MNEGF32 MRa, MRb{, CNDF}

Conditional Negation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
CNDF Condition tested

Opcode
LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1000 0000

Description
if (CNDF == true) {MRa = - MRb; }
else {MRa = MRb; }

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF, and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

Pipeline
This is a single-cycle instruction.

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MNEGF32 MRa, MRb{, CNDF} (continued)

Conditional Negation

Example 1
; Show the basic operation of MNEGF32
;
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMPYF32 MR3, MR1, MR2 ; MR3 = -6.0
MMPYF32 MR0, MR0, MR1 ; MR0 = 20.0
MMOVIZ MR1, #0.0
MCMPF32 MR3, MR1 ; NF = 1
MNEGF32 MR3, MR3, LT ; if NF = 1, MR3 = 6.0
MCMPF32 MR0, MR1 ; NF = 0
MNEGF32 MR0, MR0, GEQ ; if NF = 0, MR0 = -20.0

Example 2
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also
MABSF32 MRa, MRb

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MNOP

No Operation

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1010 0000

Description
Do nothing. This instruction is used to fill required pipeline delay slots when other
instructions are not available to fill the slots.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Pad to seperate MBCNDD and MSTOP
MNOP ; Pad to seperate MBCNDD and MSTOP
MSTOP ; End of task

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MOR32 MRa, MRb, MRc

Bitwise OR

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1000 0000

Description
Bitwise OR of MRb with MRc.

MARa(31:0) = MARb(31:0) OR MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0,
#0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0,
#0xAAAA
MMOVIZ MR1,
#0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1,
#0xFEDC
; 0101 OR 0101 = 0101 (5)
; 0101 OR 0100 = 0101 (5)
; 0101 OR 0011 = 0111 (7)
; 0101 OR 0010 = 0111 (7)
; 1010 OR 1111 = 1111 (F)
; 1010 OR 1110 = 1110 (E)
; 1010 OR 1101 = 1111 (F)
; 1010 OR 1100 = 1110 (E)
MOR32 MR2, MR1, MR0 ; MR3 = 0x5555FEFE

See also
MAND32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc

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MRCNDD {CNDF}

Return Conditional Delayed

Operands CNDF Optional condition

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1001 1010 cndf

Description
If the specified condition is true, then the RPC field of MSTF is loaded into MPC and
fetching continues from that location. Otherwise, program fetches continue without the
return.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE) MPC = RPC;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
The MRCNDD instruction is a single-cycle instruction. As shown in Table 7-19, 6
instruction slots are executed for each return; 3 slots before the return instruction (d5-d7)
and 3 slots after the return instruction (d8-d10). The total number of cycles for a return
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled.
The effective number of cycles for a return can, therefore, range from 1 to 7 cycles. The
number of cycles for a return taken cannot be the same as for a return not taken.

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MRCNDD {CNDF} (continued)

Return Conditional Delayed

Referring to the following code fragment and the pipeline diagrams in Table 7-19 and
Table 7-20, the instructions before and after MRCNDD have the following properties:

;
;
<Instruction 1> ; I1 Last instruction that can affect flags for
; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
<Instruction 10> ; I10
....
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return
MRCNDD NEQ ; Return to <Instruction 8> if not equal to zero
; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
<Destination 12> ; d12
....
....
MSTOP
....

• d4
– d4 is the last instruction that can effect the CNDF flags for the MRCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to return or not when MRCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for d4.
• d5, d6, and d7
– The three instructions proceeding MRCNDD can change MSTF flags but have no
effect on whether the MRCNDD instruction makes the return or not. This is because
the flag modification occurs after the D2 phase of the MRCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• d8, d9, and d10
– The three instructions following MRCNDD are always executed irrespective of
whether the return is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

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MRCNDD {CNDF} (continued)

Return Conditional Delayed

Table 7-19. Pipeline Activity for MRCNDD, Return Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
d11 d11 d10 d9 d8 - d7 d6
d12 d12 d11 d10 d9 d8 - d7
etc.... .... d12 d11 d10 d9 d8 -
.... .... .... d12 d11 d10 d9 d8
.... .... .... .... d12 d11 d10 d9
d12 d11 d10
d12 d11
d12

Table 7-20. Pipeline Activity for MRCNDD, Return Taken

Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
I8 I8 d10 d9 d8 - d7 d6
I9 I9 I8 d10 d9 d8 - d7
I10 I10 I9 I8 d10 d9 d8 -
etc.... .... I10 I9 I8 d10 d9 d8
.... .... I10 I9 I8 d10 d9
.... .... I10 I9 I8 d10
I10 I9 I8
I10 I9
I10

See also
MBCNDD #16BitDest, CNDF
MCCNDD 16BitDest, CNDF
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32

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MSETFLG FLAG, VALUE

Set or Clear Selected Floating-Point Status Flags

Operands FLAG 8-bit mask indicating which floating-point status flags to change.
VALUE 8-bit mask indicating the flag value: 0 or 1.

Opcode
LSW: FFFF FFFF VVVV VVVV
MSW: 0111 1001 1100 0000

Description
The MSETFLG instruction is used to set or clear selected floating-point status flags in the
MSTF register. The FLAG field is an 11-bit value that indicates which flags are changed.
That is, if a FLAG bit is set to 1, that flag is changed; all other flags are not modified. The
bit mapping of the FLAG field is:
9 8 7 6 5 4 3 2 1 0
RNDF Reserved TF Reserved ZF NF LUF LVF
32

The VALUE field indicates the value the flag can be set to: 0 or 1.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Any flag can be modified by this instruction. The MEALLOW and RPC fields cannot be
modified with this instruction.

Pipeline
This is a single-cycle instruction.

Example
To make it easier and legible, the assembler accepts a FLAG=VALUE syntax for the
MSTFLG operation as:

MSETFLG RNDF32=0, TF=0, NF=1; FLAG = 11000100; VALUE = 00XXX1XX;

See also
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32

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MSTOP

Stop Task

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1000 0000

Description
The MSTOP instruction must be placed to indicate the end of each task. In addition,
placing MSTOP in unused memory locations within the CLA program RAM can be useful
for debugging and preventing run away CLA code. When MSTOP enters the D2 phase of
the pipeline, the MIRUN flag for the task is cleared and the associated interrupt is flagged
in the PIE vector table.
There are three special cases that can occur when single-stepping a task such that the
MPC reaches the MSTOP instruction.
1. If you are single-stepping or halted in "task A" and "task B" comes in before the MPC
reaches the MSTOP, then "task B" starts if you continue to step through the MSTOP
instruction. Basically, if "task B" is pending before the MPC reaches MSTOP in "task
A" then there is no issue in "task B" starting and no special action is required.
2. In this case, you have single-stepped or halted in "task A" and the MPC has reached
the MSTOP with no tasks pending. If "task B" comes in at this point, "task B" is
flagged in the MIFR register but "task B" can or cannot start if you continue to
single-step through the MSTOP instruction of "task A". It depends on exactly when the
new task comes in. To reliably start "task B", perform a soft reset and reconfigure the
MIER bits. Once this is done, you can start single-stepping "task B".
3. Case 2 can be handled slightly differently if there is control over when "task B" comes
in (for example using the IACK instruction to start the task). In this case you have
single-stepped or halted in "task A" and the MPC has reached the MSTOP with no
tasks pending. Before forcing "task B", run free to force the CLA out of the debug
state. Once this is done you can force "task B" and continue debugging.

Restrictions
The MSTOP instruction cannot be placed 3 instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction.

Flags
This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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MSTOP (continued)

Stop Task

Pipeline
This is a single-cycle instruction. Table 7-21 shows the pipeline behavior of the MSTOP
instruction. The MSTOP instruction cannot be placed with 3 instructions of a MBCNDD,
MCCNDD, or MRCNDD instruction.
Table 7-21. Pipeline Activity for MSTOP
Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
MSTOP MSTOP I3 I2 I1
I4 I4 MSTOP I3 I2 I1
I5 I5 I4 MSTOP I3 I2 I1
I6 I6 I5 I4 MSTOP I3 I2 I1
New Task Arbitrated and
- - - - - I3 I2
Prioritized
New Task Arbitrated and
- - - - - - I3
Prioritized
I1 I1 - - - - - -
I2 I2 I1 - - - - -
I3 I3 I2 I1 - - - -
I4 I4 I3 I2 I1 - - -
I5 I5 I4 I3 I2 I1 - -
I6 I6 I5 I4 I3 I2 I1 -
I7 I7 I6 I5 I4 I3 I2 I1
....

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A - B - C
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also
MDEBUGSTOP

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MSUB32 MRa, MRb, MRc

32-Bit Integer Subtraction

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1110 0000

Description
32-bit integer addition of MRb and MRc.

MARa(31:0) = MARb(31:0) - MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
;
Calculate Y2 = A - B - C
;
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also
MADD32 MRa, MRb, MRc
MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc

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MSUBF32 MRa, MRb, MRc

32-Bit Floating-Point Subtraction

Operands MRa CLA floating-point destination register (MR0 to R1)

MRb CLA floating-point source register (MR0 to R1)
MRc CLA floating-point source register (MR0 to R1)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0100 0000

Description
Subtract the contents of two floating-point registers

MRa = MRb - MRc;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = A + B - C
;
_Cla1Task5:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MADDF32 MR0, MR1, MR0 ; Add A + B
|| MMOV32 MR1, @_C ; and in parallel load C
MSUBF32 MR0, MR0, MR1 ; Subtract C from (A + B)
MMOV32 @Y, MR0 ; (A+B) - C
MSTOP ; end of task

See also
MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRa, #16FHi, MRb

32-Bit Floating-Point Subtraction

Operands MRa CLA floating-point destination register (MR0 to R1)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to R1)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 0000 baaa

Description
Subtract MRb from the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The lower 16-bits of the mantissa are assumed to be all 0. #16FHi
is most useful for representing constants where the lowest 16-bits of the mantissa are
0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = #16FHi:0 - MRb;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.

Pipeline
This is a single-cycle instruction.

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MSUBF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Subtraction

Example
; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

See also
MSUBF32 MRa, MRb, MRc
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Subtraction with Parallel Move

Operands MRd CLA floating-point destination register (MR0 to MR3) for the
MSUBF32 operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRa CLA floating-point destination register (MR0 to MR3) for the
MMOV32 operation
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available
addressing modes. Source for the MMOV32 operation.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0010 ffee ddaa addr

Description
Subtract the contents of two floating-point registers and move from memory to a floating-
point register.

MRd = MRe - MRf;

MRa = [mem32];

Restrictions
The destination register for the MSUBF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
The MMOV32 instruction sets the NF and ZF flags.

Pipeline
Both MSUBF32 and MMOV32 complete in a single cycle.

Example
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

See also
MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa

32-Bit Floating-Point Subtraction with Parallel Move

Operands MRd CLA floating-point destination register (MR0 to MR3) for the
MSUBF32 operation
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
mem32 32-bit destination memory location for the MMOV32 operation
MRa CLA floating-point source register (MR0 to MR3) for the MMOV32
operation

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0110 ffee ddaa addr

Description
Subtract the contents of two floating-point registers and move from a floating-point
register to memory.

MRd = MRe - MRf;

[mem32] = MRa;

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.

Pipeline
Both MSUBF32 and MMOV32 complete in a single cycle.

See also
MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSWAPF MRa, MRb {, CNDF}

Conditional Swap

Operands MRa CLA floating-point register (MR0 to MR3)

MRb CLA floating-point register (MR0 to MR3)
CNDF Optional condition tested based on the MSTF flags

Opcode
LSW: 0000 0000 CNDF bbaa
MSW: 0111 1011 0000 0000

Description
Conditional swap of MRa and MRb.

if (CNDF == true) swap MRa and MRb;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected

Pipeline
This is a single-cycle instruction.

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MSWAPF MRa, MRb {, CNDF} (continued)

Conditional Swap

Example
; X is an array of 32-bit floating-point values
; and has length elements. Find the maximum value in
; the array and store the value in Result
;
; Note: MCMPF32 and MSWAPF can be replaced by MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

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MTESTTF CNDF

Test MSTF Register Flag Condition

Operands CNDF Condition to test based on MSTF flags

Opcode
LSW: 0000 0000 0000 cndf
MSW: 0111 1111 0100 0000

Description
Test the CLA floating-point condition and if true, set the MSTF[TF] flag. If the condition is
false, clear the MSTF[TF] flag. This is useful for temporarily storing a condition for later
use.

if (CNDF == true) TF = 1;
else TF = 0;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes No No No No

TF = 0;
if (CNDF == true) TF = 1;

Note: If (CNDF == UNC or UNCF), the TF flag is set to 1.

Pipeline
This is a single-cycle instruction.

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MTESTTF CNDF (continued)

Test MSTF Register Flag Condition

Example
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @_State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD _Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @_RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
_Skip1:
MMOV32 MR3, @_SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD _Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @_CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken
_Skip2:
MMOV32 @_SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

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MUI16TOF32 MRa, mem16

Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 01aa addr

Description
When converting F32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to
zero while the MF32TOI16R/UI16R operation rounds to the nearest (even) value.

MRa = UI16TOF32[mem16];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MUI16TOF32 MRa, MRb

Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1110 0000

Description
Convert an unsigned 16-bit integer to a 32-bit floating-point value. When converting
float32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to zero while
the MF32TOI16R/UI16R operation rounds to the nearest (even) value.

MRa = UI16TOF32[MRb];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVXI MR1, #0x800F ; MR1(15:0) = 32783 (0x800F)
MUI16TOF32 MR0, MR1 ; MR0 = UI16TOF32 (MR1(15:0))
; = 32783.0 (0x47000F00)

See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16

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MUI32TOF32 MRa, mem32

Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 10aa addr

Description
MRa = UI32TOF32[mem32];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
; Given x2, m2, and b2 are Uint32 numbers:
;
; x2 = Uint32(2) = 0x00000002
; m2 = Uint32(1) = 0x00000001
; b2 = Uint32(3) = 0x00000003
;
; Calculate y2 = x2 * m2 + b2
;
_Cla1Task1:
MUI32TOF32 MR0, @_m2 ; MR0 = 1.0 (0x3F800000)
MUI32TOF32 MR1, @_x2 ; MR1 = 2.0 (0x40000000)
MUI32TOF32 MR2, @_b2 ; MR2 = 3.0 (0x40400000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR3, MR2, MR3 ; Y=MX+B = 5.0 (0x40A00000)
MF32TOUI32 MR3, MR3 ; Y = Uint32(5.0) = 0x00000005
MMOV32 @_y2, MR3 ; store result
MSTOP ; end of task

See also
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb

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MUI32TOF32 MRa, MRb

Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1100 0000

Description
MRa = UI32TOF32 [MRb];

Flags
This instruction does not affect any flags:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR3, #0x8000 ; MR3(31:16) = 0x8000
MMOVXI MR3, #0x1111 ; MR3(15:0) = 0x1111
; MR3 = 2147488017
MUI32TOF32 MR3, MR3 ; MR3 = MUI32TOF32 (MR3) = 2147488017.0 (0x4F000011)

See also
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MXOR32 MRa, MRb, MRc

Bitwise Exclusive Or

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1010 0000

Description
Bitwise XOR of MRb with MRc.

MARa(31:0) = MARb(31:0) XOR MRc(31:0);

Flags
This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline
This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA
MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1, #0xFEDC
; 0101 XOR 0101 = 0000 (0)
; 0101 XOR 0100 = 0001 (1)
; 0101 XOR 0011 = 0110 (6)
; 0101 XOR 0010 = 0111 (7)
; 1010 XOR 1111 = 0101 (5)
; 1010 XOR 1110 = 0100 (4)
; 1010 XOR 1101 = 0111 (7)
; 1010 XOR 1100 = 0110 (6)
MXOR32 MR2, MR1, MR0 ; MR3 = 0x01675476

See also
MAND32 MRa, MRb, MRc
MOR32 MRa, MRb, MRc

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7.8 CLA Registers

This section describes the CLA Registers.
7.8.1 CLA Base Address Table
Table 7-22. CLA Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1
Instance Structure Protected

CLA1_ONLY_BAS
Cla1onlyRegs CLA_ONLY_REGS 0x0000_0C00 - - YES -
E
CLA_SOFTINT_R CLA1_SOFTINT_B
Cla1SoftintRegs 0x0000_0CE0 - - YES -
EGS ASE
Cla1Regs CLA_REGS CLA1_BASE 0x0000_1400 YES - - -

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7.8.2 CLA_ONLY_REGS Registers

Table 7-23 lists the memory-mapped registers for the CLA_ONLY_REGS registers. All register offset addresses
not listed in Table 7-23 should be considered as reserved locations and the register contents should not be
modified.
Table 7-23. CLA_ONLY_REGS Registers
Offset Acronym Register Name Write Protection Section
80h _MVECTBGRNDACTIVE Active register for MVECTBGRND. EALLOW Go
C0h _MPSACTL CLA PSA Control Register EALLOW Go
C2h _MPSA1 CLA PSA1 Register EALLOW Go
C4h _MPSA2 CLA PSA2 Register EALLOW Go
E0h SOFTINTEN CLA Software Interrupt Enable Register Go
E2h SOFTINTFRC CLA Software Interrupt Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 7-24 shows the codes that are used for
access types in this section.
Table 7-24. CLA_ONLY_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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7.8.2.1 _MVECTBGRNDACTIVE Register (Offset = 80h) [Reset = 0000h]

_MVECTBGRNDACTIVE is shown in Figure 7-2 and described in Table 7-25.
Return to the Summary Table.
Gives the current interrupted MPC value of the background task, if the background task was running and
interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Figure 7-2. _MVECTBGRNDACTIVE Register
15 14 13 12 11 10 9 8
i16
R-0h

7 6 5 4 3 2 1 0
i16
R-0h

Table 7-25. _MVECTBGRNDACTIVE Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R 0h Gives the current interrupted MPC value of the background task,
if the background task was running and interrupted, or reflects the
MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Reset type: SYSRSn

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7.8.2.2 _MPSACTL Register (Offset = C0h) [Reset = 0000h]

_MPSACTL is shown in Figure 7-3 and described in Table 7-26.
Return to the Summary Table.
PSA Control Register
Figure 7-3. _MPSACTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
MPSA2CFG MPSA2CLEAR MPSA1CLEAR MDWDBCYC MDWDBSTART MPABCYC MPABSTART
R/W-0h R-0/W1S-0h R-0/W1S-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-26. _MPSACTL Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7-6 MPSA2CFG R/W 0h CLA PSA2 Polynomial Configuration Bits: These bits configure the
type of polynomial used for PSA2. The polynomials chosen are
commonly used in the industry:
Mode Polynomial Type
0,0 PSA
0,1 CRC32
1,0 CRC16
1,1 CRC16-CCITT
Note: [1] Polynomial configuration should be performed when PSA2
is stopped.
Reset type: SYSRSn
5 MPSA2CLEAR R-0/W1S 0h CLA PSA2 Clear Bit:
Writing of '1' will clear contents of PSA2 register.
Writes of '0' are ignored.
Always reads back a '0'
Note: Clearing operation should be performed when PSA2 is
stopped.
Reset type: SYSRSn
4 MPSA1CLEAR R-0/W1S 0h CLA PSA1 Clear Bit:
Writing of '1' will clear contents of PSA1 register.
Writes of '0' are ignored.
Always reads back a '0'
Note: Clearing operation should be performed when PSA1 is
stopped.
Reset type: SYSRSn
3 MDWDBCYC R/W 0h CLA Data Write Data Bus PSA2 Cycle or Event Based Bit:
0 PSA2 calculated on every cycle
1 PSA2 calculated on every bus event
Reset type: SYSRSn
2 MDWDBSTART R/W 0h CLA Data Write Data Bus PSA2 Start/Stop Bit:
0 PSA2 stopped
1 PSA2 start
Reset type: SYSRSn
1 MPABCYC R/W 0h CLA Program Address Bus PSA1 Cycle/Event Based Bit:
0 PSA1 calculated on every cycle
1 PSA1 calculated on every bus event
Reset type: SYSRSn

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Table 7-26. _MPSACTL Register Field Descriptions (continued)

Bit Field Type Reset Description
0 MPABSTART R/W 0h CLA Program Address Bus PSA1 Start/Stop Bit:
0 PSA1 stopped
1 PSA1 start
Reset type: SYSRSn

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7.8.2.3 _MPSA1 Register (Offset = C2h) [Reset = 00000000h]

_MPSA1 is shown in Figure 7-4 and described in Table 7-27.
Return to the Summary Table.
PSA1 Register
Figure 7-4. _MPSA1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 7-27. _MPSA1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA1 Value: Reading this register gives the current PSA1 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA1 to a known
value. Writes to this register should only be made when PSA1 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA1CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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7.8.2.4 _MPSA2 Register (Offset = C4h) [Reset = 00000000h]

_MPSA2 is shown in Figure 7-5 and described in Table 7-28.
Return to the Summary Table.
PSA2 Register
Figure 7-5. _MPSA2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 7-28. _MPSA2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA2 Value: Reading this register gives the current PSA2 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA2 to a known
value. Writes to this register should only be made when PSA2 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA2CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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7.8.2.5 SOFTINTEN Register (Offset = E0h) [Reset = 0000h]

SOFTINTEN is shown in Figure 7-6 and described in Table 7-29.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.
Figure 7-6. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-29. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 7-29. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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7.8.2.6 SOFTINTFRC Register (Offset = E2h) [Reset = 0000h]

SOFTINTFRC is shown in Figure 7-7 and described in Table 7-30.
Return to the Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.
Figure 7-7. SOFTINTFRC Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-30. SOFTINTFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
6 TASK7 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
5 TASK6 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
4 TASK5 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
3 TASK4 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
2 TASK3 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
1 TASK2 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
0 TASK1 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn

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7.8.3 CLA_SOFTINT_REGS Registers

Table 7-31 lists the memory-mapped registers for the CLA_SOFTINT_REGS registers. All register offset
addresses not listed in Table 7-31 should be considered as reserved locations and the register contents should
not be modified.
Table 7-31. CLA_SOFTINT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h SOFTINTEN CLA Software Interrupt Enable Register Go
2h SOFTINTFRC CLA Software Interrupt Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 7-32 shows the codes that are used for
access types in this section.
Table 7-32. CLA_SOFTINT_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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7.8.3.1 SOFTINTEN Register (Offset = 0h) [Reset = 0000h]

SOFTINTEN is shown in Figure 7-8 and described in Table 7-33.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.
Figure 7-8. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-33. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 7-33. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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7.8.3.2 SOFTINTFRC Register (Offset = 2h) [Reset = 0000h]

SOFTINTFRC is shown in Figure 7-9 and described in Table 7-34.
Return to the Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.This register is only accessible by the
CLA (not the CPU).
Figure 7-9. SOFTINTFRC Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-34. SOFTINTFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
6 TASK7 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
5 TASK6 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
4 TASK5 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
3 TASK4 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
2 TASK3 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
1 TASK2 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
0 TASK1 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn

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7.8.4 CLA_REGS Registers

Table 7-35 lists the memory-mapped registers for the CLA_REGS registers. All register offset addresses not
listed in Table 7-35 should be considered as reserved locations and the register contents should not be modified.
Table 7-35. CLA_REGS Registers
Offset Acronym Register Name Write Protection Section
0h MVECT1 Task Interrupt Vector EALLOW Go
1h MVECT2 Task Interrupt Vector EALLOW Go
2h MVECT3 Task Interrupt Vector EALLOW Go
3h MVECT4 Task Interrupt Vector EALLOW Go
4h MVECT5 Task Interrupt Vector EALLOW Go
5h MVECT6 Task Interrupt Vector EALLOW Go
6h MVECT7 Task Interrupt Vector EALLOW Go
7h MVECT8 Task Interrupt Vector EALLOW Go
10h MCTL Control Register EALLOW Go
1Bh _MVECTBGRNDACTIVE Active register for MVECTBGRND. EALLOW Go
1Ch SOFTINTEN CLA Software Interrupt Enable Register Go
1Dh _MSTSBGRND Status register for the back ground task. EALLOW Go
1Eh _MCTLBGRND Control register for the back ground task. EALLOW Go
1Fh _MVECTBGRND Vector for the back ground task. EALLOW Go
20h MIFR Interrupt Flag Register EALLOW Go
21h MIOVF Interrupt Overflow Flag Register EALLOW Go
22h MIFRC Interrupt Force Register EALLOW Go
23h MICLR Interrupt Flag Clear Register EALLOW Go
24h MICLROVF Interrupt Overflow Flag Clear Register EALLOW Go
25h MIER Interrupt Enable Register EALLOW Go
26h MIRUN Interrupt Run Status Register EALLOW Go
28h _MPC CLA Program Counter Go
2Ah _MAR0 CLA Auxiliary Register 0 Go
2Bh _MAR1 CLA Auxiliary Register 1 Go
2Eh _MSTF CLA Floating-Point Status Register Go
30h _MR0 CLA Floating-Point Result Register 0 Go
34h _MR1 CLA Floating-Point Result Register 1 Go
38h _MR2 CLA Floating-Point Result Register 2 Go
3Ch _MR3 CLA Floating-Point Result Register 3 Go
42h _MPSACTL CLA PSA Control Register EALLOW Go
44h _MPSA1 CLA PSA1 Register EALLOW Go
46h _MPSA2 CLA PSA2 Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 7-36 shows the codes that are used for
access types in this section.
Table 7-36. CLA_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type

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Table 7-36. CLA_REGS Access Type Codes (continued)

Access Type Code Description
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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7.8.4.1 MVECT1 Register (Offset = 0h) [Reset = 0000h]

MVECT1 is shown in Figure 7-10 and described in Table 7-37.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-10. MVECT1 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-37. MVECT1 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.2 MVECT2 Register (Offset = 1h) [Reset = 0000h]

MVECT2 is shown in Figure 7-11 and described in Table 7-38.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-11. MVECT2 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-38. MVECT2 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.3 MVECT3 Register (Offset = 2h) [Reset = 0000h]

MVECT3 is shown in Figure 7-12 and described in Table 7-39.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-12. MVECT3 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-39. MVECT3 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.4 MVECT4 Register (Offset = 3h) [Reset = 0000h]

MVECT4 is shown in Figure 7-13 and described in Table 7-40.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-13. MVECT4 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-40. MVECT4 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.5 MVECT5 Register (Offset = 4h) [Reset = 0000h]

MVECT5 is shown in Figure 7-14 and described in Table 7-41.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-14. MVECT5 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-41. MVECT5 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.6 MVECT6 Register (Offset = 5h) [Reset = 0000h]

MVECT6 is shown in Figure 7-15 and described in Table 7-42.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-15. MVECT6 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-42. MVECT6 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.7 MVECT7 Register (Offset = 6h) [Reset = 0000h]

MVECT7 is shown in Figure 7-16 and described in Table 7-43.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-16. MVECT7 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-43. MVECT7 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.8 MVECT8 Register (Offset = 7h) [Reset = 0000h]

MVECT8 is shown in Figure 7-17 and described in Table 7-44.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-17. MVECT8 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-44. MVECT8 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.9 MCTL Register (Offset = 10h) [Reset = 0000h]

MCTL is shown in Figure 7-18 and described in Table 7-45.
Return to the Summary Table.
Control Register
Figure 7-18. MCTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED IACKE SOFTRESET HARDRESET
R-0h R/W-0h R-0/W1S-0h R-0/W1S-0h

Table 7-45. MCTL Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R 0h Reserved
2 IACKE R/W 0h IACK Operation Enable Bit: Writing a '1' to this bit will enable the
IACK operation for setting the MIFR bits in the same manner as the
MIFRC register (write of '1' will set respective MIFR bit). At reset, this
feature is disabled.
This feature enables the C28 CPU to efficiently trigger a task.
Note: IACK operation should ignore EALLOW status of C28 core
when accessing the MIFRC register.
Reset type: SYSRSn
0h (R/W) = The CLA ignores the IACK instruction. (default)
1h (R/W) = Enable the main CPU to use the IACK #16bit instruction
to set MIFR bits in the same manner as writing to the MIFRC
register. Each bit in the operand, #16bit, corresponds to a bit in the
MIFRC register. Using IACK has the advantage of not having to first
set the EALLOW bit. This allows the main CPU to efficiently trigger a
CLA task through software.
Examples IACK #0x0001 Write a 1 to MIFRC bit 0 to force task 1
IACK #0x0003 Write a 1 to MIFRC bit 0 and 1 to force task 1 and
task 2
1 SOFTRESET R-0/W1S 0h Soft Reset Bit: Writing a '1' to this bit will stop a current task, clear
the RUN flag and also clear all bits in the MIER register. Writes of '0'
are ignored and reads always return a '0'.
Note: After issuing SOFTRESET command, user should wait at least
1 clock cycle before attempting to write to MIER register.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a soft reset of the CLA. This
will stop the current task, clear the MIRUN flag and clear all bits
in the MIER register. After a soft reset you must wait at least 1
SYSCLKOUT cycle before reconfiguring the MIER bits. If these two
operations are done back-to-back then the MIER bits will not get set.
0 HARDRESET R-0/W1S 0h Hard Reset Bit: Writing a '1' to this bit will cause a HARD reset on the
CLA. The behavior of a HARD reset is the same as a system reset
SYSRSn on the CLA. Writes of '0' are ignored and reads always
return a '0'.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a hard reset of the CLA. This will
set all CLA registers to their default state.

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7.8.4.10 _MVECTBGRNDACTIVE Register (Offset = 1Bh) [Reset = 0000h]

_MVECTBGRNDACTIVE is shown in Figure 7-19 and described in Table 7-46.
Return to the Summary Table.
Gives the current interrupted MPC value of the background task, if the background task was running and
interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Figure 7-19. _MVECTBGRNDACTIVE Register
15 14 13 12 11 10 9 8
i16
R-0h

7 6 5 4 3 2 1 0
i16
R-0h

Table 7-46. _MVECTBGRNDACTIVE Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R 0h Gives the current interrupted MPC value of the background task,
if the background task was running and interrupted, or reflects the
MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Reset type: SYSRSn

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7.8.4.11 SOFTINTEN Register (Offset = 1Ch) [Reset = 0000h]

SOFTINTEN is shown in Figure 7-20 and described in Table 7-47.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA. Only reads are allowed from CPU. Writes are not allowed
from CPU.
Figure 7-20. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-47. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 7-47. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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7.8.4.12 _MSTSBGRND Register (Offset = 1Dh) [Reset = 0000h]

_MSTSBGRND is shown in Figure 7-21 and described in Table 7-48.
Return to the Summary Table.
Status bits for the backgrondtask.
Figure 7-21. _MSTSBGRND Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
RESERVED BGOVF _BGINTM RUN
R/W-0h R/W1C-0h R-0h R-0h

Table 7-48. _MSTSBGRND Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R/W 0h Reserved
2 BGOVF R/W1C 0h Value of 1 indicates a hardware trigger (which is enabled) occurred
while the MCTLBGRND.BGSTART bit is set.
Writing a value of 1 to this bit clears the BGOVF bit.
Write of 0 has no effect,
Value of 0 indicates the background task trigger did not result in a
overflow.
Reset type: SYSRSn
1 _BGINTM R 0h Value of 1 indicates that backgroiund task will not be interrupted.
This bit is set when MSETC _BGINTM bit is executed.
Value of 0 indicates that background task can be interrupted.
Reset type: SYSRSn
0 RUN R 0h Value of 1 indicates that background task is running.
Value of 0 indicates that background task is not running.
Reset type: SYSRSn

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7.8.4.13 _MCTLBGRND Register (Offset = 1Eh) [Reset = 0000h]

_MCTLBGRND is shown in Figure 7-22 and described in Table 7-49.
Return to the Summary Table.
Holds the configuration bits to start the background task, enable hardware trigger.
Figure 7-22. _MCTLBGRND Register
15 14 13 12 11 10 9 8
BGEN RESERVED
R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED TRIGEN BGSTART
R/W-0h R/W-0h R/W1S-0h

Table 7-49. _MCTLBGRND Register Field Descriptions

Bit Field Type Reset Description
15 BGEN R/W 0h 0 Background task is disabled, BGSTART will not be set either in a
hardware trigger or by writing 1 to BGSTART bit.
1 Background task is enabled and MIER[INT8] will be cleared,
preventing task 8 from triggering.
Reset type: SYSRSn
14-2 RESERVED R/W 0h Reserved
1 TRIGEN R/W 0h Hardware trigger enable for the background task.
1 Hardware trigger is enabled.
0 Hardware trigger is disabled.
Note: Trigger source for the background task will be the same as that
for task 8
Reset type: SYSRSn
0 BGSTART R/W1S 0h Value of 1 will start the background task, provided there are no other
pending tasks.
- Value of 0 has no effect if the background task has not started.
- This bit is also set by hardware, if MCTLBGRND.TRIGEN = 1 and a
hardware trigger occurs.
- This bit is cleared by hardware when a MSTOP instruction occurs in
the background task
- If the background task is running and this bit is cleared, it will not
have any effect on the task execution.
Reset type: SYSRSn

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7.8.4.14 _MVECTBGRND Register (Offset = 1Fh) [Reset = 0000h]

_MVECTBGRND is shown in Figure 7-23 and described in Table 7-50.
Return to the Summary Table.
These bits specify the start address for the background task . The value in this register is forced into the MPC
register when the background task starts.
Figure 7-23. _MVECTBGRND Register
15 14 13 12 11 10 9 8
i16
R/W-0h

7 6 5 4 3 2 1 0
i16
R/W-0h

Table 7-50. _MVECTBGRND Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R/W 0h MPC Start Address: These bits specify the start address for the
background task . The value in this register is forced into the MPC
register, when the background task starts.
Reset type: SYSRSn

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7.8.4.15 MIFR Register (Offset = 20h) [Reset = 0000h]

MIFR is shown in Figure 7-24 and described in Table 7-51.
Return to the Summary Table.
Each bit in the interrupt flag register corresponds to a CLA task. The corresponding bit is automatically set
when the task request is received from the peripheral interrupt. The bit can also be set by the main CPU
writing to the MIFRC register or using the IACK instruction to start the task. To use the IACK instruction to
begin a task first enable this feature in the MCTL register. If the bit is already set when a new peripheral
interrupt is received, then the corresponding overflow bit will be set in the MIOVF register.
The corresponding MIFR bit is automatically cleared when the task begins execution. This will occur if the
interrupt is enabled in the MIER register and no other higher priority task is pending. The bits can also be
cleared manually by writing to the MICLR register. Writes to the MIFR register are ignored.
Figure 7-24. MIFR Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-51. MIFR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 8 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 8 interrupt has been received and is pending execution

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Table 7-51. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
6 INT7 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 7 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 7 interrupt has been received and is pending execution
5 INT6 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 6 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 6 interrupt has been received and is pending execution
4 INT5 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 5 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 5 interrupt has been received and is pending execution

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Table 7-51. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 4 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 4 interrupt has been received and is pending execution
2 INT3 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 3 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 3 interrupt has been received and is pending execution
1 INT2 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 2 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 2 interrupt has been received and is pending execution

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Table 7-51. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INT1 R 0h These bits, when set to '1', indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to '1' while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 1 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 1 interrupt has been received and is pending execution

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7.8.4.16 MIOVF Register (Offset = 21h) [Reset = 0000h]

MIOVF is shown in Figure 7-25 and described in Table 7-52.
Return to the Summary Table.
Each bit in the overflow flag register corresponds to a CLA task. The bit is set when an interrupt overflow
event has occurred for the specific task. An overflow event occurs when the MIFR register bit is already
set when a new interrupt is received from a peripheral source. The MIOVF bits are only affected by
peripheral interrupt events. They do not respond to a task request by the main CPU IACK instruction or by
directly setting MIFR bits. The overflow flag will remain latched and can only be cleared by writing to the
overflow flag clear (MICLROVF) register. Writes to the MIOVF register are ignored.
Figure 7-25. MIOVF Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-52. MIOVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 8 interrupt overflow has not occurred (default)
1h (R/W) = A task 8 interrupt overflow has occurred
6 INT7 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 7 interrupt overflow has not occurred (default)
1h (R/W) = A task 7 interrupt overflow has occurred

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Table 7-52. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 6 interrupt overflow has not occurred (default)
1h (R/W) = A task 6 interrupt overflow has occurred
4 INT5 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 5 interrupt overflow has not occurred (default)
1h (R/W) = A task 5 interrupt overflow has occurred
3 INT4 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 4 interrupt overflow has not occurred (default)
1h (R/W) = A task 4 interrupt overflow has occurred

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Table 7-52. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INT3 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 3 interrupt overflow has not occurred (default)
1h (R/W) = A task 3 interrupt overflow has occurred
1 INT2 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 2 interrupt overflow has not occurred (default)
1h (R/W) = A task 2 interrupt overflow has occurred
0 INT1 R 0h These bits, when set to '1', indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 1 interrupt overflow has not occurred (default)
1h (R/W) = A task 1 interrupt overflow has occurred

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7.8.4.17 MIFRC Register (Offset = 22h) [Reset = 0000h]

MIFRC is shown in Figure 7-26 and described in Table 7-53.
Return to the Summary Table.
The interrupt force register can be used by the main CPU to start tasks through software. Writing a 1 to a
MIFRC bit will set the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0. The IACK #16bit operation can also be used to start tasks and has the same effect as the
MIFRC register. To enable IACK to set MIFR bits you must first set the MCTL[IACKE] bit. Using IACK has
the advantage of not having to first set the EALLOW bit. This allows the main CPU to efficiently trigger
CLA tasks through software.
Figure 7-26. MIFRC Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-53. MIFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 8 interrupt
6 INT7 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 7 interrupt
5 INT6 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 6 interrupt
4 INT5 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 5 interrupt

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Table 7-53. MIFRC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 4 interrupt
2 INT3 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 3 interrupt
1 INT2 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 2 interrupt
0 INT1 R-0/W1S 0h Writing a '1' to any of the bits will set the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 1 interrupt

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7.8.4.18 MICLR Register (Offset = 23h) [Reset = 0000h]

MICLR is shown in Figure 7-27 and described in Table 7-54.
Return to the Summary Table.
Normally bits in the MIFR register are automatically cleared when a task begins. The interrupt flag clear
register can be used to instead manually clear bits in the interrupt flag (MIFR) register. Writing a 1 to a
MICLR bit will clear the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0.
Figure 7-27. MICLR Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-54. MICLR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt flag
6 INT7 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt flag
5 INT6 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt flag
4 INT5 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt flag

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Table 7-54. MICLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt flag
2 INT3 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt flag
1 INT2 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt flag
0 INT1 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIFR bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt flag

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7.8.4.19 MICLROVF Register (Offset = 24h) [Reset = 0000h]

MICLROVF is shown in Figure 7-28 and described in Table 7-55.
Return to the Summary Table.
Overflow flag bits in the MIOVF register are latched until manually cleared using the MICLROVF register.
Writing a 1 to a MICLROVF bit will clear the corresponding bit in the MIOVF register. Writes of 0 are
ignored and reads always return 0.
Figure 7-28. MICLROVF Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-55. MICLROVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt overflow flag
6 INT7 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt overflow flag
5 INT6 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt overflow flag
4 INT5 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt overflow flag

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Table 7-55. MICLROVF Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt overflow flag
2 INT3 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt overflow flag
1 INT2 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt overflow flag
0 INT1 R-0/W1S 0h Writing a '1' to any of the bits will clear the corresponding MIOVF bit.
Writes of '0' are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt overflow flag

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7.8.4.20 MIER Register (Offset = 25h) [Reset = 0000h]

MIER is shown in Figure 7-29 and described in Table 7-56.
Return to the Summary Table.
Setting the bits in the interrupt enable register (MIER) allow an incoming interrupt or main CPU software to
start the corresponding CLA task. Writing a 0 will block the task, but the interrupt request will still be
latched in the flag register (MIFLG). Setting the MIER register bit to 0 while the corresponding task is
executing will have no effect on the task. The task will continue to run until it hits the MSTOP instruction.
When a soft reset is issued, the MIER bits are cleared. There should always be at least a 1 SYSCLKOUT
delay between issuing the soft reset and reconfiguring the MIER bits.
Figure 7-29. MIER Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-56. MIER Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 8 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 8 interrupt is enabled
6 INT7 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 7 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 7 interrupt is enabled

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Table 7-56. MIER Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 6 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 6 interrupt is enabled
4 INT5 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 5 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 5 interrupt is enabled
3 INT4 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 4 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 4 interrupt is enabled
2 INT3 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 3 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 3 interrupt is enabled

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Table 7-56. MIER Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INT2 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 2 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 2 interrupt is enabled
0 INT1 R/W 0h Setting any of the bits to '1' enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a '0' blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to '1', the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to '0', it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 1 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 1 interrupt is enabled

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7.8.4.21 MIRUN Register (Offset = 26h) [Reset = 0000h]

MIRUN is shown in Figure 7-30 and described in Table 7-57.
Return to the Summary Table.
The interrupt run status register (MIRUN) indicates which task is currently executing. Only one MIRUN bit
will ever be set to a 1 at any given time. The bit is automatically cleared when the task competes and the
respective interrupt is fed to the peripheral interrupt expansion (PIE) block of the device. This lets the main
CPU know when a task has completed. The main CPU can stop a currently running task by writing to the
MCTL[SOFTRESET] bit. This will clear the MIRUN flag and stop the task. In this case no interrupt will be
generated to the PIE.
Figure 7-30. MIRUN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-57. MIRUN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 8 is not executing (default)
1h (R/W) = Task 8 is executing
6 INT7 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 7 is not executing (default)
1h (R/W) = Task 7 is executing
5 INT6 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 6 is not executing (default)
1h (R/W) = Task 6 is executing

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Table 7-57. MIRUN Register Field Descriptions (continued)

Bit Field Type Reset Description
4 INT5 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 5 is not executing (default)
1h (R/W) = Task 5 is executing
3 INT4 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 4 is not executing (default)
1h (R/W) = Task 4 is executing
2 INT3 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 3 is not executing (default)
1h (R/W) = Task 3 is executing
1 INT2 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 2 is not executing (default)
1h (R/W) = Task 2 is executing
0 INT1 R 0h These bits indicate which task is currently active. Only one bit can be
set to '1' at any one time. The bit is automatically cleared to '0' when
the task completes and the respective CLAINTxn line is toggled to
indicate task completion. The CLAINTxn interrupt line can be fed to
the PIE of the CPU so the CPU knows when a task has completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 1 is not executing (default)
1h (R/W) = Task 1 is executing

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7.8.4.22 _MPC Register (Offset = 28h) [Reset = 0000h]

_MPC is shown in Figure 7-31 and described in Table 7-58.
Return to the Summary Table.
CLA Program Counter
Figure 7-31. _MPC Register
15 14 13 12 11 10 9 8
_MPC
R-0h

7 6 5 4 3 2 1 0
_MPC
R-0h

Table 7-58. _MPC Register Field Descriptions

Bit Field Type Reset Description
15-0 _MPC R 0h Program Counter: The PC value is initialized by the appropriate
MVECTx register when an interrupt (task) is serviced.
The MPC register address 16-bits and not 32-bits. Hence the
address range of the CLA with a 16-bit MPC is 64Kx16 words or
32K CLA instructions.
Notes: [1] To be consistent with C28 core implementation, the PC
value points to the instruction in D2 stage of pipeline.
[2] After a STOP operation, and with no other task pending, the PC
will remain pointing to the STOP operation.
Reset type: SYSRSn

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7.8.4.23 _MAR0 Register (Offset = 2Ah) [Reset = 0000h]

_MAR0 is shown in Figure 7-32 and described in Table 7-59.
Return to the Summary Table.
CLA Auxiliary Register 0
Figure 7-32. _MAR0 Register
15 14 13 12 11 10 9 8
_MAR0
R-0h

7 6 5 4 3 2 1 0
_MAR0
R-0h

Table 7-59. _MAR0 Register Field Descriptions

Bit Field Type Reset Description
15-0 _MAR0 R 0h CLA Auxillary Register 0
Reset type: SYSRSn

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7.8.4.24 _MAR1 Register (Offset = 2Bh) [Reset = 0000h]

_MAR1 is shown in Figure 7-33 and described in Table 7-60.
Return to the Summary Table.
CLA Auxiliary Register 1
Figure 7-33. _MAR1 Register
15 14 13 12 11 10 9 8
_MAR1
R-0h

7 6 5 4 3 2 1 0
_MAR1
R-0h

Table 7-60. _MAR1 Register Field Descriptions

Bit Field Type Reset Description
15-0 _MAR1 R 0h CLA Auxillary Register 1
Reset type: SYSRSn

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7.8.4.25 _MSTF Register (Offset = 2Eh) [Reset = 00000000h]

_MSTF is shown in Figure 7-34 and described in Table 7-61.
Return to the Summary Table.
The CLA status register (MSTF) reflects the results of different operations. These are the basic rules for
the flags:
- Zero and negative flags are cleared or set based on:
- floating-point moves to registers
- the result of compare, minimum, maximum, negative and absolute value operations
- the integer result of operations such as MMOV16, MAND32, MOR32, MXOR32, MCMP32,
MASR32, MLSR32
- Overflow and underflow flags are set by floating-point math instructions such as multiply, add, subtract
and 1/x. These flags may also be connected to the peripheral interrupt expansion (PIE) block on your
device. This can be useful for debugging underflow and overflow conditions within an application.
Figure 7-34. _MSTF Register
31 30 29 28 27 26 25 24
RESERVED _RPC
R-0h R-0h

23 22 21 20 19 18 17 16
_RPC
R-0h

15 14 13 12 11 10 9 8
_RPC MEALLOW RESERVED RNDF32 RESERVED
R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED TF RESERVED ZF NF LUF LVF
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-61. _MSTF Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-12 _RPC R 0h Return program counter
The _RPC is used to save and restore the MPC address by the
MCCNDD and MRCNDD operations
Reset type: SYSRSn
11 MEALLOW R 0h MEALLOW Status
This bit enables and disables CLA write access to EALLOW
protected registers This is independent of the state of the EALLOW
bit in the main CPU status register This status bit can be saved and
restored by the MMOV32 STF, mem32 instruction
Reset type: SYSRSn
0h (R/W) = The CLA cannot write to EALLOW protected registers.
This bit is cleared by the CLA instruction, MEDIS.
1h (R/W) = The CLA is allowed to write to EALLOW protected
registers. This bit is set by the CLA instruction, MEALLOW.
10 RESERVED R 0h Reserved

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Table 7-61. _MSTF Register Field Descriptions (continued)

Bit Field Type Reset Description
9 RNDF32 R 0h Round 32-bit Floating-Point Mode
Use the MSETFLG and MMOV32 MSTF, mem32 instructions to
change the rounding mode
Reset type: SYSRSn
0h (R/W) = If this bit is zero, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to zero (truncate).
1h (R/W) = If this bit is one, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to the nearest even value.
8-7 RESERVED R 0h Reserved
6 TF R 0h Test Flag
The MTESTTF instruction can modify this flag based on the
condition tested The MSETFLG and MMOV32 MSTF, mem32
instructions can also be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The condition tested with the MTESTTF instruction is
false.
1h (R/W) = The condition tested with the MTESTTF instruction is
true.
5-4 RESERVED R 0h Reserved
3 ZF R 0h Zero Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result of
the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not zero
1h (R/W) = The value is zero
2 NF R 0h Negative Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result of
the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not negative
1h (R/W) = The value is negative

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Table 7-61. _MSTF Register Field Descriptions (continued)

Bit Field Type Reset Description
1 LUF R 0h Latched Underflow Flag
The following instructions will set this flag to 1 if an underflow occurs:
MMPYF32, MADDF32,
MSUBF32, MMACF32, MEINVF32, MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An underflow condition has not been latched
1h (R/W) = An underflow condition has been latched
0 LVF R 0h Latched Overflow Flag
The following instructions will set this flag to 1 if an overflow
occurs: MMPYF32, MADDF32, MSUBF32, MMACF32, MEINVF32,
MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An overflow condition has not been latched
1h (R/W) = An overflow condition has been latched

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7.8.4.26 _MR0 Register (Offset = 30h) [Reset = 00000000h]

_MR0 is shown in Figure 7-35 and described in Table 7-62.
Return to the Summary Table.
CLA Floating-Point Result Register 0
Figure 7-35. _MR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 7-62. _MR0 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 0
Reset type: SYSRSn

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7.8.4.27 _MR1 Register (Offset = 34h) [Reset = 00000000h]

_MR1 is shown in Figure 7-36 and described in Table 7-63.
Return to the Summary Table.
CLA Floating-Point Result Register 1
Figure 7-36. _MR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 7-63. _MR1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 1
Reset type: SYSRSn

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7.8.4.28 _MR2 Register (Offset = 38h) [Reset = 00000000h]

_MR2 is shown in Figure 7-37 and described in Table 7-64.
Return to the Summary Table.
CLA Floating-Point Result Register 2
Figure 7-37. _MR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 7-64. _MR2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 2
Reset type: SYSRSn

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7.8.4.29 _MR3 Register (Offset = 3Ch) [Reset = 00000000h]

_MR3 is shown in Figure 7-38 and described in Table 7-65.
Return to the Summary Table.
CLA Floating-Point Result Register 3
Figure 7-38. _MR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 7-65. _MR3 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 3
Reset type: SYSRSn

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7.8.4.30 _MPSACTL Register (Offset = 42h) [Reset = 0000h]

_MPSACTL is shown in Figure 7-39 and described in Table 7-66.
Return to the Summary Table.
PSA Control Register
Figure 7-39. _MPSACTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
MPSA2CFG MPSA2CLEAR MPSA1CLEAR MDWDBCYC MDWDBSTART MPABCYC MPABSTART
R/W-0h R-0/W1S-0h R-0/W1S-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-66. _MPSACTL Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7-6 MPSA2CFG R/W 0h CLA PSA2 Polynomial Configuration Bits: These bits configure the
type of polynomial used for PSA2. The polynomials chosen are
commonly used in the industry:
Mode Polynomial Type
0,0 PSA
0,1 CRC32
1,0 CRC16
1,1 CRC16-CCITT
Note: [1] Polynomial configuration should be performed when PSA2
is stopped.
Reset type: SYSRSn
5 MPSA2CLEAR R-0/W1S 0h CLA PSA2 Clear Bit:
Writing of '1' will clear contents of PSA2 register.
Writes of '0' are ignored.
Always reads back a '0'
Note: Clearing operation should be performed when PSA2 is
stopped.
Reset type: SYSRSn
4 MPSA1CLEAR R-0/W1S 0h CLA PSA1 Clear Bit:
Writing of '1' will clear contents of PSA1 register.
Writes of '0' are ignored.
Always reads back a '0'
Note: Clearing operation should be performed when PSA1 is
stopped.
Reset type: SYSRSn
3 MDWDBCYC R/W 0h CLA Data Write Data Bus PSA2 Cycle or Event Based Bit:
0 PSA2 calculated on every cycle
1 PSA2 calculated on every bus event
Reset type: SYSRSn
2 MDWDBSTART R/W 0h CLA Data Write Data Bus PSA2 Start/Stop Bit:
0 PSA2 stopped
1 PSA2 start
Reset type: SYSRSn
1 MPABCYC R/W 0h CLA Program Address Bus PSA1 Cycle/Event Based Bit:
0 PSA1 calculated on every cycle
1 PSA1 calculated on every bus event
Reset type: SYSRSn

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Table 7-66. _MPSACTL Register Field Descriptions (continued)

Bit Field Type Reset Description
0 MPABSTART R/W 0h CLA Program Address Bus PSA1 Start/Stop Bit:
0 PSA1 stopped
1 PSA1 start
Reset type: SYSRSn

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7.8.4.31 _MPSA1 Register (Offset = 44h) [Reset = 00000000h]

_MPSA1 is shown in Figure 7-40 and described in Table 7-67.
Return to the Summary Table.
PSA1 Register
Figure 7-40. _MPSA1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 7-67. _MPSA1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA1 Value: Reading this register gives the current PSA1 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA1 to a known
value. Writes to this register should only be made when PSA1 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA1CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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7.8.4.32 _MPSA2 Register (Offset = 46h) [Reset = 00000000h]

_MPSA2 is shown in Figure 7-41 and described in Table 7-68.
Return to the Summary Table.
PSA2 Register
Figure 7-41. _MPSA2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 7-68. _MPSA2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA2 Value: Reading this register gives the current PSA2 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA2 to a known
value. Writes to this register should only be made when PSA2 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA2CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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www.ti.com Neural-network Processing Unit (NPU)

Chapter 8
Neural-network Processing Unit (NPU)

This chapter describes the features and operation of the Neural-network Processing Unit, used to improve the
efficiency of machine learning inferencing.

8.1 Introduction.............................................................................................................................................................1052

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8.1 Introduction
The Neural-network Processing Unit (NPU) can support intelligent inferencing running pre-trained models.
Capable of 600–1200MOPS (Mega Operations Per Second) with example model support for ARC fault detection
or Motor Fault detection, the NPU provides up to 10x Neural Network (NN) inferencing cycle improvement
versus a software only based implementation. Load and train models with tools from TI: Model Composer GUI
or TI's command-line Modelmaker tool for an advanced set of capabilities. Both of these options automatically
generate source code for the C28x, eliminating the need to manually write code.
Figure 8-1shows the toolchain and steps to add NPU support to a project, starting with importing or using
existing models from TI, training the models, generating the associated software libraries, and integrating into an
existing Code Composer Studio™ IDE project.

Figure 8-1. NPU Development Flow

8.1.1 NPU Related Collateral

Foundational Materials
• Model Composer

Expert Materials
• Neural Network Compiler
• Tiny ML ModelMaker

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www.ti.com Dual-Clock Comparator (DCC)

Chapter 9
Dual-Clock Comparator (DCC)

This chapter describes the Dual-Clock Comparator (DCC) module.

9.1 Introduction.............................................................................................................................................................1054
9.2 Module Operation................................................................................................................................................... 1055
9.3 Interrupts.................................................................................................................................................................1061
9.4 Software.................................................................................................................................................................. 1062
9.5 DCC Registers........................................................................................................................................................ 1064

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9.1 Introduction
The dual-clock comparator module is used for evaluating and monitoring the clock input based on a second
clock, which can be a more accurate and reliable version. This instrumentation is used to detect faults in clock
source or clock structures, thereby enhancing the system's safety metrics.
9.1.1 Features
The main features of each of the DCC modules are:
• Allows the application to make sure that a fixed ratio is maintained between frequencies of two clock signals.
• Supports the definition of a programmable tolerance window in terms of the number of reference clock cycles.
• Supports continuous monitoring without requiring application intervention.
• Supports a single-sequence mode for spot measurements.
• Allows the selection of a clock source for each of the counters, resulting in several specific use cases.

9.1.2 Block Diagram

Figure 9-1 shows how the DCC connects to the rest of the system. Figure 9-2 shows the main concept of the
DCC module.

VBUSP Bus Interface

Clock Sources

Input XBAR

APLL

Error
XOSC

Interrupt
INTOSC1,2 DCC

AUXCLK

System Control
Clock
Gates, Dividers Peripheral
Clocks

Figure 9-1. DCC Module Overview

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DCC
20 Module
DCCxCLKSRC0 Counter0

DCCxCLKSRC0
20 DCC DONE
Valid0
Compare Logic ERROR

20
DCCxCLKSRC1 Counter1

Figure 9-2. DCC Operation

9.2 Module Operation

As shown in Figure 9-2, DCC contains three counters – Counter0, Valid0 and Counter1. Initially, all counters
are loaded with the user-defined, pre-load value. Counter0 and Counter1 start decrementing once the DCC is
enabled at rates determined by the frequencies of Clock0 and Clock1, respectively. When Counter0 equals 0
(expires), the Valid0 counter decrements at a rate determined by Clock0. If Counter1 decrements to 0 in the valid
window, then no error is generated and Clock1 is considered to be good within allowable tolerance as configured
by the user.

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9.2.1 Configuring DCC Counters

Counter0 and Counter1 are configured based on the ratio between the frequencies of Clock0 and Clock1
(Fclk1 × Counter0 = Fclk0×Counter1). The Valid0 counter provides tolerance and is configured based on the
error in DCC. Since Clock0 and Clock1 are asynchronous, the start and stop of the counters do not occur
synchronously. Hence, while configuring the counters, two different sources of errors must be accounted for:
• DCC Errors due to the asynchronous timing of Clock0 and Clock1: this depends on the frequency of Clock0
and Clock1:
– If Fclk1 > Fclk0, then Async. Error (in Clock0 cycles) = 2 + 2 × (Fsysclk/Fclk0)
– If Fclk1 < Fclk0, then Async. Error (in Clock0 cycles) = 2 × (Fclk0/Fclk1) + 2 × (Fsysclk/Fclk0)
– If Fclk1 is unknown, then Async. Error (in Clock0 cycles) = 2 + 2 × (Fsysclk/Fclk0)
• Digitization Error = 8 Clock0 cycles

DCC Error (in Clock0 Cycles) = Async. Error + Digitization Error

DCC error shows up as a frequency error for clock under measurement. This error is DCC induced and does not
represent error in frequency of clock under measurement. The application needs to take this into consideration
while configuring the counters, and determine a desirable tolerance for DCC error that defines the window of
measurement. To illustrate:
Window (in Clock0 Cycles) = (DCC Error)/(0.01 × Tolerance)
For example, if DCC Error is 10 and the tolerance desired is ±0.1%, then:
Window (in Clock0 Cycles) = 10/(0.01 × 0.1) = 10000

Based on above formula for Window, if the desired tolerance is low, then the counter values are large and
increase the window of measurement. This means that counter values for a tolerance of 0.1% are larger than
that of 0.2%. So, based on the application defined tolerance, define the window of measurement in terms of
Clock0 cycles.
The clock under measurement can have an allowed frequency error. If this error is expected, then the error
can also be accounted while configuring counters. For example, if measuring INTOSC1/2 frequency using
an external crystal as a reference clock, the allowable tolerance of INTOSC1/2 (for example, ±1%) can be
accounted for and factored into the counter configuration. The formula is:
Frequency Error Allowed (in Clock0 Cycles) = Window × (Allowable Frequency Tolerance (in %) / 100)
Total Error (in Clock0 Cycles) = DCC Error + Frequency Error Allowed

The following equations are used to configure counter values:

Counter0 (DCCCNTSEED0) = Window - Total Error
Valid0 (DCCVALIDSEED0) = 2 × Total Error
Counter1 (DCCCNTSEED1) = Window × (Fclk1/Fclk0)

Note
Counter1 is a 20-bit counter, so the maximum possible value cannot exceed 1048575. If the value
does exceed, then increase the desired Tolerance for DCC error, so that Window of measurement is
lowered. The following formula can be used to compute minimum tolerance possible:
Tolerance (%) = (100 × DCC Error × (Fclk1/Fclk0)) / 1048575

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9.2.2 Single-Shot Measurement Mode

The DCC module can be programmed to count down one time by enabling the single-shot mode. In this mode,
the DCC stops operating when the down counter0 and the valid counter0 reach 0.
At the end of one sequence of counting down in this single-shot mode, the DCC gets disabled automatically,
which prevents further counting. This mode is typically used for spot-checking the frequency of a signal.
Example-1: Validating PLLRAWCLK frequency
A practical example of the usage is to validate the PLL output clock frequency using the XTAL as the reference
clock. Assume XTAL is 10MHz, PLL output frequency is 100MHz, SYSCLK is 100MHz, allowable Frequency
Tolerance is 0.1%, and DCC Tolerance required is 0.1%. The measurement sequence proceeds as follows:
• Set Clock0 source for Counter0 and Valid0 as XTAL, and Clock1 source for Counter1 as PLL output clock.
• Based on the equations defined in Section 9.2.1, calculated seed values for Counters can be Counter0 =
29940; Valid0 = 120; Counter1 = 300000
• Once the DCC is enabled, the counters Counter0 and Counter1 both start counting down from the seed
values.
• When Counter0 reaches zero, Counter0 automatically triggers the Valid0 counter.
• When Valid0 reaches zero and Counter1 is not zero, an ERROR status flag is set and a "DCC error" is
sent to the PIE. Counter1 is frozen so that the counter stops counting down any further. The application can
enable an interrupt to be generated from the PIE whenever this DCC error is indicated. Refer to the PIE
Channel Mapping table in the System Control and Interrupts chapter to determine the channel mapping of the
DCC Interrupt.
• The application then needs to clear the ERROR status flag and restart the DCC module so that the module is
ready for the next spot measurement.
If there is no error generated at the end of the sequence, then the DONE status flag is set and a DONE interrupt
is generated. The application must clear the DONE flag before restarting the DCC.
Error Conditions:
An error condition is generated by any one of the following:
1. Counter1 counts down to 0 before Counter0 reaches 0. This means that Clock1 is faster than expected, or
Clock0 is slower than expected. This error includes the case when Clock0 is stuck at 1 or 0.
2. Counter1 does not reach 0 even when Counter0 and Valid0 have both reached 0. This means that Clock1 is
slower than expected. This error includes the case when Clock1 is stuck at 1 or 0.
Any error freezes the counters from counting. An application can then read out the counter values to help
determine what caused the error.

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Example-2: Measuring AUXCLKIN frequency

Another example of single-shot mode is to measure the frequency of AUXCLKIN (unknown frequency) using
INTOSC1 (10MHz) as the reference clock and SYSCLK is 10MHz. The measurement sequence proceeds as
follows:
• Set Clock0 source for Counter0 and Valid0 as INTOSC1 (10MHz), and Clock1 source for Counter1 as
AUXCLKIN.
• Now configure counter values using equations in Section 9.2.1. For tolerance = ±0.1%, Total
Error = 10 clock0 cycles; Window = 10000 clock0 cycles; Counter0 = 9990; Valid0 = 20. Since Clock1
frequency (Fclk1) is unknown, the Counter1 value can be set to the maximum value, 1048575 (0xFFFFF).
• Once the DCC is enabled, the counters Counter0 and Counter1 both start counting down from the seed
values.
• Since Counter1 is set to the maximum value, 1048575, the counter does not expire when Counter0 and
Valid0 have expired. This generates an error that is expected and the application ignores this error and uses
Counter1 values to compute the frequency of Clock1 (Fclk1).
• Knowing the frequency of Clock0 (INTOSC1), Fclk0 = 10MHz, and using Equation 2, the frequency of
AUXCLKIN, Fclk1, can be measured:

(?HG0 × :1048575 F /A=O. %KQJPAN1; 10 × (1048575 F /A=O. %KQJPAN1)

(?HG1 = =
:%KQJPAN0 + 8=HE@0; (9990 + 20)
(2)

9.2.3 Continuous Monitoring Mode

In this mode, the DCC is used by the application to make sure that two clock signals maintain the correct
frequency ratio. Suppose the application wants to make sure that the PLL output signal always maintains a fixed
frequency relationship with the XTAL:
• In this case, the application can use the XTAL as the Clock0 signal (for Counter0 and Valid0) and the PLL
output as the Clock1 (for Counter1).
• The seed values of Counter0, Valid0 and Counter1 are selected based on the equations defined in Section
9.2.1 such that if the actual frequencies of Clock0 and Clock1 are equal to the expected frequencies, then the
Counter1 reaches zero during the count down of the Valid0 counter.
• If the Counter1 reaches zero during the count down of the Valid0 counter, then all the counters (Counter0,
Valid0, Counter1) are reloaded with the initial seed values.
• This sequence of counting down and checking then continues as long as there is no error, or until the DCC
module is disabled.
• The counters must get reloaded if the application resets and restarts the DCC module.
Error Conditions:
An error condition is generated by one of the following:
1. Counter1 counts down to 0 before Counter0 reaches 0. This means that Clock1 is faster than expected or
Clock0 is slower than expected. This condition includes the case when Clock0 is stuck at 1 or 0.
2. Counter1 does not reach 0 even when Counter0 and Valid0 have both reached 0. This means that Clock1 is
slower than expected. This condition includes the case when Clock1 is stuck at 1 or 0.
Any error freezes the counters from counting. An application can then read out the counter values to help
determine what caused the error.

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9.2.4 Error Conditions

While operating in continuous mode, the counters get reloaded with the seed values and continue counting down
under the following conditions:
• The module is reset or restarted by the application, OR
• Counter0, Valid 0, and Counter1 all reach 0 without any error.

(no error)
Error

Count0 Count0
Clock0

Valid0 Valid0
0

Count1 Count1
Clock1

0
time
reload reload
Clock1 must expire
in this window, otherwise
signal an error

Figure 9-3. Counter Relationship

Error

Count0
Clock0

Valid0
0

Count1
Clock1

0
time
reload
Counter1 does not reach 0
before VALID0 reaches 0
Figure 9-4. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting

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Error

Count0
Clock0

Valid0
0

Count1
Clock1

0
time
reload
Counter1 reaches 0 before
Counter0 reaches 0
Figure 9-5. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting

Error

Count0
Clock0

Valid0
0

Count1
Count1 does not count down
Clock1 due to an inactive clock 1

0
time
reload
An error signal is generated since Count1
does not reach 0 in the Valid0 window.
Figure 9-6. Clock1 Not Present - Results in an Error and Stops Counting

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Error
Count0
Count0 and Valid 0 do not
Clock0 count down due to an
inactive clock 0
Valid0

Count1
Clock1

time
reload
Counter1 reaches 0 at the
right time, but since Clock0 is not running,
Valid0 hasn’t started, thus an error is generated.

Figure 9-7. Clock0 Not Present - Results in an Error and Stops Counting

9.3 Interrupts
DCC generates an interrupt on either of two events:
• DCC finishes counting and all the counters expire within a defined window indicating DONE operation,
provided DCCGCTRL.DONENA = 1.
• DCC finishes counting with error where counters do not expire in a defined window. This indicates an
ERROR event, and sets an interrupt provided DCCGCTRL.ERRENA = 1.
Interrupts generated by DONE or ERROR events are ORed and flagged as a SYS_ERR interrupt. Refer to the
PIE Channel Mapping table in the System Control and Interrupts chapter to determine the interrupt channel
mapping. The application interrupt service routine needs to check the status flag inside the DCCSTATUS register
to determine whether the interrupt is due to ERROR or DONE.
DCC Error interrupts can also be configured as a Non-Maskable Interrupt (NMI) by enabling the
CLKFAILCFG.DCCx_ERROR_EN flag.

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9.4 Software
9.4.1 DCC Registers to Driverlib Functions
Table 9-1. DCC Registers to Driverlib Functions
File Driverlib Function
DCCGCTRL
dcc.h DCC_enableModule
dcc.h DCC_disableModule
dcc.h DCC_enableErrorSignal
dcc.h DCC_enableDoneSignal
dcc.h DCC_disableErrorSignal
dcc.h DCC_disableDoneSignal
dcc.h DCC_enableSingleShotMode
dcc.h DCC_disableSingleShotMode
DCCCNTSEED0
dcc.h DCC_setCounterSeeds
DCCVALIDSEED0
dcc.h DCC_setCounterSeeds
DCCCNTSEED1
dcc.h DCC_setCounterSeeds
DCCSTATUS
dcc.h DCC_getErrorStatus
dcc.h DCC_getSingleShotStatus
dcc.h DCC_clearErrorFlag
dcc.h DCC_clearDoneFlag
sysctl.c SysCtl_isPLLValid
DCCCNT0
dcc.h DCC_getCounter0Value
DCCVALID0
dcc.h DCC_getValidCounter0Value
DCCCNT1
dcc.h DCC_getCounter1Value
DCCCLKSRC1
dcc.h DCC_setCounter1ClkSource
dcc.h DCC_getCounter1ClkSource
DCCCLKSRC0
dcc.h DCC_setCounter0ClkSource
dcc.h DCC_getCounter0ClkSource

9.4.2 DCC Examples

NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/dcc
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
9.4.2.1 DCC Single shot Clock measurement
FILE: dcc_ex2_single_shot_measurement.c

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This program demonstrates Single Shot measurement of the INTOSC2 clock post trim using XTAL as the
reference clock.
The Dual-Clock Comparator Module 0 is used for the clock measurement. The clocksource0 is the reference
clock (Fclk0 = 20Mhz) and the clocksource1 is the clock that needs to be measured (Fclk1 = 10Mhz). Since the
frequency of the clock1 needs to be measured an initial seed is set to the max value of the counter.
Please refer to the TRM for details on counter seed values to be set.

External Connections
• None
Watch Variables
• result - Status if the INTOSC2 clock measurement completed successfully.
• meas_freq1 - measured clock frequency, in this case for INTOSC2.
9.4.2.2 DCC Single shot Clock verification
FILE: dcc_ex1_single_shot_verification.c
This program uses the XTAL clock as a reference clock to verify the frequency of the PLLRAW clock.
The Dual-Clock Comparator Module 0 is used for the clock verification. The clocksource0 is the reference clock
(Fclk0 = 20Mhz) and the clocksource1 is the clock that needs to be verified (Fclk1 = 150Mhz). Seed is the value
that gets loaded into the Counter.
Please refer to the TRM for details on counter seed values to be set.

External Connections
• None
Watch Variables
• status/result - Status of the PLLRAW clock verification
9.4.2.3 DCC Continuous clock monitoring
FILE: dcc_ex3_continuous_monitoring_of_clock_syscfg.c
This program demonstrates continuous monitoring of PLL Clock in the system using INTOSC2 as the reference
clock. This would trigger an interrupt on any error, causing the decrement/ reload of counters to stop. The
Dual-Clock Comparator Module 0 is used for the clock monitoring. The clocksource0 is the reference clock
(Fclk0 = 10Mhz) and the clocksource1 is the clock that needs to be monitored (Fclk1 = 150Mhz). The clock0 and
clock1 seed are set automatically by the error tolerances defined in the sysconfig file included this project. For
the sake of demo an un-realistic tolerance is assumed to generate an error on continuous monitoring.
Please refer to the TRM for details on counter seed values to be set. Note : When running in flash configuration
it is good to do a reset & restart after loading the example to remove any stale flags/states.
External Connections
• None
Watch Variables
• status/result - Status of the PLLRAW clock monitoring
• cnt0 - Counter0 Value measure when error is generated
• cnt1 - Counter1 Value measure when error is generated
• valid - Valid0 Value measure when error is generated
9.4.2.4 DCC Continuous clock monitoring
FILE: dcc_ex3_continuous_monitoring_of_clock.c

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This program demonstrates continuous monitoring of PLL Clock in the system using INTOSC2 as the reference
clock. This would trigger an interrupt on any error, causing the decrement/ reload of counters to stop.
The Dual-Clock Comparator Module 0 is used for the clock monitoring. The clocksource0 is the reference clock
(Fclk0 = 10Mhz) and the clocksource1 is the clock that needs to be monitored (Fclk1 = 150Mhz). The clock0 and
clock1 seed are set to achieve a window of 400us. Seed is the value that gets loaded into the Counter. For the
sake of demo a slight variance is given to clock1 seed value to generate an error on continuous monitoring.
Please refer to the TRM for details on counter seed values to be set. Note : When running in flash configuration
it is good to do a reset & restart after loading the example to remove any stale flags/states.
External Connections
• None
Watch Variables
• status/result - Status of the PLLRAW clock monitoring
• cnt0 - Counter0 Value measure when error is generated
• cnt1 - Counter1 Value measure when error is generated
• valid - Valid0 Value measure when error is generated
9.4.2.5 DCC Detection of clock failure
FILE: dcc_ex4_clock_fail_detect.c
This program demonstrates clock failure detection on continuous monitoring of the PLL Clock in the system
using XTAL as the osc clock source. Once the oscillator clock fails, it would trigger a DCC error interrupt,
causing the decrement/ reload of counters to stop. In this examples, the clock failure is simulated by turning off
the XTAL oscillator. Once the ISR is serviced, the osc source is changed to INTOSC1 and the PLL is turned off.
The Dual-Clock Comparator Module 0 is used for the clock monitoring. The clocksource0 is the reference clock
(Fclk0 = 20Mhz) and the clocksource1 is the clock that needs to be monitored (Fclk1 = 150Mhz). Seed is the
value that gets loaded into the Counter.
In the current example, the XTAL is expected to be a Resonator running in Crystal mode which is later switched
off to simulate the clock failure. If an SE Crystal is used, you will need to physically disconnect the clock on
the board. Please refer to the TRM for details on counter seed values to be set. Note : When running in flash
configuration it is good to do a reset & restart after loading the example to remove any stale flags/states.

External Connections
• None
Watch Variables
• status/result - Status of the clock failure detection
9.5 DCC Registers
This Section describes the DCC Registers.
9.5.1 DCC Base Address Table
Table 9-2. DCC Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1
Instance Structure Protected

Dcc0Regs DCC_REGS DCC0_BASE 0x0005_E700 YES - - YES

Dcc1Regs DCC_REGS DCC1_BASE 0x0005_E740 YES - - YES

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9.5.2 DCC_REGS Registers

Table 9-3 lists the memory-mapped registers for the DCC_REGS registers. All register offset addresses not
listed in Table 9-3 should be considered as reserved locations and the register contents should not be modified.
Table 9-3. DCC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h DCCGCTRL Starts / stops the counters. Clears the error Go
signal.
8h DCCCNTSEED0 Seed value for the counter attached to Clock Go
Source 0.
Ch DCCVALIDSEED0 Seed value for the timeout counter attached to Go
Clock Source 0.
10h DCCCNTSEED1 Seed value for the counter attached to Clock Go
Source 1.
14h DCCSTATUS Specifies the status of the DCC Module. Go
18h DCCCNT0 Value of the counter attached to Clock Source 0. Go
1Ch DCCVALID0 Value of the valid counter attached to Clock Go
Source 0.
20h DCCCNT1 Value of the counter attached to Clock Source 1. Go
24h DCCCLKSRC1 Selects the clock source for Counter 1. Go
28h DCCCLKSRC0 Selects the clock source for Counter 0. Go

Complex bit access types are encoded to fit into small table cells. Table 9-4 shows the codes that are used for
access types in this section.
Table 9-4. DCC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
R-1 R Read
-1 Returns 1s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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9.5.2.1 DCCGCTRL Register (Offset = 0h) [Reset = 00005555h]

DCCGCTRL is shown in Figure 9-8 and described in Table 9-5.
Return to the Summary Table.
Starts / stops the counters. Clears the error signal.
Figure 9-8. DCCGCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DONEENA SINGLESHOT ERRENA DCCENA
R/W-5h R/W-5h R/W-5h R/W-5h

Table 9-5. DCCGCTRL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 DONEENA R/W 5h DONE Enable
Enables/disables the done interrupt signal, but has no effect on the
done status flag in DCCSTAT register.
0101 The done signal is disabled
Others The done signal is enabled
Reset type: SYSRSn
11-8 SINGLESHOT R/W 5h Single-Shot Enable
Enables/disables repetitive operation of the DCC.
1010: Stop counting when COUNTER0 and VALID0 both reach zero
1011: Reserved
Others: Continuously repeat (until error)
Reset type: SYSRSn
7-4 ERRENA R/W 5h Error Enable
Enables/disables the error signal.
0101 The error signal is disabled
Others The error signal is enabled
Reset type: SYSRSn
3-0 DCCENA R/W 5h DCC Enable
Starts and stops the operation of the DCC.
0101 Counters are stopped
Others Counters are running
Reset type: SYSRSn

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9.5.2.2 DCCCNTSEED0 Register (Offset = 8h) [Reset = 00000000h]

DCCCNTSEED0 is shown in Figure 9-9 and described in Table 9-6.
Return to the Summary Table.
Seed value for the counter attached to Clock Source 0.
Figure 9-9. DCCCNTSEED0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED COUNTSEED0
R-0h R/W-0h

Table 9-6. DCCCNTSEED0 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-0 COUNTSEED0 R/W 0h Seed Value for Counter 0
Contains the seed value that gets loaded into Counter 0 (Clock
Source 0).
NOTE: Operating the DCC with '0' in the COUNTSEED0 register will
result in undefined operation.
Reset type: SYSRSn

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9.5.2.3 DCCVALIDSEED0 Register (Offset = Ch) [Reset = 00000000h]

DCCVALIDSEED0 is shown in Figure 9-10 and described in Table 9-7.
Return to the Summary Table.
Seed value for the timeout counter attached to Clock Source 0.
Figure 9-10. DCCVALIDSEED0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALIDSEED
R-0h R/W-0h

Table 9-7. DCCVALIDSEED0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 VALIDSEED R/W 0h Seed Value for Valid Duration Counter 0
Contains the seed value that gets loaded into the valid duration
counter for Clock Source 0.
NOTE: Operating the DCC with '0' in the VALIDSEED0 register will
result in undefined operation. VALID0 defines a window in which
COUNT1 expires. This window is meant to be at least four cycles
wide. Do not program a value less than '4' into the VALID0 register.
Reset type: SYSRSn

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9.5.2.4 DCCCNTSEED1 Register (Offset = 10h) [Reset = 00000000h]

DCCCNTSEED1 is shown in Figure 9-11 and described in Table 9-8.
Return to the Summary Table.
Seed value for the counter attached to Clock Source 1.
Figure 9-11. DCCCNTSEED1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED COUNTSEED1
R-0h R/W-0h

Table 9-8. DCCCNTSEED1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-0 COUNTSEED1 R/W 0h Seed Value for Counter 1
Contains the seed value that gets loaded into Counter 1 (Clock
Source 1).
NOTE: Operating the DCC with '0' in the COUNTSEED1 register will
result in undefined operation.
Reset type: SYSRSn

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9.5.2.5 DCCSTATUS Register (Offset = 14h) [Reset = 00000000h]

DCCSTATUS is shown in Figure 9-12 and described in Table 9-9.
Return to the Summary Table.
Specifies the status of the DCC Module.
Figure 9-12. DCCSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DONE ERR
R-0h R/W-0h R/W-0h

Table 9-9. DCCSTATUS Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 DONE R/W 0h Single-Shot Done Flag
Indicates when single-shot mode is complete without error. Writing a
'1' to this bit clears the flag.
0 Single-shot mode has not completed.
1 Single-shot mode has completed.
Reset type: SYSRSn
0 ERR R/W 0h Error Flag
Indicates whether or not an error has occurred. Writing a '1' to this bit
clears the flag.
0 No errors have occurred.
1 An error has occurred.
Reset type: SYSRSn

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9.5.2.6 DCCCNT0 Register (Offset = 18h) [Reset = 00000000h]

DCCCNT0 is shown in Figure 9-13 and described in Table 9-10.
Return to the Summary Table.
Value of the counter attached to Clock Source 0.
Figure 9-13. DCCCNT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED COUNT0
R-0h R-0h

Table 9-10. DCCCNT0 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-0 COUNT0 R 0h Current Value of Counter 0
Reset type: SYSRSn

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9.5.2.7 DCCVALID0 Register (Offset = 1Ch) [Reset = 00000000h]

DCCVALID0 is shown in Figure 9-14 and described in Table 9-11.
Return to the Summary Table.
Value of the valid counter attached to Clock Source 0.
Figure 9-14. DCCVALID0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALID0
R-0h R-0h

Table 9-11. DCCVALID0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 VALID0 R 0h Current Value of Valid 0
Reset type: SYSRSn

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9.5.2.8 DCCCNT1 Register (Offset = 20h) [Reset = 00000000h]

DCCCNT1 is shown in Figure 9-15 and described in Table 9-12.
Return to the Summary Table.
Value of the counter attached to Clock Source 1.
Figure 9-15. DCCCNT1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED COUNT1
R-0h R-0h

Table 9-12. DCCCNT1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-0 COUNT1 R 0h Current Value of Counter 1
Reset type: SYSRSn

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9.5.2.9 DCCCLKSRC1 Register (Offset = 24h) [Reset = 00000000h]

DCCCLKSRC1 is shown in Figure 9-16 and described in Table 9-13.
Return to the Summary Table.
Selects the clock source for Counter 1.
Figure 9-16. DCCCLKSRC1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED CLKSRC1
R-0/W-0h R-0h R/W-0h

Table 9-13. DCCCLKSRC1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 KEY R-0/W 0h Enables or Disables Clock Source Write for COUNT1
1010 The CLKSRC field selects the clock source for COUNT1.
Others: Previous values retained new writes on register fields has no
impact.
Reset type: SYSRSn
11-6 RESERVED R 0h Reserved
5-0 CLKSRC1 R/W 0h Clock Source Select for Counter 1
Specifies the clock source for COUNT1, when the KEY field enables
this feature.
Note: Any values not explicitly defined below are reserved.
Reset type: SYSRSn
0h (R/W) = Direct output of SYSPLL CLKOUT
1h (R/W) = Reserved
2h (R/W) = INTOSC1 output clock
3h (R/W) = INTOSC2 output clock
4h (R/W) = Reserved
5h (R/W) = Reserved
6h (R/W) = CPU1 system clock.
7h (R/W) = Reserved
8h (R/W) = Reserved
9h (R/W) = Input 15 of INPUTXBAR1
Ah (R/W) = Auxiliary clock input
Bh (R/W) = Clock input to EPWM module
Ch (R/W) = Bit clock for SPI and SCI modules
Dh (R/W) = ADC conversion clock
Eh (R/W) = Watchdog clock after dividers
Fh (R/W) = Reserved
10h (R/W) = Reserved
11h (R/W) = Reserved
12h (R/W) = Reserved
13h (R/W) = Reserved
14h (R/W) = Reserved
15h (R/W) = Reserved
16h (R/W) = Reserved
17h (R/W) = FCLK (divided clock) output from Flash wrapper
18h (R/W) = Input 11 of INPUTXBAR1
19h (R/W) = Input 12 of INPUTXBAR1
1Ah (R/W) = MCANA bit clock
1Bh (R/W) = MCANB bit clock
1Ch (R/W) = USB bit clock
1Dh (R/W) = Input 11 of INPUTXBAR2
1Eh (R/W) = Input 12 of INPUTXBAR2

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9.5.2.10 DCCCLKSRC0 Register (Offset = 28h) [Reset = 00000000h]

DCCCLKSRC0 is shown in Figure 9-17 and described in Table 9-14.
Return to the Summary Table.
Selects the clock source for Counter 0.
Figure 9-17. DCCCLKSRC0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED CLKSRC0
R-0/W-0h R-0h R/W-0h

Table 9-14. DCCCLKSRC0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 KEY R-0/W 0h Enables or Disables Clock Source Write for COUNT0
1010: The CLKSRC0 field written with key gets updated to with new
selection to clock COUNT0.
Others: Previous values retained new writes on register fields has no
impact.
Reset type: SYSRSn
11-5 RESERVED R 0h Reserved
4-0 CLKSRC0 R/W 0h Clock Source Select for Counter 0
Specifies the clock source for COUNT0, when the KEY field enables
this feature.
Note: All values not defined below are reserved.
Reset type: SYSRSn
0h (R/W) = Crystal oscillator output
1h (R/W) = INTOSC1 output
2h (R/W) = INTOSC2 output
4h (R/W) = TCK pin input
5h (R/W) = CPU1 system clock
8h (R/W) = Auxiliary clock input
Ch (R/W) = Input 16 of INPUTXBAR1
Eh (R/W) = Reserved
Fh (R/W) = Reserved

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Chapter 10
General-Purpose Input/Output (GPIO)

The GPIO module controls the device's digital and analog I/O multiplexing, which uses shared pins to maximize
application flexibility. The pins are named by the general-purpose I/O name (for example, GPIO0, GPIO25,
GPIO58). These pins can be individually selected to operate as digital I/O (also called GPIO mode), or
connected to one of several peripheral I/O signals. The input signals can be qualified to remove unwanted
noise.

10.1 Introduction...........................................................................................................................................................1077
10.2 Configuration Overview....................................................................................................................................... 1079
10.3 Digital Inputs on ADC Pins (AIOs)...................................................................................................................... 1080
10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)...........................................................................................1080
10.5 Digital General-Purpose I/O Control................................................................................................................... 1082
10.6 Input Qualification................................................................................................................................................ 1083
10.7 USB Signals.......................................................................................................................................................... 1088
10.8 PMBUS and I2C Signals.......................................................................................................................................1088
10.9 GPIO and Peripheral Muxing............................................................................................................................... 1089
10.10 Internal Pullup Configuration Requirements................................................................................................... 1096
10.11 Software...............................................................................................................................................................1096
10.12 GPIO Registers....................................................................................................................................................1102

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10.1 Introduction
Up to twelve independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to the
CPU-controlled I/O capability. Each pin output can be controlled by either a peripheral or one of the CPU
controllers.
• CPU1
• CPU1.CLA
There are up to 8 possible I/O ports:
• Port A consists of GPIO0-GPIO31
• Port B consists of GPIO32-GPIO63
• Port C consists of GPIO64-GPIO95
• Port D consists of GPIO96-GPIO127
• Port E consists of GPIO128-GPIO159
• Port F consists of GPIO160-GPIO191
• Port G consists of GPIO192-GPIO223
• Port H consists of GPIO224-GPIO255

Note
Some GPIO and I/O ports can be unavailable on particular devices. See the GPIO Registers section
for available GPIO and I/O ports.

The analog signals on this device are multiplexed with digital inputs and outputs. Some of these analog IO (AIO)
pins do not have digital output capability. Others of these pins are analog pins capable of full digital input and
output capability (AGPIO). Analog pins with AIO (digital input only) capability contain "AIO" signals in the Pin
Attributes table of the device data sheet. Analog pins with full input and output capability (AGPIO pins) contain
"GPIO" signals in the Pin Attributes table of the device data sheet. AGPIO pins also have pin names with both
analog signals and GPIO in the name.
Figure 10-1 shows the GPIO logic for a single pin.
There are two key features to note in Figure 10-1. The first is that the input and output paths are entirely
separate, connecting only at the pin. The second is that peripheral muxing takes place far from the pin. As
a result, for both CPUs and CLAs to read the physical state of the pin independent of CPU controlling and
peripheral muxing is possible. Likewise, external interrupts can be generated from peripheral activity. All pin
options such as input qualification and open-drain output are valid for all controllers and peripherals. However,
the peripheral muxing, CPU muxing, and pin options can only be configured by CPU1. Table 10-1 provides
details of GPIO registers accessible by different controllers.

Note
In open-drain mode, the GPIO does not drive the pin high, the GPIO can only pull the pin low.
Instead, use an external pull-up to the bus voltage to drive the high level. When open-drain mode is
enabled, the value in the GPyDAT register still controls the pin state. Writing a value of 1 turns off
the driver to allow the external pull-up to control the pin; writing a value of 0 pulls the pin to ground.
The open-drain configuration is automatically used by peripherals such as I2C and PMBus (no need
to enable open-drain mode locally). This mode can also be set manually by writing to the GPyODR
register and can be used when there are multiple nodes on the same net to avoid the pin contention
that a push-pull driver can cause.

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CPU1 Input Input

GPyDAT_R (R) XBAR2 XBAR1
00:00 Unused
00:01 Peripheral A
CPU1 00:10 Peripheral B
Low Power CPU1 00:11 Peripheral C
GPyPUD Pull-Up Mode Control
GPyCTRL GPyQSEL1-2
CPU1 01:00 Unused
CPU1 / CLA GPyINV 01:01 Peripheral D
SYSCLK 01:10 Peripheral E
GPyDAT (R) Sync 00 01:11 Peripheral F
3-sample 01
0 6-sample 10 10:xx Peripherals G-I
Async 11
GPIOx 1 11:xx Peripherals J-L

CPU1
Disabled when high, by
GPyDIR = input GPyGMUX1-2
or GPyMUX1-2
IO Reset = low
GPyDIR
GPyCSEL1-3
GPySET
GPyCLEAR 00 CPU1
Direc
on 01 CLA
CPU1 GPyTOGGLE
GPyODR GPyDAT (W)

0 Data 00:00 Data

00:01 Peripheral A
1 0 00:10 Peripheral B
00:11 Peripheral C

01:00 GPIO (same as 00:00)

01:01 Peripheral D
01:10 Peripheral E
01:11 Peripheral F
IO Reset 0 GPyDIR
10:xx GPIO and Peripherals G-I
1 GPyDAT
11:xx GPIO and Peripherals J-L
GPyODR

Figure 10-1. GPIO Logic for a Single Pin

Table 10-1. GPIO access by different controllers

Register Type Function CPU CLA DMA Comments

GPIO_CTRL Peripheral muxing, Pull Control ,etc. Yes NO NO

Based on
GPIO_DATA GPIODAT, SET, CLEAR, TOGGLE, and pin status, etc. Yes Yes NO GPxCSEL
configuration.

GPIO_DATA_READ Read back of GPIODAT register Yes Yes NO

10.1.1 GPIO Related Collateral

Foundational Materials
• C2000 Academy - GPIO

Getting Started Materials

• How to Maximize GPIO Usage in C2000 Devices Application Report
• [FAQ] C2000 GPIO FAQ

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10.2 Configuration Overview

I/O pin configuration consists of several steps:
1. Plan the device pin-out: Make a list of all required peripherals for the application. Using the peripheral mux
information in the device data sheet, choose which GPIOs to use for the peripheral signals. Decide which of
the remaining GPIOs to use as inputs and outputs for each CPU and CLA.
Once the peripheral muxing has been chosen, implement the mux by writing the appropriate values to
the GPyMUX1/2 and GPyGMUX1/2 registers. When changing the GPyGMUX value for a pin, always set
the corresponding GPyMUX bits to zero first to avoid glitching in the muxes. By default, all pins are general-
purpose I/Os, not peripheral signals, with the exception of GPIO35 and GPIO37.
2. (Optional) Enable internal pullup resistors: To enable or disable the pullup resistors, write to the
appropriate bits in the GPIO pullup disable registers (GPyPUD). All pullups are disabled by default. Pullups
can be used to keep input pins in a known state when there is no external signal driving them.
3. Select input qualification: If the pin is used as an input, specify the required input qualification, if any.
The input qualification sampling period is selected in the GPyCTRL registers, while the type of qualification
is selected in the GPyQSEL1 and GPyQSEL2 registers. By default, all qualification is synchronous with a
sampling period equal to PLLSYSCLK, with the exception of GPIO35 and GPIO37. For an explanation of
input qualification, see Section 10.6.
4. Select the direction of any general-purpose I/O pins: For each pin configured as a GPIO, specify the
direction of the pin as either input or output using the GPyDIR registers. By default, all GPIO pins are inputs.
Before changing a pin to an output, load the output latch with the value to be driven by writing that value to
the GPySET, GPyCLEAR, or GPyDAT registers. Once the latch is loaded, write to GPyDIR to change the pin
direction. By default, all output latches are zero.
The GPyDAT_R register can be used to read what value was written to the GPyDAT register.
5. Select low-power mode wake-up sources: GPIOs 0-63 can be used to wake the system up from low
power modes. To select one or more GPIOs for wake-up, write to the appropriate bits in the GPIOLPMSEL0
and GPIOLPMSEL1 registers. These registers are part of the CPU system register space. For more
information on low-power modes and GPIO wake-up, see the Low-Power Modes section in the System
Control and Interrupts chapter.
6. Select external interrupt sources: Configuring external interrupts is a two-step process. First, the
interrupts themselves must be enabled and the polarity must be configured using the XINTnCR registers.
Second, the XINT1-5 GPIO pins must be set by selecting the sources for Input X-BAR signals 4, 5, 6,
13, and 14, respectively. For more information on the Input X-BAR architecture, see the Crossbar (X-BAR)
chapter.

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10.3 Digital Inputs on ADC Pins (AIOs)

Some GPIOs are multiplexed with analog pins and only have digital input functionality. These are also referred to
as AIOs. Pins with only an AIO option on this port can only function in input mode. See the device data sheet for
list of AIO signals. By default, these pins function as analog pins and the GPIOs are in a high-impedance state.
The GPyAMSEL register is used to configure these pins for digital or analog operation.

Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with
adjacent analog signals. Therefore, limit the edge rate of signals connected to AIOs if adjacent
channels are being used for analog functions.

10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)

Some GPIOs are multiplexed with analog pins and have digital input and output functionality. These are also
referred to as AGPIOs. Unlike AIOs, AGPIOs have full input and output capability. By default, the AGPIOs are
not connected and must be configured. Table 10-2 shows how to configure the AGPIOs. To enable the analog
functionality, set the register AGPIOCTRLx from analog subsystem. To enable the digital functionality, set the
register GPxAMSEL from the General-Purpose Input/Output (GPIO) chapter.
Table 10-2. AGPIO Configuration
AGPIOCTRLx.GPIOy GPxAMSEL.GPIOy Pin Connected To:
(Default = 0) (Default = 1) ADC GPIOy
0 0 - Yes
(1) (1)
0 1 - -
1 0 - Yes
1 1 Yes -

(1) By default there are no signals connected to AGPIO pins. One of the other rows in the table must be chosen for pin functionality.

Note
If digital signals with sharp edges (high dv/dt) are connected to the AGPIOs, cross-talk can occur with
adjacent analog signals. The user must therefore limit the edge rate of signals connected to AGPIOs,
if adjacent channels are being used for analog functions.

The general schematic of analog subsystem with AGPIO implementation is illustrated in Figure 10-2. The
combinations of use cases for a specific analog input pin need special consideration are shown in Table 10-3.
The AGPIO analog pin path contains an extra series switch of 53Ω. This creates a low capacitance isolated
node shared by the ADC and CMPSS Comparator as shown in Figure 10-2. This node can be disturbed
when the ADC samples the channel (depending on the prior voltage stored on the ADC sample and hold
capacitor), and this disturbance can cause a false CMPSS event of up to 50ns. As shown in Table 10-3, special
considerations or workarounds need to be used for the combination of CMPSS Input, ADC Sampling, and
AGPIO. To accommodate this potential disturbance the following workarounds can be implemented:
1. Use a different pin (that is AIO pin type) for analog channels which need both ADC and CMPSS together.
2. Use the CMPSS Digital Filter with a setting of 50ns or greater, which filters the temporary disturbance.
3. Precondition the sample and hold capacitor of the ADC so the disturbance does not cause a false trip. For
example, perform a dummy read of a 3.3V connection from a different channel on the ADC immediately
before the impacted channel is read so the disturbance is in the positive direction, away from the false trip.
The opposite dummy read of a 0V signal can be used if the false trip is inverted in polarity.

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Table 10-3. The Combinations of Use Cases for a Specific Analog Input Pin
Function Used on a Specific Analog Pin Component Used

CMPSS Comparator Input Yes - Yes - Yes

ADC Sampling Yes Yes - Yes Yes

AGPIO Analog Pin Type Yes Yes Yes - -

AIO Analog Pin Type - - - Yes Yes

Result Workaround needed No special analysis or workaround needed

C2000 Device Analog

Interconnect CMPSS
+
GPIO

CMPSS MUX
–

AGPIO pin GPIO Logic –

ADC MUX
Switch RON ADC
AGPIO switch
AIO pin
Cp Ch

GPIO
VREFLO
GPIO Logic

Figure 10-2. Analog Subsystem Block Diagram with AGPIO Implementation

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10.5 Digital General-Purpose I/O Control

The values on the pins that are configured as GPIO can be changed by using the following registers.
• GPyDAT Registers
Each I/O port has one data register. Each bit in the data register corresponds to one GPIO pin. No matter
how the pin is configured (GPIO or peripheral function), the corresponding bit in the data register reflects the
current state of the pin after qualification. Writing to the GPyDAT register clears or sets the corresponding
output latch and if the pin is enabled as a general-purpose output (GPIO output), the pin is also driven either
low or high. If the pin is not configured as a GPIO output, then the value is latched but the pin is not driven.
Only if the pin is later configured as a GPIO output is the latched value driven onto the pin.
When using the GPyDAT register to change the level of an output pin, be cautious to not accidentally change
the level of another pin. For example, to change the output latch level of GPIOA0 by writing to the GPADAT
register bit 0 using a read-modify-write instruction, a problem can occur if another I/O port A signal changes
level between the read and the write stage of the instruction. Following is an analysis of why this happens:
The GPyDAT registers reflect the state of the pin, not the latch. This means the register reflects the actual
pin value. However, there is a lag between when the register is written to when the new pin value is reflected
back in the register. This can pose a problem when this register is used in subsequent program statements to
alter the state of GPIO pins. An example is shown below where two program statements attempt to drive two
different GPIO pins that are currently low to a high state.
If Read-Modify-Write operations are used on the GPyDAT registers, because of the delay between the output
and the input of the first instruction (I1), the second instruction (I2) reads the old value and writes the value
back.

GpioDataRegs.GPADAT.bit.GPIO1 = 1; //I1 performs read-modify-write of GPADAT

GpioDataRegs.GPADAT.bit.GPIO2 = 1; //I2 also a read-modify-write of GPADAT
//GPADAT gets the old value of GPIO1 due to the delay

The second instruction waits for the first to finish the write due to the write-followed-by-read protection on this
peripheral frame. There is some lag, however, between the write of (I1) and the GPyDAT bit reflecting the
new value (1) on the pin. During this lag, the second instruction reads the old value of GPIO1 (0) and writes
the value back along with the new value of GPIO2 (1). Therefore, GPIO1 pin stays low.
One answer is to put some NOPs between instructions. A better answer is to use the GPySET/GPyCLEAR/
GPyTOGGLE registers instead of the GPyDAT registers. These registers always read back a 0 and writes of
0 have no effect. Only bits that need to be changed can be specified without disturbing any other bits that are
currently in the process of changing.
• GPyDAT_R Registers
The GPyDAT_R registers are read only registers that return the value written to the GPyDAT registers instead
of pin status. Writes to these registers have no effect.
• GPySET Registers
The set registers are used to drive specified GPIO pins high without disturbing other pins. Each I/O port has
one set register and each bit corresponds to one GPIO pin. The set registers always read back 0. If the
corresponding pin is configured as an output, then writing a 1 to that bit in the set register sets the output
latch high and the corresponding pin is driven high. If the pin is not configured as a GPIO output, then the
value is latched but the pin is not driven. Only if the pin is later configured as a GPIO output is the latched
value driven onto the pin. Writing a 0 to any bit in the set registers has no effect.

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• GPyCLEAR Registers
The clear registers are used to drive specified GPIO pins low without disturbing other pins. Each I/O port
has one clear register. The clear registers always read back 0. If the corresponding pin is configured as a
general-purpose output, then writing a 1 to the corresponding bit in the clear register clears the output latch
and the pin is driven low. If the pin is not configured as a GPIO output, then the value is latched but the pin is
not driven. Only if the pin is later configured as a GPIO output is the latched value driven onto the pin. Writing
a 0 to any bit in the clear registers has no effect.
• GPyTOGGLE Registers
The toggle registers are used to drive specified GPIO pins to the opposite level without disturbing other pins.
Each I/O port has one toggle register. The toggle registers always read back 0. If the corresponding pin is
configured as an output, then writing a 1 to that bit in the toggle register flips the output latch and pulls the
corresponding pin in the opposite direction. That is, if the output pin is driven low, then writing a 1 to the
corresponding bit in the toggle register pulls the pin high. Likewise, if the output pin is high, then writing a 1
to the corresponding bit in the toggle register pulls the pin low. If the pin is not configured as a GPIO output,
then the value is latched but the pin is not driven. Only if the pin is later configured as a GPIO output is the
latched value driven onto the pin. Writing a 0 to any bit in the toggle registers has no effect.

10.6 Input Qualification

The input qualification scheme has been designed to be very flexible. Select the type of input qualification for
each GPIO pin by configuring the GPyQSEL1 and GPyQSEL2 registers. In the case of a GPIO input pin, the
qualification can be specified as only synchronized to SYSCLKOUT or qualification by a sampling window. For
pins that are configured as peripheral inputs, the input can also be asynchronous in addition to synchronized to
SYSCLKOUT or qualified by a sampling window. The remainder of this section describes the options available.
10.6.1 No Synchronization (Asynchronous Input)
This mode is used for peripherals where input synchronization is not required or the peripheral performs the
synchronization. Examples include communication ports McBSP, SCI, SPI, and I2C. In addition, the ePWM trip
zone (TZn) signals can function independent of the presence of SYSCLKOUT.

Note
Using input synchronization when the peripheral performs the synchronization can cause unexpected
results. The user must make sure that the GPIO pin is configured for asynchronous in this case.

10.6.2 Synchronization to SYSCLKOUT Only

This is the default qualification mode of all the pins at reset. In this mode, the input signal is only synchronized to
the system clock (SYSCLKOUT). Because the incoming signal is asynchronous, a SYSCLKOUT period of delay
is needed for the input to the device to be changed. No further qualification is performed on the signal.

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10.6.3 Qualification Using a Sampling Window

In this mode, the signal is first synchronized to the system clock (SYSCLKOUT) and then qualified by a specified
number of cycles before the input is allowed to change. Figure 10-3 and Figure 10-4 show how the input
qualification is performed to eliminate unwanted noise. Two parameters are specified by the user for this type
of qualification: 1) the sampling period, or how often the signal is sampled, and 2) the number of samples to be
taken.
Time between samples

GPxCTRL Reg

GPIOx SYNC Qualification Input Signal

Qualified By 3
or 6 Samples

GPxQSEL1/2
SYSCLKOUT
Number of Samples

Figure 10-3. Input Qualification Using a Sampling Window

Time between samples (sampling period):

To qualify the signal, the input signal is sampled at a regular period. The sampling period is specified by the user
and determines the time duration between samples, or how often the signal is sampled, relative to the CPU clock
(SYSCLKOUT).
The sampling period is specified by the qualification period (QUALPRDn) bits in the GPxCTRL register.
The sampling period is configurable in groups of 8 input signals. For example, GPIO0 to GPIO7 use
GPACTRL[QUALPRD0] setting and GPIO8 to GPIO15 use GPACTRL[QUALPRD1]. Table 10-4 and Table 10-5
show the relationship between the sampling period or sampling frequency and the GPxCTRL[QUALPRDn]
setting.
Table 10-4. Sampling Period
Sampling Period
If GPxCTRL[QUALPRDn] = 0 1 × TSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

Table 10-5. Sampling Frequency

Sampling Frequency
If GPxCTRL[QUALPRDn] = 0 fSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn])
Where fSYSCLKOUT is the frequency of SYSCLKOUT

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From these equations, the minimum and maximum time between samples can be calculated for a given
SYSCLKOUT frequency:

Example: Maximum Sampling Frequency:

If GPxCTRL[QUALPRDn] = 0
then the sampling frequency is fSYSCLKOUT
If, for example, fSYSCLKOUT = 60MHz
then the signal is sampled at 60MHz or one sample every 16.67ns.

Example: Minimum Sampling Frequency:

If GPxCTRL[QUALPRDn] = 0xFF (255)
then the sampling frequency is fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn])
If, for example, fSYSCLKOUT = 60MHz
then the signal is sampled at 60MHz × 1 ÷ (2 × 255) (117.647kHz) or one sample every 8.5μs.

Number of samples:
The number of times the signal is sampled is either three samples or six samples as specified in the qualification
selection (GPyQSEL1, GPyQSEL2) registers. When three or six consecutive cycles are the same, then the input
change is passed through to the device.
Total Sampling-Window Width:
The sampling window is the time during which the input signal is sampled as shown in Figure 10-4. By using the
equation for the sampling period, along with the number of samples to be taken, the total width of the window
can be determined.
For the input qualifier to detect a change in the input, the level of the signal must be stable for the duration of the
sampling-window width or longer.
The number of sampling periods within the window is always one less than the number of samples taken. For
a three-sample window, the sampling-window width is two sampling-periods wide where the sampling period is
defined in Table 10-4. Likewise, for a six-sample window, the sampling-window width is five sampling-periods
wide. Table 10-6 and Table 10-7 show the calculations used to determine the total sampling-window width based
on GPxCTRL[QUALPRDn] and the number of samples taken.
Table 10-6. Case 1: Three-Sample Sampling-Window Width
Total Sampling-Window Width
If GPxCTRL[QUALPRDn] = 0 2 × TSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 2 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

Table 10-7. Case 2: Six-Sample Sampling-Window Width

Total Sampling-Window Width
If GPxCTRL[QUALPRDn] = 0 5 × TSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

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Note
The external signal change is asynchronous with respect to both the sampling period and
SYSCLKOUT. Due to the asynchronous nature of the external signal, the input must be held stable for
a time greater than the sampling-window width to make sure the logic detects a change in the signal.
The extra time required can be up to an additional sampling period + TSYSCLKOUT .
The required duration for an input signal to be stable for the qualification logic to detect a change is
described in the data sheet.

Example Qualification Window:

For the example shown in Figure 10-4, the input qualification has been configured as follows:
• GPxQSEL1/2 = 1,0. This indicates a six-sample qualification.
• GPxCTRL[QUALPRDn] = 1. The sampling period is tw(SP) = 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT = 2 x
TSYSCLKOUT.
This configuration results in the following:
• The width of the sampling window is:
tw(IQSW) = 5 × tw(SP) = 5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT = 5 × 2 × TSYSCLKOUT
• If, for example, TSYSCLKOUT = 16.67ns, then the duration of the sampling window is:
Sampling period, tw(SP) = 2 x TSYSCLKOUT = 2 x 16.67ns = 33.3ns
Sampling window, tw(IQSW) = 5 × tw(SP) = 5 × 33.3ns = 166.7ns
• To account for the asynchronous nature of the input relative to the sampling period and SYSCLKOUT, up to
a single additional sampling period and SYSCLK period is required to detect a change in the input signal. For
this example:
tw(IQSW) + tw(SP) + TSYSCLKOUT = 166.7ns + 33.3ns + 16.67ns = 216.7ns
• In Figure 10-4, the glitch (A) is shorter then the qualification window and is ignored by the input qualifier.

(A)
GPIO Signal QUAL_SEL = 1,0 (6 samples)
0

0
1
1

0
0
0

0
0
1
0
0
0
1
1
1
1
1
1
1
1
tW(SP) Sampling Period determined by 1
GPxCTRL [QUALPRD] (B)
tW(IQSW)
(SYSCLKOUT Cycle * 2 * QUALPRD) * 5(C)
Sampling Window

SYSCLKOUT
QUADPRD=1
(SYSCLKOUT/2) (D)
Output From
Qualifier

Figure 10-4. Input Qualifier Clock Cycles

• A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling
period. It can vary from 0x00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT
cycle. For any other value 'n', the qualificiation sampling period is 2n SYSCLKOUT cycles (i.e. at every 2n
SYSCLKOUT cycles, the GPIO pin will be sampled).
• B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.

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• C. the qualification block can take either 3 or 6 samples. The QUAL_SEL Register selects which samples
mode is used.
• D. In the example shown, for the qualifier to detect the change, the input should be stable for 10
SYSCLKOUT cycles. That would ensure 5 sampling periods for detection to occur. Since external signals
are driven asynchronously, a 13-SYSCLKOUT-wide pulse ensures reliable recognition.

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10.7 USB Signals

The USB module on this device has an internal physical layer transceiver (PHY). The I/O signals are not normal
digital signals, and as a result, the signals do not connect to the pins through the normal GPIO mux path.
Instead, a special analog mux is used. To connect the USB signals to the device pins, set the GPyAMSEL bits
appropriately. See the data sheet for which GPIOs are associated with the USB signals USBDM and USBDP.
See Section 10.12 for correct GPyAMSEL register bits to set. Do not enable pullups or any other special pin
option when using the USB signals.
10.8 PMBUS and I2C Signals
To support a wider range of PMBUS and I2C IO levels, certain GPIOs on this device have configurable VIH
minimum thresholds and configurable current sinking capabilities.
• PMBUS_IO_MODESEL register configures the VIH threshold of the GPIO
• PMBUS_IO_DRVSEL register configures the current sinking capability of the GPIO

Note
The PMBUS_IO_MODESEL and PMBUS_IO_DRVSEL registers apply to the entire GPIO, not just the
PMBUS module. Any peripheral or module in the given GPIO's mux is able to utilize the customizable
VIH threshold and current sinking capability.

The list of GPIOs that have these capabilities, and the configurable levels for these GPIOs are available in the
PMBUS_IO_MODESEL and PMBUS_IO_DRVSEL registers.

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10.9 GPIO and Peripheral Muxing

10.9.1 GPIO Muxing
Up to twelve different peripheral functions are multiplexed to each pin along with a general-purpose input/output (GPIO) function. This allows you to
choose the peripheral mix and pinout that works best for your particular application. Refer to Table 10-8 for muxing combinations and definitions.
Table 10-8. GPIO Muxed Pins
0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
OUTPUTXBA CLB_OUTPUTXB
GPIO0 EPWM1_A SCIA_RX I2CA_SDA SPIA_PTE FSIRXA_CLK MCANA_RX EQEP1_INDEX EPWM3_A
R7 AR8
EQEP1_STRO CLB_OUTPUTXB
GPIO1 EPWM1_B SCIA_TX I2CA_SCL SPIA_POCI MCANA_TX EPWM10_B EPWM3_B
BE AR7
GPIO2 EPWM2_A OUTPUTXBAR1 PMBUSA_SDA SPIA_PICO SCIA_TX FSIRXA_D1 I2CB_SDA EPWM10_A MCANB_TX EPWM4_A
GPIO3 EPWM2_B OUTPUTXBAR2 OUTPUTXBAR2 PMBUSA_SCL SPIA_CLK SCIA_RX FSIRXA_D0 I2CB_SCL MCANB_RX EPWM4_B
EQEP2_STRO CLB_OUTPUTXB
GPIO4 EPWM3_A I2CA_SCL MCANA_TX OUTPUTXBAR3 SPIB_CLK FSIRXA_CLK EPWM11_B SPIA_POCI EPWM1_A
BE AR6
OUTPUTXBA CLB_OUTPUTXB
GPIO5 EPWM3_B I2CA_SDA MCANA_RX SPIA_PTE FSITXA_D1 SCIA_RX EPWM1_B
R3 AR5
CLB_OUTPUTXB
GPIO6 EPWM4_A OUTPUTXBAR4 SYNCOUT EQEP1_A SPIB_POCI FSITXA_D0 FSITXA_D1 EPWM2_A
AR8
OUTPUTXBA CLB_OUTPUTXB
GPIO7 EPWM4_B EPWM2_A EQEP1_B SPIB_PICO FSITXA_CLK SCIA_TX MCANA_TX EPWM2_B
R5 AR2
CLB_OUTPUTXB
GPIO8 EPWM5_A ADCSOCAO EQEP1_STROBE SCIA_TX SPIA_PICO I2CA_SCL FSITXA_D1 EPWM11_A
AR5
OUTPUTXBA
GPIO9 EPWM5_B SCIB_TX EQEP1_INDEX SCIA_RX SPIA_CLK I2CA_SCL FSITXA_D0 LINA_RX PMBUSA_SCL I2CB_SCL EQEP3_B
R6
CLB_OUTPUTXB
GPIO10 EPWM6_A ADCSOCBO EQEP1_A SCIB_TX SPIA_POCI I2CA_SDA FSITXA_CLK LINA_TX EQEP3_STROBE
AR4
OUTPUTXBA
GPIO11 EPWM6_B MCANA_RX EQEP1_B SCIB_RX SPIA_PTE FSIRXA_D1 LINA_RX EQEP2_A SPIA_PICO EQEP3_INDEX
R7
GPIO12 EPWM7_A MCANA_RX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0 LINA_TX SPIA_CLK
GPIO13 EPWM7_B MCANA_TX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK LINA_RX SPIA_POCI
OUTPUTXBAR CLB_OUTPUTXB
GPIO14 EPWM8_A SCIB_TX I2CB_SDA PMBUSA_SDA SPIB_CLK EQEP2_A LINA_TX EPWM3_A
3 AR7
OUTPUTXBAR CLB_OUTPUTXB
GPIO15 EPWM8_B SCIB_RX I2CB_SCL PMBUSA_SCL SPIB_PTE EQEP2_B LINA_RX EPWM3_B
4 AR6
OUTPUTXBA EQEP1_STRO
GPIO16 SPIA_PICO EPWM9_A SCIA_TX PMBUSA_SCL XCLKOUT EQEP2_B SPIB_POCI EQEP3_STROBE
R7 BE
OUTPUTXBA EQEP1_INDE
GPIO17 SPIA_POCI EPWM9_B SCIA_RX PMBUSA_SDA MCANA_TX EPWM6_A
R8 X
GPIO18 SPIA_CLK SCIB_TX MCANB_RX EPWM6_A I2CA_SCL EQEP2_A PMBUSA_CTL XCLKOUT LINA_TX EQEP3_INDEX X2
CLB_OUTPUTXB
GPIO19 SPIA_PTE SCIB_RX MCANB_TX EPWM6_B I2CA_SDA EQEP2_B PMBUSA_ALERT LINA_RX X1
AR1
ADCE_EXTMUXS
GPIO20 EQEP1_A EPWM12_A SPIB_PICO MCANA_TX I2CA_SCL SCIC_TX
EL0

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Table 10-8. GPIO Muxed Pins (continued)

0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
ADCE_EXTMUXS
GPIO21 EQEP1_B EPWM12_B SPIB_POCI MCANA_RX I2CA_SDA SCIC_RX
EL1
EQEP1_STRO CLB_OUTPUTXB
GPIO22 SCIB_TX SPIB_CLK LINA_TX LINA_TX EPWM4_A EQEP3_A
BE AR1
EQEP1_INDE CLB_OUTPUTXB
GPIO23 SCIB_RX SPIB_PTE LINA_RX LINA_RX EPWM12_A EPWM4_B USB0DM
X AR3
OUTPUTXBAR
GPIO24 EQEP2_A SPIA_PTE EPWM8_A SPIB_PICO LINA_TX PMBUSA_SCL SCIA_TX ERRORSTS EPWM9_A
1
OUTPUTXBAR
GPIO25 EQEP2_B EQEP1_A SPIB_POCI FSITXA_D1 PMBUSA_SDA SCIA_RX EQEP3_A
2
OUTPUTXBAR
GPIO26 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK FSITXA_D0 PMBUSA_CTL I2CA_SDA EQEP3_B
3
OUTPUTXBAR
GPIO27 EQEP2_STROBE OUTPUTXBAR4 SPIB_PTE FSITXA_CLK PMBUSA_ALERT I2CA_SCL EQEP3_STROBE
4
EQEP2_STRO
GPIO28 SCIA_RX EPWM7_A OUTPUTXBAR5 EQEP1_A LINA_TX SPIB_CLK ERRORSTS I2CB_SDA
BE
EQEP2_INDE AUXCLKI
GPIO29 SCIA_TX EPWM7_B OUTPUTXBAR6 EQEP1_B LINA_RX SPIB_PTE ERRORSTS I2CB_SCL
X N
EQEP1_STRO
GPIO30 SPIB_PICO OUTPUTXBAR7 FSIRXA_CLK MCANA_RX EPWM1_A EQEP3_INDEX
BE
EQEP1_INDE
GPIO31 SPIB_POCI OUTPUTXBAR8 FSIRXA_D1 MCANA_TX EPWM1_B
X
GPIO32 I2CA_SDA EQEP1_INDEX SPIB_CLK EPWM8_B LINA_TX FSIRXA_D0 MCANB_TX PMBUSA_SDA ADCSOCBO
GPIO33 I2CA_SCL SPIB_PTE OUTPUTXBAR4 LINA_RX FSIRXA_CLK MCANB_RX EQEP2_B ADCSOCAO SCIC_RX
OUTPUTXBAR
GPIO34 PMBUSA_SDA I2CB_SDA
1
GPIO35 SCIA_RX SPIA_POCI I2CA_SDA MCANB_RX PMBUSA_SCL LINA_RX EQEP1_A PMBUSA_CTL EPWM5_B TDI
OUTPUTXBAR
GPIO37 SPIA_PTE I2CA_SCL SCIA_TX MCANB_TX LINA_TX EQEP1_B PMBUSA_ALERT EPWM5_A TDO
2
CLB_OUTPUTXB
GPIO40 SPIB_PICO EPWM2_B PMBUSA_SDA FSIRXA_D0 SCIB_TX EQEP1_A LINA_TX EQEP3_STROBE
AR4
GPIO41 EPWM7_A EPWM2_A PMBUSA_SCL FSIRXA_D1 SCIB_RX EQEP1_B LINA_RX EPWM12_B SPIB_POCI USB0DP
OUTPUTXBA CLB_OUTPUTXB
GPIO42 LINA_RX PMBUSA_CTL I2CA_SDA SCIC_RX EQEP1_STROBE
R5 AR3
OUTPUTXBA PMBUSA_ALE CLB_OUTPUTXB
GPIO43 PMBUSA_ALERT I2CA_SCL SCIC_TX EQEP1_INDEX
R6 RT AR4
OUTPUTXBA CLB_OUTPUTXB
GPIO44 EQEP1_A PMBUSA_SDA FSITXA_CLK PMBUSA_CTL FSIRXA_D0 LINA_TX
R7 AR3
OUTPUTXBA PMBUSA_ALE CLB_OUTPUTXB
GPIO45 FSITXA_D0
R8 RT AR4
GPIO46 LINA_TX MCANA_TX FSITXA_D1 PMBUSA_SDA
CLB_OUTPUTXB
GPIO47 LINA_RX MCANA_RX PMBUSA_SCL
AR2
OUTPUTXBAR
GPIO48 MCANA_TX SCIA_TX PMBUSA_SDA
3

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Table 10-8. GPIO Muxed Pins (continued)

0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
OUTPUTXBAR
GPIO49 MCANA_RX SCIA_RX LINA_RX FSITXA_D0
4
GPIO50 EQEP1_A MCANA_TX SPIB_PICO I2CB_SDA FSITXA_D1
GPIO51 EQEP1_B MCANA_RX SPIB_POCI I2CB_SCL FSITXA_CLK
EQEP1_STRO CLB_OUTPUTXB
GPIO52 SPIB_CLK SYNCOUT FSIRXA_D0
BE AR5
EQEP1_INDE CLB_OUTPUTXB
GPIO53 SPIB_PTE ADCSOCAO MCANB_RX FSIRXA_D1
X AR6
OUTPUTXBAR
GPIO54 SPIA_PICO EQEP2_A ADCSOCBO LINA_TX FSIRXA_CLK
2
OUTPUTXBAR
GPIO55 SPIA_POCI EQEP2_B ERRORSTS LINA_RX
3
CLB_OUTPUTXB
GPIO56 SPIA_CLK MCANA_TX EQEP2_STROBE SCIB_TX SPIB_PICO I2CA_SDA EQEP1_A FSIRXA_D1
AR7
CLB_OUTPUTXB
GPIO57 SPIA_PTE MCANA_RX EQEP2_INDEX SCIB_RX SPIB_POCI I2CA_SCL EQEP1_B FSIRXA_CLK
AR8
GPIO58 OUTPUTXBAR1 SPIB_CLK LINA_TX MCANB_TX EQEP1_STROBE FSIRXA_D0
GPIO59 OUTPUTXBAR2 SPIB_PTE LINA_RX MCANB_RX EQEP1_INDEX
GPIO60 EPWM12_B MCANA_TX OUTPUTXBAR3 SPIB_PICO
GPIO61 MCANA_RX OUTPUTXBAR4 SPIB_POCI MCANB_RX
GPIO62 EPWM10_A OUTPUTXBAR3 MCANA_TX SCIA_TX PMBUSA_SDA
GPIO63 EPWM10_B OUTPUTXBAR4 MCANA_RX SCIA_RX LINA_RX
EQEP2_STRO
GPIO64 SCIA_RX EPWM11_A EPWM7_A OUTPUTXBAR5 EQEP1_A LINA_TX SPIB_CLK ERRORSTS I2CB_SDA
BE
GPIO65 EQEP1_A EPWM11_B SPIB_PICO MCANA_TX I2CA_SCL
GPIO66 EQEP1_B EPWM12_A SPIB_POCI MCANA_RX I2CA_SDA
GPIO67 EPWM7_B EPWM12_B MCANA_TX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK LINA_RX SPIA_POCI SCIC_RX
GPIO68 EPWM7_A EPWM3_A MCANA_RX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0 LINA_TX SPIA_CLK SCIC_TX
OUTPUTXBA
GPIO69 EPWM6_B EPWM3_B EQEP1_B SCIB_RX SPIA_PTE FSIRXA_D1 LINA_RX EQEP2_A SPIA_PICO EQEP3_INDEX
R7
GPIO70 I2CA_SCL SPIB_PTE OUTPUTXBAR4 LINA_RX FSIRXA_CLK MCANA_RX EQEP2_B ADCSOCAO EQEP3_A
OUTPUTXBA EQEP1_STRO
GPIO71 SPIA_PICO EPWM4_B EPWM9_A SCIA_TX PMBUSA_SCL XCLKOUT EQEP2_INDEX SPIB_POCI EQEP3_STROBE
R7 BE
OUTPUTXBA EQEP1_INDE
GPIO72 SPIA_POCI EPWM5_A EPWM9_B SCIA_RX PMBUSA_SDA MCANA_TX EPWM6_A EQEP3_B
R8 X
OUTPUTXBAR
GPIO73 EPWM5_B SPIA_PTE EPWM8_A SPIB_PICO LINA_TX PMBUSA_SCL SCIA_TX ERRORSTS EPWM9_A
1
GPIO74 EPWM2_B ADCSOCAO MCANA_TX SPIA_POCI EQEP1_B
GPIO75 EPWM1_B LINA_RX EPWM6_A SPIA_CLK EQEP1_STROBE SCIC_RX
GPIO76 EPWM4_A OUTPUTXBAR2 SPIA_PTE MCANA_RX EQEP1_INDEX
GPIO77 EPWM1_A OUTPUTXBAR3 SPIA_PICO MCANA_TX EQEP1_A SCIC_TX
GPIO78 EPWM8_A EPWM3_A OUTPUTXBAR1 EPWM2_B FSITXA_CLK
GPIO79 EPWM8_B EPWM3_B MCANA_RX EPWM2_A I2CA_SDA PMBUSA_SCL

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Table 10-8. GPIO Muxed Pins (continued)

0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
OUTPUTXBA CLB_OUTPUTXB
GPIO80 EPWM1_A SCIA_RX I2CB_SDA SPIA_PTE FSITXA_D0 MCANA_RX EQEP1_INDEX EPWM3_A
R7 AR8
GPIO81 EPWM1_B OUTPUTXBAR6 SCIC_RX SPIB_CLK I2CB_SCL FSITXA_D1 MCANA_TX EQEP3_INDEX
GPIO211 EPWM10_A EQEP3_A
GPIO21
EPWM10_B EQEP3_B
2
GPIO21
EPWM11_A EQEP3_STROBE
3
GPIO21
EPWM11_B EQEP3_INDEX
4
GPIO21
EPWM7_B EQEP2_A
5
GPIO22 ADCE_EXTMUXS
EPWM11_B OUTPUTXBAR3 SPIA_PICO EPWM1_A MCANA_TX EQEP1_A SCIC_TX
4 EL3
GPIO22 ADCE_EXTMUXS
EPWM10_B LINA_RX EPWM6_A SPIA_CLK EPWM1_B EQEP1_STROBE SCIC_RX
6 EL1
GPIO22
I2CB_SCL EPWM3_A OUTPUTXBAR1 EPWM2_B
7
GPIO22 ADCE_EXTMUXS
EPWM10_A ADCSOCAO MCANA_TX SPIA_POCI EPWM2_B EQEP1_B
8 EL0
GPIO23
I2CB_SDA EPWM3_B MCANA_RX EPWM2_A I2CA_SDA PMBUSA_SCL
0
GPIO23
EPWM7_A EQEP1_INDEX EPWM12_A
6
GPIO24 ADCE_EXTMUXS
EPWM11_A OUTPUTXBAR2 SPIA_PTE EPWM4_A MCANA_RX EQEP1_INDEX
2 EL2
GPIO24
EPWM12_B
7
GPIO25
EPWM12_A
3
AIO208
AIO209
AIO210
AIO225
AIO229
AIO231
AIO232
AIO233
AIO234
AIO235
AIO237
AIO238
AIO239
AIO240

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Table 10-8. GPIO Muxed Pins (continued)

0, 4, 8,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
12
AIO241
AIO244
AIO245
AIO248
AIO249
AIO251
AIO252

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10.9.2 Peripheral Muxing

For example, multiplexing for the GPIO6 pin is controlled by writing to GPAGMUX[13:12] and GPAMUX[13:12].
By writing to these bits, GPIO6 is configured as either a general-purpose digital I/O or one of several different
peripheral functions. An example of GPyGMUX and GPyMUX selection and options for a single GPIO are shown
in Table 10-9.

Note
The following table is for example only. Refer to the device data sheet to check the availability of
GPIO6 on this device. If GPIO6 is available, the functions mentioned in the table may not match the
actual functions available. See Section 10.9.1 for correct list of GPIOs and corresponding mux options
for this device.

Table 10-9. GPIO and Peripheral Muxing

GPAGMUX1[13:12] GPAMUX1[13:12] Pin Functionality
00 00 GPIO6
00 01 Peripheral 1
00 10 Peripheral 2
00 11 Peripheral 3
01 00 GPIO6
01 01 Peripheral 4
01 10 Peripheral 5
01 11
10 00 GPIO6
10 01
10 10 Peripheral 6
10 11 Peripheral 7
11 00 GPIO6
11 01 Peripheral 8
11 10 Peripheral 9
11 11 Peripheral 10

The devices have different multiplexing schemes. If a peripheral is not available on a particular device, that mux
selection is reserved on that device and must not be used.

CAUTION
If a reserved GPIO mux configuration that is not mapped to either a peripheral or GPIO mode is
selected, the state of the pin is undefined and the pin is driven. Unimplemented configurations are
for future expansion and must not be selected. In the device mux table (see the data sheet), these
options are indicated as Reserved or left blank.

Some peripherals can be assigned to more than one pin by way of the mux registers. For example,
OUTPUTXBAR1 can be assigned to GPIOs p, q, or r (where p, q, and r are example GPIO numbers), depending
on individual system requirements. An example of this is shown in Table 10-10.

Note
The following table is for example only. Bit ranges cannot correspond to OUTPUTXBAR1 on this
device. See Section 10.9.1 for correct list of GPIOs and corresponding mux options for this device.

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If none or more then one of the GPIO pins is configured as peripheral input pins, then that GPIO is set to a
hard-wired default value.
Table 10-10. Peripheral Muxing (Multiple Pins Assigned)
GMUX Configuration MUX Configuration
Choice 1: GPIOp GPyGMUX1[5:4] = 01 GPyMUX1[5:4] = 01
or Choice 2: GPIOq GPyGMUX2[17:16] = 00 GPyMUX2[17:16] = 01
or Choice 3: GPIOr GPyGMUX1[7:6] = 01 GPyMUX1[7:6] = 01

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10.10 Internal Pullup Configuration Requirements

On reset, GPIOs are in input mode and have the internal pullups disabled. An un-driven input can float to a
mid-rail voltage and cause wasted shoot-through current on the input buffer. The user must always put each
GPIO in one of these configurations:
• Input mode and driven on the board by another component to a level above Vih or below Vil
• Input mode with GPIO internal pullup enabled
• Output mode
On devices with lesser pin count packages, pull-ups on unbonded GPIOs are by default enabled to prevent
floating inputs. The user must take care to avoid disabling these pullups in the application code.
On devices with larger pin count packages, the pullups for any internally unbonded GPIO must be enabled
to prevent floating inputs. TI has provided functions in controlSUITE/C2000Ware that users can call to enable
the pullup on any unbonded GPIO for the package in use. This function, GPIO_EnabledUnbondedIOPullups(),
resides in the (Device)_Sysctrl.c file and is called by default from InitSysCtrl(). The user must take care to avoid
disabling these pullups in the application code.
10.11 Software
10.11.1 GPIO Registers to Driverlib Functions
Table 10-11. GPIO Registers to Driverlib Functions
File Driverlib Function
GPACTRL
gpio.c GPIO_setQualificationPeriod
GPAQSEL1
gpio.c GPIO_setQualificationMode
gpio.c GPIO_getQualificationMode
GPAQSEL2
- See GPAQSEL1
GPAMUX1
gpio.c GPIO_setPinConfig
GPAMUX2
- See GPAMUX1
GPADIR
gpio.c GPIO_setDirectionMode
gpio.c GPIO_getDirectionMode
GPAPUD
gpio.c GPIO_setPadConfig
gpio.c GPIO_getPadConfig
GPAINV
gpio.c GPIO_setPadConfig
gpio.c GPIO_getPadConfig
GPAODR
gpio.c GPIO_setPadConfig
gpio.c GPIO_getPadConfig
GPAAMSEL
-
GPAGMUX1
gpio.c GPIO_setPinConfig
GPAGMUX2

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Table 10-11. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
- See GPAGMUX1
GPACSEL1
gpio.c GPIO_setControllerCore
GPACSEL2
- See GPACSEL1
GPACSEL3
- See GPACSEL1
GPACSEL4
- See GPACSEL1
GPALOCK
gpio.h GPIO_lockPortConfig
gpio.h GPIO_unlockPortConfig
GPACR
gpio.h GPIO_commitPortConfig
GPBCTRL
- See GPACTRL
GPBQSEL1
- See GPAQSEL1
GPBQSEL2
- See GPAQSEL1
GPBMUX1
- See GPAMUX1
GPBMUX2
- See GPAMUX1
GPBDIR
- See GPADIR
GPBPUD
- See GPAPUD
GPBINV
- See GPAINV
GPBODR
- See GPAODR
GPBAMSEL
gpio.c GPIO_setAnalogMode
GPBGMUX1
- See GPAGMUX1
GPBGMUX2
- See GPAGMUX1
GPBCSEL1
- See GPACSEL1
GPBCSEL2
- See GPACSEL1
GPBCSEL3
- See GPACSEL1
GPBCSEL4

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Table 10-11. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
- See GPACSEL1
GPBLOCK
- See GPALOCK
GPBCR
- See GPACR
GPCCTRL
- See GPACTRL
GPCQSEL1
- See GPAQSEL1
GPCQSEL2
- See GPAQSEL1
GPCMUX1
- See GPAMUX1
GPCMUX2
- See GPAMUX1
GPCDIR
- See GPADIR
GPCPUD
- See GPAPUD
GPCINV
- See GPAINV
GPCODR
- See GPAODR
GPCGMUX1
- See GPAGMUX1
GPCGMUX2
- See GPAGMUX1
GPCCSEL1
- See GPACSEL1
GPCCSEL2
- See GPACSEL1
GPCCSEL3
- See GPACSEL1
GPCLOCK
- See GPALOCK
GPCCR
- See GPACR
GPGCTRL
- See GPACTRL
GPGQSEL2
- See GPAQSEL1
GPGMUX2
- See GPAMUX1
GPGDIR
- See GPADIR

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Table 10-11. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
GPGPUD
- See GPAPUD
GPGINV
- See GPAINV
GPGODR
- See GPAODR
GPGAMSEL
-
GPGGMUX2
- See GPAGMUX1
GPGCSEL3
- See GPACSEL1
GPGLOCK
- See GPALOCK
GPGCR
- See GPACR
GPHCTRL
- See GPACTRL
GPHQSEL1
- See GPAQSEL1
GPHQSEL2
- See GPAQSEL1
GPHMUX1
- See GPAMUX1
GPHMUX2
- See GPAMUX1
GPHDIR
- See GPADIR
GPHPUD
- See GPAPUD
GPHINV
- See GPAINV
GPHODR
- See GPAODR
GPHAMSEL
-
GPHGMUX1
- See GPAGMUX1
GPHGMUX2
- See GPAGMUX1
GPHCSEL1
- See GPACSEL1
GPHCSEL2
- See GPACSEL1
GPHCSEL3

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Table 10-11. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
- See GPACSEL1
GPHCSEL4
- See GPACSEL1
GPHLOCK
- See GPALOCK
GPHCR
- See GPACR
GPADAT
gpio.h GPIO_readPin
gpio.h GPIO_readPortData
gpio.h GPIO_writePortData
GPASET
gpio.h GPIO_writePin
gpio.h GPIO_setPortPins
GPACLEAR
gpio.h GPIO_writePin
gpio.h GPIO_clearPortPins
GPATOGGLE
gpio.h GPIO_togglePin
gpio.h GPIO_togglePortPins
GPBDAT
- See GPADAT
GPBSET
- See GPASET
GPBCLEAR
- See GPACLEAR
GPBTOGGLE
- See GPATOGGLE
GPCDAT
- See GPADAT
GPCSET
- See GPASET
GPCCLEAR
- See GPACLEAR
GPCTOGGLE
- See GPATOGGLE
GPGDAT
- See GPADAT
GPGSET
- See GPASET
GPGCLEAR
- See GPACLEAR
GPGTOGGLE
- See GPATOGGLE
GPHDAT

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Table 10-11. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
- See GPADAT
GPHSET
- See GPASET
GPHCLEAR
- See GPACLEAR
GPHTOGGLE
- See GPATOGGLE
GPADAT_R
-
GPBDAT_R
-
GPCDAT_R
-
GPGDAT_R
-
GPHDAT_R
-

10.11.2 GPIO Examples

NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/gpio
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
10.11.2.1 Device GPIO Setup
FILE: gpio_ex1_setup.c
Configures the device GPIO into two different configurations This code is verbose to illustrate how the GPIO
could be setup. In a real application, lines of code can be combined for improved code size and efficiency.
This example only sets-up the GPIO. Nothing is actually done with the pins after setup.
In general:
• All pullup resistors are enabled. For ePWMs this may not be desired.
• Input qual for communication ports (CAN, SPI, SCI, I2C) is asynchronous
• Input qual for Trip pins (TZ) is asynchronous
• Input qual for eCAP and eQEP signals is synch to SYSCLKOUT
• Input qual for some I/O's and __interrupts may have a sampling window
10.11.2.2 Device GPIO Toggle
FILE: gpio_ex2_toggle.c
Configures the device GPIO through the sysconfig file. The GPIO pin is toggled in the infinite loop. In order to
migrate the project within syscfg to any device, click the swtich button under the device view and select your
corresponding device to migrate, saving the project will auto-migrate your project settings.
: This example project has support for migration across our C2000 device families. If you are wanting to build
this project from launchpad or controlCARD, please specify in the .syscfg file the board you're using. At any time
you can select another device to migrate this example.
10.11.2.3 Device GPIO Interrupt
FILE: gpio_ex3_interrupt.c

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Configures the device GPIOs through the sysconfig file. One GPIO output pin, and one GPIO input pin is
configured. The example then configures the GPIO input pin to be the source of an external interrupt which
toggles the GPIO output pin.
10.11.2.4 External Interrupt (XINT)
FILE: gpio_ex4_aio_external_interrupt.c
In this example AIO pins are configured as digital inputs. Two other GPIO signals (connected externally to AIO
pins) are toggled in software to trigger external interrupt through AIO225 and AIO231 (AIO225 assigned to
XINT1 and AIO231 assigned to XINT2). The user is required to externally connect these signals for the program
to work properly. Each interrupt is fired in sequence: XINT1 first and then XINT2.

• GPIO5 will go high outside of the interrupts and low within the interrupts. This signal can be monitored on a
scope. External Connections
• Connect GPIO0 to AIO225. AIO225 will be assigned to XINT1
• Connect GPIO1 to AIO231. AIO231 will be assigned to XINT2
• GPIO5 can be monitored on an oscilloscope
Watch Variables
• xint1Count for the number of times through XINT1 interrupt
• xint2Count for the number of times through XINT2 interrupt
• loopCount for the number of times through the idle loop
10.11.3 LED Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/led
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
10.12 GPIO Registers
This Section describes the GPIO Registers.
10.12.1 GPIO Base Address Table
Table 10-12. GPIO Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1
Instance Structure Protected

GPIO_CTRL_RE
GpioCtrlRegs GPIOCTRL_BASE 0x0000_7C00 YES - - YES
GS
GPIO_DATA_REG
GpioDataRegs GPIODATA_BASE 0x0000_7F00 YES - YES YES
S
GpioDataReadR GPIO_DATA_REA GPIODATAREAD_BAS
0x0000_7F80 YES - YES YES
egs D_REGS E

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10.12.2 GPIO_CTRL_REGS Registers

Table 10-13 lists the memory-mapped registers for the GPIO_CTRL_REGS registers. All register offset
addresses not listed in Table 10-13 should be considered as reserved locations and the register contents should
not be modified.
Table 10-13. GPIO_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h GPACTRL GPIO A Qualification Sampling Period Control EALLOW Go
(GPIO0 to 31)
2h GPAQSEL1 GPIO A Qualifier Select 1 Register (GPIO0 to 15) EALLOW Go
4h GPAQSEL2 GPIO A Qualifier Select 2 Register (GPIO16 to EALLOW Go
31)
6h GPAMUX1 GPIO A Mux 1 Register (GPIO0 to 15) EALLOW Go
8h GPAMUX2 GPIO A Mux 2 Register (GPIO16 to 31) EALLOW Go
Ah GPADIR GPIO A Direction Register (GPIO0 to 31) EALLOW Go
Ch GPAPUD GPIO A Pull Up Disable Register (GPIO0 to 31) EALLOW Go
10h GPAINV GPIO A Input Polarity Invert Registers (GPIO0 to EALLOW Go
31)
12h GPAODR GPIO A Open Drain Output Register (GPIO0 to EALLOW Go
GPIO31)
14h GPAAMSEL GPIO A Analog Mode Select register (GPIO0 to EALLOW Go
GPIO31)
20h GPAGMUX1 GPIO A Peripheral Group Mux (GPIO0 to 15) EALLOW Go
22h GPAGMUX2 GPIO A Peripheral Group Mux (GPIO16 to 31) EALLOW Go
28h GPACSEL1 GPIO A Core Select Register (GPIO0 to 7) EALLOW Go
2Ah GPACSEL2 GPIO A Core Select Register (GPIO8 to 15) EALLOW Go
2Ch GPACSEL3 GPIO A Core Select Register (GPIO16 to 23) EALLOW Go
2Eh GPACSEL4 GPIO A Core Select Register (GPIO24 to 31) EALLOW Go
3Ch GPALOCK GPIO A Lock Configuration Register (GPIO0 to EALLOW Go
31)
3Eh GPACR GPIO A Lock Commit Register (GPIO0 to 31) EALLOW Go
40h GPBCTRL GPIO B Qualification Sampling Period Control EALLOW Go
(GPIO32 to 63)
42h GPBQSEL1 GPIO B Qualifier Select 1 Register (GPIO32 to EALLOW Go
47)
44h GPBQSEL2 GPIO B Qualifier Select 2 Register (GPIO48 to EALLOW Go
63)
46h GPBMUX1 GPIO B Mux 1 Register (GPIO32 to 47) EALLOW Go
48h GPBMUX2 GPIO B Mux 2 Register (GPIO48 to 63) EALLOW Go
4Ah GPBDIR GPIO B Direction Register (GPIO32 to 63) EALLOW Go
4Ch GPBPUD GPIO B Pull Up Disable Register (GPIO32 to 63) EALLOW Go
50h GPBINV GPIO B Input Polarity Invert Registers (GPIO32 EALLOW Go
to 63)
52h GPBODR GPIO B Open Drain Output Register (GPIO32 to EALLOW Go
GPIO63)
54h GPBAMSEL GPIO B Analog Mode Select register (GPIO32 to EALLOW Go
GPIO63)
60h GPBGMUX1 GPIO B Peripheral Group Mux (GPIO32 to 47) EALLOW Go
62h GPBGMUX2 GPIO B Peripheral Group Mux (GPIO48 to 63) EALLOW Go
68h GPBCSEL1 GPIO B Core Select Register (GPIO32 to 39) EALLOW Go
6Ah GPBCSEL2 GPIO B Core Select Register (GPIO40 to 47) EALLOW Go

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Table 10-13. GPIO_CTRL_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
6Ch GPBCSEL3 GPIO B Core Select Register (GPIO48 to 55) EALLOW Go
6Eh GPBCSEL4 GPIO B Core Select Register (GPIO56 to 63) EALLOW Go
7Ch GPBLOCK GPIO B Lock Configuration Register (GPIO32 to EALLOW Go
63)
7Eh GPBCR GPIO B Lock Commit Register (GPIO32 to 63) EALLOW Go
80h GPCCTRL GPIO C Qualification Sampling Period Control EALLOW Go
(GPIO64 to 95)
82h GPCQSEL1 GPIO C Qualifier Select 1 Register (GPIO64 to EALLOW Go
79)
84h GPCQSEL2 GPIO C Qualifier Select 2 Register (GPIO80 to EALLOW Go
95)
86h GPCMUX1 GPIO C Mux 1 Register (GPIO64 to 79) EALLOW Go
88h GPCMUX2 GPIO C Mux 2 Register (GPIO80 to 95) EALLOW Go
8Ah GPCDIR GPIO C Direction Register (GPIO64 to 95) EALLOW Go
8Ch GPCPUD GPIO C Pull Up Disable Register (GPIO64 to 95) EALLOW Go
90h GPCINV GPIO C Input Polarity Invert Registers (GPIO64 EALLOW Go
to 95)
92h GPCODR GPIO C Open Drain Output Register (GPIO64 to EALLOW Go
GPIO95)
94h GPCAMSEL GPIO C Analog Mode Select register (GPIO64 to EALLOW Go
GPIO95)
A0h GPCGMUX1 GPIO C Peripheral Group Mux (GPIO64 to 79) EALLOW Go
A2h GPCGMUX2 GPIO C Peripheral Group Mux (GPIO80 to 95) EALLOW Go
A8h GPCCSEL1 GPIO C Core Select Register (GPIO64 to 71) EALLOW Go
AAh GPCCSEL2 GPIO C Core Select Register (GPIO72 to 79) EALLOW Go
ACh GPCCSEL3 GPIO C Core Select Register (GPIO80 to 87) EALLOW Go
BCh GPCLOCK GPIO C Lock Configuration Register (GPIO64 to EALLOW Go
95)
BEh GPCCR GPIO C Lock Commit Register (GPIO64 to 95) EALLOW Go
180h GPGCTRL GPIO G Qualification Sampling Period Control EALLOW Go
(GPIO192 to 223)
184h GPGQSEL2 GPIO G Qualifier Select 2 Register (GPIO208 to EALLOW Go
223)
188h GPGMUX2 GPIO G Mux 2 Register (GPIO208 to 223) EALLOW Go
18Ah GPGDIR GPIO G Direction Register (GPIO192 to 223) EALLOW Go
18Ch GPGPUD GPIO G Pull Up Disable Register (GPIO192 to EALLOW Go
223)
190h GPGINV GPIO G Input Polarity Invert Registers (GPIO192 EALLOW Go
to 223)
192h GPGODR GPIO G Open Drain Output Register (GPIO192 to EALLOW Go
223)
194h GPGAMSEL GPIO G Analog Mode Select register (GPIO192 EALLOW Go
to 223)
1A2h GPGGMUX2 GPIO G Peripheral Group Mux (GPIO208 to 223) EALLOW Go
1ACh GPGCSEL3 GPIO G Core Select Register (GPIO208 to 215) EALLOW Go
1BCh GPGLOCK GPIO G Lock Configuration Register (GPIO192 to EALLOW Go
223)
1BEh GPGCR GPIO G Lock Commit Register (GPIO192 to 223) EALLOW Go
1C0h GPHCTRL GPIO H Qualification Sampling Period Control EALLOW Go
(GPIO224 to 255)

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Table 10-13. GPIO_CTRL_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
1C2h GPHQSEL1 GPIO H Qualifier Select 1 Register (GPIO224 to EALLOW Go
239)
1C4h GPHQSEL2 GPIO H Qualifier Select 2 Register (GPIO240 to EALLOW Go
255)
1C6h GPHMUX1 GPIO H Mux 1 Register (GPIO224 to 239) EALLOW Go
1C8h GPHMUX2 GPIO H Mux 2 Register (GPIO240 to 255) EALLOW Go
1CAh GPHDIR GPIO H Direction Register (GPIO224 to 255) EALLOW Go
1CCh GPHPUD GPIO H Pull Up Disable Register (GPIO224 to EALLOW Go
255)
1D0h GPHINV GPIO H Input Polarity Invert Registers (GPIO224 EALLOW Go
to 255)
1D2h GPHODR GPIO H Open Drain Output Register (GPIO224 to EALLOW Go
GPIO255)
1D4h GPHAMSEL GPIO H Analog Mode Select register (GPIO224 EALLOW Go
to GPIO255)
1E0h GPHGMUX1 GPIO H Peripheral Group Mux (GPIO224 to 239) EALLOW Go
1E2h GPHGMUX2 GPIO H Peripheral Group Mux (GPIO240 to 255) EALLOW Go
1E8h GPHCSEL1 GPIO H Core Select Register (GPIO224 to 231) EALLOW Go
1EAh GPHCSEL2 GPIO H Core Select Register (GPIO232 to 239) EALLOW Go
1ECh GPHCSEL3 GPIO H Core Select Register (GPIO240 to 247) EALLOW Go
1EEh GPHCSEL4 GPIO H Core Select Register (GPIO248 to 255) EALLOW Go
1FCh GPHLOCK GPIO H Lock Configuration Register (GPIO224 to EALLOW Go
255)
1FEh GPHCR GPIO H Lock Commit Register (GPIO224 to 255) EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 10-14 shows the codes that are used for
access types in this section.
Table 10-14. GPIO_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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10.12.2.1 GPACTRL Register (Offset = 0h) [Reset = 00000000h]

GPACTRL is shown in Figure 10-5 and described in Table 10-15.
Return to the Summary Table.
GPIO A Qualification Sampling Period Control (GPIO0 to 31)
Figure 10-5. GPACTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-15. GPACTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h Qualification sampling period for GPIO24 to GPIO31:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO16 to GPIO23:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO8 to GPIO15:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO0 to GPIO7:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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10.12.2.2 GPAQSEL1 Register (Offset = 2h) [Reset = 00000000h]

GPAQSEL1 is shown in Figure 10-6 and described in Table 10-16.
Return to the Summary Table.
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-6. GPAQSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-16. GPAQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO15 R/W 0h Select input qualification type for GPIO15:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO14 R/W 0h Select input qualification type for GPIO14:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO13 R/W 0h Select input qualification type for GPIO13:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO12 R/W 0h Select input qualification type for GPIO12:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO11 R/W 0h Select input qualification type for GPIO11:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 GPIO10 R/W 0h Select input qualification type for GPIO10:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-16. GPAQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GPIO9 R/W 0h Select input qualification type for GPIO9:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
17-16 GPIO8 R/W 0h Select input qualification type for GPIO8:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO7 R/W 0h Select input qualification type for GPIO7:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO6 R/W 0h Select input qualification type for GPIO6:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
11-10 GPIO5 R/W 0h Select input qualification type for GPIO5:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO4 R/W 0h Select input qualification type for GPIO4:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO3 R/W 0h Select input qualification type for GPIO3:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO2 R/W 0h Select input qualification type for GPIO2:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO1 R/W 0h Select input qualification type for GPIO1:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-16. GPAQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO0 R/W 0h Select input qualification type for GPIO0:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.12.2.3 GPAQSEL2 Register (Offset = 4h) [Reset = 00000000h]

GPAQSEL2 is shown in Figure 10-7 and described in Table 10-17.
Return to the Summary Table.
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-7. GPAQSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-17. GPAQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO31 R/W 0h Select input qualification type for GPIO31:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO30 R/W 0h Select input qualification type for GPIO30:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO29 R/W 0h Select input qualification type for GPIO29:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO28 R/W 0h Select input qualification type for GPIO28:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO27 R/W 0h Select input qualification type for GPIO27:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 GPIO26 R/W 0h Select input qualification type for GPIO26:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-17. GPAQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GPIO25 R/W 0h Select input qualification type for GPIO25:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
17-16 GPIO24 R/W 0h Select input qualification type for GPIO24:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO23 R/W 0h Select input qualification type for GPIO23:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO22 R/W 0h Select input qualification type for GPIO22:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
11-10 GPIO21 R/W 0h Select input qualification type for GPIO21:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO20 R/W 0h Select input qualification type for GPIO20:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO19 R/W 0h Select input qualification type for GPIO19:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO18 R/W 0h Select input qualification type for GPIO18:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO17 R/W 0h Select input qualification type for GPIO17:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-17. GPAQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO16 R/W 0h Select input qualification type for GPIO16:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.12.2.4 GPAMUX1 Register (Offset = 6h) [Reset = 00000000h]

GPAMUX1 is shown in Figure 10-8 and described in Table 10-18.
Return to the Summary Table.
GPIO A Mux 1 Register (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-8. GPAMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-18. GPAMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO15 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO14 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO13 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO12 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO11 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO10 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO9 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO8 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO7 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO6 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO5 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO4 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO3 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO2 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO1 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-18. GPAMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO0 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.5 GPAMUX2 Register (Offset = 8h) [Reset = 00000000h]

GPAMUX2 is shown in Figure 10-9 and described in Table 10-19.
Return to the Summary Table.
GPIO A Mux 2 Register (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-9. GPAMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-19. GPAMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO31 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO30 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO29 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO28 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO27 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO26 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO25 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO24 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO23 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO22 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO21 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO20 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO19 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO18 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO17 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-19. GPAMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO16 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.6 GPADIR Register (Offset = Ah) [Reset = 00000000h]

GPADIR is shown in Figure 10-10 and described in Table 10-20.
Return to the Summary Table.
GPIO A Direction Register (GPIO0 to 31)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 10-10. GPADIR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-20. GPADIR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
30 GPIO30 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
29 GPIO29 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO28 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO27 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 GPIO26 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
25 GPIO25 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO24 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO23 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO22 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO21 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 10-20. GPADIR Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO19 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
18 GPIO18 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
17 GPIO17 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO16 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO15 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO14 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO13 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO12 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO11 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO10 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO9 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO8 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO7 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO6 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO5 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO4 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO3 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO2 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO1 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO0 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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10.12.2.7 GPAPUD Register (Offset = Ch) [Reset = FFFFFFFFh]

GPAPUD is shown in Figure 10-11 and described in Table 10-21.
Return to the Summary Table.
GPIO A Pull Up Disable Register (GPIO0 to 31)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
Figure 10-11. GPAPUD Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-21. GPAPUD Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
30 GPIO30 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
29 GPIO29 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
28 GPIO28 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
27 GPIO27 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
26 GPIO26 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
25 GPIO25 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
24 GPIO24 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
23 GPIO23 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO22 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO21 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 10-21. GPAPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
19 GPIO19 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
18 GPIO18 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
17 GPIO17 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO16 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO15 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
14 GPIO14 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO13 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO12 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO11 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO10 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO9 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO8 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO7 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 GPIO6 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
5 GPIO5 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 GPIO4 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
3 GPIO3 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO2 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO1 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO0 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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10.12.2.8 GPAINV Register (Offset = 10h) [Reset = 00000000h]

GPAINV is shown in Figure 10-12 and described in Table 10-22.
Return to the Summary Table.
GPIO A Input Polarity Invert Registers (GPIO0 to 31)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 10-12. GPAINV Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-22. GPAINV Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 10-22. GPAINV Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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10.12.2.9 GPAODR Register (Offset = 12h) [Reset = 00000000h]

GPAODR is shown in Figure 10-13 and described in Table 10-23.
Return to the Summary Table.
GPIO A Open Drain Output Register (GPIO0 to GPIO31)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 10-13. GPAODR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-23. GPAODR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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Table 10-23. GPAODR Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO21 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO20 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

1124 TMS320F28P55x Real-Time Microcontrollers SPRUJ53B – APRIL 2024 – REVISED SEPTEMBER 2024
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10.12.2.10 GPAAMSEL Register (Offset = 14h) [Reset = FF7FFFFFh]

GPAAMSEL is shown in Figure 10-14 and described in Table 10-24.
Return to the Summary Table.
GPIO A Analog Mode Select register (GPIO0 to GPIO31)
Selects between digital and analog functionality for GPIO pins.
0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other
GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For
all the IOs, the corresponding bits in these registers dont have any affect.
Figure 10-14. GPAAMSEL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED GPIO28 RESERVED RESERVED RESERVED GPIO24
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO23 RESERVED GPIO21 GPIO20 RESERVED RESERVED GPIO17 GPIO16
R/W-0h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
RESERVED RESERVED GPIO13 GPIO12 GPIO11 RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-24. GPAAMSEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 RESERVED R/W 1h Reserved
28 GPIO28 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
27 RESERVED R/W 1h Reserved
26 RESERVED R/W 1h Reserved
25 RESERVED R/W 1h Reserved
24 GPIO24 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Analog Mode select for this pin
Reset type: SYSRSn
22 RESERVED R/W 1h Reserved
21 GPIO21 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
20 GPIO20 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
19 RESERVED R/W 1h Reserved
18 RESERVED R/W 1h Reserved

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Table 10-24. GPAAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO17 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
16 GPIO16 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
15 RESERVED R/W 1h Reserved
14 RESERVED R/W 1h Reserved
13 GPIO13 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
12 GPIO12 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
11 GPIO11 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
10 RESERVED R/W 1h Reserved
9 RESERVED R/W 1h Reserved
8 RESERVED R/W 1h Reserved
7 RESERVED R/W 1h Reserved
6 RESERVED R/W 1h Reserved
5 RESERVED R/W 1h Reserved
4 RESERVED R/W 1h Reserved
3 RESERVED R/W 1h Reserved
2 RESERVED R/W 1h Reserved
1 RESERVED R/W 1h Reserved
0 RESERVED R/W 1h Reserved

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10.12.2.11 GPAGMUX1 Register (Offset = 20h) [Reset = 00000000h]

GPAGMUX1 is shown in Figure 10-15 and described in Table 10-25.
Return to the Summary Table.
GPIO A Peripheral Group Mux (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-15. GPAGMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-25. GPAGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO15 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO14 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO13 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO12 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO11 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO10 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO9 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO8 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO7 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO6 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO5 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO4 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO3 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO2 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO1 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-25. GPAGMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO0 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.12 GPAGMUX2 Register (Offset = 22h) [Reset = 00000000h]

GPAGMUX2 is shown in Figure 10-16 and described in Table 10-26.
Return to the Summary Table.
GPIO A Peripheral Group Mux (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-16. GPAGMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-26. GPAGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO31 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO30 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO29 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO28 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO27 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO26 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO25 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO24 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO23 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO22 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO21 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO20 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO19 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO18 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO17 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-26. GPAGMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO16 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.13 GPACSEL1 Register (Offset = 28h) [Reset = 00000000h]

GPACSEL1 is shown in Figure 10-17 and described in Table 10-27.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-17. GPACSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO7 GPIO6 GPIO5 GPIO4
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-27. GPACSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO7 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO6 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO5 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO4 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO3 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO2 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO1 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO0 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.14 GPACSEL2 Register (Offset = 2Ah) [Reset = 00000000h]

GPACSEL2 is shown in Figure 10-18 and described in Table 10-28.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-18. GPACSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-28. GPACSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO15 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO14 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO13 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO12 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO11 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO10 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO9 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO8 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.15 GPACSEL3 Register (Offset = 2Ch) [Reset = 00000000h]

GPACSEL3 is shown in Figure 10-19 and described in Table 10-29.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-19. GPACSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-29. GPACSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO23 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO22 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO21 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO20 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO19 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO18 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO17 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO16 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.16 GPACSEL4 Register (Offset = 2Eh) [Reset = 00000000h]

GPACSEL4 is shown in Figure 10-20 and described in Table 10-30.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-20. GPACSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-30. GPACSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO31 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO30 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO29 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO28 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO27 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO26 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO25 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO24 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.17 GPALOCK Register (Offset = 3Ch) [Reset = 00000000h]

GPALOCK is shown in Figure 10-21 and described in Table 10-31.
Return to the Summary Table.
GPIO A Lock Configuration Register (GPIO0 to 31)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 10-21. GPALOCK Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-31. GPALOCK Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 10-31. GPALOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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10.12.2.18 GPACR Register (Offset = 3Eh) [Reset = 00000000h]

GPACR is shown in Figure 10-22 and described in Table 10-32.
Return to the Summary Table.
GPIO A Lock Commit Register (GPIO0 to 31)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 10-22. GPACR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 10-32. GPACR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
30 GPIO30 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
29 GPIO29 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
28 GPIO28 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
27 GPIO27 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
26 GPIO26 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
25 GPIO25 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
24 GPIO24 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
23 GPIO23 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO22 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO21 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO20 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 10-32. GPACR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
18 GPIO18 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
17 GPIO17 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO16 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO15 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO14 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
13 GPIO13 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO12 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO11 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO10 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO9 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO8 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO7 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 GPIO6 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
5 GPIO5 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 GPIO4 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
3 GPIO3 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO2 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO1 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO0 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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10.12.2.19 GPBCTRL Register (Offset = 40h) [Reset = 00000000h]

GPBCTRL is shown in Figure 10-23 and described in Table 10-33.
Return to the Summary Table.
GPIO B Qualification Sampling Period Control (GPIO32 to 63)
Figure 10-23. GPBCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-33. GPBCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h Qualification sampling period for GPIO56 to GPIO63:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO48 to GPIO55:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO40 to GPIO47:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO32 to GPIO39:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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10.12.2.20 GPBQSEL1 Register (Offset = 42h) [Reset = 00000CC0h]

GPBQSEL1 is shown in Figure 10-24 and described in Table 10-34.
Return to the Summary Table.
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-24. GPBQSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-3h R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h

Table 10-34. GPBQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO47 R/W 0h Select input qualification type for GPIO47:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO46 R/W 0h Select input qualification type for GPIO46:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO45 R/W 0h Select input qualification type for GPIO45:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO44 R/W 0h Select input qualification type for GPIO44:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO43 R/W 0h Select input qualification type for GPIO43:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 GPIO42 R/W 0h Select input qualification type for GPIO42:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-34. GPBQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GPIO41 R/W 0h Select input qualification type for GPIO41:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
17-16 GPIO40 R/W 0h Select input qualification type for GPIO40:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 GPIO37 R/W 3h Select input qualification type for GPIO37:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 RESERVED R/W 0h Reserved
7-6 GPIO35 R/W 3h Select input qualification type for GPIO35:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO34 R/W 0h Select input qualification type for GPIO34:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO33 R/W 0h Select input qualification type for GPIO33:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO32 R/W 0h Select input qualification type for GPIO32:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.12.2.21 GPBQSEL2 Register (Offset = 44h) [Reset = 00000000h]

GPBQSEL2 is shown in Figure 10-25 and described in Table 10-35.
Return to the Summary Table.
GPIO B Qualifier Select 2 Register (GPIO48 to 63)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-25. GPBQSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-35. GPBQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO63 R/W 0h Select input qualification type for GPIO63:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO62 R/W 0h Select input qualification type for GPIO62:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO61 R/W 0h Select input qualification type for GPIO61:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO60 R/W 0h Select input qualification type for GPIO60:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO59 R/W 0h Select input qualification type for GPIO59:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 GPIO58 R/W 0h Select input qualification type for GPIO58:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-35. GPBQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GPIO57 R/W 0h Select input qualification type for GPIO57:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
17-16 GPIO56 R/W 0h Select input qualification type for GPIO56:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO55 R/W 0h Select input qualification type for GPIO55:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO54 R/W 0h Select input qualification type for GPIO54:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
11-10 GPIO53 R/W 0h Select input qualification type for GPIO53:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO52 R/W 0h Select input qualification type for GPIO52:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO51 R/W 0h Select input qualification type for GPIO51:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO50 R/W 0h Select input qualification type for GPIO50:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO49 R/W 0h Select input qualification type for GPIO49:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-35. GPBQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO48 R/W 0h Select input qualification type for GPIO48:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.12.2.22 GPBMUX1 Register (Offset = 46h) [Reset = 00000CC0h]

GPBMUX1 is shown in Figure 10-26 and described in Table 10-36.
Return to the Summary Table.
GPIO B Mux 1 Register (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-26. GPBMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-3h R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h

Table 10-36. GPBMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO47 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO46 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO45 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO44 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO43 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO42 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO41 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO40 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 GPIO37 R/W 3h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 RESERVED R/W 0h Reserved
7-6 GPIO35 R/W 3h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO34 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO33 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO32 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.23 GPBMUX2 Register (Offset = 48h) [Reset = 00000000h]

GPBMUX2 is shown in Figure 10-27 and described in Table 10-37.
Return to the Summary Table.
GPIO B Mux 2 Register (GPIO48 to 63)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-27. GPBMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-37. GPBMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO63 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO62 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO61 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO60 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO59 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO58 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO57 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO56 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO55 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO54 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO53 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO52 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO51 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO50 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO49 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-37. GPBMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO48 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.24 GPBDIR Register (Offset = 4Ah) [Reset = 00000000h]

GPBDIR is shown in Figure 10-28 and described in Table 10-38.
Return to the Summary Table.
GPIO B Direction Register (GPIO32 to 63)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 10-28. GPBDIR Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-38. GPBDIR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
30 GPIO62 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
29 GPIO61 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO60 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO59 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 GPIO58 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
25 GPIO57 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO56 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO55 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO54 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO53 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 10-38. GPBDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO52 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO51 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
18 GPIO50 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
17 GPIO49 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO48 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO47 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO46 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO45 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO44 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO43 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO42 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO41 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO40 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO34 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO33 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO32 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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10.12.2.25 GPBPUD Register (Offset = 4Ch) [Reset = FFFFFFFFh]

GPBPUD is shown in Figure 10-29 and described in Table 10-39.
Return to the Summary Table.
GPIO B Pull Up Disable Register (GPIO32 to 63)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
Figure 10-29. GPBPUD Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-39. GPBPUD Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
30 GPIO62 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
29 GPIO61 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
28 GPIO60 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
27 GPIO59 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
26 GPIO58 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
25 GPIO57 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
24 GPIO56 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
23 GPIO55 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO54 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO53 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 10-39. GPBPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO52 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
19 GPIO51 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
18 GPIO50 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
17 GPIO49 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO48 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO47 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
14 GPIO46 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO45 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO44 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO43 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO42 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO41 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO40 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 RESERVED R/W 1h Reserved
6 RESERVED R/W 1h Reserved
5 GPIO37 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 RESERVED R/W 1h Reserved
3 GPIO35 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO34 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO33 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO32 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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10.12.2.26 GPBINV Register (Offset = 50h) [Reset = 00000000h]

GPBINV is shown in Figure 10-30 and described in Table 10-40.
Return to the Summary Table.
GPIO B Input Polarity Invert Registers (GPIO32 to 63)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 10-30. GPBINV Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-40. GPBINV Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 10-40. GPBINV Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO52 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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10.12.2.27 GPBODR Register (Offset = 52h) [Reset = 00000000h]

GPBODR is shown in Figure 10-31 and described in Table 10-41.
Return to the Summary Table.
GPIO B Open Drain Output Register (GPIO32 to GPIO63)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 10-31. GPBODR Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-41. GPBODR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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Table 10-41. GPBODR Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO53 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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10.12.2.28 GPBAMSEL Register (Offset = 54h) [Reset = FFFFFDFFh]

GPBAMSEL is shown in Figure 10-32 and described in Table 10-42.
Return to the Summary Table.
GPIO B Analog Mode Select register (GPIO32 to GPIO63)
Selects between digital and analog functionality for GPIO pins.
0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other
GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For
all the IOs, t
Figure 10-32. GPBAMSEL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO41 RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-0h R/W-1h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO33 RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-42. GPBAMSEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 RESERVED R/W 1h Reserved
28 RESERVED R/W 1h Reserved
27 RESERVED R/W 1h Reserved
26 RESERVED R/W 1h Reserved
25 RESERVED R/W 1h Reserved
24 RESERVED R/W 1h Reserved
23 RESERVED R/W 1h Reserved
22 RESERVED R/W 1h Reserved
21 RESERVED R/W 1h Reserved
20 RESERVED R/W 1h Reserved
19 RESERVED R/W 1h Reserved
18 RESERVED R/W 1h Reserved
17 RESERVED R/W 1h Reserved
16 RESERVED R/W 1h Reserved
15 RESERVED R/W 1h Reserved
14 RESERVED R/W 1h Reserved

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Table 10-42. GPBAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
13 RESERVED R/W 1h Reserved
12 RESERVED R/W 1h Reserved
11 RESERVED R/W 1h Reserved
10 RESERVED R/W 1h Reserved
9 GPIO41 R/W 0h Analog Mode select for this pin
Reset type: SYSRSn
8 RESERVED R/W 1h Reserved
7 RESERVED R/W 1h Reserved
6 RESERVED R/W 1h Reserved
5 RESERVED R/W 1h Reserved
4 RESERVED R/W 1h Reserved
3 RESERVED R/W 1h Reserved
2 RESERVED R/W 1h Reserved
1 GPIO33 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
0 RESERVED R/W 1h Reserved

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10.12.2.29 GPBGMUX1 Register (Offset = 60h) [Reset = 00000CC0h]

GPBGMUX1 is shown in Figure 10-33 and described in Table 10-43.
Return to the Summary Table.
GPIO B Peripheral Group Mux (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-33. GPBGMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-3h R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h

Table 10-43. GPBGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO47 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO46 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO45 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO44 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO43 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO42 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO41 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO40 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 GPIO37 R/W 3h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 RESERVED R/W 0h Reserved
7-6 GPIO35 R/W 3h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO34 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO33 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO32 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.30 GPBGMUX2 Register (Offset = 62h) [Reset = 00000000h]

GPBGMUX2 is shown in Figure 10-34 and described in Table 10-44.
Return to the Summary Table.
GPIO B Peripheral Group Mux (GPIO48 to 63)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-34. GPBGMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-44. GPBGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO63 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO62 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO61 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO60 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO59 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO58 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO57 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO56 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO55 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO54 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO53 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO52 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO51 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO50 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO49 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-44. GPBGMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO48 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.31 GPBCSEL1 Register (Offset = 68h) [Reset = 00000000h]

GPBCSEL1 is shown in Figure 10-35 and described in Table 10-45.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-35. GPBCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO37 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-45. GPBCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R/W 0h Reserved
27-24 RESERVED R/W 0h Reserved
23-20 GPIO37 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 RESERVED R/W 0h Reserved
15-12 GPIO35 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO34 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO33 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO32 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.32 GPBCSEL2 Register (Offset = 6Ah) [Reset = 00000000h]

GPBCSEL2 is shown in Figure 10-36 and described in Table 10-46.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-36. GPBCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-46. GPBCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO47 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO46 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO45 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO44 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO43 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO42 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO41 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO40 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.33 GPBCSEL3 Register (Offset = 6Ch) [Reset = 00000000h]

GPBCSEL3 is shown in Figure 10-37 and described in Table 10-47.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-37. GPBCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-47. GPBCSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO55 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO54 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO53 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO52 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO51 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO50 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO49 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO48 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.34 GPBCSEL4 Register (Offset = 6Eh) [Reset = 00000000h]

GPBCSEL4 is shown in Figure 10-38 and described in Table 10-48.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-38. GPBCSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO63 GPIO62 GPIO61 GPIO60
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-48. GPBCSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO63 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO62 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO61 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO60 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO59 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO58 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO57 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO56 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.35 GPBLOCK Register (Offset = 7Ch) [Reset = 00000000h]

GPBLOCK is shown in Figure 10-39 and described in Table 10-49.
Return to the Summary Table.
GPIO B Lock Configuration Register (GPIO32 to 63)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 10-39. GPBLOCK Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-49. GPBLOCK Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 10-49. GPBLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO52 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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10.12.2.36 GPBCR Register (Offset = 7Eh) [Reset = 00000000h]

GPBCR is shown in Figure 10-40 and described in Table 10-50.
Return to the Summary Table.
GPIO B Lock Commit Register (GPIO32 to 63)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 10-40. GPBCR Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 10-50. GPBCR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
30 GPIO62 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
29 GPIO61 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
28 GPIO60 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
27 GPIO59 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
26 GPIO58 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
25 GPIO57 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
24 GPIO56 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
23 GPIO55 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO54 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO53 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO52 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 10-50. GPBCR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
18 GPIO50 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
17 GPIO49 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO48 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO47 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO46 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
13 GPIO45 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO44 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO43 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO42 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO41 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO40 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 RESERVED R/WSonce 0h Reserved
6 RESERVED R/WSonce 0h Reserved
5 GPIO37 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 RESERVED R/WSonce 0h Reserved
3 GPIO35 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO34 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO33 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO32 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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10.12.2.37 GPCCTRL Register (Offset = 80h) [Reset = 00000000h]

GPCCTRL is shown in Figure 10-41 and described in Table 10-51.
Return to the Summary Table.
GPIO C Qualification Sampling Period Control (GPIO64 to 95)
Figure 10-41. GPCCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-51. GPCCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R/W 0h Reserved
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO80 to GPIO87:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO72 to GPIO79:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO64 to GPIO71:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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10.12.2.38 GPCQSEL1 Register (Offset = 82h) [Reset = 00000000h]

GPCQSEL1 is shown in Figure 10-42 and described in Table 10-52.
Return to the Summary Table.
GPIO C Qualifier Select 1 Register (GPIO64 to 79)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-42. GPCQSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-52. GPCQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO79 R/W 0h Select input qualification type for GPIO79:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO78 R/W 0h Select input qualification type for GPIO78:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO77 R/W 0h Select input qualification type for GPIO77:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO76 R/W 0h Select input qualification type for GPIO76:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO75 R/W 0h Select input qualification type for GPIO75:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 GPIO74 R/W 0h Select input qualification type for GPIO74:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-52. GPCQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GPIO73 R/W 0h Select input qualification type for GPIO73:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
17-16 GPIO72 R/W 0h Select input qualification type for GPIO72:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO71 R/W 0h Select input qualification type for GPIO71:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO70 R/W 0h Select input qualification type for GPIO70:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
11-10 GPIO69 R/W 0h Select input qualification type for GPIO69:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO68 R/W 0h Select input qualification type for GPIO68:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO67 R/W 0h Select input qualification type for GPIO67:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO66 R/W 0h Select input qualification type for GPIO66:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO65 R/W 0h Select input qualification type for GPIO65:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-52. GPCQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO64 R/W 0h Select input qualification type for GPIO64:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.12.2.39 GPCQSEL2 Register (Offset = 84h) [Reset = 00000000h]

GPCQSEL2 is shown in Figure 10-43 and described in Table 10-53.
Return to the Summary Table.
GPIO C Qualifier Select 2 Register (GPIO80 to 95)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-43. GPCQSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-53. GPCQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 RESERVED R/W 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 RESERVED R/W 0h Reserved
3-2 GPIO81 R/W 0h Select input qualification type for GPIO81:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO80 R/W 0h Select input qualification type for GPIO80:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.12.2.40 GPCMUX1 Register (Offset = 86h) [Reset = 00000000h]

GPCMUX1 is shown in Figure 10-44 and described in Table 10-54.
Return to the Summary Table.
GPIO C Mux 1 Register (GPIO64 to 79)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-44. GPCMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-54. GPCMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO79 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO78 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO77 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO76 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO75 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO74 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO73 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO72 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO71 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO70 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO69 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO68 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO67 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO66 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO65 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-54. GPCMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO64 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.41 GPCMUX2 Register (Offset = 88h) [Reset = 00000000h]

GPCMUX2 is shown in Figure 10-45 and described in Table 10-55.
Return to the Summary Table.
GPIO C Mux 2 Register (GPIO80 to 95)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-45. GPCMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-55. GPCMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 RESERVED R/W 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 RESERVED R/W 0h Reserved
3-2 GPIO81 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO80 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.42 GPCDIR Register (Offset = 8Ah) [Reset = 00000000h]

GPCDIR is shown in Figure 10-46 and described in Table 10-56.
Return to the Summary Table.
GPIO C Direction Register (GPIO64 to 95)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 10-46. GPCDIR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-56. GPCDIR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 GPIO81 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO80 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO79 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO78 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 10-56. GPCDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
13 GPIO77 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO76 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO75 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO74 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO73 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO72 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO71 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO70 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO69 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO68 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO67 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO66 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO65 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO64 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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10.12.2.43 GPCPUD Register (Offset = 8Ch) [Reset = FFFFFFFFh]

GPCPUD is shown in Figure 10-47 and described in Table 10-57.
Return to the Summary Table.
GPIO C Pull Up Disable Register (GPIO64 to 95)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
Figure 10-47. GPCPUD Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-57. GPCPUD Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 RESERVED R/W 1h Reserved
28 RESERVED R/W 1h Reserved
27 RESERVED R/W 1h Reserved
26 RESERVED R/W 1h Reserved
25 RESERVED R/W 1h Reserved
24 RESERVED R/W 1h Reserved
23 RESERVED R/W 1h Reserved
22 RESERVED R/W 1h Reserved
21 RESERVED R/W 1h Reserved
20 RESERVED R/W 1h Reserved
19 RESERVED R/W 1h Reserved
18 RESERVED R/W 1h Reserved
17 GPIO81 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO80 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO79 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 10-57. GPCPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
14 GPIO78 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO77 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO76 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO75 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO74 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO73 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO72 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO71 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 GPIO70 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
5 GPIO69 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 GPIO68 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
3 GPIO67 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO66 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO65 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO64 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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10.12.2.44 GPCINV Register (Offset = 90h) [Reset = 00000000h]

GPCINV is shown in Figure 10-48 and described in Table 10-58.
Return to the Summary Table.
GPIO C Input Polarity Invert Registers (GPIO64 to 95)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 10-48. GPCINV Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-58. GPCINV Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 GPIO81 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO78 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 10-58. GPCINV Register Field Descriptions (continued)

Bit Field Type Reset Description
13 GPIO77 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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10.12.2.45 GPCODR Register (Offset = 92h) [Reset = 00000000h]

GPCODR is shown in Figure 10-49 and described in Table 10-59.
Return to the Summary Table.
GPIO C Open Drain Output Register (GPIO64 to GPIO95)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 10-49. GPCODR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-59. GPCODR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 GPIO81 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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Table 10-59. GPCODR Register Field Descriptions (continued)

Bit Field Type Reset Description
14 GPIO78 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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10.12.2.46 GPCAMSEL Register (Offset = 94h) [Reset = 00000000h]

GPCAMSEL is shown in Figure 10-50 and described in Table 10-60.
Return to the Summary Table.
GPIO C Analog Mode Select register (GPIO64 to GPIO95)
Selects between digital and analog functionality for GPIO pins.
0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other
GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For
all the IOs, t
Figure 10-50. GPCAMSEL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-60. GPCAMSEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved

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Table 10-60. GPCAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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10.12.2.47 GPCGMUX1 Register (Offset = A0h) [Reset = 00000000h]

GPCGMUX1 is shown in Figure 10-51 and described in Table 10-61.
Return to the Summary Table.
GPIO C Peripheral Group Mux (GPIO64 to 79)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-51. GPCGMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-61. GPCGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO79 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO78 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO77 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO76 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO75 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO74 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO73 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO72 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO71 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO70 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO69 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO68 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO67 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO66 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO65 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-61. GPCGMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO64 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.48 GPCGMUX2 Register (Offset = A2h) [Reset = 00000000h]

GPCGMUX2 is shown in Figure 10-52 and described in Table 10-62.
Return to the Summary Table.
GPIO C Peripheral Group Mux (GPIO80 to 95)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-52. GPCGMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-62. GPCGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 RESERVED R/W 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 RESERVED R/W 0h Reserved
3-2 GPIO81 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO80 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.49 GPCCSEL1 Register (Offset = A8h) [Reset = 00000000h]

GPCCSEL1 is shown in Figure 10-53 and described in Table 10-63.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-53. GPCCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO71 GPIO70 GPIO69 GPIO68
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-63. GPCCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO71 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO70 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO69 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO68 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO67 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO66 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO65 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO64 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.50 GPCCSEL2 Register (Offset = AAh) [Reset = 00000000h]

GPCCSEL2 is shown in Figure 10-54 and described in Table 10-64.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-54. GPCCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO79 GPIO78 GPIO77 GPIO76
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-64. GPCCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO79 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO78 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO77 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO76 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO75 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO74 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO73 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO72 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.51 GPCCSEL3 Register (Offset = ACh) [Reset = 00000000h]

GPCCSEL3 is shown in Figure 10-55 and described in Table 10-65.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-55. GPCCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-65. GPCCSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R/W 0h Reserved
27-24 RESERVED R/W 0h Reserved
23-20 RESERVED R/W 0h Reserved
19-16 RESERVED R/W 0h Reserved
15-12 RESERVED R/W 0h Reserved
11-8 RESERVED R/W 0h Reserved
7-4 GPIO81 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO80 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.52 GPCLOCK Register (Offset = BCh) [Reset = 00000000h]

GPCLOCK is shown in Figure 10-56 and described in Table 10-66.
Return to the Summary Table.
GPIO C Lock Configuration Register (GPIO64 to 95)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 10-56. GPCLOCK Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-66. GPCLOCK Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 GPIO81 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 10-66. GPCLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
14 GPIO78 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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10.12.2.53 GPCCR Register (Offset = BEh) [Reset = 00000000h]

GPCCR is shown in Figure 10-57 and described in Table 10-67.
Return to the Summary Table.
GPIO C Lock Commit Register (GPIO64 to 95)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 10-57. GPCCR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 10-67. GPCCR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/WSonce 0h Reserved
30 RESERVED R/WSonce 0h Reserved
29 RESERVED R/WSonce 0h Reserved
28 RESERVED R/WSonce 0h Reserved
27 RESERVED R/WSonce 0h Reserved
26 RESERVED R/WSonce 0h Reserved
25 RESERVED R/WSonce 0h Reserved
24 RESERVED R/WSonce 0h Reserved
23 RESERVED R/WSonce 0h Reserved
22 RESERVED R/WSonce 0h Reserved
21 RESERVED R/WSonce 0h Reserved
20 RESERVED R/WSonce 0h Reserved
19 RESERVED R/WSonce 0h Reserved
18 RESERVED R/WSonce 0h Reserved
17 GPIO81 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO80 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO79 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO78 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 10-67. GPCCR Register Field Descriptions (continued)

Bit Field Type Reset Description
13 GPIO77 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO76 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO75 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO74 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO73 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO72 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO71 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 GPIO70 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
5 GPIO69 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 GPIO68 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
3 GPIO67 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO66 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO65 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO64 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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10.12.2.54 GPGCTRL Register (Offset = 180h) [Reset = 00000000h]

GPGCTRL is shown in Figure 10-58 and described in Table 10-68.
Return to the Summary Table.
GPIO G Qualification Sampling Period Control (GPIO192 to 223)
Figure 10-58. GPGCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED QUALPRD2 RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-68. GPGCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R/W 0h Reserved
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO208 to GPIO215:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 RESERVED R/W 0h Reserved
7-0 RESERVED R/W 0h Reserved

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10.12.2.55 GPGQSEL2 Register (Offset = 184h) [Reset = 00000000h]

GPGQSEL2 is shown in Figure 10-59 and described in Table 10-69.
Return to the Summary Table.
GPIO G Qualifier Select 2 Register (GPIO208 to 223)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-59. GPGQSEL2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO215 GPIO214 GPIO213 GPIO212
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO211 GPIO210 GPIO209 GPIO208
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-69. GPGQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 GPIO215 R/W 0h Select input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO214 R/W 0h Select input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-69. GPGQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GPIO213 R/W 0h Select input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO212 R/W 0h Select input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO211 R/W 0h Select input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO210 R/W 0h Select input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO209 R/W 0h Select input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO208 R/W 0h Select input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.12.2.56 GPGMUX2 Register (Offset = 188h) [Reset = 00000000h]

GPGMUX2 is shown in Figure 10-60 and described in Table 10-70.
Return to the Summary Table.
GPIO G Mux 2 Register (GPIO208 to 223)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-60. GPGMUX2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO215 GPIO214 GPIO213 GPIO212
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO211 GPIO210 GPIO209 GPIO208
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-70. GPGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 GPIO215 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO214 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO213 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO212 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO211 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO210 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO209 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-70. GPGMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO208 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.57 GPGDIR Register (Offset = 18Ah) [Reset = 00000000h]

GPGDIR is shown in Figure 10-61 and described in Table 10-71.
Return to the Summary Table.
GPIO G Direction Register (GPIO192 to 223)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 10-61. GPGDIR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-71. GPGDIR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 GPIO215 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO214 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO213 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
20 GPIO212 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO211 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
18 GPIO210 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
17 GPIO209 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 10-71. GPGDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
16 GPIO208 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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10.12.2.58 GPGPUD Register (Offset = 18Ch) [Reset = FFFFFFFFh]

GPGPUD is shown in Figure 10-62 and described in Table 10-72.
Return to the Summary Table.
GPIO G Pull Up Disable Register (GPIO192 to 223)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
Figure 10-62. GPGPUD Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-72. GPGPUD Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 RESERVED R/W 1h Reserved
28 RESERVED R/W 1h Reserved
27 RESERVED R/W 1h Reserved
26 RESERVED R/W 1h Reserved
25 RESERVED R/W 1h Reserved
24 RESERVED R/W 1h Reserved
23 GPIO215 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO214 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO213 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
20 GPIO212 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
19 GPIO211 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
18 GPIO210 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 10-72. GPGPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO209 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO208 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 RESERVED R/W 1h Reserved
14 RESERVED R/W 1h Reserved
13 RESERVED R/W 1h Reserved
12 RESERVED R/W 1h Reserved
11 RESERVED R/W 1h Reserved
10 RESERVED R/W 1h Reserved
9 RESERVED R/W 1h Reserved
8 RESERVED R/W 1h Reserved
7 RESERVED R/W 1h Reserved
6 RESERVED R/W 1h Reserved
5 RESERVED R/W 1h Reserved
4 RESERVED R/W 1h Reserved
3 RESERVED R/W 1h Reserved
2 RESERVED R/W 1h Reserved
1 RESERVED R/W 1h Reserved
0 RESERVED R/W 1h Reserved

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10.12.2.59 GPGINV Register (Offset = 190h) [Reset = 00000000h]

GPGINV is shown in Figure 10-63 and described in Table 10-73.
Return to the Summary Table.
GPIO G Input Polarity Invert Registers (GPIO192 to 223)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 10-63. GPGINV Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-73. GPGINV Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 GPIO215 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO214 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO213 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
20 GPIO212 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO211 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
18 GPIO210 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
17 GPIO209 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 10-73. GPGINV Register Field Descriptions (continued)

Bit Field Type Reset Description
16 GPIO208 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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10.12.2.60 GPGODR Register (Offset = 192h) [Reset = 00000000h]

GPGODR is shown in Figure 10-64 and described in Table 10-74.
Return to the Summary Table.
GPIO G Open Drain Output Register (GPIO92 to 223)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 10-64. GPGODR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-74. GPGODR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 GPIO215 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO214 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
21 GPIO213 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO212 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
19 GPIO211 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO210 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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Table 10-74. GPGODR Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO209 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO208 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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10.12.2.61 GPGAMSEL Register (Offset = 194h) [Reset = 00FF0000h]

GPGAMSEL is shown in Figure 10-65 and described in Table 10-75.
Return to the Summary Table.
GPIO G Analog Mode Select register (GPIO192 to 223)
Selects between digital and analog functionality for GPIO pins.
0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other
GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For
all the IOs, t
Figure 10-65. GPGAMSEL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-75. GPGAMSEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 GPIO215 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-75. GPGAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
22 GPIO214 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
21 GPIO213 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
20 GPIO212 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
19 GPIO211 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
18 GPIO210 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-75. GPGAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO209 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
16 GPIO208 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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10.12.2.62 GPGGMUX2 Register (Offset = 1A2h) [Reset = 00000000h]

GPGGMUX2 is shown in Figure 10-66 and described in Table 10-76.
Return to the Summary Table.
GPIO G Peripheral Group Mux (GPIO208 to 223)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-66. GPGGMUX2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO215 GPIO214 GPIO213 GPIO212
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO211 GPIO210 GPIO209 GPIO208
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-76. GPGGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 GPIO215 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO214 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO213 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO212 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO211 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO210 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO209 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-76. GPGGMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO208 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.63 GPGCSEL3 Register (Offset = 1ACh) [Reset = 00000000h]

GPGCSEL3 is shown in Figure 10-67 and described in Table 10-77.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-67. GPGCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO211 GPIO210 GPIO209 GPIO208
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-77. GPGCSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO215 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO214 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO213 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO212 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO211 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO210 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO209 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO208 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.64 GPGLOCK Register (Offset = 1BCh) [Reset = 00000000h]

GPGLOCK is shown in Figure 10-68 and described in Table 10-78.
Return to the Summary Table.
GPIO G Lock Configuration Register (GPIO192 to 223)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 10-68. GPGLOCK Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-78. GPGLOCK Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 GPIO215 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO214 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO213 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
20 GPIO212 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
19 GPIO211 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
18 GPIO210 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO209 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 10-78. GPGLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
16 GPIO208 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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10.12.2.65 GPGCR Register (Offset = 1BEh) [Reset = 00000000h]

GPGCR is shown in Figure 10-69 and described in Table 10-79.
Return to the Summary Table.
GPIO G Lock Commit Register (GPIO192 to 223)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 10-69. GPGCR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 10-79. GPGCR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/WSonce 0h Reserved
30 RESERVED R/WSonce 0h Reserved
29 RESERVED R/WSonce 0h Reserved
28 RESERVED R/WSonce 0h Reserved
27 RESERVED R/WSonce 0h Reserved
26 RESERVED R/WSonce 0h Reserved
25 RESERVED R/WSonce 0h Reserved
24 RESERVED R/WSonce 0h Reserved
23 GPIO215 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO214 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO213 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO212 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
19 GPIO211 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
18 GPIO210 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
17 GPIO209 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO208 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 10-79. GPGCR Register Field Descriptions (continued)

Bit Field Type Reset Description
15 RESERVED R/WSonce 0h Reserved
14 RESERVED R/WSonce 0h Reserved
13 RESERVED R/WSonce 0h Reserved
12 RESERVED R/WSonce 0h Reserved
11 RESERVED R/WSonce 0h Reserved
10 RESERVED R/WSonce 0h Reserved
9 RESERVED R/WSonce 0h Reserved
8 RESERVED R/WSonce 0h Reserved
7 RESERVED R/WSonce 0h Reserved
6 RESERVED R/WSonce 0h Reserved
5 RESERVED R/WSonce 0h Reserved
4 RESERVED R/WSonce 0h Reserved
3 RESERVED R/WSonce 0h Reserved
2 RESERVED R/WSonce 0h Reserved
1 RESERVED R/WSonce 0h Reserved
0 RESERVED R/WSonce 0h Reserved

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10.12.2.66 GPHCTRL Register (Offset = 1C0h) [Reset = 00000000h]

GPHCTRL is shown in Figure 10-70 and described in Table 10-80.
Return to the Summary Table.
GPIO H Qualification Sampling Period Control (GPIO224 to 255)
Figure 10-70. GPHCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-80. GPHCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/513
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/512
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/511
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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10.12.2.67 GPHQSEL1 Register (Offset = 1C2h) [Reset = 00000000h]

GPHQSEL1 is shown in Figure 10-71 and described in Table 10-81.
Return to the Summary Table.
GPIO H Qualifier Select 1 Register (GPIO224 to 239)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-71. GPHQSEL1 Register
31 30 29 28 27 26 25 24
GPIO239 GPIO238 GPIO237 GPIO236
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO235 GPIO234 GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO231 GPIO230 GPIO229 GPIO228
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-81. GPHQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO239 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO238 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO237 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO236 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO235 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-81. GPHQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 GPIO234 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
19-18 GPIO233 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
17-16 GPIO232 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO231 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO230 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
11-10 GPIO229 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO228 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO227 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO226 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO225 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO224 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.12.2.68 GPHQSEL2 Register (Offset = 1C4h) [Reset = 00000000h]

GPHQSEL2 is shown in Figure 10-72 and described in Table 10-82.
Return to the Summary Table.
GPIO H Qualifier Select 2 Register (GPIO240 to 255)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-72. GPHQSEL2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO247 RESERVED GPIO245 GPIO244
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-82. GPHQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 GPIO253 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO252 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO251 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 RESERVED R/W 0h Reserved
19-18 GPIO249 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-82. GPHQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
17-16 GPIO248 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO247 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 RESERVED R/W 0h Reserved
11-10 GPIO245 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO244 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 RESERVED R/W 0h Reserved
5-4 GPIO242 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO241 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO240 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.12.2.69 GPHMUX1 Register (Offset = 1C6h) [Reset = 00000000h]

GPHMUX1 is shown in Figure 10-73 and described in Table 10-83.
Return to the Summary Table.
GPIO H Mux 1 Register (GPIO224 to 239)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-73. GPHMUX1 Register
31 30 29 28 27 26 25 24
GPIO239 GPIO238 GPIO237 GPIO236
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO235 GPIO234 GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO231 GPIO230 GPIO229 GPIO228
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-83. GPHMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO239 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO238 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO237 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO236 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO235 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO234 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO233 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO232 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO231 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO230 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO229 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-83. GPHMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 GPIO228 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO227 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO226 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO225 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO224 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.70 GPHMUX2 Register (Offset = 1C8h) [Reset = 00000000h]

GPHMUX2 is shown in Figure 10-74 and described in Table 10-84.
Return to the Summary Table.
GPIO H Mux 2 Register (GPIO240 to 255)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-74. GPHMUX2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO247 RESERVED GPIO245 GPIO244
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-84. GPHMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 GPIO253 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO252 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO251 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 RESERVED R/W 0h Reserved
19-18 GPIO249 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO248 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO247 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 RESERVED R/W 0h Reserved
11-10 GPIO245 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO244 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 RESERVED R/W 0h Reserved
5-4 GPIO242 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-84. GPHMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 GPIO241 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO240 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.71 GPHDIR Register (Offset = 1CAh) [Reset = 00000000h]

GPHDIR is shown in Figure 10-75 and described in Table 10-85.
Return to the Summary Table.
GPIO H Direction Register (GPIO224 to 255)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 10-75. GPHDIR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 GPIO235 GPIO234 GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-85. GPHDIR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO253 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO252 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO251 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 RESERVED R/W 0h Reserved
25 GPIO249 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO248 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO247 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 RESERVED R/W 0h Reserved
21 GPIO245 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
20 GPIO244 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 RESERVED R/W 0h Reserved
18 GPIO242 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 10-85. GPHDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO241 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO240 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO239 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO238 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO237 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO236 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO235 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO234 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO233 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO232 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO231 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO230 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO229 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO228 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO227 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO226 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO225 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO224 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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10.12.2.72 GPHPUD Register (Offset = 1CCh) [Reset = FFFFFFFFh]

GPHPUD is shown in Figure 10-76 and described in Table 10-86.
Return to the Summary Table.
GPIO H Pull Up Disable Register (GPIO224 to 255)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
Figure 10-76. GPHPUD Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 GPIO235 GPIO234 GPIO233 GPIO232
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-86. GPHPUD Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 GPIO253 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
28 GPIO252 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn

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Table 10-86. GPHPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
27 GPIO251 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
26 RESERVED R/W 1h Reserved
25 GPIO249 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
24 GPIO248 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
23 GPIO247 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
22 RESERVED R/W 1h Reserved
21 GPIO245 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
20 GPIO244 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
19 RESERVED R/W 1h Reserved

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Table 10-86. GPHPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO242 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
17 GPIO241 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
16 GPIO240 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
15 GPIO239 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
14 GPIO238 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
13 GPIO237 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn

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Table 10-86. GPHPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
12 GPIO236 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
11 GPIO235 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
10 GPIO234 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
9 GPIO233 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
8 GPIO232 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
7 GPIO231 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn

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Table 10-86. GPHPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
6 GPIO230 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
5 GPIO229 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
4 GPIO228 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
3 GPIO227 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
2 GPIO226 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
1 GPIO225 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn

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Table 10-86. GPHPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
0 GPIO224 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn

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10.12.2.73 GPHINV Register (Offset = 1D0h) [Reset = 00000000h]

GPHINV is shown in Figure 10-77 and described in Table 10-87.
Return to the Summary Table.
GPIO H Input Polarity Invert Registers (GPIO224 to 255)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 10-77. GPHINV Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 GPIO235 GPIO234 GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-87. GPHINV Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO253 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
28 GPIO252 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
27 GPIO251 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
26 RESERVED R/W 0h Reserved
25 GPIO249 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn

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Table 10-87. GPHINV Register Field Descriptions (continued)

Bit Field Type Reset Description
24 GPIO248 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
23 GPIO247 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
22 RESERVED R/W 0h Reserved
21 GPIO245 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
20 GPIO244 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
19 RESERVED R/W 0h Reserved
18 GPIO242 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
17 GPIO241 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
16 GPIO240 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
15 GPIO239 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
14 GPIO238 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn

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Table 10-87. GPHINV Register Field Descriptions (continued)

Bit Field Type Reset Description
13 GPIO237 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
12 GPIO236 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
11 GPIO235 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
10 GPIO234 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
9 GPIO233 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
8 GPIO232 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
7 GPIO231 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
6 GPIO230 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
5 GPIO229 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn

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Table 10-87. GPHINV Register Field Descriptions (continued)

Bit Field Type Reset Description
4 GPIO228 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
3 GPIO227 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
2 GPIO226 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
1 GPIO225 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
0 GPIO224 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn

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10.12.2.74 GPHODR Register (Offset = 1D2h) [Reset = 00000000h]

GPHODR is shown in Figure 10-78 and described in Table 10-88.
Return to the Summary Table.
GPIO H Open Drain Output Register (GPIO224 to GPIO255)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 10-78. GPHODR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 GPIO235 GPIO234 GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-88. GPHODR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO253 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO252 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO251 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
26 RESERVED R/W 0h Reserved
25 GPIO249 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO248 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO247 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
22 RESERVED R/W 0h Reserved
21 GPIO245 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO244 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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Table 10-88. GPHODR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 RESERVED R/W 0h Reserved
18 GPIO242 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO241 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO240 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO239 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO238 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO237 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO236 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO235 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO234 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO233 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO232 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO231 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO230 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO229 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO228 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO227 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO226 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO225 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO224 R/W 0h Output Open-Drain control for this pin
Reset type: SYSRSn

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10.12.2.75 GPHAMSEL Register (Offset = 1D4h) [Reset = FFFFFFFFh]

GPHAMSEL is shown in Figure 10-79 and described in Table 10-89.
Return to the Summary Table.
GPIO H Analog Mode Select register (GPIO224 to GPIO255)
Selects between digital and analog functionality for GPIO pins.
0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other
GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For
all the IOs, t
Figure 10-79. GPHAMSEL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 GPIO235 GPIO234 GPIO233 GPIO232
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-89. GPHAMSEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 GPIO253 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
28 GPIO252 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-89. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
27 GPIO251 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
26 RESERVED R/W 1h Reserved
25 GPIO249 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
24 GPIO248 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
23 GPIO247 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
22 RESERVED R/W 1h Reserved
21 GPIO245 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-89. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO244 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
19 RESERVED R/W 1h Reserved
18 GPIO242 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
17 GPIO241 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
16 GPIO240 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
15 GPIO239 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-89. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
14 GPIO238 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
13 GPIO237 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
12 GPIO236 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
11 GPIO235 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
10 GPIO234 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-89. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
9 GPIO233 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
8 GPIO232 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
7 GPIO231 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
6 GPIO230 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
5 GPIO229 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-89. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
4 GPIO228 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
3 GPIO227 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
2 GPIO226 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
1 GPIO225 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
0 GPIO224 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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10.12.2.76 GPHGMUX1 Register (Offset = 1E0h) [Reset = 00000000h]

GPHGMUX1 is shown in Figure 10-80 and described in Table 10-90.
Return to the Summary Table.
GPIO H Peripheral Group Mux (GPIO224 to 239)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-80. GPHGMUX1 Register
31 30 29 28 27 26 25 24
GPIO239 GPIO238 GPIO237 GPIO236
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO235 GPIO234 GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO231 GPIO230 GPIO229 GPIO228
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-90. GPHGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO239 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO238 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO237 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO236 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO235 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO234 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO233 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO232 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO231 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO230 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO229 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO228 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-90. GPHGMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GPIO227 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO226 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO225 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO224 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.77 GPHGMUX2 Register (Offset = 1E2h) [Reset = 00000000h]

GPHGMUX2 is shown in Figure 10-81 and described in Table 10-91.
Return to the Summary Table.
GPIO H Peripheral Group Mux (GPIO240 to 255)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-81. GPHGMUX2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO247 RESERVED GPIO245 GPIO244
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-91. GPHGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 GPIO253 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO252 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO251 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 RESERVED R/W 0h Reserved
19-18 GPIO249 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO248 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO247 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 RESERVED R/W 0h Reserved
11-10 GPIO245 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO244 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 RESERVED R/W 0h Reserved
5-4 GPIO242 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-91. GPHGMUX2 Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 GPIO241 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO240 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.12.2.78 GPHCSEL1 Register (Offset = 1E8h) [Reset = 00000000h]

GPHCSEL1 is shown in Figure 10-82 and described in Table 10-92.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-82. GPHCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO231 GPIO230 GPIO229 GPIO228
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-92. GPHCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO231 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO230 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO229 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO228 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO227 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO226 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO225 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO224 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.79 GPHCSEL2 Register (Offset = 1EAh) [Reset = 00000000h]

GPHCSEL2 is shown in Figure 10-83 and described in Table 10-93.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-83. GPHCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO239 GPIO238 GPIO237 GPIO236
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO235 GPIO234 GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-93. GPHCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO239 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO238 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO237 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO236 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO235 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO234 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO233 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO232 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.80 GPHCSEL3 Register (Offset = 1ECh) [Reset = 00000000h]

GPHCSEL3 is shown in Figure 10-84 and described in Table 10-94.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-84. GPHCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-94. GPHCSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO247 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 RESERVED R/W 0h Reserved
23-20 GPIO245 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO244 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 RESERVED R/W 0h Reserved
11-8 GPIO242 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO241 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO240 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.81 GPHCSEL4 Register (Offset = 1EEh) [Reset = 00000000h]

GPHCSEL4 is shown in Figure 10-85 and described in Table 10-95.
Return to the Summary Table.
Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-85. GPHCSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO253 GPIO252
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-95. GPHCSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R/W 0h Reserved
27-24 RESERVED R/W 0h Reserved
23-20 GPIO253 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO252 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO251 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 RESERVED R/W 0h Reserved
7-4 GPIO249 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO248 R/W 0h Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.12.2.82 GPHLOCK Register (Offset = 1FCh) [Reset = 00000000h]

GPHLOCK is shown in Figure 10-86 and described in Table 10-96.
Return to the Summary Table.
GPIO H Lock Configuration Register (GPIO224 to 255)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 10-86. GPHLOCK Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 GPIO235 GPIO234 GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-96. GPHLOCK Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO253 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
28 GPIO252 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
27 GPIO251 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
26 RESERVED R/W 0h Reserved

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Table 10-96. GPHLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
25 GPIO249 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
24 GPIO248 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
23 GPIO247 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
22 RESERVED R/W 0h Reserved
21 GPIO245 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
20 GPIO244 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
19 RESERVED R/W 0h Reserved
18 GPIO242 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
17 GPIO241 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
16 GPIO240 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn

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Table 10-96. GPHLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
15 GPIO239 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
14 GPIO238 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
13 GPIO237 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
12 GPIO236 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
11 GPIO235 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
10 GPIO234 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
9 GPIO233 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
8 GPIO232 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn

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Table 10-96. GPHLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
7 GPIO231 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
6 GPIO230 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
5 GPIO229 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
4 GPIO228 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
3 GPIO227 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
2 GPIO226 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
1 GPIO225 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
0 GPIO224 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn

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10.12.2.83 GPHCR Register (Offset = 1FEh) [Reset = 00000000h]

GPHCR is shown in Figure 10-87 and described in Table 10-97.
Return to the Summary Table.
GPIO H Lock Commit Register (GPIO224 to 255)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 10-87. GPHCR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 GPIO235 GPIO234 GPIO233 GPIO232
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 10-97. GPHCR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/WSonce 0h Reserved
30 RESERVED R/WSonce 0h Reserved
29 GPIO253 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
28 GPIO252 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
27 GPIO251 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
26 RESERVED R/WSonce 0h Reserved
25 GPIO249 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
24 GPIO248 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn

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Table 10-97. GPHCR Register Field Descriptions (continued)

Bit Field Type Reset Description
23 GPIO247 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
22 RESERVED R/WSonce 0h Reserved
21 GPIO245 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
20 GPIO244 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
19 RESERVED R/WSonce 0h Reserved
18 GPIO242 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
17 GPIO241 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
16 GPIO240 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
15 GPIO239 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
14 GPIO238 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
13 GPIO237 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
12 GPIO236 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
11 GPIO235 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn

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Table 10-97. GPHCR Register Field Descriptions (continued)

Bit Field Type Reset Description
10 GPIO234 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
9 GPIO233 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
8 GPIO232 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
7 GPIO231 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
6 GPIO230 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
5 GPIO229 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
4 GPIO228 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
3 GPIO227 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
2 GPIO226 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
1 GPIO225 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
0 GPIO224 R/WSonce 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn

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10.12.3 GPIO_DATA_REGS Registers

Table 10-98 lists the memory-mapped registers for the GPIO_DATA_REGS registers. All register offset
addresses not listed in Table 10-98 should be considered as reserved locations and the register contents should
not be modified.
Table 10-98. GPIO_DATA_REGS Registers
Offset Acronym Register Name Write Protection Section
0h GPADAT GPIO A Data Register (GPIO0 to 31) Go
2h GPASET GPIO A Data Set Register (GPIO0 to 31) Go
4h GPACLEAR GPIO A Data Clear Register (GPIO0 to 31) Go
6h GPATOGGLE GPIO A Data Toggle Register (GPIO0 to 31) Go
8h GPBDAT GPIO B Data Register (GPIO32 to 63) Go
Ah GPBSET GPIO B Data Set Register (GPIO32 to 63) Go
Ch GPBCLEAR GPIO B Data Clear Register (GPIO32 to 63) Go
Eh GPBTOGGLE GPIO B Data Toggle Register (GPIO32 to 63) Go
10h GPCDAT GPIO C Data Register (GPIO64 to 95) Go
12h GPCSET GPIO C Data Set Register (GPIO64 to 95) Go
14h GPCCLEAR GPIO C Data Clear Register (GPIO64 to 95) Go
16h GPCTOGGLE GPIO C Data Toggle Register (GPIO64 to 95) Go
30h GPGDAT GPIO G Data Register (GPIO192 to 223) Go
32h GPGSET GPIO G Data Set Register (GPIO192 to 223) Go
34h GPGCLEAR GPIO G Data Clear Register (GPIO192 to 223) Go
36h GPGTOGGLE GPIO G Data Toggle Register (GPIO192 to 223) Go
38h GPHDAT GPIO H Data Register (GPIO224 to 255) Go
3Ah GPHSET GPIO H Data Set Register (GPIO224 to 255) Go
3Ch GPHCLEAR GPIO H Data Clear Register (GPIO224 to 255) Go
3Eh GPHTOGGLE GPIO H Data Toggle Register (GPIO224 to 255) Go

Complex bit access types are encoded to fit into small table cells. Table 10-99 shows the codes that are used for
access types in this section.
Table 10-99. GPIO_DATA_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.

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Table 10-99. GPIO_DATA_REGS Access Type Codes (continued)

Access Type Code Description
y When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.

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10.12.3.1 GPADAT Register (Offset = 0h) [Reset = 00000000h]

GPADAT is shown in Figure 10-88 and described in Table 10-100.
Return to the Summary Table.
GPIO A Data Register (GPIO0 to 31)
Reading this register indicates the current status of the GPIO pin, irrespective of which mode the pin is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode, otherwise the
value written is latched but ignored. The state of the output register latch will remain in its current state until the
next write operation. A system reset will clear all bits and latched values to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN (after qualification), not the state of the
output latch of the GPIODAT register.
Figure 10-88. GPADAT Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-100. GPADAT Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Data Register for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Data Register for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Data Register for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Data Register for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Data Register for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Data Register for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Data Register for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Data Register for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 10-100. GPADAT Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO21 R/W 0h Data Register for this pin
Reset type: SYSRSn
20 GPIO20 R/W 0h Data Register for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Data Register for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Data Register for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Data Register for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Data Register for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Data Register for this pin
Reset type: SYSRSn

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10.12.3.2 GPASET Register (Offset = 2h) [Reset = 00000000h]

GPASET is shown in Figure 10-89 and described in Table 10-101.
Return to the Summary Table.
GPIO A Data Set Register (GPIO0 to 31)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-89. GPASET Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-101. GPASET Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
30 GPIO30 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
29 GPIO29 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
28 GPIO28 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
27 GPIO27 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
26 GPIO26 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
25 GPIO25 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
24 GPIO24 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
23 GPIO23 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO22 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO21 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO20 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 10-101. GPASET Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
18 GPIO18 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
17 GPIO17 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO16 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO15 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO14 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
13 GPIO13 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO12 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO11 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO10 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO9 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO8 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO7 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 GPIO6 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
5 GPIO5 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 GPIO4 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
3 GPIO3 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO2 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO1 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO0 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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10.12.3.3 GPACLEAR Register (Offset = 4h) [Reset = 00000000h]

GPACLEAR is shown in Figure 10-90 and described in Table 10-102.
Return to the Summary Table.
GPIO A Data Clear Register (GPIO0 to 31)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-90. GPACLEAR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-102. GPACLEAR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
30 GPIO30 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
29 GPIO29 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
28 GPIO28 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
27 GPIO27 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
26 GPIO26 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
25 GPIO25 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
24 GPIO24 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
23 GPIO23 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO22 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO21 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO20 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 10-102. GPACLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
18 GPIO18 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
17 GPIO17 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO16 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO15 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO14 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
13 GPIO13 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO12 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO11 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO10 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO9 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO8 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO7 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 GPIO6 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
5 GPIO5 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 GPIO4 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
3 GPIO3 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO2 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO1 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO0 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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10.12.3.4 GPATOGGLE Register (Offset = 6h) [Reset = 00000000h]

GPATOGGLE is shown in Figure 10-91 and described in Table 10-103.
Return to the Summary Table.
GPIO A Data Toggle Register (GPIO0 to 31)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-91. GPATOGGLE Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-103. GPATOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
30 GPIO30 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
29 GPIO29 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
28 GPIO28 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
27 GPIO27 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
26 GPIO26 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
25 GPIO25 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
24 GPIO24 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
23 GPIO23 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO22 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO21 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO20 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 10-103. GPATOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
18 GPIO18 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
17 GPIO17 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO16 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO15 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO14 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
13 GPIO13 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO12 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO11 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO10 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO9 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO8 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO7 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 GPIO6 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
5 GPIO5 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 GPIO4 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
3 GPIO3 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO2 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO1 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO0 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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10.12.3.5 GPBDAT Register (Offset = 8h) [Reset = 00000000h]

GPBDAT is shown in Figure 10-92 and described in Table 10-104.
Return to the Summary Table.
GPIO B Data Register (GPIO32 to 63)
Reading this register indicates the current status of the GPIO pin, irrespective of which mode the pin is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode, otherwise the
value written is latched but ignored. The state of the output register latch will remain in its current state until the
next write operation. A system reset will clear all bits and latched values to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN (after qualification), not the state of the
output latch of the GPIODAT register.
Figure 10-92. GPBDAT Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-104. GPBDAT Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h Data Register for this pin
Reset type: SYSRSn
30 GPIO62 R/W 0h Data Register for this pin
Reset type: SYSRSn
29 GPIO61 R/W 0h Data Register for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Data Register for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Data Register for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Data Register for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Data Register for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Data Register for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 10-104. GPBDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO53 R/W 0h Data Register for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Data Register for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Data Register for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Data Register for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Data Register for this pin
Reset type: SYSRSn

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10.12.3.6 GPBSET Register (Offset = Ah) [Reset = 00000000h]

GPBSET is shown in Figure 10-93 and described in Table 10-105.
Return to the Summary Table.
GPIO B Data Set Register (GPIO32 to 63)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-93. GPBSET Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-105. GPBSET Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
30 GPIO62 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
29 GPIO61 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
28 GPIO60 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
27 GPIO59 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
26 GPIO58 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
25 GPIO57 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
24 GPIO56 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
23 GPIO55 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO54 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO53 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO52 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 10-105. GPBSET Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
18 GPIO50 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
17 GPIO49 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO48 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO47 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO46 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
13 GPIO45 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO44 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO43 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO42 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO41 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO40 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 RESERVED R-0/W 0h Reserved
6 RESERVED R-0/W 0h Reserved
5 GPIO37 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 RESERVED R-0/W 0h Reserved
3 GPIO35 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO34 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO33 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO32 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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10.12.3.7 GPBCLEAR Register (Offset = Ch) [Reset = 00000000h]

GPBCLEAR is shown in Figure 10-94 and described in Table 10-106.
Return to the Summary Table.
GPIO B Data Clear Register (GPIO32 to 63)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-94. GPBCLEAR Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-106. GPBCLEAR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
30 GPIO62 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
29 GPIO61 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
28 GPIO60 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
27 GPIO59 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
26 GPIO58 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
25 GPIO57 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
24 GPIO56 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
23 GPIO55 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO54 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO53 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO52 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 10-106. GPBCLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
18 GPIO50 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
17 GPIO49 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO48 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO47 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO46 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
13 GPIO45 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO44 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO43 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO42 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO41 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO40 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 RESERVED R-0/W 0h Reserved
6 RESERVED R-0/W 0h Reserved
5 GPIO37 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 RESERVED R-0/W 0h Reserved
3 GPIO35 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO34 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO33 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO32 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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10.12.3.8 GPBTOGGLE Register (Offset = Eh) [Reset = 00000000h]

GPBTOGGLE is shown in Figure 10-95 and described in Table 10-107.
Return to the Summary Table.
GPIO B Data Toggle Register (GPIO32 to 63)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-95. GPBTOGGLE Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-107. GPBTOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
30 GPIO62 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
29 GPIO61 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
28 GPIO60 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
27 GPIO59 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
26 GPIO58 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
25 GPIO57 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
24 GPIO56 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
23 GPIO55 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO54 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO53 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO52 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 10-107. GPBTOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
18 GPIO50 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
17 GPIO49 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO48 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO47 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO46 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
13 GPIO45 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO44 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO43 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO42 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO41 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO40 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 RESERVED R-0/W 0h Reserved
6 RESERVED R-0/W 0h Reserved
5 GPIO37 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 RESERVED R-0/W 0h Reserved
3 GPIO35 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO34 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO33 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO32 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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10.12.3.9 GPCDAT Register (Offset = 10h) [Reset = 00000000h]

GPCDAT is shown in Figure 10-96 and described in Table 10-108.
Return to the Summary Table.
GPIO C Data Register (GPIO64 to 95)
Reading this register indicates the current status of the GPIO pin, irrespective of which mode the pin is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode, otherwise the
value written is latched but ignored. The state of the output register latch will remain in its current state until the
next write operation. A system reset will clear all bits and latched values to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN (after qualification), not the state of the
output latch of the
Figure 10-96. GPCDAT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-108. GPCDAT Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 RESERVED R/W 0h Reserved
20 RESERVED R/W 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 GPIO81 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO80 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO79 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 10-108. GPCDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
14 GPIO78 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO77 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO76 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO75 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO74 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO73 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO72 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO71 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 GPIO70 R/W 0h Data Register for this pin
Reset type: SYSRSn
5 GPIO69 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 GPIO68 R/W 0h Data Register for this pin
Reset type: SYSRSn
3 GPIO67 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO66 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO65 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO64 R/W 0h Data Register for this pin
Reset type: SYSRSn

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10.12.3.10 GPCSET Register (Offset = 12h) [Reset = 00000000h]

GPCSET is shown in Figure 10-97 and described in Table 10-109.
Return to the Summary Table.
GPIO C Data Set Register (GPIO64 to 95)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-97. GPCSET Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-109. GPCSET Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W 0h Reserved
30 RESERVED R-0/W 0h Reserved
29 RESERVED R-0/W 0h Reserved
28 RESERVED R-0/W 0h Reserved
27 RESERVED R-0/W 0h Reserved
26 RESERVED R-0/W 0h Reserved
25 RESERVED R-0/W 0h Reserved
24 RESERVED R-0/W 0h Reserved
23 RESERVED R-0/W 0h Reserved
22 RESERVED R-0/W 0h Reserved
21 RESERVED R-0/W 0h Reserved
20 RESERVED R-0/W 0h Reserved
19 RESERVED R-0/W 0h Reserved
18 RESERVED R-0/W 0h Reserved
17 GPIO81 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO80 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO79 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO78 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 10-109. GPCSET Register Field Descriptions (continued)

Bit Field Type Reset Description
13 GPIO77 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO76 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO75 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO74 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO73 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO72 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO71 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 GPIO70 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
5 GPIO69 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 GPIO68 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
3 GPIO67 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO66 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO65 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO64 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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10.12.3.11 GPCCLEAR Register (Offset = 14h) [Reset = 00000000h]

GPCCLEAR is shown in Figure 10-98 and described in Table 10-110.
Return to the Summary Table.
GPIO C Data Clear Register (GPIO64 to 95)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-98. GPCCLEAR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-110. GPCCLEAR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W 0h Reserved
30 RESERVED R-0/W 0h Reserved
29 RESERVED R-0/W 0h Reserved
28 RESERVED R-0/W 0h Reserved
27 RESERVED R-0/W 0h Reserved
26 RESERVED R-0/W 0h Reserved
25 RESERVED R-0/W 0h Reserved
24 RESERVED R-0/W 0h Reserved
23 RESERVED R-0/W 0h Reserved
22 RESERVED R-0/W 0h Reserved
21 RESERVED R-0/W 0h Reserved
20 RESERVED R-0/W 0h Reserved
19 RESERVED R-0/W 0h Reserved
18 RESERVED R-0/W 0h Reserved
17 GPIO81 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO80 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO79 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO78 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 10-110. GPCCLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
13 GPIO77 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO76 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO75 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO74 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO73 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO72 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO71 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 GPIO70 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
5 GPIO69 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 GPIO68 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
3 GPIO67 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO66 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO65 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO64 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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10.12.3.12 GPCTOGGLE Register (Offset = 16h) [Reset = 00000000h]

GPCTOGGLE is shown in Figure 10-99 and described in Table 10-111.
Return to the Summary Table.
GPIO C Data Toggle Register (GPIO64 to 95)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-99. GPCTOGGLE Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPIO81 GPIO80
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-111. GPCTOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W 0h Reserved
30 RESERVED R-0/W 0h Reserved
29 RESERVED R-0/W 0h Reserved
28 RESERVED R-0/W 0h Reserved
27 RESERVED R-0/W 0h Reserved
26 RESERVED R-0/W 0h Reserved
25 RESERVED R-0/W 0h Reserved
24 RESERVED R-0/W 0h Reserved
23 RESERVED R-0/W 0h Reserved
22 RESERVED R-0/W 0h Reserved
21 RESERVED R-0/W 0h Reserved
20 RESERVED R-0/W 0h Reserved
19 RESERVED R-0/W 0h Reserved
18 RESERVED R-0/W 0h Reserved
17 GPIO81 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO80 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO79 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO78 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 10-111. GPCTOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
13 GPIO77 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO76 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO75 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO74 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO73 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO72 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO71 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 GPIO70 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
5 GPIO69 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 GPIO68 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
3 GPIO67 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO66 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO65 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO64 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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10.12.3.13 GPGDAT Register (Offset = 30h) [Reset = 00000000h]

GPGDAT is shown in Figure 10-100 and described in Table 10-112.
Return to the Summary Table.
GPIO G Data Register (GPIO192 to 223)
Reading this register indicates the current status of the GPIO pin, irrespective of which mode the pin is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode, otherwise the
value written is latched but ignored. The state of the output register latch will remain in its current state until the
next write operation. A system reset will clear all bits and latched values to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN (after qualification), not the state of the
output latch of the
Figure 10-100. GPGDAT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-112. GPGDAT Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 GPIO215 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO214 R/W 0h Data Register for this pin
Reset type: SYSRSn
21 GPIO213 R/W 0h Data Register for this pin
Reset type: SYSRSn
20 GPIO212 R/W 0h Data Register for this pin
Reset type: SYSRSn
19 GPIO211 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO210 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 10-112. GPGDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO209 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO208 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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10.12.3.14 GPGSET Register (Offset = 32h) [Reset = 00000000h]

GPGSET is shown in Figure 10-101 and described in Table 10-113.
Return to the Summary Table.
GPIO G Data Set Register (GPIO192 to 223)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-101. GPGSET Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-113. GPGSET Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W 0h Reserved
30 RESERVED R-0/W 0h Reserved
29 RESERVED R-0/W 0h Reserved
28 RESERVED R-0/W 0h Reserved
27 RESERVED R-0/W 0h Reserved
26 RESERVED R-0/W 0h Reserved
25 RESERVED R-0/W 0h Reserved
24 RESERVED R-0/W 0h Reserved
23 GPIO215 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO214 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO213 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO212 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
19 GPIO211 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
18 GPIO210 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
17 GPIO209 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO208 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 10-113. GPGSET Register Field Descriptions (continued)

Bit Field Type Reset Description
15 RESERVED R-0/W 0h Reserved
14 RESERVED R-0/W 0h Reserved
13 RESERVED R-0/W 0h Reserved
12 RESERVED R-0/W 0h Reserved
11 RESERVED R-0/W 0h Reserved
10 RESERVED R-0/W 0h Reserved
9 RESERVED R-0/W 0h Reserved
8 RESERVED R-0/W 0h Reserved
7 RESERVED R-0/W 0h Reserved
6 RESERVED R-0/W 0h Reserved
5 RESERVED R-0/W 0h Reserved
4 RESERVED R-0/W 0h Reserved
3 RESERVED R-0/W 0h Reserved
2 RESERVED R-0/W 0h Reserved
1 RESERVED R-0/W 0h Reserved
0 RESERVED R-0/W 0h Reserved

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10.12.3.15 GPGCLEAR Register (Offset = 34h) [Reset = 00000000h]

GPGCLEAR is shown in Figure 10-102 and described in Table 10-114.
Return to the Summary Table.
GPIO G Data Clear Register (GPIO192 to 223)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-102. GPGCLEAR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-114. GPGCLEAR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W 0h Reserved
30 RESERVED R-0/W 0h Reserved
29 RESERVED R-0/W 0h Reserved
28 RESERVED R-0/W 0h Reserved
27 RESERVED R-0/W 0h Reserved
26 RESERVED R-0/W 0h Reserved
25 RESERVED R-0/W 0h Reserved
24 RESERVED R-0/W 0h Reserved
23 GPIO215 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO214 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO213 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO212 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
19 GPIO211 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
18 GPIO210 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
17 GPIO209 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO208 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 10-114. GPGCLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
15 RESERVED R-0/W 0h Reserved
14 RESERVED R-0/W 0h Reserved
13 RESERVED R-0/W 0h Reserved
12 RESERVED R-0/W 0h Reserved
11 RESERVED R-0/W 0h Reserved
10 RESERVED R-0/W 0h Reserved
9 RESERVED R-0/W 0h Reserved
8 RESERVED R-0/W 0h Reserved
7 RESERVED R-0/W 0h Reserved
6 RESERVED R-0/W 0h Reserved
5 RESERVED R-0/W 0h Reserved
4 RESERVED R-0/W 0h Reserved
3 RESERVED R-0/W 0h Reserved
2 RESERVED R-0/W 0h Reserved
1 RESERVED R-0/W 0h Reserved
0 RESERVED R-0/W 0h Reserved

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10.12.3.16 GPGTOGGLE Register (Offset = 36h) [Reset = 00000000h]

GPGTOGGLE is shown in Figure 10-103 and described in Table 10-115.
Return to the Summary Table.
GPIO G Data Toggle Register (GPIO192 to 223)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-103. GPGTOGGLE Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO215 GPIO214 GPIO213 GPIO212 GPIO211 GPIO210 GPIO209 GPIO208
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-115. GPGTOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W 0h Reserved
30 RESERVED R-0/W 0h Reserved
29 RESERVED R-0/W 0h Reserved
28 RESERVED R-0/W 0h Reserved
27 RESERVED R-0/W 0h Reserved
26 RESERVED R-0/W 0h Reserved
25 RESERVED R-0/W 0h Reserved
24 RESERVED R-0/W 0h Reserved
23 GPIO215 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO214 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO213 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO212 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
19 GPIO211 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
18 GPIO210 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
17 GPIO209 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO208 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 10-115. GPGTOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
15 RESERVED R-0/W 0h Reserved
14 RESERVED R-0/W 0h Reserved
13 RESERVED R-0/W 0h Reserved
12 RESERVED R-0/W 0h Reserved
11 RESERVED R-0/W 0h Reserved
10 RESERVED R-0/W 0h Reserved
9 RESERVED R-0/W 0h Reserved
8 RESERVED R-0/W 0h Reserved
7 RESERVED R-0/W 0h Reserved
6 RESERVED R-0/W 0h Reserved
5 RESERVED R-0/W 0h Reserved
4 RESERVED R-0/W 0h Reserved
3 RESERVED R-0/W 0h Reserved
2 RESERVED R-0/W 0h Reserved
1 RESERVED R-0/W 0h Reserved
0 RESERVED R-0/W 0h Reserved

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10.12.3.17 GPHDAT Register (Offset = 38h) [Reset = 00000000h]

GPHDAT is shown in Figure 10-104 and described in Table 10-116.
Return to the Summary Table.
GPIO H Data Register (GPIO224 to 255)
Reading this register indicates the current status of the GPIO pin, irrespective of which mode the pin is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode, otherwise the
value written is latched but ignored. The state of the output register latch will remain in its current state until the
next write operation. A system reset will clear all bits and latched values to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN (after qualification), not the state of the
output latch of the
Figure 10-104. GPHDAT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 GPIO235 GPIO234 GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-116. GPHDAT Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO253 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
28 GPIO252 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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Table 10-116. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
27 GPIO251 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
26 RESERVED R/W 0h Reserved
25 GPIO249 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
24 GPIO248 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
23 GPIO247 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
22 RESERVED R/W 0h Reserved

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Table 10-116. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO245 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
20 GPIO244 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
19 RESERVED R/W 0h Reserved
18 GPIO242 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
17 GPIO241 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
16 GPIO240 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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Table 10-116. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
15 GPIO239 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
14 GPIO238 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
13 GPIO237 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
12 GPIO236 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
11 GPIO235 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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Table 10-116. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
10 GPIO234 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
9 GPIO233 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
8 GPIO232 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
7 GPIO231 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
6 GPIO230 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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Table 10-116. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
5 GPIO229 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
4 GPIO228 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
3 GPIO227 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written i