[AMDGPU][True16][MC] added missing testlines for t16 test #135823
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-mc Author: Brox Chen (broxigarchen) ChangesThis is a NFC patch. Update testlines for true16 mc inst including: The tabelgen change is done, but these are testlines that are not yet up-to-date Patch is 139.91 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/135823.diff 26 Files Affected:
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s
index 188e87d20412f..f952d658405c4 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace
//===----------------------------------------------------------------------===//
// VINTERP src operands must be VGPRs.
@@ -25,20 +25,20 @@ v_interp_p2_f32 v0, v1, 2, v3
v_interp_p2_f32 v0, v1, v2, 3
// GCN-ERR: :[[@LINE-1]]:29: error: invalid operand for instruction
-v_interp_p10_f16_f32 v0, s1, v2, v3
+v_interp_p10_f16_f32 v0, s1, v2, v3.l
// GCN-ERR: :[[@LINE-1]]:26: error: invalid operand for instruction
-v_interp_p10_f16_f32 v0, v1, s2, v3
-// GCN-ERR: :[[@LINE-1]]:30: error: invalid operand for instruction
+v_interp_p10_f16_f32 v0, v1.l, s2, v3.l
+// GCN-ERR: :[[@LINE-1]]:32: error: invalid operand for instruction
-v_interp_p10_f16_f32 v0, v1, v2, s3
-// GCN-ERR: :[[@LINE-1]]:34: error: invalid operand for instruction
+v_interp_p10_f16_f32 v0, v1.l, v2, s3
+// GCN-ERR: :[[@LINE-1]]:36: error: invalid operand for instruction
-v_interp_p2_f16_f32 v0, 1, v2, v3
-// GCN-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
+v_interp_p2_f16_f32 v0.l, 1, v2, v3.l
+// GCN-ERR: :[[@LINE-1]]:27: error: invalid operand for instruction
-v_interp_p2_f16_f32 v0, v1, 2, v3
-// GCN-ERR: :[[@LINE-1]]:29: error: invalid operand for instruction
-
-v_interp_p2_f16_f32 v0, v1, v2, 3
+v_interp_p2_f16_f32 v0.l, v1.l, 2, v3.l
// GCN-ERR: :[[@LINE-1]]:33: error: invalid operand for instruction
+
+v_interp_p2_f16_f32 v0.l, v1.l, v2, 3
+// GCN-ERR: :[[@LINE-1]]:37: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
index 1aefd1f0a7d19..9541f5f645e35 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
@@ -2,7 +2,7 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
-v_bfrev_b32_e32 v5, v1
+v_bfrev_b32 v5, v1
// GFX11: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e]
v_bfrev_b32 v5, v255
@@ -464,6 +464,9 @@ v_cvt_f16_f32 v5.h, src_scc
v_cvt_f16_f32 v127.h, 0xaf123456
// GFX11: v_cvt_f16_f32_e32 v127.h, 0xaf123456 ; encoding: [0xff,0x14,0xfe,0x7f,0x56,0x34,0x12,0xaf]
+v_cvt_f16_f32 v127.l, 0.5
+// GFX11: v_cvt_f16_f32_e32 v127.l, 0.5 ; encoding: [0xf0,0x14,0xfe,0x7e]
+
v_cvt_f16_i16 v5.l, v1.l
// GFX11: v_cvt_f16_i16_e32 v5.l, v1.l ; encoding: [0x01,0xa3,0x0a,0x7e]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
index 2bdb9ecfb7658..40786454584e7 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
@@ -2,7 +2,7 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0]
+v_bfrev_b32 v5, v1 quad_perm:[3,2,1,0]
// GFX11: v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0xff]
v_bfrev_b32 v5, v1 quad_perm:[0,1,2,3]
@@ -389,6 +389,9 @@ v_cvt_f16_f32 v5.h, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
v_cvt_f16_f32 v127.h, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_cvt_f16_f32_dpp v127.h, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x14,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+v_cvt_f16_f32 v127.l, v1 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_cvt_f16_f32_dpp v127.l, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x14,0xfe,0x7e,0x01,0x5f,0x01,0x01]
+
v_cvt_f16_i16 v5.l, v1.l quad_perm:[3,2,1,0]
// GFX11: v_cvt_f16_i16_dpp v5.l, v1.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
@@ -515,6 +518,9 @@ v_cvt_f32_f16 v5, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
v_cvt_f32_f16 v255, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_cvt_f32_f16_dpp v255, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x16,0xfe,0x7f,0xff,0x6f,0x35,0x30]
+v_cvt_f32_f16 v5, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_cvt_f32_f16_dpp v5, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x16,0x0a,0x7e,0x7f,0x5f,0x01,0x01]
+
v_cvt_f32_i32 v5, v1 quad_perm:[3,2,1,0]
// GFX11: v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
index ba0c3495de2bb..160a0ec2c4eb6 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
@@ -2,7 +2,7 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
-v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
+v_bfrev_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]
v_bfrev_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
index b1eb63699409f..55a25ad3ec81b 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --sort --version 5
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
@@ -116,6 +116,24 @@ v_cvt_f16_f32_e32 v128, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
v_cvt_f16_f32_e32 v128, 0xaf123456 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:36: error: invalid operand for instruction
+v_cvt_f16_f32_e32 v128.h, 0xaf123456
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v128.h, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v128.h, 0xaf123456 quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v128.l, 0xaf123456
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v128.l, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v128.l, 0xaf123456 quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
v_cvt_f16_f32_e32 v255, v1
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
@@ -134,6 +152,42 @@ v_cvt_f16_f32_e32 v255, v255 dpp8:[7,6,5,4,3,2,1,0]
v_cvt_f16_f32_e32 v255, v255 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
+v_cvt_f16_f32_e32 v255.h, v1.h
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.h, v1.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.h, v255.h
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.l, v1.l
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.l, v1.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.l, v255.l
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f16_f32_e32 v255.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
v_cvt_f16_i16_e32 v128.h, 0xfe0b
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
@@ -227,6 +281,24 @@ v_cvt_f32_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
v_cvt_f32_f16_e32 v5, v199 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction
+v_cvt_f32_f16_e32 v5.h, v199.h
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f32_f16_e32 v5.h, v199.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f32_f16_e32 v5.h, v199.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f32_f16_e32 v5.l, v199.l
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f32_f16_e32 v5.l, v199.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
+v_cvt_f32_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
+
v_cvt_i16_f16_e32 v128.h, 0xfe0b
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
index 5cb81c640f413..78550ddc734ca 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --sort --version 5
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
@@ -242,6 +242,9 @@ v_cvt_f16_f32 v255.h, ttmp15
v_cvt_f16_f32 v255.h, v1
// GFX11: v_cvt_f16_f32_e64 v255.h, v1 op_sel:[0,1] ; encoding: [0xff,0x40,0x8a,0xd5,0x01,0x01,0x00,0x00]
+v_cvt_f16_f32 v255.h, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_cvt_f16_f32_e64_dpp v255.h, v1 op_sel:[0,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x40,0x8a,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
v_cvt_f16_f32 v255.h, v1 quad_perm:[3,2,1,0]
// GFX11: v_cvt_f16_f32_e64_dpp v255.h, v1 op_sel:[0,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x40,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
index 163010adf7bd4..b1233620fe613 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
@@ -4,7 +4,7 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
-v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo
// W32: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x40]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
index 2695059853b08..471f3f1baa677 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
@@ -4,7 +4,7 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
-v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
// W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
@@ -459,15 +459,15 @@ v_cndmask_b32 v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 boun
// W64: v_cndmask_b32_dpp v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+v_cndmask_b32 v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
// W64: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+v_cndmask_b32 v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
// W64: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+v_cndmask_b32 v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
// W64: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
index b379a5d06b99b..bce9f42ae52bc 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
@@ -4,7 +4,7 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
-v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
+v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
// W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
index dedbcb55d7976..38a7319fd6734 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
@@ -3,11 +3,11 @@
v_fmaak_f32 v0, 0xff32, v0, 0
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
-v_fmaak_f16 v0, 0xff32, v0, 0
+v_fmaak_f16 v0.l, 0xff32, v0.l, 0
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
v_fmamk_f32 v0, 0xff32, 1, v0
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
-v_fmamk_f16 v0, 0xff32, 1, v0
+v_fmamk_f16 v0.l, 0xff32, 1, v0.l
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
index ce452957b0198..14949ed257000 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
@@ -644,13 +644,13 @@ v_ashrrev_i16 v5.l, src_scc, vcc_lo
v_ashrrev_i16 v255.l, 0xfe0b, vcc_hi
// GFX11: v_ashrrev_i16 v255.l, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x3a,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
-v_ashrrev_i16 v5.l, v1.h, v2.l
+v_ashrrev_i16 v5.l, v1.h, v2.l op_sel:[1,0,0]
// GFX11: v_ashrrev_i16 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x3a,0xd7,0x01,0x05,0x02,0x00]
-v_ashrrev_i16 v5.l, v255.l, v255.h
+v_ashrrev_i16 v5.l, v255.l, v255.h op_sel:[0,1,0]
// GFX11: v_ashrrev_i16 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x3a,0xd7,0xff,0xff,0x03,0x00]
-v_ashrrev_i16 v255.h, 0xfe0b, vcc_hi
+v_ashrrev_i16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1]
// GFX11: v_ashrrev_i16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1] ; encoding: [0xff,0x40,0x3a,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
v_ashrrev_i64 v[5:6], v1, vcc
@@ -2732,13 +2732,13 @@ v_lshlrev_b16 v5.l, src_scc, vcc_lo
v_lshlrev_b16 v255.l, 0xfe0b, vcc_hi
// GFX11: v_lshlrev_b16 v255.l, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x38,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
-v_lshlrev_b16 v5.l, v1.h, v2.l
+v_lshlrev_b16 v5.l, v1.h, v2.l op_sel:[1,0,0]
// GFX11: v_lshlrev_b16 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x38,0xd7,0x01,0x05,0x02,0x00]
-v_lshlrev_b16 v5.l, v255.l, v255.h
+v_lshlrev_b16 v5.l, v255.l, v255.h op_sel:[0,1,0]
// GFX11: v_lshlrev_b16 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x38,0xd7,0xff,0xff,0x03,0x00]
-v_lshlrev_b16 v255.h, 0xfe0b, vcc_hi
+v_lshlrev_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1]
// GFX11: v_lshlrev_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1] ; encoding: [0xff,0x40,0x38,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
v_lshlrev_b64 v[5:6], v1, vcc
@@ -2813,13 +2813,13 @@ v_lshrrev_b16 v5.l, src_scc, vcc_lo
v_lshrrev_b16 v255.l, 0xfe0b, vcc_hi
// GFX11: v_lshrrev_b16 v255.l, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x39,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
-v_lshrrev_b16 v5.l, v1.h, v2.l
+v_lshrrev_b16 v5.l, v1.h, v2.l op_sel:[1,0,0]
// GFX11: v_lshrrev_b16 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x39,0xd7,0x01,0x05,0x02,0x00]
-v_lshrrev_b16 v5.l, v255.l, v255.h
+v_lshrrev_b16 v5.l, v255.l, v255.h op_sel:[0,1,0]
// GFX11: v_lshrrev_b16 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x39,0xd7,0xff,0xff,0x03,0x00]
-v_lshrrev_b16 v255.h, 0xfe0b, vcc_hi
+v_lshrrev_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1]
// GFX11: v_lshrrev_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1] ; encoding: [0xf...
[truncated]
|
|
CI error is not related |
Sisyph
reviewed
Apr 28, 2025
| @@ -1114,16 +1114,16 @@ v_lshrrev_b16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 | |||
| v_lshrrev_b16_e64_dpp v255.l, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] fi:0 | |||
| // GFX11: v_lshrrev_b16_e64_dpp v255.l, v255.l, v255.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x00,0x39,0xd7,0xe9,0xfe,0x03,0x00,0xff,0x00,0x00,0x00] | |||
|
|
|||
| v_lshrrev_b16_e64_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] | |||
| v_lshrrev_b16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] | |||
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What is the point of adding op_sel operand all over? We don't have it on every 16 bit instruction instruction either, even after this patch. Probably can just drop all the line changes that just add op_sel.
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The op_sel syntax needed to be added for these tests if I understand correctly. Noted they are not added on all testlines but part of them.
But I removed them from this patch since it might be cleaner to do it seperately
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This is a NFC patch.
Update testlines for true16 mc inst including:
v_min_num_f16
v_max_num_f16
v_cvt_f16_f32
v_cmp_tru_f16
v_cmpx_tru_f16
v_min_num_f16
v_max_num_f16
v_cvt_pknorm_i16_f16
v_med3_f16
The functional change is done, but these are testlines that are not yet up-to-date