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merged 3 commits into from
May 8, 2025
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[AMDGPU][True16][MC] added missing testlines for t16 test #135823

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302f981
clean up of true16 mc changes
broxigarchen Apr 11, 2025
10e85d7
revert some unnecessary change
broxigarchen May 7, 2025
7df22d7
revert opsel change
broxigarchen May 7, 2025
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clean up of true16 mc changes
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@broxigarchen
broxigarchen committed May 7, 2025
commit 302f98102873e77bf1b5959397739d593cc953da
26 changes: 13 additions & 13 deletions llvm/test/MC/AMDGPU/gfx11_asm_vinterp_err.s
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@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 %s 2>&1 | FileCheck %s -check-prefix=GCN-ERR --implicit-check-not=error: --strict-whitespace

//===----------------------------------------------------------------------===//
// VINTERP src operands must be VGPRs.
Expand All @@ -25,20 +25,20 @@ v_interp_p2_f32 v0, v1, 2, v3
v_interp_p2_f32 v0, v1, v2, 3
// GCN-ERR: :[[@LINE-1]]:29: error: invalid operand for instruction

v_interp_p10_f16_f32 v0, s1, v2, v3
v_interp_p10_f16_f32 v0, s1, v2, v3.l
// GCN-ERR: :[[@LINE-1]]:26: error: invalid operand for instruction

v_interp_p10_f16_f32 v0, v1, s2, v3
// GCN-ERR: :[[@LINE-1]]:30: error: invalid operand for instruction
v_interp_p10_f16_f32 v0, v1.l, s2, v3.l
// GCN-ERR: :[[@LINE-1]]:32: error: invalid operand for instruction

v_interp_p10_f16_f32 v0, v1, v2, s3
// GCN-ERR: :[[@LINE-1]]:34: error: invalid operand for instruction
v_interp_p10_f16_f32 v0, v1.l, v2, s3
// GCN-ERR: :[[@LINE-1]]:36: error: invalid operand for instruction

v_interp_p2_f16_f32 v0, 1, v2, v3
// GCN-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
v_interp_p2_f16_f32 v0.l, 1, v2, v3.l
// GCN-ERR: :[[@LINE-1]]:27: error: invalid operand for instruction

v_interp_p2_f16_f32 v0, v1, 2, v3
// GCN-ERR: :[[@LINE-1]]:29: error: invalid operand for instruction

v_interp_p2_f16_f32 v0, v1, v2, 3
v_interp_p2_f16_f32 v0.l, v1.l, 2, v3.l
// GCN-ERR: :[[@LINE-1]]:33: error: invalid operand for instruction

v_interp_p2_f16_f32 v0.l, v1.l, v2, 3
// GCN-ERR: :[[@LINE-1]]:37: error: invalid operand for instruction
5 changes: 4 additions & 1 deletion llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
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Expand Up @@ -2,7 +2,7 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefix=GFX11 %s

v_bfrev_b32_e32 v5, v1
v_bfrev_b32 v5, v1
// GFX11: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e]

v_bfrev_b32 v5, v255
Expand Down Expand Up @@ -464,6 +464,9 @@ v_cvt_f16_f32 v5.h, src_scc
v_cvt_f16_f32 v127.h, 0xaf123456
// GFX11: v_cvt_f16_f32_e32 v127.h, 0xaf123456 ; encoding: [0xff,0x14,0xfe,0x7f,0x56,0x34,0x12,0xaf]

v_cvt_f16_f32 v127.l, 0.5
// GFX11: v_cvt_f16_f32_e32 v127.l, 0.5 ; encoding: [0xf0,0x14,0xfe,0x7e]

v_cvt_f16_i16 v5.l, v1.l
// GFX11: v_cvt_f16_i16_e32 v5.l, v1.l ; encoding: [0x01,0xa3,0x0a,0x7e]

Expand Down
8 changes: 7 additions & 1 deletion llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s

v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0]
v_bfrev_b32 v5, v1 quad_perm:[3,2,1,0]
// GFX11: v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0xff]

v_bfrev_b32 v5, v1 quad_perm:[0,1,2,3]
Expand Down Expand Up @@ -389,6 +389,9 @@ v_cvt_f16_f32 v5.h, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
v_cvt_f16_f32 v127.h, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_cvt_f16_f32_dpp v127.h, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x14,0xfe,0x7f,0xff,0x6f,0x35,0x30]

v_cvt_f16_f32 v127.l, v1 row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: v_cvt_f16_f32_dpp v127.l, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x14,0xfe,0x7e,0x01,0x5f,0x01,0x01]

v_cvt_f16_i16 v5.l, v1.l quad_perm:[3,2,1,0]
// GFX11: v_cvt_f16_i16_dpp v5.l, v1.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0xff]

Expand Down Expand Up @@ -515,6 +518,9 @@ v_cvt_f32_f16 v5, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
v_cvt_f32_f16 v255, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_cvt_f32_f16_dpp v255, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x16,0xfe,0x7f,0xff,0x6f,0x35,0x30]

v_cvt_f32_f16 v5, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: v_cvt_f32_f16_dpp v5, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x16,0x0a,0x7e,0x7f,0x5f,0x01,0x01]

v_cvt_f32_i32 v5, v1 quad_perm:[3,2,1,0]
// GFX11: v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0xff]

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11 %s

v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
v_bfrev_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_bfrev_b32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x70,0x0a,0x7e,0x01,0x77,0x39,0x05]

v_bfrev_b32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
Expand Down
74 changes: 73 additions & 1 deletion llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
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@@ -1,4 +1,4 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --sort --version 5
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize32 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s

Expand Down Expand Up @@ -116,6 +116,24 @@ v_cvt_f16_f32_e32 v128, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
v_cvt_f16_f32_e32 v128, 0xaf123456 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:36: error: invalid operand for instruction

v_cvt_f16_f32_e32 v128.h, 0xaf123456
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v128.h, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v128.h, 0xaf123456 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v128.l, 0xaf123456
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v128.l, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v128.l, 0xaf123456 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255, v1
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode

Expand All @@ -134,6 +152,42 @@ v_cvt_f16_f32_e32 v255, v255 dpp8:[7,6,5,4,3,2,1,0]
v_cvt_f16_f32_e32 v255, v255 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.h, v1.h
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.h, v1.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.h, v255.h
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.h, v255.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.l, v1.l
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.l, v1.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.l, v255.l
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_f32_e32 v255.l, v255.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f16_i16_e32 v128.h, 0xfe0b
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

Expand Down Expand Up @@ -227,6 +281,24 @@ v_cvt_f32_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
v_cvt_f32_f16_e32 v5, v199 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction

v_cvt_f32_f16_e32 v5.h, v199.h
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f32_f16_e32 v5.h, v199.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f32_f16_e32 v5.h, v199.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f32_f16_e32 v5.l, v199.l
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f32_f16_e32 v5.l, v199.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_f32_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

v_cvt_i16_f16_e32 v128.h, 0xfe0b
// GFX11: :[[@LINE-1]]:19: error: invalid operand for instruction

Expand Down
5 changes: 4 additions & 1 deletion llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
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@@ -1,4 +1,4 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --sort --version 5
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s

Expand Down Expand Up @@ -308,6 +308,9 @@ v_cvt_f16_f32 v255.h, ttmp15
v_cvt_f16_f32 v255.h, v1
// GFX11: v_cvt_f16_f32_e64 v255.h, v1 op_sel:[0,1] ; encoding: [0xff,0x40,0x8a,0xd5,0x01,0x01,0x00,0x00]

v_cvt_f16_f32 v255.h, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_cvt_f16_f32_e64_dpp v255.h, v1 op_sel:[0,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x40,0x8a,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]

v_cvt_f16_f32 v255.h, v1 quad_perm:[3,2,1,0]
// GFX11: v_cvt_f16_f32_e64_dpp v255.h, v1 op_sel:[0,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x40,0x8a,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
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Expand Up @@ -4,7 +4,7 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s

v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo
// W32: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x40]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode

Expand Down
8 changes: 4 additions & 4 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s

v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
// W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode

Expand Down Expand Up @@ -459,15 +459,15 @@ v_cndmask_b32 v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 boun
// W64: v_cndmask_b32_dpp v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode

v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
v_cndmask_b32 v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
// W64: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode

v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
v_cndmask_b32 v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
// W64: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode

v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
v_cndmask_b32 v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
// W64: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode

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2 changes: 1 addition & 1 deletion llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
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Expand Up @@ -4,7 +4,7 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s

v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0]
// W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05]
// W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode

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4 changes: 2 additions & 2 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s
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Expand Up @@ -3,11 +3,11 @@
v_fmaak_f32 v0, 0xff32, v0, 0
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed

v_fmaak_f16 v0, 0xff32, v0, 0
v_fmaak_f16 v0.l, 0xff32, v0.l, 0
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed

v_fmamk_f32 v0, 0xff32, 1, v0
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed

v_fmamk_f16 v0, 0xff32, 1, v0
v_fmamk_f16 v0.l, 0xff32, 1, v0.l
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
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