Basic Computer Organization and Design 1

Basic Computer Instructions

Basic Computer Instruction Format

1. Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

2. Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

3. Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

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Basic Computer Organization and Design 2

Basic Computer Instructions

 Only 3 bits are used for operation code

 It may seem computer is restricted to eight different

operations

 however register reference and input output instructions use

remaining 12 bit as part of operation code

 so total number of instruction can exceed 8

Infact total no. of instructions chosen for basic computer is 25

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Basic Computer Organization and Design 3

Basic Computer
Hex Code
Instructions
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
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• In basic computer instruction format, the
opcodes 000 to 110 are reserved for …………..
a) Register Reference Instructions
b) Input Output Instructions
c) Memory Reference Instructions
d) None of the above
Basic Computer Organization and Design 5

Instruction Set Completeness

A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is
known to be computable.

The set of instructions are said to be complete if computer includes a

sufficient number of instruction in each of the following categories :
 Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CMA, CLA
Transfer Instructions
- Data transfers between the main memory and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/output Instructions
- Input and output
- INP, OUT

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Basic Computer Organization and Design 6

Control Unit

 Control unit (CU) of a processor translates from machine

instructions to the control signals for the microoperations
that implement them

 Control units are implemented in one of two ways

Hardwired Control
CU is made up of sequential and combinational circuits to generate
the control signals
Advantage : optimized to provide fast mode of operations
Disadvantage : requires changes in wiring if design has been modified
Microprogrammed Control
A control memory on the processor contains microprograms that
activate the necessary control signals

 We will consider a hardwired implementation of the control

unit for the Basic Computer
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Basic Computer Orgsnization and Design 7

Timing and Control

Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
signals
logic

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

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Basic Computer Orgsnization and Design 8

Timing Signals
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

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• Which of the following counters is used in the
design of Hardwired control unit?
a) 3-bit Sequence Counter
b) 4-bit Sequence Counter
c) 5-bit Sequence Counter
d) 6-bit Sequence Counter
Basic Computer Orgsnization and Design 10

Instruction Cycle

 In Basic Computer, a machine instruction is executed in the

following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect
address
4. Execute the instruction

 After an instruction is executed, the cycle starts again at step

1, for the next instruction

Note: Every different processor has its own (different) instruction cycle

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Basic Computer Organization and Design 11

Fetch and Decode

Initially PC loaded with address of first instruction and Sequence

counter cleared to 0, giving timing signal T0

T0: AR PC

T1: IR  M [AR], PC  PC + 1

T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

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Fetch and Decode

Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0
Memory
unit 7
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus

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Basic Computer Organization and Design 13

Fetch and Decode

 Figure shows how first two statements are implemented in bus system

 At T0 :
 1. Place the content of PC into bus by making S2S1S0=010
 Transfer the content of bus to AR by enabling the LD input of
AR

 At T1 :
 1. Enable read input of memory
 2. Place content of bus by making S2S1S0=111
 3. Transfer content of bus to IR by enabling the LD input of IR
 4. Increment PC by enabling the INR input of PC

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Basic Computer Organization and Design 14

Determine the Type of Instructions

Start
SC <-- 0

T0
AR <-- PC

T1
IR <-- M[AR], PC <-- PC + 1

T2
Decode Opcode in IR(12-14),
AR <-- IR(0-11), I <-- IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR <-- M[AR] Nothing
input-output register-reference
instruction instruction
SC <-- 0 SC <-- 0 Execute T4
memory-reference
instruction
SC <-- 0

Fig : Flow chart for Instruction Cycle

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