Stick Diagrams

UNIT-II
Stick Diagrams

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 Stick Diagrams

Stick Diagrams

N+ N+

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 Stick Diagrams

Stick Diagrams

VDD
VDD
X

X
x Stick x x
x Diagra X
m

Gnd Gnd

3
 Stick Diagrams

Stick Diagrams

VDD
VDD
X

X
x x x
x X

Gnd Gnd

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 Stick Diagrams

Stick Diagrams

 VLSI design aims to translate circuit concepts

onto silicon.
 stick diagrams are a means of capturing
topography and layer information using
simple diagrams.
 Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
 Acts as an interface between symbolic circuit
and the actual layout.
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 Stick Diagrams

Stick Diagrams

 Does show all components/vias.

 It shows relative placement of components.
 Goes one step closer to the layout
 Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

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 Stick Diagrams

Stick Diagrams

 Does not show

• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..

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 Stick Diagrams

Stick Diagrams – Notations

Metal 1

poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.

Similarly for contacts, via, tub etc..

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 Stick Diagrams

Stick Diagrams – Some rules

Rule 1.
When two or more ‘sticks’ of the same type cross
or touch each other that represents electrical
contact.

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 Stick Diagrams

Stick Diagrams – Some rules

Rule 2.
When two or more ‘sticks’ of different type cross
or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).

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 Stick Diagrams

Stick Diagrams – Some rules

Rule 3.
When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor.

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 Stick Diagrams

Stick Diagrams – Some rules

Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have
to be on the other side.

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 Stick Diagrams

How to draw Stick Diagrams

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Stick Diagrams

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Stick Diagrams

Power

A Out

Ground

15
 Introduction to
CMOS VLSI
Design

MOS devices: static and

dynamic behavior
 Outline

 DC Response
 Logic Levels and Noise Margins
 Transient Response
 Delay Estimation
 DC Response

 DC Response: Vout vs. Vin for a gate

 Ex: Inverter
• When Vin = 0 -> Vout = VDD
• When Vin = VDD -> Vout = 0 VDD
• In between, Vout depends on
Idsp
transistor size and current Vin Vout
• By KCL, must settle such that Idsn

Idsn = |Idsp|
• We could solve equations
• But graphical solution gives more insight
 Transistor Operation

 Current depends on region of transistor behavior

 For what Vin and Vout are nMOS and pMOS in
• Cutoff?
• Linear?
• Saturation?
 nMOS Operation

Cutoff Linear Saturated

Vgsn < Vgsn > Vgsn >

Vdsn < Vdsn >

VDD

Idsp
Vin Vout
Idsn
 nMOS Operation

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD

Idsp
Vin Vout
Idsn
 nMOS Operation

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD
Vgsn = Vin
Idsp
Vdsn = Vout Vin Vout
Idsn
 nMOS Operation

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin
Idsp
Vdsn = Vout Vin Vout
Idsn
 pMOS Operation

Cutoff Linear Saturated

Vgsp > Vgsp < Vgsp <

Vdsp > Vdsp <

VDD

Idsp
Vin Vout
Idsn
 pMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD

Idsp
Vin Vout
Idsn

MOS equations Slide 25

 pMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD
Vgsp = Vin - VDD Vtp < 0
Idsp
Vdsp = Vout - VDD Vin Vout
Idsn

MOS equations Slide 26

 pMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0
Idsp
Vdsp = Vout - VDD Vin Vout
Idsn
 I-V Characteristics

 Make pMOS is wider than nMOS such that bn =

bp
V gsn5

Vgsn4
Idsn

Vgsn3
-Vdsp
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5
 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
 Load Line Analysis

 For a given Vin:

• Plot Idsn, Idsp vs. Vout
• Vout must be where |currents| are equal in
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout
 Load Line Analysis

 Vin = 0
Vin0

Idsn, |Idsp|

Vin0
VDD
Vout

MOS equations Slide 31

 Load Line Analysis

 Vin = 0.2VDD

Vin1
Idsn, |Idsp|

Vin1
VDD
Vout
 Load Line Analysis

 Vin = 0.4VDD

Idsn, |Idsp|

Vin2
Vin2

VDD
Vout

MOS equations Slide 33

 Load Line Analysis

 Vin = 0.6VDD

Idsn, |Idsp|

Vin3
Vin3

VDD
Vout
 Load Line Analysis

 Vin = 0.8VDD

Vin4
Idsn, |Idsp|

Vin4
VDD
Vout
 Load Line Analysis

 Vin = VDD
Vin0 Vin5

Vin1
Idsn, |Idsp|

Vin2
Vin3
Vin4
VDD
Vout
 Load Line Summary

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
 DC Transfer Curve

 Transcribe points onto Vin vs. Vout plot

VDD
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3 Vin2 D
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin
 Operating Regions

 Revisit transistor operating regions

Region nMOS pMOS VDD

A B
A Cutoff Linear
Vout
B Saturation Linear C
C Saturation Saturation
D Linear Saturation D
E
0
E Linear Cutoff Vtn VDD/2 VDD+Vtp
VDD
Vin
 Beta Ratio

 If bp / bn  1, switching point will move from

VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
VDD
bp
 10
bn
Vout 2
1
0.5
bp
 0.1
bn

0
VDD
Vin
 Noise Margins

 How much noise can a gate input see before it

does not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND
 Logic Levels

 To maximize noise margins, select logic levels at

Vout

VDD

b p/b n > 1

Vin Vout

Vin
0
VDD
 Logic Levels

 To maximize noise margins, select logic levels at

• unity gain point of DC transfer characteristic
Vout

Unity Gain Points

VDD
Slope = -1
VOH

b p/b n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|
 Transient Response

 DC analysis tells us Vout if Vin is constant

 Transient analysis tells us Vout(t) if Vin(t) changes
• Requires solving differential equations
 Input is usually considered to be a step or ramp
• From 0 to VDD or vice versa
 Inverter Step Response

 Ex: find step response of inverter driving load

capVin (t ) 
Vin(t)
Vout (t  t0 )  Vout(t)
Cload
dVout (t )
 Idsn(t)
dt
 Inverter Step Response

 Ex: find step response of inverter driving load

cap
Vin(t)
Vout(t)
Vin (t )  u(t  t0 )VDD Cload

Idsn(t)
Vout (t  t0 ) 
dVout (t )

dt
 Inverter Step Response

 Ex: find step response of inverter driving load

cap
Vin(t)
Vout(t)
Vin (t )  u(t  t0 )VDD Cload

Vout (t  t0 )  VDD Idsn(t)

dVout (t )

dt
 Inverter Step Response

 Ex: find step response of inverter driving load

cap
Vin(t)
Vout(t)
Vin (t )  u(t  t0 )VDD Cload

Vout (t  t0 )  VDD Idsn(t)

dVout (t ) I dsn (t )

dt Cload
 t  t0

I dsn (t )   Vout  VDD  Vt
  VDD  Vt
 Vout
 Inverter Step Response

 Ex: find step response of inverter driving load

cap
Vin (t )  u(t  t0 )VDD Vin(t)
Vout(t)
Vout (t  t0 )  VDD Cload

Idsn(t)
dVout (t ) I dsn (t )

dt Cload

 0 t  t0

I dsn (t )   b
   Vout  VDD  Vt
2
2 V DD V

 b VDD  Vt  out 2  V (t ) V  V  V
V (t )
 out
  
out DD t
 Inverter Step Response
 Ex: find step response of inverter driving load
cap
Vin (t )  u(t  t0 )VDD Vin(t)
Vout(t)
Cload
Vout (t  t0 )  VDD
Idsn(t)
dVout (t ) I dsn (t )

dt Cload Vin(t)


 0 t  t0 Vout(t)

I dsn (t )   b
   Vout  VDD  Vt
2
2 V DD V t
t0

 b VDD  Vt  out 2  V (t ) V  V  V
V (t )
 out
  
out DD t
 Delay Definitions

 tpdr: rising propagation delay

• From input to rising output crossing VDD/2
 tpdf: falling propagation delay
• From input to falling output crossing VDD/2
 tpd: average propagation delay
• tpd = (tpdr + tpdf)/2
 tr: rise time
• From output crossing 0.2 VDD to 0.8 VDD
 tf: fall time
• From output crossing 0.8 VDD to 0.2 VDD
 Delay Definitions

 tcdr: rising contamination delay

• From input to rising output crossing VDD/2
 tcdf: falling contamination delay
• From input to falling output crossing VDD/2
 tcd: average contamination delay
• tpd = (tcdr + tcdf)/2
 Simulated Inverter Delay
 Solving differential equations by hand is too hard
 SPICE simulator solves the equations
numerically
• Uses more accurate I-V models too!
 But simulations take time to write
2.0

1.5

1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5

0.0

0.0 200p 400p 600p 800p 1n

t(s)
 Delay Estimation
 We would like to be able to easily estimate delay
• Not as accurate as simulation
• But easier to ask “What if?”
 The step response usually looks like a 1st order
RC response with a decaying exponential.
 Use RC delay models to estimate delay
• C = total capacitance on output node
• Use effective resistance R
• So that tpd = RC
 Characterize transistors by finding their effective
R
• Depends on average current as gate switches
 RC Delay Models

 Use equivalent circuits for MOS transistors

• Ideal switch + capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely
d proportional to width
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
 Delay Components

 Delay has two parts

• Parasitic delay
 6 or 7 RC
 Independent of load
• Effort delay
 4h RC
 Proportional to load capacitance
 Diffusion Capacitance

 we assumed contacted diffusion on every s / d.

 Good layout minimizes diffusion area
 Ex: NAND3 layout shares one diffusion contact
• Reduces output capacitance by 2C
• Merged uncontacted diffusion might help too
2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C

3C 3C 3C 3 3C