
- Digital Electronics - Home
- Digital Electronics Basics
- Types of Digital Systems
- Types of Signals
- Logic Levels And Pulse Waveforms
- Digital System Components
- Digital Logic Operations
- Digital Systems Advantages
- Number Systems
- Number Systems
- Binary Numbers Representation
- Binary Arithmetic
- Signed Binary Arithmetic
- Octal Arithmetic
- Hexadecimal Arithmetic
- Complement Arithmetic
- Base Conversions
- Base Conversions
- Binary to Decimal Conversion
- Decimal to Binary Conversion
- Binary to Octal Conversion
- Octal to Binary Conversion
- Octal to Decimal Conversion
- Decimal to Octal Conversion
- Hexadecimal to Binary Conversion
- Binary to Hexadecimal Conversion
- Hexadecimal to Decimal Conversion
- Decimal to Hexadecimal Conversion
- Octal to Hexadecimal Conversion
- Hexadecimal to Octal Conversion
- Binary Codes
- Binary Codes
- 8421 BCD Code
- Excess-3 Code
- Gray Code
- ASCII Codes
- EBCDIC Code
- Code Conversion
- Error Detection & Correction Codes
- Logic Gates
- Logic Gates
- AND Gate
- OR Gate
- NOT Gate
- Universal Gates
- XOR Gate
- XNOR Gate
- CMOS Logic Gate
- OR Gate Using Diode Resistor Logic
- AND Gate vs OR Gate
- Two Level Logic Realization
- Threshold Logic
- Boolean Algebra
- Boolean Algebra
- Laws of Boolean Algebra
- Boolean Functions
- DeMorgan's Theorem
- SOP and POS Form
- POS to Standard POS Form
- Minimization Techniques
- K-Map Minimization
- Three Variable K-Map
- Four Variable K-Map
- Five Variable K-Map
- Six Variable K-Map
- Don't Care Condition
- Quine-McCluskey Method
- Min Terms and Max Terms
- Canonical and Standard Form
- Max Term Representation
- Simplification using Boolean Algebra
- Combinational Logic Circuits
- Digital Combinational Circuits
- Digital Arithmetic Circuits
- Multiplexers
- Multiplexer Design Procedure
- Mux Universal Gate
- 2-Variable Function Using 4:1 Mux
- 3-Variable Function Using 8:1 Mux
- Demultiplexers
- Mux vs Demux
- Parity Bit Generator and Checker
- Comparators
- Encoders
- Keyboard Encoders
- Priority Encoders
- Decoders
- Arithmetic Logic Unit
- 7-Segment LED Display
- Code Converters
- Code Converters
- Binary to Decimal Converter
- Decimal to BCD Converter
- BCD to Decimal Converter
- Binary to Gray Code Converter
- Gray Code to Binary Converter
- BCD to Excess-3 Converter
- Excess-3 to BCD Converter
- Adders
- Half Adders
- Full Adders
- Serial Adders
- Parallel Adders
- Full Adder using Half Adder
- Half Adder vs Full Adder
- Full Adder with NAND Gates
- Half Adder with NAND Gates
- Binary Adder-Subtractor
- Subtractors
- Half Subtractors
- Full Subtractors
- Parallel Subtractors
- Full Subtractor using 2 Half Subtractors
- Half Subtractor using NAND Gates
- Sequential Logic Circuits
- Digital Sequential Circuits
- Clock Signal and Triggering
- Latches
- Shift Registers
- Shift Register Applications
- Binary Registers
- Bidirectional Shift Register
- Counters
- Binary Counters
- Non-binary Counter
- Design of Synchronous Counter
- Synchronous vs Asynchronous Counter
- Finite State Machines
- Algorithmic State Machines
- Flip Flops
- Flip-Flops
- Conversion of Flip-Flops
- D Flip-Flops
- JK Flip-Flops
- T Flip-Flops
- SR Flip-Flops
- Clocked SR Flip-Flop
- Unclocked SR Flip-Flop
- Clocked JK Flip-Flop
- JK to T Flip-Flop
- SR to JK Flip-Flop
- Triggering Methods:Flip-Flop
- Edge-Triggered Flip-Flop
- Master-Slave JK Flip-Flop
- Race-around Condition
- A/D and D/A Converters
- Analog-to-Digital Converter
- Digital-to-Analog Converter
- DAC and ADC ICs
- Realization of Logic Gates
- NOT Gate from NAND Gate
- OR Gate from NAND Gate
- AND Gate from NAND Gate
- NOR Gate from NAND Gate
- XOR Gate from NAND Gate
- XNOR Gate from NAND Gate
- NOT Gate from NOR Gate
- OR Gate from NOR Gate
- AND Gate from NOR Gate
- NAND Gate from NOR Gate
- XOR Gate from NOR Gate
- XNOR Gate from NOR Gate
- NAND/NOR Gate using CMOS
- Full Subtractor using NAND Gate
- AND Gate Using 2:1 MUX
- OR Gate Using 2:1 MUX
- NOT Gate Using 2:1 MUX
- Memory Devices
- Memory Devices
- RAM and ROM
- Cache Memory Design
- Programmable Logic Devices
- Programmable Logic Devices
- Programmable Logic Array
- Programmable Array Logic
- Field Programmable Gate Arrays
- Digital Electronics Families
- Digital Electronics Families
- CPU Architecture
- CPU Architecture
Three Variable Function using 8:1 Multiplexer
Let's start this chapter with a basic introduction of 8:1 multiplexer before moving on to cover how a three variable logic function can be implemented using an 8:1 multiplexer.
Introduction to 8:1 Multiplexer
A multiplexer (or MUX) is a digital logic circuit that accepts multiple data inputs and allows only one of them at a time to pass through the output line. Hence, multiplexer is also known as data selector. In other words, a multiplexer is a digital circuit which
Based on the number of input data lines, there are several types of multiplexers. But, this article is meant for explaining the implementation of a logic function in three variables using an 8:1 multiplexer. So, let us discuss the basics of 8:1 multiplexer only.
A 8:1 multiplexer is one which has eight input data lines, i.e., I0, I1, I2,I7, three select lines, i.e. S0, S1, and S2, and one output line Y. The block diagram of the 8:1 mux is shown in Figure 1.

The logic level applied to the three select lines decides which data input passes through the output channel of the multiplexer. The operation of the 8:1 multiplexer can be understood with the help of its truth table which is given below.
Select Lines | Output | ||
---|---|---|---|
S2 | S1 | S0 | Y |
0 | 0 | 0 | I0 |
0 | 0 | 1 | I1 |
0 | 1 | 0 | I2 |
0 | 1 | 1 | I3 |
1 | 0 | 0 | I4 |
1 | 0 | 1 | I5 |
1 | 1 | 0 | I6 |
1 | 1 | 1 | I7 |
Now, let us discuss the realization of a three-variable logic function using an 8:1 multiplexer with the help of an example.
Example
Implement the following logical function using an 8:1 multiplexer.
$$\mathrm{F \lgroup A,B,C \rgroup \: = \: \sum m \lgroup 0,1,2,5,7 \rgroup }$$
Solution
The truth table of the 8:1 multiplexer for the given logic function is as follows −
Select Lines | Output | ||
---|---|---|---|
S2 | S1 | S0 | Y |
0 | 0 | 0 | 1 |
0 | 0 | 1 | 1 |
0 | 1 | 0 | 1 |
0 | 1 | 1 | 0 |
1 | 0 | 0 | 0 |
1 | 0 | 1 | 1 |
1 | 1 | 0 | 0 |
1 | 1 | 1 | 1 |
Using this truth table, we can draw the logic block diagram to realize the function F using an 8:1 MUX which is shown in Figure 2.

Here, the inputs A, B, and C are applied to the select lines S2, S1, and S0 respectively. From the truth table, it is clear that the function F = 1, when ABC = 000, 001, 010, 101, 111. Thus, we connect logic 1 to the data input lines I0, I1, I2, I5, and I7, and the logic 0 is connected to all other data input lines, i.e. I3, I4, and I6.
Conclusion
In this way, we can easily implement a given 3-variable Boolean function using an 8:1 multiplexer. To excel in the implementation of a three-variable Boolean using 8:1 MUX, try to solve the following tutorial problems.
Solving Problems
Q1. − Implement the following Boolean function using 8-to-1 MUX.
$$\mathrm{F\lgroup X,Y,Z \rgroup \: = \: \sum m \lgroup 0,2,5,7 \rgroup}$$
Q2. − Implement the following three variable logic function using an 8:1 multiplexer.
$$\mathrm{F \lgroup A,B,C \rgroup \: = \: \sum m \lgroup 0,1,3,4,6 \rgroup}$$