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CO Lab9 Task

This document contains Verilog code for designing a computer data path including an ALU, shifter, register file, and function unit. It first defines logic gate primitives like AND, OR, and MUX. It then shows code for a 4-bit ALU, shifter, and function unit combining the two. Testbench code is provided to simulate the function unit. Finally, code is given to design the register file using D flip-flops and a decoder, and to combine it with the function unit.

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Babar Rasheed
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43 views

CO Lab9 Task

This document contains Verilog code for designing a computer data path including an ALU, shifter, register file, and function unit. It first defines logic gate primitives like AND, OR, and MUX. It then shows code for a 4-bit ALU, shifter, and function unit combining the two. Testbench code is provided to simulate the function unit. Finally, code is given to design the register file using D flip-flops and a decoder, and to combine it with the function unit.

Uploaded by

Babar Rasheed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 17

Date: 31-05-2013

UNIVERSITY OF ENGINEERING
AND TECHNOLOGY, TAXILA

DEPARTMENT OF ELECTRICAL ENGINEERING

TITLE: Simple Computer Data Path


LAB:

GROUP:

B2

SUBJECT: Computer Organization


SUBMITTED TO: Sir Tahir Muhammad
SUBMITTED BY: Ameer Hamza
REGISTRATION NUMBER:

2011-EE-197

31-05-2013

Lab-09

TASK: 1
A) Write Gate Level Code For The Given Diagram

/*Subject: Computer Organization


Name: Ameer Hamza
Registration Number: 2011-EE-197
Group: B2
Lab Number: 9
Description: Gate level code for Shifter*/
/*__________4x1 MUX__________*/
module MUX_4x1(Q,D0,D1,D2,D3,S);//Define 4x1 Mux
output Q;//Declare I/O ports
input D0,D1,D2,D3;input [1:0]S;
wire W0,W1,W2,W3;//Declare internal nets
and X0(W0,D0,~S[1],~S[0]);//Instantiate logic gate primitives
and X1(W1,D1,~S[1],S[0]);
and X2(W2,D2,S[1],~S[0]);
and X3(W3,D3,S[1],S[0]);
or X4(Q,W0,W1,W2,W3);
endmodule
/*__________SHIFTER__________*/
module SHIFTER(H,B,IR,IL,S);//Define Shifter module

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output [3:0]H;//Declare I/O ports


input [3:0]B;input [1:0]S;input IR,IL;
MUX_4x1 X0(H[0],B[0],B[1],IL,D3,S);//Instantiate 4x1 Mux four times
MUX_4x1 X1(H[1],B[1],B[2],B[0],D3,S);
MUX_4x1 X2(H[2],B[2],B[3],B[1],D3,S);
MUX_4x1 X3(H[3],B[3],IR,B[2],D3,S);
endmodule
B) Combine ALU & Shifter Into Function Unit
/*Subject: Computer Organization
Name: Ameer Hamza
Registration Number: 2011-EE-197
Group: B2
Lab Number: 9
Description: Designing Function Unit*/
/*__________HALF ADDER__________*/
module HA(s,c,a,b);//Define half adder
output s,c;//Declare I/O ports
input a,b;
xor X0(s,a,b);//Instantiate logic gate primitives
and X1(c,a,b);
endmodule
/*__________FULL ADDER__________*/
module FA(s,c,a,b,cin);//Define full adder
output s,c;//Declare I/O ports
input a,b,cin;
wire w1,w2,w3;//Internal wires declaration
HA X0(w1,w2,a,b);//Instantiate two half adders
HA X1(s,w3,w1,cin);
or X2(c,w3,w2);//Instantiate OR gate

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endmodule
/*__________4-BIT ADDER__________*/
module FBA(s,c,a,b,cin,v);//Define 4-bit adder
output [3:0]s;output c,v;//Declare I/O ports
input [3:0]a,b;input cin;
wire c1,c2,c3;//Declare internal nets
FA X0(s[0],c1,a[0],b[0],cin);//Instantiate four 1-bit full adders
FA X1(s[1],c2,a[1],b[1],c1);
FA X2(s[2],c3,a[2],b[2],c2);
FA X3(s[3],c,a[3],b[3],c3);
xor X4(v,c,c3);
endmodule
/*__________ARITHMETIC UNIT__________*/
module AU(G,c,x,y,S,cin,ov);//Define module for arithmetic unit
output [3:0]G;output c,ov;//Declare I/O ports
input [3:0]x,y;input [2:1]S;input cin;
wire [11:0]w;wire [3:0]v;//Declare internal nets
not X0(w[0],y[3]);//Instantiate logic gate primitives
not X1(w[1],y[2]);
not X2(w[2],y[1]);
not X3(w[3],y[0]);
and X4(w[4],y[3],S[1]);
and X5(w[5],w[0],S[2]);
and X6(w[6],y[2],S[1]);
and X7(w[7],w[1],S[2]);
and X8(w[8],y[1],S[1]);
and X9(w[9],w[2],S[2]);
and X10(w[10],y[0],S[1]);
and X11(w[11],w[3],S[2]);

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or X12(v[3],w[4],w[5]);
or X13(v[2],w[6],w[7]);
or X14(v[1],w[8],w[9]);
or X15(v[0],w[10],w[11]);
FBA X16(G,c,x,v,cin,ov);//Instantiate 4-bit full adder
endmodule
/*__________LOGIC UNIT__________*/
module LU(g,s,x,y);//Define module for logic unit
output g;//Declare I/O ports
input x,y;input [1:0]s;
not X0(w0,x);//Instantiate logic gate primitives
xor X1(w1,x,y);
or X2(w2,x,y);
and X3(w3,x,y);
MUX_4x1 X5(g,w3,w2,w1,w0,s);//Instantiate 4x1 Mux
endmodule
/*__________4-BIT LOGIC UNIT__________*/
module LU_4b(g,s,x,y);//Define module for 4-bit logic circuit
output [3:0]g;//Declare I/O ports
input [3:0]x,y;input [1:0]s;
LU X0(g[0],s,x[0],y[0]);//Instantiate four 1-bit logic circuits
LU X1(g[1],s,x[1],y[1]);
LU X2(g[2],s,x[2],y[2]);
LU X3(g[3],s,x[3],y[3]);
endmodule
/*__________ALU (COMBINING AU & LU)__________*/
module ALU(G,C,X,Y,S,V);//Define ALU module
output [3:0]G;output C,V;//Declare I/O ports
input [3:0]X,Y,S;

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wire [3:0]W0,W1;//Declare internal nets


AU X0(W0,C,X,Y,S[2:1],S[0],V);//Instantiate Arithmetic Circuit
LU_4b X1(W1,S[1:0],X,Y);//Instantiate 4-Bit Logic Circuit
Q_MUX_2x1 X2(G,S[3],W0,W1);//Instantiate Quad 2x1 Mux
endmodule
/*__________SHIFTER__________*/
module SHIFTER(H,B,IR,IL,S);//Define module for Shifter
output [3:0]H;//Declare I/O ports
input [3:0]B;input [1:0]S;input IR,IL;
MUX_4x1 X0(H[0],B[0],B[1],IL,D3,S);//Instantiate 4x1 Mux four times
MUX_4x1 X1(H[1],B[1],B[2],B[0],D3,S);
MUX_4x1 X2(H[2],B[2],B[3],B[1],D3,S);
MUX_4x1 X3(H[3],B[3],IR,B[2],D3,S);
endmodule
/*__________FUNCTION UNIT (COMBINING ALU & SHIFTER)__________*/
module FU(F,A,B,FS,V,C,N,Z);//Define module for Function Unit
output [3:0]F;output C,N,Z,V;//Declare I/O ports
input [3:0]A,B,FS;
wire [3:0]G,H;wire MF;//Declare internal nets
ALU X0(G,C,A,B,FS,V);//Instantiate ALU
SHIFTER X1(H,B,1'b0,1'b0,FS[1:0]);//Instantiate Shifter
Q_MUX_2x1 X2(F,MF,G,H);//Instantiate Quad 2x1 Mux
and X3(MF,FS[3],FS[2]);//Instantiate AND gate
buf X4(N,FS[3]);//Connecting wire Or assigning FS[3] to N
and X5(Z,~F[0],~F[1],~F[2],~F[3]);//Instantiate AND gate
endmodule
C) Test Bench To Verify The Function Unit
/*Subject: Computer Organization
Name: Ameer Hamza

2011-EE-197

31-05-2013

Lab-09

Registration Number: 2011-EE-197


Group: B2
Lab Number: 9
Description: Test bench for Function Unit*/
/*__________TESTBENCH__________*/
module TEST();//Define stimulus/test module
reg [3:0]A,B,FS;//Declare input varibales
wire [3:0]F;wire V,C,N,Z;//Declare output variables
FU X0(F,A,B,FS,V,C,N,Z);//Instantiate Function Unit
initial
begin
A=4'd7;B=4'd5;FS=4'd0;//Stimulating inputs
repeat(14)
#5 FS=FS+1'b1;
end
endmodule
Wave:

TASK: 2
A) Combine Register File & Function Unit
/*Subject: Computer Organization
Name: Ameer Hamza
Registration Number: 2011-EE-197
Group: B2
Lab Number: 9

2011-EE-197

31-05-2013

Lab-09

Description: Combining Register File & Function Unit*/


/*__________2x1 MUX__________*/
module MUX_2x1(Q,S,D0,D1);//Define module for 2x1 Mux
output Q;//Declare I/O ports
input S,D0,D1;
not X0(S0,S);//Instantiate logic gate primitives
and X1(W0,S0,D0);
and X2(W1,S,D1);
or X3(Q,W0,W1);
endmodule
/*__________QUAD 2x1 MUX__________*/
module Q_MUX_2x1(Q,S,D0,D1);//Define module for 2x1 Quad Mux
output [3:0]Q;//Declare I/O ports
input [3:0]D0,D1;input S;
MUX_2x1 X0(Q[0],S,D0[0],D1[0]);//Instantiate 2x1 Mux four times
MUX_2x1 X1(Q[1],S,D0[1],D1[1]);
MUX_2x1 X2(Q[2],S,D0[2],D1[2]);
MUX_2x1 X3(Q[3],S,D0[3],D1[3]);
endmodule
/*__________4x1 MUX__________*/
module MUX_4x1(Q,I0,I1,I2,I3,S);//Define module for 4x1 Mux
output Q;//Declare I/O ports
input I0,I1,I2,I3;input [1:0]S;
wire [3:0]W;//Declare internal nets
and X0(W[0],I0,~S[0],~S[1]);//Instantiate logic gate primitives
and X1(W[1],I1,S[0],~S[1]);
and X2(W[2],I2,~S[0],S[1]);
and X3(W[3],I3,S[0],S[1]);
or X4(Q,W[0],W[1],W[2],W[3]);

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endmodule
/*__________QUAD 4x1 MUX__________*/
module Q_MUX_4x1(Q,I0,I1,I2,I3,S);//Define module for 4x1 Quad Mux
output [3:0]Q;//Declare I/O ports
input [3:0]I0,I1,I2,I3;input [1:0]S;
MUX_4x1 X0(Q[0],I0[0],I1[0],I2[0],I3[0],S);//Instantiate 4x1 Mux four times
MUX_4x1 X1(Q[1],I0[1],I1[1],I2[1],I3[1],S);
MUX_4x1 X2(Q[2],I0[2],I1[2],I2[2],I3[2],S);
MUX_4x1 X3(Q[3],I0[3],I1[3],I2[3],I3[3],S);
endmodule
/*__________2x4 DECODER__________*/
module DEC_2x4(D,I);//Define module for 2x4 Decoder
output [3:0]D;//Declare I/O ports
input [1:0]I;
and X0(D[0],~I[0],~I[1]);//Instantiate logic gate primitives
and X1(D[1],I[0],~I[1]);
and X2(D[2],~I[0],I[1]);
and X3(D[3],I[0],I[1]);
endmodule
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||||
||||||||||DESIGNING THE REGISTER FILE||||||||||
||||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/*__________D-FLIP FLOP DESIGN__________*/
/*Using Behavorial Modeling for D-Flip Flop Design*/
module DFF(OUT,IN,RST,CLK);
parameter n=4;
output [n-1:0]OUT;
input [n-1:0]IN;
input RST;

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input CLK;
reg [n-1:0]OUT;
always @(posedge CLK)
begin
if (RST)
OUT=0;
else
OUT=IN;
end
endmodule
/*__________REGISTER__________*/
module REG(A,IN,LD,CLK,RST);//Define module for register
output [3:0]A;//Declare I/O ports
input [3:0]IN;input LD,CLK,RST;
wire [3:0]W;//Declare internal nets
Q_MUX_2x1 X0(W,LD,A,IN);//Instantiate 2x1 Quad Mux
DFF X1(A,W,RST,CLK);//Instantiate D-Flip Flop
endmodule
/*__________REGISTER HIERARCHY__________*/
module REG_HIER(R0_OUT,R1_OUT,R2_OUT,R3_OUT,DATA,LD,CLK,RST);//Define module
for registers hierarchy
output [3:0]R0_OUT,R1_OUT,R2_OUT,R3_OUT;//Declare I/O ports
input [3:0]DATA,LD;input CLK,RST;
REG X0(R0_OUT,DATA,LD[0],CLK,RST);//Instantiate register four times
REG X1(R1_OUT,DATA,LD[1],CLK,RST);
REG X2(R2_OUT,DATA,LD[2],CLK,RST);
REG X3(R3_OUT,DATA,LD[3],CLK,RST);
endmodule
/*__________REGISTER FILE__________*/
//Define module for Register File

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module REG_FILE(A_DATA,B_DATA,AS,BS,DS,LD_EN,D_DATA,CLK,RST);
output [3:0]A_DATA,B_DATA;//Declare I/O ports
input [1:0]AS,BS,DS;input LD_EN,CLK,RST;input [3:0]D_DATA;
wire [3:0]DEC_OUT,LOAD,R0_OUT,R1_OUT,R2_OUT,R3_OUT;//Declare internal nets
DEC_2x4 X0(DEC_OUT,DS);//Instantiate 2x4 Decoder
and X1(LOAD[0],LD_EN,DEC_OUT[0]);//Instantiate logic gate primitives
and X2(LOAD[1],LD_EN,DEC_OUT[1]);
and X3(LOAD[2],LD_EN,DEC_OUT[2]);
and X4(LOAD[3],LD_EN,DEC_OUT[3]);
//Instantiate register hierarchy
REG_HIER X5(R0_OUT,R1_OUT,R2_OUT,R3_OUT,D_DATA,LOAD,CLK,RST);
//Instantiate 4x1 Quad Mux
Q_MUX_4x1 X6(A_DATA,R0_OUT,R1_OUT,R2_OUT,R3_OUT,AS);
Q_MUX_4x1 X7(B_DATA,R0_OUT,R1_OUT,R2_OUT,R3_OUT,BS);
endmodule
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||||
||||||||||DESIGNING THE FUNCTION UNIT|||||||||
||||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/*__________HALF ADDER__________*/
module HA(s,c,a,b);//Define half adder
output s,c;//Declare I/O ports
input a,b;
xor X0(s,a,b);//Instantiate logic gate primitives
and X1(c,a,b);
endmodule
/*__________FULL ADDER__________*/
module FA(s,c,a,b,cin);//Define full adder
output s,c;//Declare I/O ports
input a,b,cin;

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wire w1,w2,w3;//Internal wires declaration


HA X0(w1,w2,a,b);//Instantiate two half adders
HA X1(s,w3,w1,cin);
or X2(c,w3,w2);//Instantiate OR gate
endmodule
/*__________4-BIT ADDER__________*/
module FBA(s,c,a,b,cin,v);//Define 4-bit adder
output [3:0]s;output c,v;//Declare I/O ports
input [3:0]a,b;input cin;
wire c1,c2,c3;//Declare internal nets
FA X0(s[0],c1,a[0],b[0],cin);//Instantiate four 1-bit full adders
FA X1(s[1],c2,a[1],b[1],c1);
FA X2(s[2],c3,a[2],b[2],c2);
FA X3(s[3],c,a[3],b[3],c3);
xor X4(v,c,c3);
endmodule
/*__________ARITHMETIC UNIT__________*/
module AU(G,c,x,y,S,cin,ov);//Define module for arithmetic unit
output [3:0]G;output c,ov;//Declare I/O ports
input [3:0]x,y;input [2:1]S;input cin;
wire [11:0]w;wire [3:0]v;//Declare internal nets
not X0(w[0],y[3]);//Instantiate logic gate primitives
not X1(w[1],y[2]);
not X2(w[2],y[1]);
not X3(w[3],y[0]);
and X4(w[4],y[3],S[1]);
and X5(w[5],w[0],S[2]);
and X6(w[6],y[2],S[1]);
and X7(w[7],w[1],S[2]);

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and X8(w[8],y[1],S[1]);
and X9(w[9],w[2],S[2]);
and X10(w[10],y[0],S[1]);
and X11(w[11],w[3],S[2]);
or X12(v[3],w[4],w[5]);
or X13(v[2],w[6],w[7]);
or X14(v[1],w[8],w[9]);
or X15(v[0],w[10],w[11]);
FBA X16(G,c,x,v,cin,ov);//Instantiate 4-bit full adder
endmodule
/*__________LOGIC UNIT__________*/
module LU(g,s,x,y);//Define module for logic unit
output g;//Declare I/O ports
input x,y;input [1:0]s;
not X0(w0,x);//Instantiate logic gate primitives
xor X1(w1,x,y);
or X2(w2,x,y);
and X3(w3,x,y);
MUX_4x1 X5(g,w3,w2,w1,w0,s);//Instantiate 4x1 Mux
endmodule
/*__________4-BIT LOGIC UNIT__________*/
module LU_4b(g,s,x,y);//Define module for 4-bit logic circuit
output [3:0]g;//Declare I/O ports
input [3:0]x,y;input [1:0]s;
LU X0(g[0],s,x[0],y[0]);//Instantiate four 1-bit logic circuits
LU X1(g[1],s,x[1],y[1]);
LU X2(g[2],s,x[2],y[2]);
LU X3(g[3],s,x[3],y[3]);
endmodule

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/*__________ALU (COMBINING AU & LU)__________*/


module ALU(G,C,X,Y,S,V);//Define ALU module
output [3:0]G;output C,V;//Declare I/O ports
input [3:0]X,Y,S;
wire [3:0]W0,W1;//Declare internal nets
AU X0(W0,C,X,Y,S[2:1],S[0],V);//Instantiate Arithmetic Circuit
LU_4b X1(W1,S[1:0],X,Y);//Instantiate 4-Bit Logic Circuit
Q_MUX_2x1 X2(G,S[3],W0,W1);//Instantiate Quad 2x1 Mux
endmodule
/*__________SHIFTER__________*/
module SHIFTER(H,B,IR,IL,S);//Define module for Shifter
output [3:0]H;//Declare I/O ports
input [3:0]B;input [1:0]S;input IR,IL;
MUX_4x1 X0(H[0],B[0],B[1],IL,D3,S);//Instantiate 4x1 Mux four times
MUX_4x1 X1(H[1],B[1],B[2],B[0],D3,S);
MUX_4x1 X2(H[2],B[2],B[3],B[1],D3,S);
MUX_4x1 X3(H[3],B[3],IR,B[2],D3,S);
endmodule
/*__________FUNCTION UNIT (COMBINING ALU & SHIFTER)__________*/
module FU(F,A,B,FS,V,C,N,Z);//Define module for Function Unit
output [3:0]F;output C,N,Z,V;//Declare I/O ports
input [3:0]A,B,FS;
wire [3:0]G,H;wire MF;//Declare internal nets
ALU X0(G,C,A,B,FS,V);//Instantiate ALU
SHIFTER X1(H,B,1'b0,1'b0,FS[1:0]);//Instantiate Shifter
Q_MUX_2x1 X2(F,MF,G,H);//Instantiate Quad 2x1 Mux
and X3(MF,FS[3],FS[2]);//Instantiate AND gate
buf X4(N,FS[3]);//Connecting wire Or assigning FS[3] to N [Signed Number]

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and X5(Z,~F[0],~F[1],~F[2],~F[3]);//Instantiate AND gate [Zero Select]


endmodule
/*||||||||||||||||||||||||||||||||||||||||||||||||||||||
||||||||||SIMPLE COMPUTER DATA PATH|||||||||
||||||||||||||||||||||||||||||||||||||||||||||||||||||*/
/*__________SIMPLE COMPUTER DATA PATH__________*/
//Define module for Simple Computer Data Path
module SCD(ADD_OUT,DATA_OUT,C,V,N,Z,DATA_IN,CONST_IN,CW,CLK,RST);
output [3:0]ADD_OUT,DATA_OUT;output C,V,N,Z;//Declare I/O ports
input [3:0]DATA_IN,CONST_IN;input [12:0]CW;input CLK,RST;
wire [3:0]A_DATA,B_DATA,D_DATA,F;//Declare internal nets
//Instantiate Register File
REG_FILE X0(A_DATA,B_DATA,CW[10:9],CW[8:7],CW[12:11],CW[0],D_DATA,CLK,RST);
Q_MUX_2x1 X1(DATA_OUT,CW[6],B_DATA,CONST_IN);//Instantiate Quad 2x1 Mux
FU X2(F,A_DATA,DATA_OUT,CW[5:2],V,C,N,Z);//Instantiate Function Unit
Q_MUX_2x1 X3(D_DATA,CW[1],F,DATA_IN);//Instantiate Quad 2x1 Mux
buf X4(ADD_OUT[0],A_DATA[0]);//Connecting the Address Out terminal
buf X5(ADD_OUT[1],A_DATA[1]);
buf X6(ADD_OUT[2],A_DATA[2]);
buf X7(ADD_OUT[3],A_DATA[3]);
endmodule
B) Test Bench To Verify The Data Path Of Simple Computer
/*Subject: Computer Organization
Name: Ameer Hamza
Registration Number: 2011-EE-197
Group: B2
Lab Number: 9
Description: Test bench for SC Data Path*/
/*__________TESTBENCH__________*/

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module TEST();//Define stimulus/test module


reg [3:0]DATA_IN,CONST_IN;reg [12:0]CW;reg CLK,RST;//Declare input variables
wire [3:0]ADD_OUT,DATA_OUT;wire C,V,N,Z;//Declare output variables
// Instantiate Simple Computer Data Path
SCD X0(ADD_OUT,DATA_OUT,C,V,N,Z,DATA_IN,CONST_IN,CW,CLK,RST);
always #5 CLK=~CLK;//Use always block for clock
initial
begin
//>>>>>Loading All Registers With '7' & Starting Clock At '0'<<<<<
CLK=0;DATA_IN=4'd7;CONST_IN=4'd0;RST=0;CW=13'b0000000000011;
#10 CW=13'b0101010000011;
#10 CW=13'b1010100000011;
#10 CW=13'b1111110000011;
/*My Registration Number Is [2011-EE-197], So
Reg4-Reg3
Reg5-Reg0
Reg6-Reg1
Reg7-Reg2*/
//>>>>>Perform The Given Micro-Operations<<<<<
#10 CW=13'b0110110010101;//R1<R2-R3
#10 CW=13'b1100010111001;//R3<slR1
#10 CW=13'b1010100000101;//R2<R2+1
#10 CW=13'b0100100010101;//R1<R0-R2
#10 CW=13'b0000110000000;//DATA_OUT<R3
#10 CW=13'b1100000000011;DATA_IN=4'd5;//R3<DATA_IN
#10 CW=13'b0011110101001;//R0<0
end
endmodule

31-05-2013
Wave:

Lab-09

2011-EE-197

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