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Reg - No: S. Veerasamy Chettiar College of Engineering and Technology

This document appears to be an exam for a Digital Logic Circuits course, containing: - Details about the course such as subject code, year, date and time of exam. - Questions divided into two parts - Part A contains 5 short answer questions about digital logic concepts. Part B contains 3 longer answer questions involving designing digital circuits like converters using K-maps or multiplexers. - The questions require students to define terms, design circuits, minimize logic expressions and compare digital IC logic families.

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krishnandrk
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20 views

Reg - No: S. Veerasamy Chettiar College of Engineering and Technology

This document appears to be an exam for a Digital Logic Circuits course, containing: - Details about the course such as subject code, year, date and time of exam. - Questions divided into two parts - Part A contains 5 short answer questions about digital logic concepts. Part B contains 3 longer answer questions involving designing digital circuits like converters using K-maps or multiplexers. - The questions require students to define terms, design circuits, minimize logic expressions and compare digital IC logic families.

Uploaded by

krishnandrk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Reg.

No:
S. VEERASAMY CHETTIAR COLLEGE OF ENGINEERING AND TECHNOLOGY
College Road, S.V.C Nagar, Puliyangudi- 627 855
Department of Electrical and Electronics Engineering
Academic Year 2015-2016(ODD Semester)
Internal Test-I
Subject Code/Title
: EE6301/ Digital Logic Circuits
Year/Semester
: II /III
Name of the Faculty/Dept : M.K.Anandkumar /EEE

Date: 22/08/15
Time: 9.00 AM to10.30AM
Maximum Marks: 50

(Answer ALL the Questions)


PART-A (5*2=10)

1.
2.
3.
4.
5.

Define minterm and maxterm?


What is a logic gate?
Prove A+AB = A.
Define combinational logic.
What are error detecting codes?
PART-B (8+16+16=40)

6. a) Explain about the different types of logic gates.

(8)

OR
b) Design Half Subtractor and half adder and implement its logic gates.

(8)

7. a) Design a BCD to EXCESS 3 Code converter.

(16)

OR
b) Implement the following Boolean function

(16)

8. a) i) Implement the following Boolean expression using a suitable multiplexer


F(A,B,C,D) = (0,1,3,4,8,9,15)
ii) Implement the following Boolean function using 8:1 MUX
F(A,B,C,D) = ABD+ACD+BCD+ACD
OR
b) Design Half Subtractor and half adder and implement its logic gates

Staff in-charge
Reg.No:

(08)
(08)
(16)

HOD/EEE

S. VEERASAMY CHETTIAR COLLEGE OF ENGINEERING AND TECHNOLOGY


College Road, S.V.C Nagar, Puliyangudi- 627 855
Department of Electrical and Electronics Engineering
Academic Year 2015-2016(ODD Semester)
Internal Test-I
Subject Code/Title
: EE6301/ Digital Logic Circuits
Year/Semester
: II /III
Name of the Faculty/Dept : M.K.Anandkumar /EEE

Date: 22/08/15
Time: 9.00 AM to10.30AM
Maximum Marks: 50

(Answer ALL the Questions)


PART-A (5*2=10)

1. What is a karnaugh map?


2.
3.
4.
5.

What is binary encoder?


List the applications of decoder..
Define Boolean algebra.
Define Decoder.
PART-B (8+16+16=40)

6. a) Minimize the following expressions using K-map


i) Y(A,B,C) = m(1,3,5,7)
ii)Y(A,B,C) = m(0,1,4,5)
iii)Y(A,B,C) = m(0,2,4,6)
OR
b)Reduce the following using Karnaugh map technique:
F(W,X,Y,Z) = m(0,7,8,9,10,12)+d(2,5,13)

(8)

7. a) Design a 4 bit binary to gray code converter and implement it using logic gates. (16)
OR
b) i) Express the function Y=A+B.C in canonical SOP and POS form
ii) Comparison of Digital Ic Logic Families

(8)
(8)

8. a) i) Design a Binary to gray code


ii) Design a Excess 3 to binary code

(8)
(8)

(2)
(3)
(3)

OR
b) Explain the basic principles of TTL and ECL logic families.

Staff in-charge

(16)

HOD/EEE

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