Hardware Description

Language
VHDL and Verilog
Design process
Cont. …
World of Integrated Circuits
 2 competing implementation approaches
• ASIC Application Specific • FPGA Field Programmable Gate
Integrated Circuit Array
• designs must be sent for expensive • designs must be sent for
and time consuming fabrication in expensive and time consuming
semiconductor company fabrication in semiconductor
• designed all the way from company
behavioral description to physical • designed all the way from
layout behavioral description to physical
layout
Which Way to Go?
Introduction
• A hardware description language (HDL) is a computer-based language that
describes the hardware of digital systems in a textual form.
• It resembles an ordinary computer programming language, such as C, but is
specifically oriented to describing hardware structures and the behavior of
logic circuits.
• It can be used to represent logic diagrams, truth tables, Boolean
expressions, and complex abstractions of the behavior of a digital system.
• Design entry creates an HDL-based description of the functionality that is
to be implemented in hardware.
• Depending on the HDL, the description can be in a variety of forms:
Boolean logic equations, truth tables, a netlist of interconnected gates, or
an abstract behavioral model.
 Introduction to VHDL
• In the public domain, there are two standard HDLs that are supported by
the IEEE: VHDL and Verilog.
• In VHDL an entity is used to describe a hardware module. An entity can be
described using,
• Entity declaration
• Architecture
• Configuration
• Package declaration
• Package body
 VHDL: Entity Declaration
• It defines the names, input output signals and modes of a hardware
module.
entity entity_name is
• Syntax : Port declaration;
end entity_name;

An entity declaration should start with ‘entity’ and end with ‘end’
keywords. The direction will be input, output or inout.
In Port can be read
Out Port can be written
Inou
Port can be read and written
t
Buff Port can be read and written, it can have
er only one source.
 VHDL: Architecture
• Architecture can be described using structural, dataflow, behavioral or
mixed style.
architecture architecture_name of entity_name
architecture_declarative_part;
begin
Statements;
end architecture_name;
• Here, we should specify the entity name for which we are writing the architecture body.
• The architecture statements should be inside the ‘begin’ and ‘énd’ keyword.
• Architecture declarative part may contain variables, constants, or component
declaration
VHDL: code examples
• Logic Operation – AND GATE
VHDL: code examples
• Logic Operation – OR Gate
VHDL: code examples
• Logic Operation – NOT Gate
VHDL: code examples
• Logic Operation – NAND Gate
VHDL: code examples
• Logic Operation – XOR Gate
VHDL: code examples
• Logic Operation – X-NOR Gate
VHDL: code examples
• VHDL Code for a Half-Adder
VHDL: code examples
• VHDL Code for a Multiplexer
Verilog Introduction
• Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL).
• It is a language used for describing a digital system like a network
switch or a microprocessor or a memory or a flip−flop.
• It means, by using a HDL we can describe any digital hardware at any
level.
• Designs, which are described in HDL are independent of technology,
very easy for designing and debugging, and are normally more useful
than schematics, particularly for large circuits.
Verilog Introduction
• The designers of Verilog wanted a language with syntax similar to the C
programming language, which was already widely used in engineering
software development.
• Like C, Verilog is case-sensitive and has a basic preprocessor (though less
sophisticated than that of ANSI C/C++). Its control flow keywords (if/else,
for, while, case, etc.) are equivalent, and its operator precedence is
compatible with C.
• Syntactic differences include: required bit-widths for variable declarations,
demarcation of procedural blocks (Verilog uses begin/end instead of curly
braces {}), and many other minor differences.
• Verilog requires that variables be given a definite size. In C these sizes are
assumed from the 'type' of the variable (for instance an integer type may
be 8 bits).
Verilog Introduction
• Verilog supports a design at many levels of abstraction.
• The major three are −
• Behavioral level
• Register-transfer level
• Gate level
Verilog Introduction
• Behavioral level
• This level describes a system by concurrent algorithms (Behavioral).
• Every algorithm is sequential, which means it consists of a set of
instructions that are executed one by one.
• Functions, tasks and blocks are the main elements.
• There is no regard to the structural realization of the design.
Verilog Introduction
• Register−Transfer Level
• Designs using the Register−Transfer Level specify the characteristics of
a circuit using operations and the transfer of data between the
registers.
• Modern definition of an RTL code is "Any code that is synthesizable is
called RTL code".
Verilog Introduction
• Gate Level
• Within the logical level, the characteristics of a system are described
by logical links and their timing properties.
• All signals are discrete signals. They can only have definite logical
values (`0', `1', `X', `Z`).
• The usable operations are predefined logic primitives (basic gates).
• Gate level modelling may not be a right idea for logic design.
• Gate level code is generated using tools like synthesis tools and his
netlist is used for gate level simulation and for backend.
Verilog Introduction
• Verilog Keywords
• Words that have special meaning in Verilog are called the Verilog
keywords.
• For example, assign, case, while, wire, reg, and, or, nand, and module.
• They should not be used as identifiers.
• Verilog keywords also include compiler directives, and system tasks
and functions.
Cont. …
• It is common to directly use the most primitive building-blocks available,
such as, logic gates, or larger blocks which have already been defined
elsewhere.
• Verilog provides AND, NOT, OR, XOR, NAND, XNOR, NOR gates, among
others.
• Verilog allows each logic gate to have any valid number of inputs.
• For instance, a single NOR gate can have four inputs, computing

• In Verilog we can request an XNOR function to be applied to its inputs, as if

• represents in "structural" form the logic network which computes

• The variable names acting as arguments in the logic gate functions, implicitly
show the internal connections among the various gates themselves.
• These variables are of the "wire" type. The development of a logic circuit from
scratch, starting from primitive gates is called structural or "gate-level" modeling.
 Cont. …
• In Verilog constants are specified in the traditional form of a series of digits with or without a sign, but also
in the following form
• <size> <base format> <number>
• where <size> contains decimal digits that specify the size of the constant in the number of bits.
• The <size> is optional.
• The <base format> is the single character ' followed by one of the following characters b, d, o and h, which
stand for binary, decimal, octal and hexadecimal, respectively.
• The <number> part contains digits which are legal for the <base format>.
• Some examples:
• 549 // decimal number
• 'h08FF // 16-bit hexadecimal number
• 4'b11 // 4-bit binary number 11 (0011)
• 3'b10x // 3-bit binary number with least significant bit unknown/don't care
• 12'o1345 // 12-bit octal number
• 5'd3 // 5-bit decimal number 3 (00011)
• -4'b11 // 4-bit two's complement negation of binary number 11 (1101)
 Next
Simulation and Synthesis