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An Efficient Model Predictive Control Using Virtual Voltage

Vectors for Three-phase Three-level Converters with Constant
Switching Frequency
Yong Yang, Senior,Member, IEEE, Huiqing Wen, Senior Member, IEEE, Rong Chen, Mingdi Fan, Senior Member, IEEE,
Xinan Zhang, Member, IEEE, Margarita Norambuena, Senior Member, IEEE, Jose Rodriguez, Life Fellow, IEEE

Abstract— In this paper, an efficient model predictive control PWM approaches in 3P-3L converters are the carrier PWM
(MPC) using virtual voltage vectors for three-phase three-level and space vector PWM (SVPWM) [6]-[8]. However, by using
converters is proposed. The proposed MPC achieves constant these techniques, it is generally very difficult to
switching frequency by applying four voltage vectors, including simultaneously achieve multiple objectives such as the neutral
one virtual voltage vectors and three other voltage vectors, in
point (NP) voltage balancing and common mode voltages
each control cycle. In addition, to reduce the computational
burden, two-stage MPC approach is adopted. The first stage (CMV) reduction. Furthermore, with the conventional
chooses one of six medium voltage vectors that minimizes the proportional integral (PI) or proportional resonant (PR)
cost function. Then, in the second stage, these voltage vectors technique for the closed-loop control in 3P-3L converters, the
including virtual voltage vectors which locate the same sector controller gain tuning process is tedious. Besides, it is
with the optimal medium voltage vector, are involved in the difficult to obtain a good balance between the dynamic and
MPC optimization. The advantages of the proposed MPC over steady-state performance [9].
the classical MPC have been validated through experimental Model predictive control (MPC) can fully consider the
results. system constraints and nonlinear characteristics in the control
process. In addition, MPC features fast dynamic response,
Index Terms—Virtual voltage vector, model predictive control, excellent steady-state performance and straightforward
multilevel converters.
implementation [10]-[12]. Thus, with the rapid developments
of digital signal processors (DSPs), MPC is widely utilized in
I. INTRODUCTION
power electronic converters. Generally, the computational

C ompared with the conventional two-level converters, the

three-phase three-level converters possess the advantages
of lower output voltage harmonic distortion, higher efficiency
burden of MPC increases exponentially with the increase of
the output voltage levels in three-phase DC/AC inverter. In
order to reduce the computational burden, many advanced
and lower voltage stress on power semiconductors [1]-[5]. MPC algorithms have been proposed. In [13] and [14], based
Thus, they have been widely utilized in distribution on the reference voltage vector obtained by the deadbeat
generation systems and electric vehicles (EVs). control principle, the number of candidate voltage vectors
greatly diminishes from 8 to 3. Therefore, the computational
To effectively control the three-phase three-level (3P-3L)
converter, the most widely used method is linear controllers efficiency is significantly improved. Similarly, in [15], a
combined with PWM techniques. Currently, the widely utilized simplified MPC algorithm based on Lyapunov function has
been proposed, which reduces 18% execution time compared
Manuscript received September 10, 2020; revised January 7, 2021 and to the conventional MPC method. In addition, through the
March 6, 2021; accepted April 11, 2021. This work was supported in part by appropriate selection of voltage vectors participating in the
the National Natural Science Foundation of China under Grant 51977136, MPC enumeration optimization, some advanced MPC
Grant 51907137 and Grant 52007127, in part by the Open Research Fund of algorithms have been proposed for 3P-3L converters with
National Rail Transportation Electrification and Automation Engineering
Technology Research Center (NEEC-2019-B08), in part by Projects KSF-T- reduced computational burden [16]-[19]. To further improve
04, in part by the Jiangsu Planned Projects for Postdoctoral Research Funds the steady-state performance of 3P-3L converters, multistep
2020Z444, the China Postdoctoral Science Foundation 2020M681693, and in MPC algorithms with sphere decoding have been proposed
part by ANID through projects FB0008, ACT192013, 11180233 and [20],[21]. However, multistep MPC for 3P-3L will greatly
1210208. (Corresponding authors: Huiqing Wen and Rong Chen.)
Yong Yang, Rong Chen and Mingdi Fan are with the School of Rail
increase the computational burden compared to the
Transportation, Soochow University, Suzhou 215131, China (e-mail: conventional one step MPC.
[email protected]; [email protected]; [email protected]). The above-mentioned efficient MPC algorithms in [13]-[21]
Huiqing Wen is with the Electrical and Electronics Department, the Xi’an utilize only one voltage vector per control cycle, which
Jiaotong-Liverpool University, Suzhou 215123, China (e-mail: inevitably results in variable switching frequency (VSF). In
[email protected]) .
Xinan Zhang is with the Department of Electrical, Electronic and addition, it requires high sampling frequency to obtain
Computer Engineering, University of Western Australia, Perth, WA 6009, satisfactory steady-state performance. To solve the above-
Australia (e-mail: [email protected]). mentioned VSF problems, some MPC methods with the
M. Norambuena is with the Faculty of Engineering, Universidad Tecnica constant switching frequency (CSF) have been proposed. The
Federico Santa Maria, Valparaíso 2390123, Chile (e-mail:
[email protected]).
application of two voltage vectors, namely one non-zero one
Jose Rodriguez is with the Faculty of Engineering, Universidad Andres zero voltage vectors per control cycle, was presented for
Bello, Santiago 8370146, Chile (email: [email protected]). three-phase two-level (3P-2L) converters in [22] and [23],

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which leads to lower output current ripple and CSF. To including one virtual voltage vector and three other voltage
further improve the steady-state performance, the employment vectors, will be applied in each control cycle to achieve the
of three voltage vectors in each control cycle is proposed CSF. Main contributions of this work will be summarized as:
[24]-[27]. The difference of the MPC methods in [22] and [23] 1) Two-stage MPC based on virtual voltage vectors: In the
lies in the method of calculating the time durations of three first stage, through the evaluation of six medium voltage
voltage vectors. In [24] and [25], the time durations are vectors, the optimal medium voltage vector that minimizes
obtained by minimizing the error between the reference and the cost function will be selected. Then, in the second stage,
actual power. Similarly, the time durations are derived by one virtual voltage vector and seven real voltage vectors that
minimizing the error between the reference and actual phase are located in the same sector are chosen to form the optimal
currents in [26]. In [27], the time durations of different voltage vector of the proposed MPC.
voltage vectors can be obtained based on their cost function 2) CSF MPC based on virtual voltage vectors: In total,
values, i.e. the time duration of every voltage vector is four voltage vectors are involved in each control cycle,
inversely proportional to its corresponding cost function value. including one virtual voltage vector and three real voltage
The afore-mentioned MPC algorithms in [24]-[27] are vectors.
designed for the 3P-2L converter and thus, are not directly 3) Effective NP voltage balance: The NP voltage can be
applicable to 3P-3L converters. Recently, MPC algorithms balanced by utilizing proper small redundant voltage vectors
featuring CSF for 3P-3L converters were proposed in [28]- and virtual voltage vectors.
[30]. However, [28] requires the calculation of time durations 4) Excellent balance between the steady-state and
in all 24 small triangle sectors, which substantially increases dynamic performance: A comprehensive evaluation of the
the computational complexity. In [29], an efficient MPC with proposed MPC under different conditions is conducted.
CSF was presented, which considerably reduces the number Moreover, a fair comparison with the conventional SVPWM
of small triangle sectors involved in MPC optimization from
and the classical MPC for the 3P-3L prototype has been made.
24 to 3. However, it is complex to compute time durations of
The rest of the paper is organized as follows. The topology
distinct voltage vectors. A two-stage MPC with CSF for the
and mathematical model of the T-type 3P-3L converter is
3P-3L-inverter-fed PMSM drive has been proposed in [30],
presented in Section Ⅱ. Section Ⅲ presents the principle of
which can reduce the cost function evaluation number and
the proposed MPC based on virtual voltage vectors. Section
alleviate the computational burden. However, the calculated
time durations of some voltage vectors may be negative under Ⅳ shows comparative experimental results for different
certain operations, which will deteriorate the PMSM drive control methods. Finally, the conclusion is summarized in
performance. Section Ⅴ.
For the 3P-3L converter, the inherent NP voltage variation II. TOPOLOGY AND MATHEMATICAL MODEL
should be considered. MPC can easily achieve multiple
objectives by adding objective terms in the cost function. The circuit of the T-type 3P-3L converter is depicted in
Therefore, the NP voltage of T-type 3P-3L converter can be Fig.1 [5], where Vdc is the dc-link input voltage, and it is
effectively controlled by adopting MPC strategies [31]-[33]. assumed to be constant. Vc1 and Vc2 represent the dc-link top
However, there are several weighting factors in the cost and bottom capacitor voltages, respectively. idc1, iP and iN
function and the selection of proper weighting factors is represent the dc-link input current, the positive dc-link
usually time-consuming due to the lack of theoretical capacitor current and the negative dc-link current,
guidelines. To eliminate weighting factors of MPC, small respectively. ic1, ic2 and io are the dc-link upper capacitor
redundant voltage vectors are utilized to balance the NP current, the dc-link lower capacitor current, and the neutral
voltage like the conventional SVPWM methods [28]-[30]. point (NP) current, respectively. isx (x=a,b,c) represents the
However, it is difficult to balance the NP voltage once the phase-x output current. C1 and C2 indicate the dc-link upper
converter operates at high modulation index or low power capacitor and the dc-link lower capacitor, respectively, which
factor. In order to solve the above-mentioned problems, the are assumed to be equal (C1=C2=C). R and L mean load
virtual space vector PWM (VSVPWM) technique has been resistance and inductance.
proposed [34]-[38]. The virtual voltage vectors, which have Each leg of the 3P-3L converter has different switching
no influences on the NP voltage, are linearly synthesized by combinations that can generate 3 switching states, which are
the existing voltage vectors. Nevertheless, the VSVPWM is denoted as “P”, “O” and “N”. “P” means the power switches
generally used together with linear controllers. Therefore, it is Sx1 (x=a,b,c) and Sx2 (x=a,b,c) turn on at the same time, “O”
naturally associated with the drawbacks of linear controllers. indicates that the power switches Sx2 (x=a,b,c) and Sx3 (x=a,b,c)
In order to address this issue, some MPC algorithms with the are turned on. “N” implies that the power switches Sx3
utilization of virtual voltage vectors have been presented to (x=a,b,c) and Sx4 (x=a,b,c) are turned on.
ensure excellent control performance and well balanced NP Define Sx (i=a,b,c) as the switching state and it is expressed
voltage [39], [40]. However, the number of applied voltage as:
vectors per control cycle is changing, resulting in a variable 1 S i1 and S i 2 on, S i 3 and S i 4 off
 (1)
switching frequency. Sx   0 S i 2 and S i 3 on, S i1 and S i 4 off
In this paper, a computationally efficient MPC algorithm  -1 S i 3 and S i 4 on, S i1 a n d S i 2 off

without weighting factors has been proposed with the merit of Assuming the NP voltage is controlled at Vc1 =Vc2=Vdc/2.
achieving the fast dynamic response, NP voltage balance, and Thus, the converter output voltages with respect to O as
CSF simultaneously. Specifically, four voltage vectors, reference voltage can be derived as:

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Vao  SaVdc / 2 derived as

 isa  isb  isc  0 (5)
Vbo  SbVdc / 2 (2)
V  S V / 2 Combining (2) , (4) and (5), the neutral-point voltage Vno is
 co c dc calculated as
Vno  (Vao  Vbo Vco ) / 3 (6)
Substituting (2) and (6) into (4), it can be obtained as
isc (k )
 (2Sa  Sb  Sc )Vdc / 3  Ldisa / dt  Risa
isb ( k ) 
(Sa  2Sb  Sc )Vdc / 3  Ldisb / dt  Risb (7)
isa ( k ) (S  S  2S )V / 3  Ldi / dt  Ri
 a b c dc sc sc

Define switching states SSa, SSb, and SSc as:

(a)  SSa  (2Sa  Sb  Sc ) / 3

SSb  (Sa  2Sb  Sc ) / 3 (8)
S  (S  S  2S ) / 3
 Sc a b c

isa Suppose the sampling period Ts is sufficiently small

compared with the period of output currents, then, by utilizing
Forward Euler method, the future output currents at the
(k+1)th instant can be predicted as:
(b) isx (k 1)  (SSx (k )Vdc  Risx (k ))Ts / L  isx (k ) x  a, b, c (9)
Fig. 1. Circuit structure. (a) T-type 3P-3L converters. (b) T-type phase-a leg. As shown in Fig.1, according to Kirchhoff current laws, the
The output voltage vector Vconv of the 3P-3L converter is dc-link capacitor currents are obtained as:
given as:  ic1  idc  iP
Vconv  2(Vao Vbo 2Vco )/ 3  (10)
(3) ic2  ic1  io  idc  iP  io
where α=e2π/3. Furthermore, the positive dc-link current and the NP current
For the 3P-3L converter, the output voltage vector Vconv is can be expressed by switching states as:
synthesized by three phase output voltages. As shown in (1),
each phase generates 3 switching states. Therefore, the 3P-3L iP   (Sx  (Sx )2 )isx / 2
converter can generate 27 (33) switching states in total. These
 xa,b,c
 (11)
 o  (1 (Sx ) )isx
 2
27 voltage vectors can be expressed by (3) and are depicted in i
Fig. 2 in the stationary αβ reference frame. In terms of the  xa,b,c
magnitude of voltage vectors, they can be divided into zero, Unbalanced NP voltages will lead to higher harmonics of
small, medium and large voltage vectors. output currents. Thus, it is necessary to balance the NP
From Fig.1, according to Kirchhoff voltage and current voltage and achieve the energy balance between the dc-link
laws, the converter output voltages in the continuous time upper and lower capacitors. Therefore, the dc-link input
domain can be obtained as: current will be zero. Combining (10) and (11), dc-link
Vxn  Vxo Vno  Ldisx / dt  Risx x  a, b, c (4) capacitor currents are obtained as:
where Vno is the neutral-point voltage. ic1    (Sx  (Sx )2 )isx / 2
 xa,b,c
 (12)
 i
 c2    (Sx  (Sx )2 )isx / 2   (1 (Sx )2 )isx
V19 (NPN) V18 (OPN) V17 (PPN)
 xa,b,c xa,b,c

In the continuous time domain, the dc-link capacitor

V20 (NPO) V7 (OPO) V5 (PPO) V16 (PON)
voltages are expressed as:
V8 (NON) V6 (OON)
 V (t)  V (0)  t i ( )d
 c1 c1 0 c1
V21 (NPP) V9 (OPP) V0 (-1-1-1)
V1 (000)
V3 (POO) V15 (PNN)
  t
(13)
Vc2 (t)  Vc2 (0)    ic2 ( )d
V10 (NOO) V2 (111) V4 (ONN)

 0
V22 (NOP) V11 (OOP)
V12 (NNO)
V13 (POP)
V14 (ONO) V26 (PNO) Combining (12) and (13), the predictive dc-link capacitor
voltages are obtained as:
Vc1(k 1)  Vc1(k)  Ts  (Sx  (Sx )2 )isx / 2C
V23 (NNP) V24 (ONP) V25 (PNP)  x a,b,c

   s (  (Sx  (Sx ) )isx / 2   (1  (Sx ) )) / C
2 2
V
 c2 (k 1) Vc2 (k ) T
 x a,b,c x a,b,c

Fig. 2. 27 voltage vectors for 3P-3L converters. (14)

Assuming there is no neutral-point system, it can be

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III. VIRTUAL VOLTAGE VECTORS MPC TABLE Ⅰ. CANDIDATE VOLTAGE VECTORS IN DISTINCT SECTORS
Optimal medium Candidate voltage vectors
A. MPC without Weighting Factors voltage vector
V16 V1, V3, V4, V5, V6, V15, V16, V17
In the process of constructing the cost function, different V18 V1, V5, V6, V7, V8, V17, V18, V19
constraints can be added to achieve different control V20 V1, V7, V8, V9, V10, V19, V20, V21
objectives. For the 3P-3L converter, there are generally two V22 V1, V9, V10, V11, V12, V21, V22, V23
primary control objectives. One objective is to accurately V24 V1, V11, V12, V13, V14, V23, V24, V25
V26 V1, V13, V14, V3, V4, V25, V26, V15
track the output current references, and the other control
objective is to effectively control the NP voltage. Hence, the B. CSF MPC with Virtual Voltage Vectors
cost function of 3P-3L converters is constructed as:
The inherent drawback of the 3P-3L converter is the
Jc   isx* (k 1)  isx (k 1)  dc1 Vc1(k 1) Vc2 (k 1) (15) requirement of balancing the NP voltage. To effectively
xa,b,c
control the NP voltage, virtual voltage vectors that have no
where λdc1 is the weighing factor for balancing the NP voltage. influence on the NP voltage can be linearly synthesized by
There is a trade-off between the current reference tracking and nearest three voltage vectors. Take the virtual voltage vector
the NP voltage balancing. When a larger value of the VV1 as example, VV1 can be synthesized as:
weighing factor λdc1 is set, higher priority has been put on the
VV1  (V4  V5  V16 ) / 3 (17)
NP voltage balancing, and vice versa [41].
From (9), (14) and (15), it can be clearly seen that 27 Suppose the three voltage vectors V4, V5 and V16 are
iterative predictions of currents and voltages as well as 27 applied with the same time duration in one switching cycle,
iterative cost function evaluations are needed, which implies a the NP current of the virtual voltage vector VV1 operation can
heavy calculation burden. In addition, a tedious tuning be derived as
process is required to find a proper weighting factor in (15). ioV1  (isa  isb  isc ) / 3  0 (18)
In order to eliminate weighting factors, the cost function for As shown in (18), the average NP current per switching
the proposed MPC algorithm is established as: cycle for VV1 action is zero. Therefore, the virtual voltage
Js  
xa,b,c
isx* (k 1)  isx (k 1) (16) vector VV1 has no impact on the NP voltage. Similarly, other
five virtual voltage vectors of the 3P-3L converter have been
To reduce the computational burden, a two-stage MPC is constructed and are listed in Table Ⅱ.
proposed. The first stage is to select one of six medium TABLE Ⅱ. VIRTUAL VOLTAGE VECTORS
voltage vectors (V16, V18, V20, V22, V24, V26) shown in Fig. 3
that minimizes the cost function (16). After the optimal Sectors Virtual voltage vectors
1 VV1=(V4+V5+V16)/3
medium voltage vector is chosen, these voltage vectors
2 VV2=(V5+V8+V18)/3
located in the same sector as the optimal medium voltage
3 VV3=(V8+V9+V20)/3
vector take part in MPC optimization. Candidate voltage 4 VV4=(V9+V12+V22)/3
vectors in distinct sectors are listed in Table I. 5 VV5=(V12+V13+V24)/3
Ⅱ 6 VV6=(V4+V13+V26)/3
 V18 (OPN) For the conventional SVPWM approach, the reference
V19 (NPN) V17 (PPN)
voltage vector can be synthesized by the nearest voltage
vectors according to the voltage-second balance law. Fig.4
Ⅲ V20 (NPO)
depicts the time durations of different voltage vectors
V7 (OPO) V5 (PPO) Ⅰ
V6 (OON)
including virtual voltage vector for Sector I. As shown in
V8 (NON) V16 (PON)
Fig.4, each large sector is further divided into 3 new tetragons
1 with two design considerations: one is that each tetragon
V21 (NPP) V0 (-1-1-1)
V9 (OPP) V3 (POO) V15 (PNN) contains two small redundant voltage vectors and one virtual
V10 (NOO)
V1 (000)
V4 (ONN) 
V2 (111) voltage vector, which are in favor of balancing the NP voltage.
The other consideration is that the computational burden can
V11 (OOP) V13 (POP)
V26 (PNO)
be reduced when each large sector is only divided into 3
V12 (NNO) V14 (ONO) tetragons compared with the division of 4 triangular sectors in
Ⅵ
Ⅳ V22 (NOP) [28].
Assume the reference voltage vector Vref is located in the
V23 (NNP) V25 (PNP) tetragon S2 of Sector I, as shown in Fig. 4, the following
V24 (ONP) equation (19) should be satisfied.
Ⅴ
 V16ta  V3tb  V15tc  VV1td  Vref Ts
Fig. 3. 6 medium voltage vectors in the first-stage MPC optimization. 
 ta  tb  tc  td  Ts (19)
As shown in Table I, there are only 8 instead of 27 0  t , t , t , t  T
candidate voltage vectors in the second stage, which largely  a b c d s

diminishes the computational burden. where Ts is the control cycle, which is the same as the
sampling period in the system.

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JS 2  ( Js16ta  J s3tb  J s15tc  JsV1td ) / Ts (22)
V17 (PPN) Similarly, the tetragon cost functions for the tetragon S1
and the tetragon S3 are obtained and defined as JS1 and JS3,
respectively. The tetragon cost function with the minimum
value is chosen as the optimal tetragon. Then, the
V5 (PPO) corresponding voltage vectors will take part in MPC
V6 (OON) V16 (PON) optimization process and applied in the next control cycle.
VV1 C. NP Voltage Balancing
For the 3P-3L converter, there are six pairs of small
Vref V15 (PNN)
V3 (POO) redundant voltage vectors in total, which can be classified into
V1 (000) V4 (ONN) positive and negative small redundant voltage vectors. They
may generate the same output voltages while opposite effects
Fig. 4. Time durations for distinct voltage vectors in Sector Ⅰ. on the NP voltage. In addition, positive small redundant
decreases the dc-link upper voltage when the 3P-3L converter
There are multiple voltage vectors applied in each control
cycle for the SVPWM approach. Therefore, SVPWM supplies the pure resistance load, and vice versa for the
approach features CSF, which is beneficial for the filter negative small redundant voltage vectors. Thus, the small
design. From the equation (19), there are only three equations redundant voltage vectors can be utilized in balancing the NP
for four time durations’ calculations. Thus, the values of time voltage. The NP balancing factor can be defined as:
durations of distinct voltage vectors are not unique, which fNP  kNP (Vc1 Vc2 ) / Vdc (1  fNP  1) (23)
makes the time duration calculation complex. where kNP is the adjusting factor for the NP voltage balancing.
In order to achieve CSF for the converter output Table III shows the voltage vector sequences in Section I.
voltages/currents, MPC with multiple voltage vectors Moreover, action sequences and time durations for different
including the virtual voltage vector in VSVPWM approach is
voltage vectors in Sector Ⅰ are shown in Fig.5. As shown in
developed in this paper. Its main difference from the existing
Fig.5, it can be observed that the time duration of the positive
VSVPWM approaches lies in how the time durations of
small voltage vectors will increase once the upper dc-link
different voltage vectors are calculated. The SVPWM
approach is based on the voltage-second balance law while capacitor voltage is greater than the lower dc-link capacitor
the MPC approach is mainly based on the numerical value of voltage. Similarly, other large sectors such as Sectors Ⅱ, Ⅲ,
cost function. Specifically, the voltage vector that produces a Ⅳ, Ⅴ and Ⅵ can be obtained. Based on above analysis, the
larger cost function will be applied for a smaller time duration control strategy of the proposed MPC algorithm is
in the next control cycle. summarized in Fig.6.
According to the cost function (16), the cost function TABLE Ⅲ. VOLTAGE VECTORS SEQUENCES IN SECTOR I
values for voltage vectors V16, V3, V15 and VV1 are denoted as
Tetragons Voltage vector sequences
Js16, Js3, Js15 and Jsv1, respectively. In addition, the cost S1 ONN-OON-PON-POO-PPO-PPP-PPO-POO-PON-
function values of redundant voltage vectors V3 (V4) and V5 OON-ONN
(V6) are the same. Thus, only voltage vectors V3 and V5 are S2 ONN-PNN-PON-POO-PPO-POO-PON-PNN-ONN
involved in the time duration calculation. Consequently, when S3 ONN-OON-PON-PPN-PPO-PPN-PON-OON-ONN
the reference vector Vref is located in the tetragon S2, time Ts
durations ta, tb, tc and td are calculated as: V4 V6 V1 6 V3 V5 V2 V5 V3 V1 6 V6 V4

ta  kTs / Js16 , 0  ta  Ts O

 t  kT / J , 0  t  T
 b
N
s s3 b s

 tc  kTs / Js15 , 0  tc  Ts (20) N

t1 t2 t3 t4 t5 t6 t5 t4 t3 t2 t1
t  kT / J , 0  t  T t1 
1  f NP
(tb  td / 3) t2 
1  f NP
(tc  td / 3) t1  td / 6 t4 
1  f NP
(tb  td / 3)
d s sV1 d s 4
1  f NP
4 4

ta  tb  tc  td  Ts t5 
4
(tc  td / 3) t6  ta

Solving the equation (20), it can be obtained as: (a)

 ta  Js3Js15JsV1Ts / J V15 V16 V3 V15

V4 V16 V4
t  J J J T / J
 b s16 s15 sV1 s
 tc  Js16 Js3JsV1Ts / J
 (21)
 td  Js16 Js3Js15Ts / J
 J  Js3Js15JsV1  Js16 Js15JsV1 

 Js16 Js3JsV1  Js16Js3Js15 t1 
1  f NP
(tb  td / 3) t2  tc / 2 t3  ta / 2  td / 6 t4 
1  f NP
(tb  td / 3) t5  td / 3
4 4
After the time durations are acquired, the tetragon cost
(b)
function of the tetragon S2 is defined as:

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V4 V6 V16 V3 V16 V15 V4

1  f NP 1  f NP
t1  td / 6 t2  (tc  td / 3) t3  ta / 2  td / 6 t4  tb / 2 t5  (tc  td / 3)
4 2
(c)
Fig. 5. Voltage vector action sequences and time durations for different
voltage vectors in Sector Ⅰ. (a) Tetragon S1. (b) Tetragon S2. (c) Tetragon S3.

IV. EXPERIMENT RESULTS

The effectiveness of the virtual voltage vector MPC
algorithm is evaluated through experimental results. A down-
scaled experimental platform is constructed to verify the Fig.7. Experimental platform.
proposed MPC algorithm, which is depicted in Fig. 7. To
The control delay should be considered when these MPC
accomplish MPC algorithms, digital signal processor (DSP)
methods are implemented in DSPs. Thus, these selected
TMS320F2808 from TI Instrument is adopted. Furthermore,
voltage vectors by MPC algorithms at the (k)th instant will be
complex programmable logic device (CPLD) (EMP7256) is
applied in the (k+1)th instant. To compensate for the control
utilized to extend PWM signals and generate dead-times. The
delay, a two-step prediction method proposed in [42] is
output currents and the dc-link capacitor voltages are sampled
adopted in the system.
by LEM current sensors and LEM voltage sensors, and then
To verify the proposed method, different conditions are
set to the 12 bit A/D block of the DSP TMS320F2808. The
evaluated, which is shown in Table Ⅴ, where I* represents the
main experimental parameters are listed in Table Ⅳ.
amplitude reference of output currents, and f* means the given
frequency of output currents.
A. Execution Time for Different MPC Algorithms
isc ( k )
There are three MPC algorithms and defined as followings:
isb (k ) Algorithm-Ⅰ: The VSF MPC for the 3P-3L converter
proposed in [43] is considered as Algorithm-Ⅰ.
isa (k ) Algorithm-Ⅱ: The CSF MPC proposed in [28] is regarded as
Algorithm-Ⅱ, which evaluates 24 triangular cost functions
(each sector contains 4 triangular sectors).
Vc1 (k ) Algorithm-Ⅲ: The CSF MPC proposed in the paper is
Vc 2 (k ) regarded as Algorithm-Ⅲ.
Table Ⅵ shows the execution time for three MPC methods
when these methods are implemented by utilizing the DSP
TMS320F2808. The execution time contains two parts. One
part is measurements and other task, which includes A/D
sampling, values initialization, hardware protection and so on.
isa ( k ) isa* ( k  1) The other part implements the MPC algorithm by using C-
isa* (k )
isb ( k ) isb* ( k  1) isb* ( k ) language. As listed in Table Ⅵ, it can be found as: 1)
isc (k ) isc* ( k  1)
Vdc (k ) isc* (k ) Algorithm-Ⅰ has the shortest execution time, and Algorithm-
Fig. 6. Control strategy of the proposed MPC algorithm. Ⅱ has the longest execution time. 2) Compared with the CSF
TABLE Ⅳ. MAIN EXPERIMENTAL PARAMETERS MPC in [28], the presented CSF of the execution time has
been significantly reduced. Specifically, it is only 26.8% of
Parameter Description Values
the conventional CSF MPC due to the utilization of two-stage
Vdc Dc-link input voltage 180 V
C1, C2 Dc-link capacitors 500 μF MPC. 3) The execution time of the presented CSF MPC
L Filter inductance 10 mH algorithm is slightly higher than the VSF MPC in [14].
R Resistance 20 Ω However, there is a great idle time for the presented CSF
fs Sampling frequency 10 kHz
kNP Adjusting factor 5 MPC during 100 µs control cycle.
TABLE Ⅴ. TEST CONDITIONS TABLE Ⅵ. EXECUTION TIME

Conditions I * *
f MPC Measurements MPC time Total time
Condition 1 2A 50 Hz algorithms and other tasks
Condition 2 4A 50 Hz Algorithm-Ⅰ 11.3 µs 20.3 µs 31.6 µs
Condition 3 From 4 A to 2 A 50 Hz Algorithm-Ⅱ 11.3 µs 125.2 µs 136.3µs
Algorithm-Ⅲ 11.3 µs 33.5 µs 44.8 µs

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B. Steady-state Performance Evaluation
To verify the feasibility of the presented MPC based on
virtual voltage vectors, steady-state performance has been
evaluated and compared with the conventional SVPWM in [6]
and the classical MPC. The MPC method proposed in [43] is
considered as the classical MPC algorithm, where one voltage
vector that minimizes the cost function will be selected and (a) (b)
applied in the next control cycle. In order to better compare Fig. 9. Experiment results: the line-line output voltage uab, dc-link capacitor
the classical MPC with the proposed MPC, the sampling voltages and phase-a current for the conventional SVPWM under Condition 1
(a) and Condition 2 (b).
frequency of the classical MPC (20 kHz) is set to two times of
the presented MPC (10 kHz) [44]. The sampling frequency of
the conventional SVPWM is set the same as the proposed
MPC, which is 10 kHz. Fig.8, Fig.9, Fig.10, Fig.11, Fig.12
and Fig.13 display steady-state experimental results of output
currents, dc-link capacitor voltages and fast Fourier transform
(FFT) of the phase-a output current under Condition 1 and
Condition 2. From these steady-state experimental results, it
(a) (b)
can be clearly observed that: 1) The output current is
sinusoidal with high quality by using these three different
methods. The total harmonic distortion (THD) values for the
conventional SVPWM, the classical MPC, and the proposed
MPC under Condition 1 are 5.42%, 6.05% and 5.36%,
respectively. The corresponding THD values under Condition (c) (d)
2 are 3.18%, 3.88% and 3.08%, respectively. The THD value Fig. 10. Steady-state experiment results of line-line output voltage uab ,three
of the proposed MPC algorithm is slightly lower than that of output currents and FFT of the phase-a current under Condition 1. (a) and (c)
for the classical MPC in [43]. (b) and (d) for the proposed MPC.
the conventional SVPWM. Moreover, the proposed MPC has
better output current waveform compared with the classical
MPC although its sampling frequency is only half of the
classical MPC. 2) The dc-link upper and lower capacitor
voltages for both MPC algorithms are well controlled, and the
experimental peak-to-peak ripple is less than 3 V. 3) High-
order harmonics of output currents by using the conventional
SVPWM and the presented MPC are mainly concentrated on
the sampling frequency and its multiple sampling frequencies (a) (b)
such as 10 kHz, 20 kHz and so on. However, higher-order
harmonics for the classical MPC method are scattered over
different frequencies, which will complicate the design of the
filter.
(c) (d)
Fig. 11. Steady-state experiment results of line-line output voltage uab, three
output currents and FFT of the phase-a current under Condition 2. (a) and (c)
for the classical MPC in [43]. (b) and (d) for the proposed MPC.

(a) (b)

(c) (d) (a) (b)

Fig. 8. Experimental results: the line-line output voltage uab, output currents Fig. 12. Steady-state experiment results of line-line output voltage uab , dc-
and FFT of phase-a current for the conventional SVPWM under Condition 1 link capacitor voltages and phase-a current under Condition 1. (a) Classical
(a) and Condition 2 (b). FFT of phase-a current for the conventional SVPWM MPC in [43]. (b) Proposed MPC.
under Condition 1 (c) and Condition 2 (d).

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(a) (b) (a) (b)

Fig. 13. Steady-state experiment results of line-line output voltage uab , dc- Fig. 16. Experiment results of line-line output voltage uab, dc-link capacitor
link capacitor voltages and phase-a current under Condition 2. (a) Classical voltages and phase-a current for dc-link capacitor voltage balancing
MPC in [43]. (b) Proposed MPC. evaluation. (a) Classical MPC in [43]. (b) Proposed MPC.

C. Dynamic Performance Evaluation E. Performance Comparison with the Same Average

Switching Frequency
Dynamic performance of both MPC methods has been
To make a fair comparison of the proposed MPC and the
evaluated in this section. Fig.14 and Fig.15 display the classical MPC algorithm, the average switching frequency
dynamic experiment results of output currents and dc-link should be set to the same [45], which is about 7.92 kHz when
capacitor voltages for both MPC algorithms under Condition the sampling frequencies for the proposed MPC and the
3. From Fig.14 and Fig.15, it is summarized as: 1) Output classical MPC under Condition 2 are set as 10 kHz and 30
currents can track current references with fast response, and it kHz, respectively. Fig.17 and Fig.18 display steady-state
takes less than 1 ms to track the current references. 2) Dc-link experimental results by using the classical MPC algorithm in
top and bottom capacitor voltages are effectively controlled [43] with the 30 kHz sampling frequency. From Fig.10 (b),
even when the current references are stepped. These dynamic Fig.11 (b), Fig.12 (b), Fig.13 (b), Fig.17 and Fig.18, it can be
noted that the quality of output currents and the peak-to-peak
experimental results indicate that both MPC methods have
ripple of dc-link capacitor voltages by using two MPC
fast dynamic performance. algorithms are quite similar. One difference is that higher-
order harmonics of output currents by using the classical
MPC are scattered over different frequencies, which will
result in the difficulty in designing filters.

(a) (b)
Fig. 14. Dynamic experiment results of line-line output voltage uab, three
output currents under Condition 3. (a) Classical MPC in [43]. (b) Proposed
MPC.
(a) (b)

(c) (d)
Fig. 17. Steady-state experimental results by using the classical MPC with 30
(a) (b) kHz sampling frequency: output currents under Condition 1 (a) and Condition
Fig. 15. Dynamic experiment results of line-line output voltage uab, dc-link 2 (b). FFT of phase-a current under Condition 1 (c) and Condition 2 (d).
capacitor voltages and phase-a current under Condition 3. (a) Classical MPC
in [43]. (b) Proposed MPC.

D. Dc-link Capacitor Voltage Balancing Evaluation

To further verify the capacity in balancing the dc-link
capacitor voltages, a resistance 150 Ω is connected in parallel
with the dc-link lower capacitor through the switch (S). Fig.16
shows the experiment results of line-line output voltage uab,
(a) (b)
dc-link capacitor voltages and phase-a current when the Fig. 18. Steady-state experimental results by using the classical MPC with 30
switch S is switched on or off with I*=4 A and f*=50 Hz. From kHz sampling frequency: line-line output voltage uab, dc-link capacitor
Fig.16, it can be concluded that the dc-link capacitor voltages voltages, and phase-a current under Condition 1 (a) and Condition 2 (b).
for both MPC methods are well balanced, and the peak-to- F. Parameter Robustness Evaluation
peak ripple of the dc-link capacitor voltages is basically
unchanged even after adding a 150 Ω resistance in parallel In practical systems, the real inductance Lr will change
with the dc-link lower capacitor voltage. Thus, both MPC under different operation conditions. However, the model
algorithms have strong capacity in balancing the dc-link inductance L in the MPC algorithm is fixed. To evaluate the
capacitor voltages. parameter robustness of the proposed MPC algorithm, the

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fixed switching frequency,” IEEE Trans. Ind. Appl., vol. 53, no. 1, pp. [45] H. Young, M. Perez, J. Rodriguez, and H. Abu-Rub, “Assessing finite
296-304, Jan./Feb. 2017. control-set model predictive control: A comparison with a linear current
[28] F. Donoso, A. Mora, R. Cardenas, A. A. Cárdenas, D. Sáez, and M. controller in two-level voltage source inverters,” IEEE Ind. Electron.
Rivera, “Finite-Set model predictive control strategies for a 3L-NPC Mag., vol. 8, no. 1, pp. 44-52, Mar. 2014.
inverter operating with fixed switching frequency,” IEEE Trans. Ind.
Electron., vol. 65, no. 5, pp. 3954-3965, May 2018.
[29] A. Mora, R. Cardenas-Dobson, R. P. Aguilera, A. Angulo, F.
Donoso,and J. Rodriguez, “Computationally efficient cascaded optimal
switching sequence MPC for grid-connected three-level NPC converters,” Yong Yang (M’15-SM’20) received the B.S. degree
IEEE Trans. Power Electron., vol. 34, no. 12, pp. 12464-12475, 2019. in automation from Xiangtan University, Xiangtan,
[30] D. Zhou, L. Ding and Y. Li, “Two-stage model predictive control of China, in 2003, the M.S. degree in Electrical
neutral-point-clamped inverter-fed permanent-magnet synchronous motor Engineering from Guizhou University, Guiyang,
drives under balanced and unbalanced DC links,” IEEE Trans. Ind. China, in 2006, and the Ph.D. degree in Electrical
Electron., vol. 68, no. 5, pp. 3750-3759, May 2021. Engineering from Shanghai University, Shanghai,
[31] Y. Yaramasu, B. Wu, S. Alepuz, and S. Kouro, “Predictive control for China, in 2010.
low-voltage ride-through enhancement of three-level-boost and NPC He is currently an associate professor with the
converter-based PMSG wind turbine,” IEEE Trans. Ind. Electron., vol. School of Rail Transportation, Soochow University.
61, no. 12, pp. 6832-6843, Dec. 2014. From December 2017 to December 2018, he was a Visiting Scholar with
[32] A. C. Prado, S. Alepuz, J. Bordonau, J. N. Apruzzese, P. Corts, and J. Center for High Performance Power Electronics (CHPPE) of The Ohio State
Rodriguez, “Model predictive current control of grid-connected neutral- University, Columbus, USA. He has coauthored more than 70 journal and
point-clamped converters to meet low-voltage ride-through requirements,” conference papers. His current research interests include model predictive
IEEE Trans. Ind. Electron., vol. 62, no. 3, pp. 1503–1514, Mar. 2015. control in power electronic converters, distributed energy resource interfacing
[33] A. C. Prado, S. A lepuz, J. Bordonau, P. Cortes, and J. Rodriguez, and high-performance motor drive control.
“Predictive control of a back-to-back NPC converter-based wind power
system,” IEEE Trans. Ind. Electron., vol. 63, no. 7, pp. 4615–4627, Jul.
2016.
[34] S. B. Monge, J. Bordonau, D. Boroyevich, and S. Somavilla, “The
Huiqing Wen (M’13-SM’17) received his B.S. and
nearest three virtual space vector PWM modulation for the M.S. degrees in Electrical Engineering from Zhejiang
comprehensive neutral-point balancing in the three-level NPC inverter,” University, Hangzhou, China, in 2002 and 2006,
IEEE Power Electron.Lett., vol. 2, no. 1, pp. 11–15, Mar. 2004. respectively; and his Ph.D. degree in Electrical
[35] S. B. Monge, S. Somavilla, J. Bordonau, and D. Boroyevich, “Capacitor Engineering from the Chinese Academy of Sciences,
voltage balance for the neutral-point-clamped converter using the virtual Beijing, China, in 2009. From 2009 to 2010, he was an
space vector concept with optimized spectral performance,” IEEE Trans. Electrical Engineer working in the Research and
Power Electron., vol. 22, no. 4, pp. 1128–1135, Jul. 2007. Development Center, GE (China) Co., Ltd., Shanghai,
[36] A. Choudhury, P. Pillay, and S. S. Williamson, “DC bus voltage China. From 2010 to 2011, he was an Engineer at the
balancing algorithm for three-level neutral-point-clamped (NPC) traction China Coal Research Institute, Beijing, China. From 2011 to 2012, he was a
inverter drive with modified virtual space vector,” IEEE Trans. Ind. Appl., Postdoctoral Fellow at the Masdar Institute of Science and Technology, Abu
vol. 52, no. 5, pp. 3958–3967, Sep./Oct. 2016. Dhabi, United Arab Emirates.
[37] C. Hu, X. Yu, D. G. Holmes, W. Shen, Q. Wang, F. Luo and N. Liu, He is presently working as an Associate Professor at the Xi’an Jiaotong-
“An improved virtual space vector modulation scheme for three-level Liverpool University, Suzhou, China. His current research interests include
active neutral-point-clamped inverter,” IEEE Trans. Power Electron., vol. bidirectional DC-DC converters, power electronics in flexible AC transmission
32, no. 10, pp. 7419–7434, Oct. 2017. applications, electrical vehicles, and high-power, three-level electrical driving
[38] W. Jiang et al., “A novel virtual space vector modulation with reduced systems.
common-mode voltage and eliminated neutral point voltage oscillation
for neutral point clamped three-level inverter,” IEEE Trans. Ind.
Electron., vol. 67, no. 2, pp. 884–894, Feb. 2020.
[39] J. Lee, J. Lee, H. Moon, and K. Lee, “An improved finite-set model
predictive control based on discrete space vector modulation methods for

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Transactions on Industrial Electronics

IEEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Universidad Andres Bello in Santiago, Chile. He has coauthored two books,
Rong Chen received the B.S. degree in several book chapters and more than 400 journal and conference papers. His
communication engineering from Soochow main research interests include multilevel inverters, new converter topologies,
University, Suzhou, China, in 2006, the M.S. degree control of power converters, and adjustable-speed drives. He has received a
in communication and information system from number of best paper awards from journals of the IEEE. Dr. Rodriguez is
Soochow University in 2009, and the Ph.D. degree in member of the Chilean Academy of Engineering. In 2014 he received the
signal and information processing from Soochow National Award of Applied Sciences and Technology from the government of
University in 2013. Chile. In 2015 he received the Eugene Mittelmann Award from the Industrial
Currently, she is an associate professor with the Electronics Society of the IEEE. In years 2014 to 2020 he has been included in
School of Rail Transportation, Soochow University. the list of Highly Cited Researchers published by Web of Science.
Her research interests include signal processing and synchronous phasor
measuring.

Mingdi Fan (M’16-SM’20)) received B.S. degree in

electrical engineering and the Ph.D. degree in detection
technology and automation device from Northwestern
Polytechnical University, Xi’an, China, in 2008 and
2014. From 2010 to 2011, he worked as a visiting
scholar in Kassel University, Germany.
He is currently an Associate Professor with the
School of Rail Transportation, Soochow University.
His current research interests include model predictive
control for power converters and motor drives.

Xinan Zhang (S'10-M'14) received the B.E. degree in

electrical engineering and automation from Fudan
University, China, in 2008. He received the Ph.D.
degree from Nanyang Technological University
(NTU), Singapore, in 2014. Then, he worked as
postdoc researcher in NTU and the University of New
South Wales from 2014 to 2017. He worked as a
Lecturer in NTU from June 2017 to September 2019.
Since September 2019, he joined the University of Western Australia as a
Senior Lecturer. His research interests include electrical machine drives,
control and modulation of power electronic converters and design of hybrid
energy storage systems.

Margarita Norambuena (S'12-M'14-SM'21)received

the B.S. and M. S. degrees in electric engineering
from the Universidad Tecnica Federico Santa Maria
(UTFSM), Valparaiso, Chile, in 2013. She received
the Ph.D. degree (summa cum laude) in electronics
engineering from the UTFSM in 2017 and received
the Doktoringenieur (Dr-Ing.) degree (summa cum
laude) from the Technische Universitat Berlin (TUB)
in 2018. In 2019 she received the award “IEEE IES
Best student paper award” for her doctoral work.
She is an Assistant Professor at Universidad Tecnica Federico Santa Maria.
Her research interest includes multilevel converters, model predictive control
of power converters and drives, energy storage systems, renewable energy
and microgrids systems. Dr. Norambuena serves as an Associate Editor for
IEEE JESTPE.

Jose Rodriguez (M´81-SM´94-F´10-LF´20) received

the Engineer degree in electrical engineering from the
Universidad Tecnica Federico Santa Maria, in
Valparaiso, Chile, in 1977 and the Dr.-Ing. degree in
electrical engineering from the University of Erlangen,
Erlangen, Germany, in 1985.
He has been with the Department of Electronics
Engineering, Universidad Tecnica Federico Santa
Maria, since 1977, where he was full Professor and
President. Since 2015 he was the President and since 2019 he is full professor at

0278-0046 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Brighton. Downloaded on June 20,2021 at 23:43:43 UTC from IEEE Xplore. Restrictions apply.