UNIT – III

Control Unit
 Introduction

• Instruction Set Processor (ISP)

• Central Processing Unit (CPU)
• A typical computing task consists of a series of steps specified by a
sequence of machine instructions that constitute a program.
• An instruction is executed by carrying out a sequence of more
rudimentary operations.
 Fundamental Concepts

• Processor fetches one instruction at a time and perform the operation

specified.
• Instructions are fetched from successive memory locations until a branch
or a jump instruction is encountered.
• Processor keeps track of the address of the memory location containing
the next instruction to be fetched using Program Counter (PC).
• Instruction Register (IR)
 Executing an Instruction

• Fetch the contents of the memory location pointed to by the PC. The
contents of this location are loaded into the IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable, increment the contents of
the PC by 4 (fetch phase).
PC ← [PC] + 4
• Carry out the actions specified by the instruction in the IR (execution
phase).
 Processor Organization
Internal processor
bus

Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1 
control ALU
lines
Carry-in Datapath
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

 Internal organization of the processor

• ALU
• Registers for temporary storage
• Various digital circuits for executing different micro operations.(gates,
MUX , decoders , counters).
• Internal path for movement of data between ALU and registers.
• Driver circuits for transmitting signals to external units.
• Receiver circuits for incoming signals from external units.
• PC:
 Keeps track of execution of a program
 Contains the memory address of the next instruction to be fetched and
executed.

• MAR:
 Holds the address of the location to be accessed.
 I/P of MAR is connected to Internal bus and an O/p to external bus.

• MDR:
 Contains data to be written into or read out of the addressed location.
 IT has 2 inputs and 2 Outputs.
 Data can be loaded into MDR either from memory bus or from internal
processor bus.

The data and address lines are connected to the internal bus via MDR and MAR
Registers:
 The processor registers R0 to Rn-1 vary considerably from one processor to
another.
 Registers are provided for general purpose used by programmer.
 Special purpose registers-index & stack registers.
 Registers Y,Z &TEMP are temporary registers used by processor during the
execution of some instruction.
Multiplexer:
 Select either the output of the register Y or a constant value 4 to be provided as
input A of the ALU.
 Constant 4 is used by the processor to increment the contents of PC.
ALU:
Used to perform arithmetic and logical operation.
Data Path:
The registers, ALU and interconnecting bus are collectively referred to as the data
path.
 Register Transfers Internal processor
bus

The input and output gates for register Ri Riin

are controlled by signals is Rin and Riout .

Ri

Rin Is set to1 – data available on common

Ri out
bus are loaded into Ri.
Yin

Riout Is set to1 – the contents of register

are placed on the bus. Y

Constant 4
Riout Is set to 0 – the bus can be used for
Select MUX
transferring data from other registers .
A B
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
 Data transfer between two registers

EX:
Transfer the contents of R1 to R4.
1. Enable output of register R1 by setting R1out=1. This places the contents of R1 on
the processor bus.
2. Enable input of register R4 by setting R4in=1. This loads the data from the
processor bus into register R4.
 Performing an Arithmetic or Logic Operation
The ALU is a combinational circuit that has no internal storage.
ALU gets the two operands from MUX and bus. Internal processor
bus
Riin
The result is temporarily stored in register Z.
Ri
The sequence of operations to add the contents of register R1 to
those of R2 and store the result in R3 is:
Riout
1. R1out, Yin
Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in Y

Constant 4

Step 1: Output of the register R1 and input of the Select MUX

register Y are enabled, causing the contents of R1 to
be transferred to Y. A B
ALU
Step 2: The multiplexer’s select signal is set to select
Y causing the multiplexer to gate the contents of Zin
register Y to input A of the ALU.
Z

Step 3: The contents of Z are transferred to the

Z out
destination register R3.
Figure 7.2. Input and output gating for the registers in Figure 7.1.
 Register Transfers

• All operations and data transfers are controlled by the processor clock.
Bus

D Q
1
Q
Riout

Ri in
Clock

Figure7.3.
Figure 7.3.Input
Input
andand output
output gating
gating for register
for one one register
bit. bit.
 Fetching a Word from Memory
• Address into MAR; issue Read operation; data into MDR.
Memory-b us Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Figure 7.4. Connection and control signals for register MDR.

Figure 7.4. Connection and control signals for register MDR.

The response time of each memory access varies (cache miss, memory-mapped I/O,…).
To accommodate this, the processor waits until it receives an indication that the
requested operation has been completed (Memory-Function-Completed, MFC).
Move (R1), R2
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]
 Timing

Step 1 2 3

Clock

MARin
Assume MAR
is always available Address
on the address lines
of the memory bus. Read

MR

 Move (R1), R2 MDRinE

1. R1out, MARin, Read

Data
2. MDRinE, WMFC
3. MDRout, R2in MFC

MDR out

Figure 7.5. Timing of a memory Read operation.

 Storing a word in memory

• Address is loaded into MAR

• Data to be written loaded into MDR.
• Write command is issued.
• Example : Move R2,(R1)
R1out,MARin
R2out,MDRin,Write
MDRoutE, WMFC
 Execution of a Complete Instruction

Internal processor
Add (R3), R1 bus

• Fetch the instruction Control signals

• Fetch the first operand (the contents of the PC

memory location pointed to by R3) Instruction

Address
• Perform the addition lines
decoder and
MAR control logic
• Load the result into R1
Memory
bus

MDR
Add (R3), R1 Data
lines IR

Step Action
Y
Constant 4 R0
1 PC out , MAR in , Read,Select4,Add, Zin
2 Zout , PC in , Y in , WMF C Select MUX
3 MDR out , IR in
Add
4 R3out , MAR in , Read Sub
A B
R n - 1 
ALU
control
5 R1out , Y in , WMF C lines
ALU
Carry-in
6 MDR out , SelectY,Add, Zin XOR TEMP

7 Zout , R1in , End

Z

Figure7.6. Control sequence

for executionof theinstructionAdd (R3),R1.
Figure 7.1. Single-bus organization of the datapath inside a processor.
 Execution of Branch Instructions
• A branch instruction replaces the contents of PC with the branch target
address, which is usually obtained by adding an offset X given in the
branch instruction.
• The offset X is usually the difference between the branch target address
and the address immediately following the branch instruction.
• UnConditional branch
 Execution of Branch Instructions

StepAction

1 PCout , MAR in , Read,Select4,Add, Zin

2 Zout, PCin , Yin, WMF C
3 MDRout , IR in
4 Offset-field-of-IR
out, Add, Zin

5 Zout, PCin , End

Control sequence for an unconditional branch instruction.

 Multiple-Bus Organization
Bus A Bus B Bus C

• Allow the contents of two

Incrementer

PC different registers to be accessed

simultaneously and have their
Register
file
contents placed on buses A and
B.
Constant 4
• Allow the data on bus C to be
MUX

A loaded into a third register during

ALU R
the same clock cycle.
B
• Incrementer unit.
Instruction
decoder • ALU simply passes one of its
IR
two input operands unmodified to
bus C
MDR
 control signal: R=A or R=B
MAR

Memory bus Address

data lines lines

Figure 7.8. Three-bus organization of the datapath.

• General purpose registers are combined into a single block called registers.
• 3 ports,2 output ports –access two different registers and have their
contents on buses A and B
• Third port allows data on bus c during same clock cycle.
• Bus A & B are used to transfer the source operands to A & B inputs of the
ALU.
• ALU operation is performed.
• The result is transferred to the destination over the bus C.
• ALU may simply pass one of its 2 input operands unmodified to bus C.
• The ALU control signals for such an operation R=A or R=B.
• Incrementer unit is used to increment the PC by 4.
• Using the incrementer eliminates the need to add the constant value 4 to
the PC using the main ALU.
• The source for the constant 4 at the ALU input multiplexer can be used to
increment other address such as load multiple & store multiple
 Multiple-Bus Organization

• Add R4, R5, R6

StepAction

1 PCout, R=B, MAR in , Read, IncPC

2 WMFC
3 MDRoutB, R=B, IR in
4 R4outA, R5outB, SelectA,Add, R6in, End

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.
• Step 1:The contents of PC are passed
through the ALU using R=B control signal & loaded into MAR to start a
memory read operation
At the same time PC is incremented by 4
• Step 2:The processor waits for MFC
• Step 3: Loads the data ,received into MDR ,then transfers them to IR.
• Step 4: The execution phase of the instruction requires only one control
step to complete.
• To execute instructions, the processor must have some means of
generating the control signals needed in the proper sequence.
• Two categories: hardwired control and micro programmed control
 Hardwired Control
To execute instructions, the processor must have some means of generating the
control signals needed in proper sequence.

The sequence of operations carried out by machine is determined by wiring of

logic elements hence called Hardwired Control.

Hardwired system can operate at high speed; but with little flexibility.

Required control signals are determined by the following information:

• Contents of the control step counter
• Contents of the instruction register
• Contents of the condition code flags
• External input signals such as MFC and interrupt requests
 Control Unit Organization

CLK Control step

Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals

Figure 7.10. Control unit organization.

Step decoder provides a separate signal line for each time slot or step in control sequence
O/P of decoder consists of separate line for each machine instruction
I/P signals to encoder are combined to generate individual control signals Z in and Zout

CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS 1
External
INS 2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

I/P signals to encoder are combined to generate individual control signals Z in

Generating Zin

• Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
I/P signals to encoder are combined to generate individual control signals i.e. End signal
This end signal starts a new instruction fetch cycle by resetting the control step counter to its starting value.

Another RUN signal is used when set=1, causes counter to be incremented by 1 at the end of every clock cycle,

When RUN=0 the counter stops counting, this used when WMFC is issued
Generating End Signal

• End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…

Branch<0
Add Branch
N N

T7 T5 T4 T5

End

Figure 7.13. Generation of the End control signal.

 A Complete Processor

Instruction Integer Floating-point

unit unit unit

Instruction Data
cache cache

Bus interface
Processor

System bus

Main Input/
memory Output

Figure 7.14. Block diagram of a complete processor.

Microprogrammed Control
 Microprogrammed Control
• Control signals are generated by a program similar to machine language
programs.
• Control Word (CW); micro routine; microinstruction

MDRout

WMFC
MAR in

Select
PCout
Micro -

R1out

R3out
Read
PCin

R1 in
Add

End
Z out
IRin
Yin
instruction

Zin
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An example of microinstructions for Figure 7.6.

 Overview

Step Action

1 PC out , MAR in , Read,Select4,Add, Zin

2 Zout , PC in , Y in , WMF C
3 MDR out , IR in
4 R3out , MAR in , Read
5 R1out , Y in , WMF C
6 MDR out , SelectY,Add, Zin
7 Zout , R1in , End

Figure7.6. Control sequence

for executionof theinstructionAdd (R3),R1.
 Basic organization of a micro programmed control unit

Starting
• One function
Control store IR address
generator cannot be carried
out by this simple
organization.

Clock P C

Control
store CW

Figure 7.16. Basic organization of a microprogrammed control unit.

 Conditional branch
• The previous organization cannot handle the situation when the control unit is
required to check the status of the condition codes or external inputs to
choose between alternative courses of action.
• Use conditional branch microinstruction.

Address
Microinstruction

0 PCout , MAR in ,Read,Select4,Add, Zin

1 Zout , PCin , Yin , WMF C
2 MDRout , IRin
3 Branchtostartingaddress ofappropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, thenbranchtomicroinstruction
0
26 Offset-field-of-IR
out ,SelectY,Add, Zin

27 Zout , PCin , End

Figure 7.17. Microroutine for the instruction Branch<0.

 Microprogrammed Control
External
inputs

Starting and
branch address Condition
IR codes
generator

Clock m PC

Control
store CW

Figure 7.18. Organization of the control unit to allow conditional branching in

the microprogram.
 Microinstructions

• A straightforward way to structure microinstructions is to assign one bit

position to each control signal.
• However, this is very inefficient.
• The length can be reduced: most signals are not needed simultaneously,
and many signals are mutually exclusive.
• All mutually exclusive signals are placed in the same group in binary
coding.
Partial Format for the Microinstructions
Microinstruction

F1 F2 F3 F4 F5

F1 (4 bits) F2 (3 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits)

0000: No transfer 000: No transfer 000: No transfer 0000: Add 00: No action
0001: PCout 001: PCin 001: MARin 0001: Sub 01: Read
0010: MDRout 010: IRin 010: MDRin 10: Write
0011: Zout 011: Z in 011: TEMP in
0100: R0out 100: R0in 100: Y in 1111: XOR
0101: R1out 101: R1in
0110: R2out 110: R2 in 16 ALU
functions
0111: R3 out 111: R3 in
1010: TEMPout
1011: Offset out

F6 F7 F8

F6 (1 bit) F7 (1 bit) F8 (1 bit)

0: SelectY 0: No action 0: Continue

1: Select4 1: WMFC 1: End

Figure 7.19. An example of a partial format for field-encoded microinstructions.

 Micro program Sequencing

• If all micro programs require only straightforward sequential execution of

microinstructions except for branches, letting a μPC governs the
sequencing would be efficient.
• However, two disadvantages:
 Having a separate micro routine for each machine instruction results in a
large total number of microinstructions and a large control store.
 Longer execution time because it takes more time to carry out the
required branches.
• Example: Add Src, Rdst
• Four addressing modes: register, auto increment, auto decrement, and
indexed (with indirect forms).
- Bit-ORing
- Wide-Branch Addressin
- WMFC
 Mode

Contents of IR OP code 0 1 0 Rsrc Rdst

11 10 8 7 4 3 0

Address Microinstruction
(octal)

000 PCout, MARin , Read, Select4 , Add, Zin

001 Zout , PCin, Yin, WMFC
002 MDRout, IRin
003 m Branch {m PC ¬ 101 (from Instruction decoder);
m PC5,4 ¬ [IR10,9]; m PC3 ¬ [IR 10]×[IR9]×[IR8]}
121 Rsrcout , MARin , Read, Select4, Add, Zin
122 Zout , Rsrcin
123 mBranch {mPC ¬ 170;mPC0 ¬ [IR8]}, WMFC
170 MDRout, MARin , Read, WMFC
171 MDRout, Yin
172 Rdstout , SelectY, Add, Zin
173 Zout , Rdstin , End

Figure 7.21. Microinstruction for Add (Rsrc)+,Rdst.

Note: Microinstruction at location 170 is not executed for this addressing mode.
 Microinstructions with Next-Address Field

• The microprogram requires several branch microinstructions, which

perform no useful operation in the datapath.
• A powerful alternative approach is to include an address field as a part of
every microinstruction to indicate the location of the next
microinstruction to be fetched.
• Pros: separate branch microinstructions are virtually eliminated; few
limitations in assigning addresses to microinstructions.
• Cons: additional bits for the address field (around 1/6)
Microinstructions with Next-Address Field
IR

External Condition
Inputs codes

Decoding circuits

 AR

Control store

Next address IR

Microinstruction decoder

Control signals

Figure 7.22. Microinstruction-sequencing organization.

 Microinstruction

F0 F1 F2 F3

F0 (8 bits) F1 (3 bits) F2 (3 bits) F3 (3 bits)

Address of next 000: No transfer 000: No transfer 000: No transfer

microinstruction 001: PC out 001: PCin 001: MAR in
010: MDR out 010: IRin 010: MDR in
011: Z out 011: Z in 011: TEMP in
100: Rsrc out 100: Rsrc in 100: Y in
101: Rdst out 101: Rdst in
110: TEMP out

F4 F5 F6 F7

F4 (4 bits) F5 (2 bits) F6 (1 bit) F7 (1 bit)

0000: Add 00: No action 0: SelectY 0: No action

0001: Sub 01: Read 1: Select4 1: WMFC
10: Write
1111: XOR

F8 F9 F10

F8 (1 bit) F9 (1 bit) F10 (1 bit)

0: NextAdrs 0: No action 0: No action

1: InstDec 1: ORmode 1: OR indsrc

Figure 7.23. Format for microinstructions in the example of Section 7.5.3.

 Implementation of the Micro routine
Octal
address F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10

0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0
0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0 2 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

1 2 1 0 1 0 1 0 0 1 0 1 0 0 01 1 0 0 1 0 0 0 0 01 1 0 0 0 0
1 2 2 0 1 1 1 1 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 00 0 1 0 0 1

1 7 0 0 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0
1 7 1 0 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 7 2 0 1 1 1 1 0 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 7 3 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 7.24. Implementation of the microroutine of Figure 7.21 using a

next-microinstruction address field. (See Figure 7.23 for encoded signals.)
 R15in R15out R0 in R0out

Decoder

Decoder

IR Rsrc Rdst

InstDecout
External
inputs ORmode
Decoding
circuits
Condition ORindsrc
codes

AR

Control store

Next address F1 F2 F8 F9 F10

Rdst out

Rdst in
Microinstruction
decoder
Rsrc out

Rsrc in

Other control signals

Figure 7.25. Some details of the control-signal-generating circuitry.

bit-ORing