14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 1

Efficient VLSI Implementation of Modulo 2n 1  Addition and Multiplication

Reto Zimmermann
Swiss Federal Institute of Technology (ETH)
Integrated Systems Laboratory
CH-8092 Zürich, Switzerland
[email protected]

Abstract 1.1. Foundations

New VLSI circuit architectures for addition and multi- Binary numbers with  bits are denoted as

  
plication modulo 2   1  and 2   1  are proposed that 1
2 0 in the following text, where
allow the implementation of highly efficient combinational
and pipelined circuits for modular arithmetic. It is shown 1  

2  (1)
that the parallel-prefix adder architecture is well suited to 
0
realize fast end-around-carry adders used for modulo addi-
tion. Existing modulo multiplier architectures are improved Reduction of a number modulo a number  (“ mod
for higher speed and regularity. These allow the use of  ”) can be accomplished by a division (with the remain-
common multiplier speed-up techniques like Wallace-tree der as result) or by iteratively subtracting the modulus until
addition and Booth recoding, resulting in the fastest known   . For the moduli 2   1  and 2   1 , the mod-
modulo multipliers. Finally, a high-performance modulo ulo reduction of a number with at most 2 bits can be
multiplier-adder for the IDEA block cipher is presented. computed simply by an addition or subtraction. Since
The resulting circuits are compared qualitatively and quan-
titatively, i.e., in a standard-cell technology, with existing 2 mod 2   1 
2   2   1 
1 (2)
solutions and ordinary integer adders and multipliers. the reduction modulo 2   1  can be formulated as

mod 2   1 
 mod 2   div 2   mod 2   1 
(3)
1. Introduction
where the modulo operation on the right hand side is used
for final correction if the addition yields a result  2   1
Arithmetic modulo 2   1  (Mersenne numbers) and (i.e., 2   1 has to be subtracted once). Thus, the modulo
modulo 2   1  (Fermat numbers) is used in various ap- 2   1  reduction is computed by adding the high  -bit
plications, e.g., residue number systems (RNS) [11] and word ( div 2  ) to the low  -bit word ( mod 2  ) and then
cryptography [8]. Efficient and fast modulo adders and conditionally subtracting 2   1 [5].
multipliers are a prerequisite for corresponding high per- Analogously, since
formance integrated circuits. The main focus in this work
is on modulo 2   1  multiplication as used in the IDEA 2  mod 2   1 
2   2   1 
 1 (4)
(International Data Encryption Algorithm) block cipher [8].
As tangential results, modulo 2   1  addition and modulo the reduction modulo 2   1  can be computed as
2   1  addition and multiplication are treated as well. The mod 2   1 
 mod 2   div 2   mod 2   1 
algorithms for addition are described and compared with (5)
existing solutions in Section 2, while the same is done for where the modulo operation on the right hand side is used
multiplication in Section 3. Section 4 describes the IDEA for final correction if the subtraction yields a negative result
modulo multiplier-adder. Experimental results are given in (i.e., 2   1 has to be added once). Thus, the modulo
Section 5. 2   1  reduction is computed by subtracting the high  -
This work has been funded in part by Ascom Systec AG and in part by bit word from the low  -bit word and then conditionally
Microswiss, a Microelectronics Program of the Swiss Government. adding 2   1 [5, 13].
14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 2

Furthermore, the modulo operator has the property that a !" " ":- .1 1 ' / "+,
%*+, - .1 1 ) 1 %*+, - : 01 ' / -+,: 0 1 )
sum (product) modulo  is equivalent to the sum (product) ##
$
:
1
of its operands modulo  : 1 3#2
# 1 #
2
   mod 
 mod   mod   mod  (6) %&" '( ") %*+" ' / "+ ) %*+" ' / "+ )


:0 :0 :0 :0
   mod 
 mod    mod   mod  (7)
(" " %*+, ": 01 ' / "+,
:0
1)
11
#2 4
5 7#
11
2. Modulo addition # 2 #
6" %*+" ' / "+ ) %*+" ' / "+ )
:0 :0 :0 :0
Modulo carry-propagate addition is the basic operation
in modular arithmetic: Figure 1. Prefix adder logic operators.


   mod 2   1 (8)
  and carry-out  , respectively. :  and  :  denote
All known solutions rely on end-around-carry adders and the group generate and propagate signals for the group of
our solution on parallel-prefix adders more particular, both bits 


at level  . The  operator is repeatedly applied
of which are introduced in this section. according to a given prefix structure of  levels in order to
compute the group generate signal  :0 (
   1 ) for each
2.1. Parallel-prefix adders bit position  .
Prefix structures and adders can be visualized using di-
In a prefix problem,  inputs  1  2  0 and an ar- rected acyclic graphs (DAGs) with the edges standing for
 
bitrary associative operator  are used to compute  outputs signals or signal pairs and the nodes representing the four
 
     1    0 for 
0


  1. Thus, each logic operators depicted in Fig. 1. Fig. 2 shows the general
output   is dependent on all inputs  of same or lower

prefix adder structure and Fig. 3 the parallel-prefix struc-

magnitude ( ). Carry propagation in binary addition is ture with the least depth (i.e., resulting in the fastest circuit)
a prefix problem [7]. The  -bit carry-propagate addition [15]. The square ( 8) and diamond (9 ) nodes form the pre-
  and postprocessing stages, respectively. The black nodes
 
2   
   (9) (  ) evaluate the prefix operator  and the white nodes ( : )

 pass the signals unchanged to the next prefix level. A variety
with input operands and , carry-in   , sum output ,
 of other prefix structures with different depths and sizes ex-
and carry-out  can be expressed by the logic equations: ist which represent alternative circuit area-delay trade-offs.
preprocessing: Also, an efficient algorithm for area optimization of prefix
   structures under arbitrary depths constraints exists [15].
 0 0  0 0  0 0 if 
0

  It is shown in [16] that — at least for cell-based design,
 otherwise

  
 (10)
e.g., standard cells — the class of prefix adders contains the
most efficient adder architectures for the entire range of area-
delay trade-offs, i.e., from the smallest ripple-carry adder
prefix computation:
(serial-prefix) to the fastest carry-lookahead adder (Sklansky
 0:  0: 
     parallel-prefix). The simple and highly regular structure
    : 1  :
  : 1  : 1 
:  : 
1  1  of prefix adders allows for easy synthesis, e.g., by netlist
1
generators in pure parameterized VHDL code [17].
1   :
 1   1   
: : 1  :
1 1 1

1 :  
(11) 2.2. End-around-carry adders
postprocessing: In end-around-carry adders, the carry-out is fed back into
  1
 :0 the carry-in, i.e.,
     

(12)  
   (13)

for 
0


  1, 
1


 , and 0  in order to realize some special function (see below). If done
where   and   are the operand input signals,   and   the with an ordinary adder, where the carry-out depends on the
generate and propagate,   the carry, and   the sum output carry-in, a combinational loop is created that may lead to an
signals at bit position  .  0 and  correspond to the carry-in unwanted race condition [4]. Different solutions exist:

14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 3

a n-1
b n-1
a n-2
b n-2

a n-1
b n-1
a n-2
b n-2
a1
b1
a0
b0

a1
b1
a0
b0
... preprocessing ... ... ...
c in

(gn-1 , p n-1 ) (g0 , p0 )

add.epsi///figures
carry-propagation
52 mm
82 structure) prefix structure
addmm1dz.epsi///figures
(prefix
c n p n-1 c1 p0 c0 75 59 mm

c in
... postprocessing ... c out
c out
... ...
s n-1

s n-2

s1

s0

s n-1

s n-2

s1

s0
Figure 2. Prefix adder structure.

Figure 4. End-around-carry parallel-prefix

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
adder structure.
0

1 Since the individual prefix levels in a parallel-prefix adder

sk.epsi///figures
2 82 36 mm basically implement incrementer structures (i.e., they com-
3 pute new generate signals depending on a group-generate
4
input signal of ‘0’ or ‘1’), an adder with incorporated out-
put incrementer can be built simply by adding an additional
prefix level [16]. Fig. 4 depicts the structure of such an
Figure 3. Parallel-prefix structure by Sklan- end-around-carry parallel-prefix adder. The prefix-structure
sky. size is only increased by  black nodes and the critical path
by one black node, which results in highly area and delay
efficient end-around-carry adders. Note that an  -bit end-
around-carry parallel-prefix adder has the same delay but
a) In some cases, an additional logical operation on the is smaller compared to an ordinary 2 -bit parallel-prefix
feedback carry can eliminate the race condition [4]. adder.
b) The addition is done in two cycles (i.e., the carry-out
of the first cycle is added in the second cycle) [2]. 2.3. Modulo 2n  1  addition
c) An adder followed by an incrementer is used.
Modulo 2   1  addition or, which is the same, one’s
d) Two adders compute both possible results (i.e., for a
complement addition can be formulated as
carry-in of ‘0’ and ‘1’) in parallel and the correct sum


is selected afterwards according to the carry-out.    2  1 


   1  mod 2 
However, the solutions a)–c) realize two carry propagations    mod 2   1 


 if   2   1
in series and thus are slow, while solution d) requires two 
 otherwise
adders and a multiplexer which results in a large circuit. One
(14)
approach for fast modulo addition is based on a modification The modulo 2  reduction is automatically performed if an  -
of the traditional carry-lookahead adder [4]. There, the bit adder is used. Note that the value “11 1” never occurs
logic formula for the carry-out is re-substituted as carry-in
and that only one single representation “00 0” of zero
in the logic formulae for the sum bits. Thereby, the carry- exists. Equation (14) can be rewritten using the condition
lookahead logic is roughly doubled since each sum bit now
  2 :
is a function of all input bits.

In our approach, an adder is required which computes    2   1 

the carry-out independently of the carry-in (i.e., only as
   1  mod 2 
   mod 2   1 

carry-out of the sum  ) and which propagates the 

 if   2

carry-in to the sum output very quickly (i.e., fast output  otherwise
incrementer) [12]. (15)
14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 4


Now, zero has a double representation (“00 0” and with the property that  1 is computed (i.e., an extra ‘1’
“11 1”). Since the new condition   2  is equiva- is added). In many applications, such as multipliers (see
lent to 
1, where  is the carry-out of the addition Section 3), this property can easily be dealt with. Here, the
 , equation (15) can be rewritten as value 2  must be treated separately as a special case.
   mod 2   1 
     mod 2 (16)
2.5. Modulo carry-save addition
which basically is equivalent to (13). Therefore, modulo
2   1  addition with a double representation of zero can be A carry-save adder adds three  -bit input operands 1 ,
2 , and 3 without carry-propagation, yielding a redundant
realized by the  -bit end-around-carry parallel-prefix adder 
of Fig. 4 with  
 . sum represented by a
sum-bit vector
 1  2  0
  
The additional condition of 
2   1
11 1 and a carry-bit vector
  1  1 :
 
found in (14) is equivalent to   1:0
1 (i.e., group propa-  

  
2 
1  2  3 (21)
gate signal computed in a prefix adder). Therefore, modulo
2   1  addition with a single representation of zero can be It is composed of  full-adders arranged in parallel and
realized by the end-around-carry parallel-prefix adder with has constant delay [6, 14].   2 carry-save adders can
  
    1:0 (i.e., with an additional OR-gate in the be arranged in a linear or tree structure for fast addition

carry-feedback path). of  operands, resulting in an adder array or adder tree

(Wallace tree), respectively [6]. In an adder array, the carry-
save adder at level  with redundant sum output    

2.4. Modulo 2n  1  addition

adds the addition operand to the redundant sum output

   1   1  of the adder at level   1:

Diminished-one number representation. For modulo

2   1  addition, the diminished-one number system is of-  
  
   1   11 11  


 (22)
ten used, where the number is represented by
 1 
and the value 0 is not used or treated separately [1] (i.e., where  can be regarded as carry-in and  
 as
 
requires an additional zero-indication bit which is omitted carry-out of the carry-save adder. Analogously to the end-
here). Ordinary addition in this number system looks as around carry-propagate adders in the previous text, a modulo
follows: 2   1  end-around carry-save adder array can be realized
 by feeding the carry-out 
 1 back into the carry-in  of


 the next level, i.e., 

  1 . A modulo 2   1  carry-
  1     1
1 
save adder array is realized by inverting the feedback carry,
 i.e., 

 1 . The same principle of feeding back the
 1
(17) 
carry-outs into the carry-ins can also be applied to adder
Modulo 2  1  addition can now be formulated as trees. Fig. 5 shows an  -operand end-around carry-save


   1  2   1  adder using (m,2)-compressors (   denotes the  -th bit of
  

   mod 2  ). As an example, Fig. 6 gives an (8,2)-compressor with
   1  mod 2   1 


 if   2 linear structure for adder arrays (slower, more regular) and
 with tree structure for adder trees (faster, less regular).
  1 otherwise
(18) Multi-operand adders can now be built using a modulo
The sum  is incremented if   2  , i.e., if carry-save adder array or tree and a final modulo carry-

0. Thus, modulo 2  1  addition can be realized by propagate adder. The resulting circuits are very similar to
the end-around-carry parallel-prefix adder with  
 ordinary multi-operand adders but more regular, since the

(i.e., with an inverter in the carry-feedback path): carry-outs have not to be accumulated but can be fed back
into the adder structure as carry-ins. Note that modulo
   1  mod 2   1 
     mod 2 2   1  adders with normal number representation require
(19) an additional correction term due to the property of (20).
The diminished-one number representation, however, of-
ten requires the conversion from and to the normal number 2.6. Discussion
representation using incrementation/decrementation, which
might be too expensive when compared to its advantages. The proposed modulo carry-propagate adders are supe-
rior to the solutions based on two carry propagations from
Normal number representation. Equation (19) can also
the literature [2]. It is also assumed that they result in smaller
be used for the modulo 2   1  addition of numbers in
circuits than the modified carry-lookahead adder from [4].
normal representation
A quantitative comparison with the latter, however, has not
   1  mod 2   1 
     mod 2  (20) been carried out due to its complex circuit structure.
14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 5

a 0,n-1 a m-1,n-1 a 0,2 a m-1,2 a 0,1 a m-1,1 a 0,0 a m-1,0 highly regular modulo carry-save adder arrays and trees can
... ... ... ... be realized.
m-4:0
C out C inm-4:0 In this paper, the multiplier from [13], which bases on
(m,2) (m,2) (m,2) (m,2) the diminished-one number representation, is improved by
csvadd.epsi
84 34 mm

term (i.e.,
eliminating the precomputation of a correction
counts the number of ‘0’ in the multiplier ) and by using a
faster final adder. Also, the algorithm is extended for Booth
s n-1 c n-1 s2 c2 s1 c1 s0 c0
recoding and for modulo 2   1  multiplication as well as
for modulo 2   1  multiplication using normal number
Figure 5. m-operand end-around carry-save representation.
adder using (m,2)-compressors.
3.1. Modulo 2n  1  multiplication
a0a1 a2a3a4a5a6a7
a0a1 a2a3 a4a5 a6a7
According to (3), modulo 2   1  multiplication can be
FA 0
c out FA FA c in0 formulated as


0
c out c in0 1
c out c in1
 mod 2   1  (24)
FA




  mod 2    div 2   mod 2   1 
2
1 c out FA FA c in2
c out c in1
cpr82lin.epsi cpr82tree.epsi
3
c in3


37 c out
FA 52 mm 42 50 mm
2
c out c in2 4

where  mod 2  corresponds to the low output word and
c in4

c out FA
div 2  to the high output word of the multiplication


3
c out c in3
 . Therefore, modulo 2   1  multiplication can be
4
c out c in4

FA
FA
accomplished by an  -bit unsigned multiplication followed
by an  -bit modulo 2   1  addition. The major drawback
c s
c s
of this solution is that two carry-propagate adders in series
(a) (b)
are required (i.e., one as final adder in the multiplier and one
in the modulo adder), resulting in a larger and considerably
Figure 6. (a) Linear- and (b) tree-structured slower circuit compared to an ordinary multiplier. On the
(8,2)-compressor. other hand, a standard unsigned multiplier can be used for
modulo multiplication.
However, one carry-propagate addition can be saved if
3. Modulo multiplication the redundant product 
   after the carry-save adder
(i.e., before the final adder) is already reduced by the modu-
For modulo multiplication, lus. Then, the addition of (24) is not required anymore and

one single modulo 2  1  adder is sufficient to resolve

 mod 2   1 (23) the redundant product representation. A modulo-reduced
redundant product 
   can be obtained by
various ROM-based solutions using table-lookup have been
proposed and compared [10, 3]. Sophisticated methods exist 1. modulo-reducing the partial products [3], and
to reduce the table sizes by combining smaller table-lookups
2. using modulo carry-save addition to add them up.
with simple arithmetic operations, such as additions. For
word lengths larger than eight bits, however, these solutions Equation (24) can be rewritten as sum of partial products:
still require prohibitively large ROMs or many clock cycles
for evaluation.

 mod 2   1  (25)
For high-performance modulo multiplication, dedicated
1 
multipliers are required which can be implemented as com-
2    mod 2   1 
binational or pipelined circuits. Solutions based on ordinary 
0
integer multiplication with subsequent modulo correction
using adders are proposed in [3, 5]. A modulo 2   1  multi- 
1  

 2  mod 2   1   mod 2   1 
plier architecture with modulo-reduced, Booth-recoded par- 
0
tial products and with concurrent modulo reduction during

1  
carry-save addition is proposed in [3] and improved in [9].
 2  mod 2   2  div 2   mod 2   1 
It is shown in [13] that modulo 2   1  multipliers with 
0
14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 6

X Y Table 1. Bit-pair recoded modulo 2n  1  par-

tial products.
modulo partial-product generator
2
".1 2
" 2
" ,1 //"
...

PPn-1 PP0 0 0 0 0 0   0 0   0
mulmodm1.epsi
  , ",  ,  , "
0 0 1 2 1  0 1 
 , ",  , "
2
modulo44
carry-save
43 mm adder
  ,
0 1 0 2 1  0 1 
 , ",  , " ,
2

  ,
PC PS 0 1 1 2 2 2  0 1 
 "  "
2 1
  
1 0 0 2

,
 " 2 ,2    0
 
, 1  , ,
  2" 1
modulo carry-propagate adder
1 0 1  , ,
  2" 1
   ,    ,

,2 ,1     0   ,1      ,2"
0 1 2
1 1 0 
P
1 1 1  0 0   0 0   0
Figure 7. Modulo 2n  1  multiplier architec-
ture.
tiplication is to reduce the number of partial products by


1

applying bit-pair recoding (Booth recoding) [6]. Equation

      1  0 0 0  0 0 1   
 
(1) can be rewritten for the multiplier as
 
0 mod 2   1 

 2
 

1
22  2  
 
2  2  2 1  (26)

      1  0   1     mod 2  1 
0
1
  

0  2   1 0  1  2

1 where    1    1
0. The resulting   2  1 bit pairs

  mod 2  1  2   1  2   are used to specify   2  1 partial products

0
according to Table 1 (note that the third bit  2  1 must also
where  
    1  0  1   (implemented

be considered), which are summed up as follows:
   
using AND-gates) is the  -th partial product modulo 2  1 . 
Note that all  -bit partial products   have the same mag-

 2
nitude (as opposed to ordinary multiplication, where the  mod 2   1 
  mod 2   1 (27)

partial products have increasing magnitude), i.e., the num- 0

ber of product bits to add is the same for all bit positions. The carry-save adder is thereby cut in half (i.e., only half
This allows their addition by a highly regular modulo carry- the number of partial products have to be added) while some
save adder composed of  ( ,2)-compressors, yielding the recoding logic is added. With respect to circuit delay, the re-
modulo-reduced redundant product 
  . Fig. 7 depicts coding logic is roughly compensated by the shallower adder
the multiplier architecture with the partial-product genera- tree (note that in an adder tree, only about two full-adders
tion,  -operand carry-save addition, and carry-propagate are saved on the critical path if the number of operands
addition steps, which are all performed modulo 2   1  is cut in half). Delay can only be reduced if a carry-save
(note that all signal buses are  bits wide). adder array is used. With respect to circuit area, it has been
observed that — at least for cell-based design using effi-
Wallace-tree addition. The first speed-up technique for
cient full-adder cells — the additional recoding logic is not
multiplication is to accelerate the addition of the partial prod-
necessarily compensated by the smaller carry-save adder.
ucts using a carry-save adder tree (Wallace tree) [6]. This
Therefore, bit-pair recoding not always yields faster and
technique is easily applicable to modulo carry-save adders
smaller multiplier circuits (see the results in Section 5).
(and thus to modulo multipliers), as already described in
Section 2. The resulting tree structures are even more reg-
ular than in ordinary multipliers, because the same number 3.2. Modulo 2n  1  multiplication
of bits is added for each bit position and the carry-outs
are fed back into the carry-ins. In cell-based design, the Modulo 2   1  multiplication is considered here for
lower regularity of tree structures compared to linear ones application in the IDEA cipher. That is,  -bit numbers
has a negligible impact on circuit area, while a considerable in normal representation are used for operands and result,
speed-up is achieved. Therefore, the use of carry-save adder where the value 0 is not used and the value 2 is represented
trees is always recommended. by “00 0”. The presented algorithm can easily be adapted
for number representations with the value 0 included and the
Booth recoding. The second speed-up technique for mul- value 2  indicated by a separate bit.
14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 7

According to (5), modulo 2   1  multiplication using  ‘1’. The complement modulo 2  1  is computed as
the normal number representation can be formulated as

  mod 2   1 
 2 mod 2   1  (30)
 mod 2   1  (28)


The term    0 00 0 
  1 11 1  2  is

  mod 2    div 2   mod 2   1 
added in (29) so that the constant 1 10 0  2 can be
Likewise to modulo 2   1  multiplication, an  -bit un- factored out in order to get simpler partial products. Also,
signed multiplication followed by an  -bit modulo 2   1  the data-dependent correction term used in [13] can be
subtraction can be performed [3]. Again, the multiplication eliminated this way. A ‘1’ is added to each partial product
can be accelerated by performing partial-product generation in the second last equation of (29) for their modulo 2  1 
and carry-save addition modulo 2   1 . addition, as required in (20). The sum of the remaining
Equation (28) can be rewritten as sum of partial products: constants can be represented by one single constant term:


 mod 2   1  (29) 
1
  1  mod 2   1 
2
1
1 0
0 (31)

1   


2    mod 2  1  0


0
Thus, modulo 2   1  multiplication is per-

1  

  mod 2   1   mod 2   1  formed by adding the modulo-reduced partial products
 
       1  0   1        0 01 1
2

0
(implemented using simplified multiplexers due to constant

1  

  2  mod 2   2  div 2  mod 2  1  inputs) and the constant 2 by an   1 -operand carry-save
 addition and a final carry-propagate addition, which are all
0
performed modulo 2   1 . Note that a total of  modulo

1

      1  0 0 0  2   1  additions are carried out which, according to (20),
0 0 1    mod 2 
 also add the  ‘1’ found in the last equation of (29).
0  1
  The value 2  , which in our case is represented by 0 (and
1
    

    1  00 0  otherwise by an extra bit), must be treated separately. The

0  0 0  
following cases have to be distinguished:
 1  

   0 00 0   mod 2  1   2   mod 2   1 
   mod 2   1 





  2  mod 2   1  if
2

1     



    1  00 0  
2  mod 2   1 
  mod 2   1 


    
  2  mod 2   1  if 
2 
0 1 1  2  



 1   2  2  mod 2   1 
1

2


 if
 1 11 1  2   mod 2  1 

 mod 2   1  otherwise

1     (32)

    1  00 0  A 2  -correction unit is required to compute the redundant

0  0 0    product
 1 

 0 01 1 


 
 1  if
2
      1 10 0  2   mod 2   1  
  
 1 if 
2  (33)



1     0 0  if

2

   1  0   1     
  which is then selected by a multiplexer before the final adder.
0  0 01 1  1  Note that the constants from (32) are diminished by 1 in
1 10 0  1  mod 2   1  (33) because the final modulo adder adds an extra ‘1’. With
 1 2  represented by 0, the correction unit requires two zero-

    1  0  1    detectors which, however, are not on the critical path. One
    
0   0 01 1  1  additional multiplexer is on the critical path through the
multiplier. Fig. 8 depicts the architecture of the modulo
 2  mod 2   1 
2   1  multiplier.
 
1

   1   2  mod 2   1  Wallace-tree addition. As in modulo 2   1  multipli-

0
cation, adder trees can be applied very easily to speed up
where “0 01 1” denotes the number with    ‘0’ and carry-save addition in modulo 2   1  multiplication.
14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 8

X Y Table 2. Bit-pair recoded modulo 2n  1  par-

tial products.

2
".1 2
" 2
" ,1 //"


0 0 0 0 0   0 1   1
 , ",
,      ,2"
modulo partial-product generator
  
0 0 1 2 1  0
 , ",
PPn-1 ... PP0 0 1 0


2 1  0
 , ",
  1
,      ,2"
2 0 1 1


2 2 2  0
  1
,     ,2" ,1
2n - correction modulo carry-save adder
1 0 0 2
  "
, ,   
   ,1
1  ,2" ,1
 , "
mulmodp1.epsi
   2" 2 0 ,
P’C P’S 80 69 mm 1 0 1  , ,     0   1     2
1 1 0 

,2 ,1    0 ,1    ,2"
  2" 1
1 1 1  0 1   1 0   0

PC PS


Thereby, the two additional terms and  have to be
modulo carry-propagate adder
added in the modulo carry-save adder, resulting
in only a
P small area and delay increase. The special case of 
0
has to be treated separately and the constant correction term
Figure 8. Modulo 2n  1  multiplier architec- to be adapted.
ture.
3.4. Discussion
Booth recoding. Bit-pair recoding to reduce the number The described modulo 2   1  multiplier is almost as
of partial products is also possible for modulo 2   1  efficient as an ordinary integer multiplier with respect to


multiplication. An additional correction term is required circuit size and delay, but has an even more regular struc-
which depends on the multiplier by the logic equations: ture. Booth recoding and Wallace-tree addition can both be

applied for speed-up. The  -bit modulo final adder is as fast

10 1  10 1  0 1


0
   but smaller than the 2 -bit final adder used for  -bit integer

1  0 1


1
 multiplication.

 2  1  2   2  1  2 1   2  2 1 The same holds true for the modulo 2   1  multiplier


2
 
2 1
 2  1 (34) which is slightly less efficient due to the additional correction
term and the 2  -correction. It is suited for normal and
for 
1


 2  1. Also, the additional constant is 1 diminished-one number representation. The correction term
instead of 2. The derivation of the constant and correction is constant as opposed to [13], where the precomputation of
terms is not given here due to its complexity. The terms the data-dependent correction term adds a delay of some
have been exhaustively verified in a circuit implementation. full-adders (i.e., an   1 -bit counter). Compared to [9],
The  2  1 partial products are given in Table 2 and two carry-save adder stages for modulo reduction after the
summed up as follows: carry-save adder array are eliminated.


 mod 2   1  (35) 


 2 4. Modulo 2n  1  multiplication-addition

   1   1   mod 2  1 

0 In the IDEA cipher algorithm, two of the four modulo
2   1  multiplications required for one encryption round
3.3. Diminished-one multiplication are followed immediately by a modulo 2  addition [8]:


The modulo 2   1  multiplication algorithm of Fig. 8 
 mod 2   1 
can easily be adapted for the diminished-one number repre- 

   mod 2  (37)
sentation of input operands and output product [13]:



 mod 2   1  This multiply-add structure is on the critical path of the

IDEA data path and should therefore be made as fast as pos-
 1
  1    1  mod 2   1 


sible. A common speed-up technique is to include the output
 1
      1  mod 2   1 


addition as carry-save addition before the final adder of the

      mod 2   1  (36) multiplier, thus reducing the number of carry-propagation
14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 9

X Y Table 3. Unit-gate adder results.

adder area delay

3


integer  log 4 2 log 3
%
mod 2  1 )
modulo partial-product generator 2
3


log 7 2 log 5
%

mod 2 1 )
PPn-1 ... PP0
2
3


2
log 7 2 log 5
2
2n - correction modulo carry-save adder

P’C P’S
Table 4. Unit-gate multiplier results.
mulmodp1add.epsi
83 91 mm multiplier area delay
2

% )
2 log
6
integer  8 3 log  3 4
%
% )

mod 2  1 )
PC PS
2
3

8 log  7 4 2 log 6
%

%
)

mod 2 1 )
2
A 2
3


9 log11 4 1 2 log 9
%
)
2

2


%
)


mod 2 1 9 2 log 25 4 1 2 log 13
carry-save adder

SC SS

modulo carry-propagate adder

c out
modulo carry-propagate adder parallel-prefix adder architecture described in Section 2. A
modulo 2   1  multiplier, a modulo 2   1  multiplier
P S and multiplier-adder (denoted as “ mod 2   1   ”), and
an integer multiplier have been implemented using Wallace
Figure 9. Modulo 2n  1  multiplier-adder ar-
trees for carry-save addition and the modulo parallel-prefix
chitecture.
adders for final addition, but with no Booth recoding. All
units have been described as parameterized circuit genera-

steps in series from two to one. Because the product  and tors in synthesizable VHDL code [17].
the sum both are used as outputs, two parallel final adders
are required. And because the final adder of a modulo mul- 5.1. Unit-gate model
tiplier also performs a final modulo correction step (i.e., by
adding  according to (20)), the same correction has to Circuit size and delay estimates can be given on a unit-
be done in both final adders: gate basis. Thereby, each two-input monotonic gate (e.g.,


    1  mod 2  1  AND, NAND) counts as one gate (area and delay), an XOR
as two gates (area and delay), and a full-adder has an area


      mod 2 (38)
  of seven gates and a delay of four gates. Tables 3 and 4


    1  mod 2   1    mod 2  give the gate-count and gate-delay estimates as a function


       mod 2  of the word length  for the adders and multipliers, respec-
  tively. Thereby,    denotes the depth of the Wallace tree


     mod 2  (39)
  in multipliers [13]:
where
 

    is the carry-save addition of

%  3 4 5–6 7–9 10–13 14–19 20–28 29–42 43–63   
the redundant product  
   and the addend yielding )
 1 2 3 4 5 6 7 8 9 
the redundant sum 
 , and  is the inverted carry-
out of the final adder for product  (38). Fig. 9 depicts the
architecture of the modulo 2   1  multiplier-adder (again, 5.2. Standard-cell implementation
all buses are  bits wide). In this solution, the number of
carry propagations has been reduced from four when using Circuits have been synthesized from their VHDL de-
standard components (i.e., multiplier final adder, modulo scriptions and optimized for highest speed with the syn-
adder-incrementer, and output adder) down to one. thesis tools by Synopsys, Inc. A 0.25  m standard-cell
library under typical PTV conditions (i.e., typical process,
5. Implementations and results 25  C, 2.5 V) has been used. For comparison, integer and
modulo 2   1  adders and multipliers have been synthe-
A modulo 2   1  adder, a modulo 2   1  adder, sized using standard components from the Synopsys De-
and an integer adder have been implemented based on the signWare Foundation Library (denoted as “DW”) with the
14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, April 1999 10

Table 5. Standard-cell adder results. highly regular structure of the units allows their description
by circuit generators purely in parameterized synthesizable
8 bit 16 bit 32 bit 64 bit VHDL code, which makes them suitable for efficient imple-
adder
area delay area delay area delay area delay mentation of high-performance modulo-arithmetic units in
%
integer 4239 0.52 7137 0.71 15336 0.93 34065 1.14 modern cell-based VLSI technologies.
mod %2   1 ) 4365 0.78 10611 0.93 19269 1.17 43452 1.43
mod 2 1 )


4806 0.77 8181 1.06 23706 1.16 45000 1.44
References
%
DW integer 4923 0.55 15021 0.75 22608 0.89 50130 1.09
DW 2  1 ) 6975 0.92 14400 1.30 30771 1.58 70443 1.95 


[1] D. P. Agrawal and T. R. N. Rao. Modulo (2 1) arithmetic
logic. IEEE J. on Electronic Circuits and Syst., 2:186–188,
Nov. 1978.
Table 6. Standard-cell multiplier results.
[2] M. A. Bayoumi, G. A. Jullien, and W. C. Miller. A VLSI
8 bit 16 bit 32 bit implementation of residue adders. IEEE Trans. Circuits and
multiplier
area delay area delay area delay Syst., CAS-34(3):284–288, Mar. 1987.
% 
Regular
[3] A. V. Curiger, H. Bonnenberg, and H. Kaeslin. VLSI
% 1 ). IEEE J.
integer 16668 2.32 61542 3.33 237564 4.51
mod %2  1 ) 16740 2.54 60894 3.51 233127 4.83 architectures for multiplication modulo 2
mod %2 1 )

Solid-State Circuits, 26(7):990–994, July 1991.
20232 2.47 66213 3.60 236574 4.76
mod 2 1 )



23256 2.91 74835 3.95 258858 5.02 
[4] C. Efstathiou, D. Nikolos, and J. Kalamatianos. Area-time
efficient modulo 2  1 adder design. IEEE Trans. Circuits
%
DW integer 18306 2.55 57690 3.46 202131 4.26
DW mod 2  1 ) 22194 3.70 70902 4.98 228573 6.16 and Syst., 41(7):463–467, July 1994.
%
[5] A. Hiasat. New memoryless, mod 2 1 ) residue multiplier.
Electronics Letters, 28(3):314–315, Jan. 1992.
[6] I. Koren. Computer Arithmetic Algorithms. Prentice Hall,
fastest circuit architectures (i.e., fast carry-lookahead adder
1993.
“clf”, Booth-Wallace multiplier “wall”). Thereto, modulo
[7] R. E. Ladner and M. J. Fischer. Parallel prefix computation.
addition requires an integer adder and an incrementer (16),
J. ACM, 27(4):831–838, Oct. 1980.
while modulo multiplication requires an integer multiplier,
[8] X. Lai and J. L. Massey. A proposal for a new block encryp-
an adder, and an incrementer (24). The results are given in
tion standard. In Advances in Cryptology – EUROCRYPT’90,
Tables 5 and 6. The differences between the custom and the pages 389–404, Berlin, Germany: Springer-Verlag,
% 
1990.
1 ) multi-
DesignWare integer adders and multipliers are mainly due to [9] Y. Ma. A simplified architecture for modulo 2
the different carry-lookahead adder structures and to Booth plication. IEEE Trans. Comput., 47(3):333–337, Mar. 1998. 
recoding (i.e., not used in the custom multipliers). All cus- [10] A. Skavantzos and P. B. Rao. New multipliers modulo 2  1.
tom modulo arithmetic units show considerable speed and, IEEE Trans. Comput., 41(8):957–961, Aug. 1992.
in most cases, also area advantages compared to the solu- [11] M. A. Soderstrand, W. K. Jenkins, G. A. Jullien, and F. J.
tions based on standard components. The proposed modulo Taylor. Residue Number System Arithmetic: Modern Appli-
2   1  multiplier-adder allows the implementation of a cations in Digital Signal Processing. IEEE Press, New York,
high-performance IDEA cipher engine delivering up to 720 1986.
Mbit/s data rate at 100 MHz clock frequency. [12] A. Tyagi. A reduced-area scheme for carry-select adders.
IEEE Trans. Comput., 42(10):1162–1170, Oct. 1993.
6. Conclusions [13] Z. Wang, G. A. Jullien, and W. C. Miller. An efficient tree


architecture for modulo 2 1 multiplication. J. VLSI Signal
Processing Systems, 14(3):241–248, Dec. 1996.
Parallel-prefix adders with an additional prefix level have
[14] S. Wei and K. Shimizu. Modulo 2
 1 arithmetic hardware
been used to implement novel fast and simple end-around-
algorithm using signed-digit number representation. IEICE
carry adders for modulo 2   1  addition. Modulo 2   1  Trans. Inform. & Systems, E79-D(3):242–246, Mar. 1996.
multiplication has been realized using modulo-reduced par-
[15] R. Zimmermann. Non-heuristic optimization and synthesis
tial products, modulo carry-save adders, and a modulo final of parallel-prefix adders. In Proc. Int. Workshop on Logic and
adder, resulting in the fastest modulo multiplier circuits re- Architecture Synthesis, pages 123–132, Grenoble, France,
ported in the literature. Their architecture allows the use of Dec. 1996.
Wallace-tree addition and Booth recoding of partial prod- [16] R. Zimmermann. Binary Adder Architectures for Cell-Based
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has been presented for the efficient circuit implementation of Technology (ETH) Zurich, Hartung-Gorre Verlag, 1998.
of the IDEA block cipher. The performance of all pro- [17] R. Zimmermann. VHDL library of arithmetic units. In Proc.
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units for ordinary integer addition and multiplication. The Switzerland, Sept. 1998.