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Tutorial - 4: Control Lines (Choose The Function) Outputs

The document provides tutorials on implementing various logic circuits in Verilog including a 1-hot multiplexer, modular design of cascaded multiplexers, implementing a Boolean function with multiplexers, generating odd/even parity bits, and a logic unit with different functions selected by control lines.

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Rohan sharma
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158 views

Tutorial - 4: Control Lines (Choose The Function) Outputs

The document provides tutorials on implementing various logic circuits in Verilog including a 1-hot multiplexer, modular design of cascaded multiplexers, implementing a Boolean function with multiplexers, generating odd/even parity bits, and a logic unit with different functions selected by control lines.

Uploaded by

Rohan sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Tutorial -4

1. Verilog code to design a block that “selects 1 among 2n input lines and connects it the 1-bit
output line, based on the value of n-Bit input control lines”. For example, if value of n=3 and the
value of control line is 000 (or 111) the 1st (8th) input line is connected to the output.
For implementation, consider 3 select lines (i.e., n=3), where based on the value of n, the
corresponding input line is connected to the output.

Please implement using the following options


a. If-else
b. Case
c. Select lines as the index of the input Bus Array.

2. Now, we need to implement a “4:1 selector block”, but using “2:1 sector blocks”. Use modular
Verilog design for the same.

3. Implement the following Boolean Function F of three variables A,B,C using a selector block.
F(A,B,C)=A’B’C’ + A’B’C + A’BC + ABC (‘ implies complement).

4. Design a Verilog code to generate Odd/Even Parity Bit. The input is 4-Bit Binary Number on
which the parity bit is to be generated. There is another 1-Bit input, “odd_even”; if odd_even is
0 (1), odd (even) parity is to be generated. The output is a single Bit line “parity”.

5. Design a simple Logic Unit with the following functionalities.


Inputs: Control 2 Bits, A and B: 4 Bit Binary Numbers
Output: LU_out 1 Bit.

Control Lines (Choose the function) Outputs

| 00 | LU_Out = 0, if A > B;

LU_Out =1, if A <= B;

| 01 | LU_Out = 0, if A is even;

LU_Out = 1, if A is odd;

| 01 | LU_Out = 0, if B is even;

LU_Out = 1, if B is odd;

| 11 | LU_Out = 0, if A+B does not result in an overflow;

LU_Out = 1, if A+B result in an overflow

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