Southern Leyte State University - Main Campus

College of Engineering

CPE 316L - INTRODUCTION TO HARDWARE DESCRIPTION LANGUAGE (HDL)

Module 2 - Lab
Combinational Circuits

CO1. Design, Simulate various Verilog descriptions for Combinational circuits.

ILO1. Write the code for various adder/subtractor function to analyze its behavior to be verified
without actually manufacturing the circuit

Enabling Learning Outcomes:

1. Write a complete Verilog code of half adder and full adder, half and full
subtractor using three (3) different modelling styles.

Overview
Half Adder Module in Verilog

Half adders are a basic building block for new digital designers. A half-adder shows how two
bits can be added together with a few simple logic gates. In practice they are not often used because
they are limited to two one-bit inputs. For adding together larger numbers a full-adder can be used.
A single half-adder has two one-bit inputs, a sum output, and a carry-out output. Refer to figure 1, the
truth table of Half-adder to see how these bits operate.

In this module the sample code will be given for dataflow modeling of a half adder circuit.
There is also a test bench that stimulates the design and ensures that it behaves correctly.

1|P age
Verilog Code for Half Adder Gate Level Modelling

Verilog Testbench Code for Half Adder Gate Level Modelling

2|P age
Full Adder Module in Verilog

Full adders are a basic building block for new digital designers. Lots of introductory courses
in digital design present full adders to beginners. Once you understand how a full adder works, you
can see how more complicated circuits can be built using only simple gates. I just want to make it
clear to someone new that in reality, FPGA designers are not coding full adders by hand. The tools
are advanced enough to know how to add two numbers together. It's still a good exercise, which is
why it is presented here.

A single full-adder has two one-bit inputs, a carry-in input, a sum output, and a carry-out
output. Many of them can be used together to create a ripple carry adder which can be used to add
large numbers together. A single full-adder is shown in the picture below.

The next picture shows the entire schematic of the full adder and its corresponding truth
table. The red text ties into the code below. w_WIRE_1, w_WIRE_2, w_WIRE_3 are the intermediate
signals shown in the red text on the schematic.

3|P age
 Verilog Code for Full Adder in Gate Level Modelling

The Half-Subtractor circuit

A half-subtractor is a combinational circuit that performs the subtraction of two bits. It

consists of two inputs and two outputs. Consider that we want to subtract two 1-bit numbers. The
numbers are x and y. A difference bit (D) and a borrow bit (B) will be generated.

The binary subtraction consists of four possible elementary operations: 0-0, 0-1, 1-0, and 1-1.

4|P age
Half-Subtractor Truth table

Half-Subtractor Schematic Diagram

Verilog Code for Half Subtractor in Data-flow Modelling

5|P age
Verilog Testbench Code for Half Subtractor – Dataflow Modelling

Full Subtractor

A full subtractor is a combinational circuit that performs the subtraction of three bits. It
consists of three inputs and two outputs. Consider that we want to subtract three 1-bit numbers.
The numbers are X, Y and Z then a difference bit (D) and a borrow bit (B) will get generated.

Full Subtractor Truth table

6|P age
Full Subtractor Schematic Diagram

Verilog Code for Full Subtractor using Data-flow Modelling

Task: Write the Verilog code of the ff. combinational circuits using three (3) modelling style. Also
create it’s intended Testbench.

1. Half Adder

2 Full Adder

3.Half Subtractor

4. Full Subtractor

7|P age
Guidelines in creating/submitting outputs

1. You can use RecForth or any screen recorder application to record your
simulated outputs.

1.1 In case you do not have a computer, you can use Smartphone to record
your output.

2. In creating a video (recorded video), Start with greetings, then state your
Complete name, Course, Subject, and Title of the laboratory activites that you are
going to perform.

3. No need to write the code/program from scratch, all you have to do is to

discuss the code that you already have (5-10 mins). Just convince me that you
really understand what you are doing.

4. Privately comment THE LINK your recorded video/output simulation to the

following google classroom link.

Link: https://classroom.google.com/c/NDk4OTI2MzE5MTQz?cjc=uolh5gd

Class code : uolh5gd

4. Deadline: April 29, 2022

8|P age
Annex A.
RUBRIC IN PROJECTS/OUTPUTS

Projects/Outputs Level Points Indicators

Work/project is exceptional and impressive. A

distinctive sophisticated application of
Exemplary 10 knowledge and skills are evident.

Work/project exceeds the standard; thorough

and effective application of knowledge and
9 skills are evident
Strong

Work/project meets the standard; acceptable

and it displays the application of essential
Proficient 8 knowledge and skills

Work/project does not yet meet the standard;

show basic but inconsistent application of
Developing 7 knowledge and skills; work needs further
development

Work/project shows partial application of

knowledge and skills; lacks depth or
Emerging 6 incomplete and needs considerable
development errors and omissions are present

Learning 0 No work presented

Rating Scale:

10 1.0 – 1.5

9 1.6 – 2.0

8 2.1 – 2.5

7 2.6 – 3.0

6 3.1 – 3.5 Conditional

0 3.6 & above Failed

9|P age