Chapter 4

xi yi Carryin ci Sum s i Carryout c i+1

At the ith stage:
0 0 0 0 0 Input:
0 0 1 1 0 ci is the carry-in
0 1 0 1 0
0 1 1 0 1 Output:
1 0 0 1 0 si is the sum
1 0 1 0 1
1 1 0 0 1 ci+1 carry-out to (i+1)st
1 1 1 1 1 state
si = xi yi ci + xi yi ci + xi yi ci + xi yi ci = x i yi ci
ci+1 = yi c i + x i ci + x i y i

Example:

X 7 0 1 1 1 Carryout xi Carryin
+ Y = +6 = +00 1 1 1 1 0 0 0 yi
ci+1 ci
Z 13 1 1 0 1 si

Legendforstage i
 Sum Carry
yi
c
i
xi
xi
yi si c
c i +1
i
ci
x
xi yi i
yi

ci + 1 Fulladder ci
(FA)

s
i

Full Adder (FA): Symbol for the complete circuit

for a single stage of addition.
Cascade n full adder (FA) blocks to form a n-bit adder.
Carries propagate or ripple through this cascade, n-bit ripple carry adder.

xn 1
yn 1 x1 y1 x0 y0

cn 1
c1
cn FA FA FA c0

sn 1
s1 s0
Mostsignificantbit Leastsignificantbit
(MSB)position (LSB)position

Carry-in c0 into the LSB position provides a convenient way to

perform subtraction.
 K n-bit numbers can be added by cascading k n-bit adders.

xk n 1 yk n 1 x2n 1 y2n 1
xn y n xn 1
yn 1 x0 y0

cn
nbit nbit nbit c
c kn 0
adder adder adder

s s s s s s
kn 1 k 1 n 2n 1 n n 1 0

Each n-bit adder forms a block, so this is cascading of blocks.

Carries ripple or propagate through blocks, Blocked Ripple Carry Adder
Recall X Y is equivalent to adding 2s complement of Y to X.
2s complement is equivalent to 1s complement + 1.
X Y = X + Y + 1
2s complement of positive and negative numbers is computed similarly.

xn 1
yn 1 x1 y1 x0 y0

cn 1
c1
cn FA FA FA 1

sn 1
s1 s0
Mostsignificantbit Leastsignificantbit
(MSB)position (LSB)position
 y y y
n 1 1 0
Add/Sub
control

x x x
n 1 1 0

c nbitadder
n c
0

s s s
n 1 1 0

Add/sub control = 0, addition.

Add/sub control = 1, subtraction.
Detecting overflows
Overflows can only occur when the sign of the two operands is
the same.
Overflow occurs if the sign of the result is different from the
sign of the operands.
Recall that the MSB represents the sign.
xn-1, yn-1, sn-1 represent the sign of operand x, operand y and result s
respectively.
Circuit to detect overflow can be implemented by the
following logic expressions:

Overflow xn 1 yn 1sn 1 xn 1 yn 1sn 1

Overflow cn cn 1
 x0 y0
Consider 0th stage:
c1 is available after 2 gate delays.
s1 is available after 1 gate delay.
c1 FA c0

s0

Sum Carry
yi
c
i
xi
xi
yi si c
c i +1
i
ci
x
i
yi
 Cascade of 4 Full Adders, or a 4-bit adder

x0 y0 x0 y0 x0 y0 x0 y0

FA FA FA FA c0
c4 c3 c2 c1

s3 s2 s1 s0

s0 available after 1 gate delays, c1 available after 2 gate delays.

s1 available after 3 gate delays, c2 available after 4 gate delays.
s2 available after 5 gate delays, c3 available after 6 gate delays.
s3 available after 7 gate delays, c4 available after 8 gate delays.
For an n-bit adder, sn-1 is available after 2n-1 gate delays
cn is available after 2n gate delays.
Recall the equations:

si xi yi ci
ci 1 xi yi xi ci yi ci
Second equation can be written as:

ci 1 xi yi ( xi yi )ci
We can write:
ci 1 Gi Pi ci
where Gi xi yi and Pi xi yi

Gi is called generate function and Pi is called propagate function

Gi and Pi are computed only from xi and yi and not ci, thus they can
be computed in one gate delay after X and Y are applied to the
inputs of an n-bit adder.
 ci 1 Gi Pi ci
ci Gi 1 Pi 1ci 1
ci1 Gi Pi (Gi 1 Pi 1ci 1 )
continuing
ci1 Gi Pi (Gi 1 Pi 1 (Gi 2 Pi 2 ci 2 ))
until
ci1 Gi PiGi 1 Pi Pi1 Gi 2 .. Pi Pi 1 ..P1G0 Pi Pi 1 ...P0 c 0
All carries can be obtained 3 gate delays after X, Y and c0 are applied.
-One gate delay for Pi and Gi
-Two gate delays in the AND-OR circuit for ci+1
All sums can be obtained 1 gate delay after the carries are
computed.
Independent of n, n-bit addition requires only 4 gate delays.
This is called Carry Lookahead adder.
 x y x y x y x y
3 3 2 2 1 1 0 0

c4
c
3
c
2
c
1
. c
4-bit
carry-lookahead
Bcell Bcell Bcell Bcell 0

adder
s s s s
3 2 1 0

G3 P3 G2 P2 G P G P
1 1 0 0

Carrylookaheadlogic
xi yi

. .
. c
i

B-cell for a single stage

Bcell

Gi P i
si
Carry lookahead adder (contd..)
Performing n-bit addition in 4 gate delays independent of n is
good only theoretically because of fan-in constraints.

ci1 Gi PiGi 1 Pi Pi1 Gi 2 .. Pi Pi 1 ..P1G0 Pi Pi 1 ...P0 c0

Last AND gate and OR gate require a fan-in of (n+1) for a n-bit
adder.
For a 4-bit adder (n=4) fan-in of 5 is required.
Practical limit for most gates.
In order to add operands longer than 4 bits, we can cascade 4-bit
Carry-Lookahead adders. Cascade of Carry-Lookahead adders is
called Blocked Carry-Lookahead adder.
 Carry-out from a 4-bit block can be given as:
c4 G3 P3 G2 P3 P2 G1 P3 P2 P1 G0 P3 P2 P1P0 c0
Rewrite this as:

P0I P3 P2 P1 P0
G0I G3 P3 G2 P3 P2 G1 P3 P2 P1G0
Subscript I denotes the blocked carry lookahead and identifies the block.

Cascade 4 4-bit adders, c16 can be expressed as:

I I I I I I I I 0 I I I 0 0
c16 G3 P3 G2 P3 P2 G1 P3 P2 P1 G0 P3 P2 P1 P0 c0
 x1512 y1512 x118 y118 x74 y74 x30 y30

c16 4bitadder
c12
4bitadder
c8
4bitadder
c4
4bitadder . c0

s1512 s118 s74 s30

G3 I P3 I G2 I P 2I G 1I P 1I G 0I P0 I

Carrylookaheadlogic

After xi, yi and c0 are applied as inputs:

- Gi and Pi for each stage are available after 1 gate delay.
- PI is available after 2 and GI after 3 gate delays.
- All carries are available after 5 gate delays.
- c16 is available after 5 gate delays.
- s15 which depends on c12 is available after 8 (5+3)gate delays
(Recall that for a 4-bit carry lookahead adder, the last sum bit is
available 3 gate delays after all inputs are available)
Product of 2 n-bit numbers is at most a 2n-bit number.
Unsigned multiplication can be viewed as addition of shifted
versions of the multiplicand.
 Multiplication of unsigned
numbers (contd..)
We added the partial products at end.
Alternative would be to add the partial products at each stage.

Rules to implement multiplication are:

If the ith bit of the multiplier is 1, shift the multiplicand and add the
shifted multiplicand to the current value of the partial product.
Hand over the partial product to the next stage
Value of the partial product at the start stage is 0.
 Typical multiplication cell

Bitofincomingpartialproduct(PPi)
jthmultiplicandbit

ithmultiplierbit ithmultiplierbit

carryout FA carryin

Bit of outgoing partial product (PP(i+1))

 Combinatorial array multiplier
Multiplicand
0 m3 0 m2 0 m1 0 m0
(PP0)
q0
0
PP1 p0
q1
0

r
lie
PP2

tip
p1

ul
q2

M
0
PP3 p2
q3
0
,
p7 p6 p5 p4 p3

Product is: p7,p6,..p0

Multiplicand is shifted by displacing it through an array of adders.

Combinatorial array multiplier
(contd..)
Combinatorial array multipliers are:
Extremely inefficient.
Have a high gate count for multiplying numbers of practical size such as 32-
bit or 64-bit numbers.
Perform only one function, namely, unsigned integer product.

Improve gate efficiency by using a mixture of

combinatorial array techniques and sequential
techniques requiring less combinational logic.
Sequential multiplication
Recall the rule for generating partial products:
If the ith bit of the multiplier is 1, add the appropriately shifted multiplicand
to the current partial product.
Multiplicand has been shifted left when added to the partial product.

However, adding a left-shifted multiplicand to an

unshifted partial product is equivalent to adding an
unshifted multiplicand to a right-shifted partial
product.
 RegisterA(initially0)

Shiftright

C an a0 q q
1 n 1 0

MultiplierQ
Add/Noadd
control

n-bit
Adder
MUX Control
sequencer

0 0

m m0
n 1

MultiplicandM
 M
1101
Initialconfiguration
0 0000 1011
C A Q
0 1101 1011 Add
Shift Firstcycle
0 0110 1101

1 0011 1101 Add

Shift Secondcycle
0 1001 1110

0 1001 1110 Noadd

Shift Thirdcycle
0 0100 1111

1 0001 1111 Add

Shift Fourthcycle
0 1000 1111

Product
Signed Multiplication
Considering 2s-complement signed operands, what will happen to (-
13)(+11) if following the same method of unsigned multiplication?

1 0 0 1 1 13
0 1 0 1 1 ( + 11)

1 1 1 1 1 1 0 0 1 1

1 1 1 1 1 0 0 1 1
Signextensionis
showninblue 0 0 0 0 0 0 0 0

1 1 1 0 0 1 1

0 0 0 0 0 0

1 1 0 1 1 1 0 0 0 1 143

Signextensionofnegativemultiplicand.
Signed Multiplication
For a negative multiplier, a straightforward solution is
to form the 2s-complement of both the multiplier and
the multiplicand and proceed as in the case of a
positive multiplier.
This is possible because complementation of both
operands does not change the value or the sign of the
product.
A technique that works equally well for both negative
and positive multipliers Booth algorithm.
Booth Algorithm
Consider in a multiplication, the multiplier is positive
0011110, how many appropriately shifted versions of
the multiplicand are added in a standard procedure?

0 1 0 1 1 0 1
0 0 +1 +1 + 1+1 0
0 0 0 0 0 0 0
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0
Booth Algorithm
Since 0011110 = 0100000 0000010, if we use the
expression to the right, what will happen?
0 1 0 1 1 0 1
0 +1 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
2'scomplementof
1 1 1 1 1 1 1 0 1 0 0 1 1
themultiplicand
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0
Booth

Algorithm
In general, in the Booth scheme, -1 times the shifted multiplicand is
selected when moving from 0 to 1, and +1 times the shifted
multiplicand is selected when moving from 1 to 0, as the multiplier
is scanned from right to left.
0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0

0 +1 1 +1 0 1 0 +1 0 0 1 +1 1 + 1 0 1 0 0

Boothrecodingofamultiplier.
Booth Algorithm
0 1 1 0 1 ( + 13) 0 1 1 0 1
X1 1 0 1 0 6 0 1 +1 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 0 78

Boothmultiplicationwithanegativemultiplier.
Booth Algorithm
Multiplier
V ersionofmultiplicand
selectedbybiti
Bit i Bit i 1

0 0 0 XM
0 1 + 1 XM
1 0 1 XM
1 1 0 XM

Boothmultiplierrecodingtable.
Booth Algorithm
Best case a long string of 1s (skipping over 1s)
Worst case 0s and 1s are alternating
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Worstcase
multiplier
+1 1 +1 1 +1 1 +1 1 +1 1 +1 1 +1 1 +1 1

1 1 0 0 0 1 0 1 1 0 1 1 1 1 0 0
Ordinary
multiplier
0 1 0 0 + 1 1 +1 0 1 +1 0 0 0 1 0 0

0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1
Good
multiplier
0 0 0 +1 0 0 0 0 1 0 0 0 +1 0 0 1
Bit-Pair Recoding of Multipliers
Bit-pair recoding halves the maximum number of
summands (versions of the multiplicand).
Signextension Implied0torightofLSB
1 1 1 0 1 0 0

0 0 1 +1 1 0

0 1 2

(a)ExampleofbitpairrecodingderivedfromBoothrecoding
Bit-Pair Recoding of Multipliers
Multiplierbitpair Multiplierbitontheright Multiplicand
selectedatposition i
i+1 i i1

0 0 0 0 XM
0 0 1 +1 XM
0 1 0 +1 XM
0 1 1 +2 XM
1 0 0 2 XM
1 0 1 1 XM
1 1 0 1 XM
1 1 1 0 XM

(b)Tableofmultiplicandselectiondecisions
Bit-Pair Recoding of Multipliers 0 1 1 0 1
0 1 +1 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 1 1 0 1 ( + 13) 0 0 0 0 0 0
1 1 0 1 0 6 1 1 1 0 1 1 0 0 1 0 78

0 1 1 0 1
0 1 2
1 1 1 1 1 0 0 1 1 0
1 1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 0

Figure6.15.Multiplicationrequiringonlyn/2summands.39
Carry-Save Addition of Summands
CSA speeds up the addition process.

P7 P6 P5 P4 P3 P2 P1 40P0
 Carry-Save Addition of Summands(Cont.,)

P7 P6 P5 P4 P3 P2 P1 P0
Carry-Save Addition of
Summands(Cont.,)
Consider the addition of many summands, we can:
Group the summands in threes and perform carry-save addition on
each of these groups in parallel to generate a set of S and C vectors in
one full-adder delay
Group all of the S and C vectors into threes, and perform carry-save
addition on them, generating a further set of S and C vectors in one
more full-adder delay
Continue with this process until there are only two vectors remaining
They can be added in a RCA or CLA to produce the desired product
Carry-Save Addition of Summands
1 0 1 1 0 1 (45) M

X 1 1 1 1 1 1 (63) Q

1 0 1 1 0 1 A
1 0 1 1 0 1 B

1 0 1 1 0 1 C
1 0 1 1 0 1 D
1 0 1 1 0 1 E
1 0 1 1 0 1 F

1 0 1 1 0 0 0 1 0 0 1 1 (2,835) Product

Figure6.17.AmultiplicationexampleusedtoillustratecarrysaveadditionasshowninFigure6.18.
 1 0 1 1 0 1 M

x 1 1 1 1 1 1 Q

1 0 1 1 0 1 A

1 0 1 1 0 1 B

1 0 1 1 0 1 C

1 1 0 0 0 0 1 1 S
1
0 0 1 1 1 1 0 0 C
1

1 0 1 1 0 1 D
1 0 1 1 0 1 E
1 0 1 1 0 1 F

1 1 0 0 0 0 1 1 S
2
0 0 1 1 1 1 0 0 C
2

1 1 0 0 0 0 1 1 S1

0 0 1 1 1 1 0 0 C
1
1 1 0 0 0 0 1 1 S2
1 1 0 1 0 1 0 0 0 1 1 S
3
0 0 0 0 1 0 1 1 0 0 0 C3
0 0 1 1 1 1 0 0 C2
0 1 0 1 1 1 0 1 0 0 1 1 S4
+ 0 1 0 1 0 1 0 0 0 0 0 C
4
1 0 1 1 0 0 0 1 0 0 1 1 Product

Figure6.18. ThemultiplicationexamplefromFigure6.17performedusing
carrysaveaddition.
Manual Division
21 10101
13 274 1101 100010010
26 1101
14 10000
13 1101
1 1110
1101
1

Longhanddivisionexamples.
Longhand Division Steps
Position the divisor appropriately with respect to the
dividend and performs a subtraction.
If the remainder is zero or positive, a quotient bit of 1
is determined, the remainder is extended by another
bit of the dividend, the divisor is repositioned, and
another subtraction is performed.
If the remainder is negative, a quotient bit of 0 is
determined, the dividend is restored by adding back
the divisor, and the divisor is repositioned for another
subtraction.
Circuit Arrangement
Shiftleft

an an1 a0 qn1 q0
DividendQ
A Quotient
Setting

N+1bit Add/Subtract
adder
Control
Sequencer

0 mn1 m0

DivisorM

Figure6.21.Circuitarrangementforbinarydivision.
Restoring Division
Shift A and Q left one binary position
Subtract M from A, and place the answer back in A
If the sign of A is 1, set q0 to 0 and add M back to A
(restore A); otherwise, set q0 to 1
Repeat these steps n times
Examples Initially 0

Shift
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1 0 0 0

0 0 0
Subtract 1 1 1 0 1 Firstcycle
Set q0 1 1 1 1 0
Restore 1 1
0 0 0 0 1 0 0 0 0
1 0 Shift 0 0 0 1 0 0 0 0
1 1 1 0 0 0 Subtract 1 1 1 0 1
1 1 Set q0 1 1 1 1 1 Secondcycle
Restore 1 1
1 0 0 0 0 1 0 0 0 0 0
Shift 0 0 1 0 0 0 0 0
Subtract 1 1 1 0 1
Set q0 0 0 0 0 1 Thirdcycle

Shift 0 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1 0 0 1
Set q0 1 1 1 1 1 Fourthcycle
Restore 1 1
0 0 0 1 0 0 0 1 0

Remainder Quotient

Figure6.22.Arestoringdivisionexample.
Nonrestoring Division
Avoid the need for restoring A after an
unsuccessful subtraction.
Any idea?
Step 1: (Repeat n times)
If the sign of A is 0, shift A and Q left one bit position and
subtract M from A; otherwise, shift A and Q left and add M
to A.
Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.
Step2: If the sign of A is 1, add M to A
 Examples Initially

Shift
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1 0 0 0

0 0 0 Firstcycle
Subtract 1 1 1 0 1
Set q 0 1 1 1 1 0 0 0 0 0

Shift 1 1 1 0 0 0 0 0
Add 0 0 0 1 1 Secondcycle

Set q 1 1 1 1 1 0 0 0 0
0

Shift 1 1 1 1 0 0 0 0
1 1 1 1 1 Add 0 0 0 1 1 Thirdcycle
Restore
0 0 0 1 1 Set q 0 0 0 0 1 0 0 0 1
remainder 0
Add 0 0 0 1 0
Remainder Shift 0 0 0 1 0 0 0 1
Subtract 1 1 1 0 1 Fourthcycle
Set q 1 1 1 1 1 0 0 1 0
0

Quotient
Anonrestoringdivisionexample.
 If b is a binary vector, then we have seen that it can be interpreted as
an unsigned integer by:
V(b)=b31.231+b30.230+bn3.229+....+b1.21+b0.20

This vector has an implicit binary point to its immediate right:

b31b30b29....................b1b0.implicitbinarypoint

Suppose if the binary vector is interpreted with the implicit binary point is
just left of the sign bit:
implicitbinarypoint .b31b30b29....................b1b0

The value of b is then given by:

V(b)=b31.21+b30.22+b29.23+....+b1.231+b0.232
The value of the unsigned binary fraction is:
V(b)=b31.21+b30.22+b29.23+....+b1.231+b0.232

The range of the numbers represented in this format is:

0 V (b) 1 2 32 0.9999999998

In general for a n-bit binary fraction (a number with an assumed binary

point at the immediate left of the vector), then the range of values is:

0 V (b) 1 2 n
Previous representations have a fixed point. Either the point is to the immediate
right or it is to the immediate left. This is called Fixed point representation.
Fixed point representation suffers from a drawback that the representation can
only represent a finite range (and quite small) range of numbers.

A more convenient representation is the scientific representation, where

the numbers are represented in the form:

x m1 .m2 m3 m4 b e
Components of these numbers are:

Mantissa (m), implied base (b), and exponent (e)

A number such as the following is said to have 7 significant digits
e
x 0.m1 m2 m 3 m4 m 5 m6 m7 b

Fractions in the range 0.0 to 0.9999999 need about 24 bits of precision

(in binary). For example the binary fraction with 24 1s:
111111111111111111111111=0.9999999404

Not every real number between 0 and 0.9999999404 can be represented

by a 24-bit fractional number.
The smallest non-zero number that can be represented is:

000000000000000000000001=5.96046x108

Every other non-zero number is constructed in increments of this value.

In a 32-bit number, suppose we allocate 24 bits to represent a fractional
mantissa.
Assume that the mantissa is represented in sign and magnitude format,
and we have allocated one bit to represent the sign.
We allocate 7 bits to represent the exponent, and assume that the
exponent is represented as a 2s complement integer.
There are no bits allocated to represent the base, we assume that the
base is implied for now, that is the base is 2.
Since a 7-bit 2s complement number can represent values in the range
-64 to 63, the range of numbers that can be represented is:

0.0000001x264<=|x|<=0.9999999x263

In decimal representation this range is:

0.5421x1020<=|x|<=9.2237x1018
 1724

SignExponentFractionalmantissa
bit
24-bit mantissa with an implied binary point to the immediate left
7-bit exponent in 2s complement form, and implied base is 2.
 Consider the number: x=0.0004056781x1012

If the number is to be represented using only 7 significant mantissa digits,

the representation ignoring rounding is: x=0.0004056x1012

If the number is shifted so that as many significant digits are brought into
7 available slots:
x=0.4056781x109=0.0004056x1012

Exponent of x was decreased by 1 for every left shift of x.

A number which is brought into a form so that all of the available mantissa
digits are optimally used (this is different from all occupied which may
not hold), is called a normalized number.

Same methodology holds in the case of binary mantissas

0001101000(10110)x28=1101000101(10)x25
A floating point number is in normalized form if the most significant
1 in the mantissa is in the most significant bit of the mantissa.
All normalized floating point numbers in this system will be of the form:

0.1xxxxx.......xx

Range of numbers representable in this system, if every number must be

normalized is:
0.5x264<=|x|<1x263
 The procedure for normalizing a floating point number is:
Do (until MSB of mantissa = = 1)
Shift the mantissa left (or right)
Decrement (increment) the exponent by 1
end do

Applying the normalization procedure to: .000111001110....0010x262

gives: .111001110........x265

But we cannot represent an exponent of 65, in trying to normalize the

number we have underflowed our representation.
Applying the normalization procedure to: 1.00111000............x263
gives: 0.100111..............x264

This overflows the representation.

So far we have assumed an implied base of 2, that is our floating point
numbers are of the form:
x=m2e

If we choose an implied base of 16, then:

x=m16e

Then:
y=(m.16).16e1(m.24).16e1=m.16e=x

Thus, every four left shifts of a binary mantissa results in a decrease of 1

in a base 16 exponent.
Normalization in this case means shifting the mantissa until there is a 1 in
the first four bits of the mantissa.
Rather than representing an exponent in 2s complement form, it turns out to be
more beneficial to represent the exponent in excess notation.
If 7 bits are allocated to the exponent, exponents can be represented in the range of
-64 to +63, that is:
-64 <= e <= 63
Exponent can also be represented using the following coding called as excess-64:

E = Etrue + 64
In general, excess-p coding is represented as:
E = Etrue + p

True exponent of -64 is represented as 0

0 is represented as 64
63 is represented as 127

This enables efficient comparison of the relative sizes of two floating point numbers.
IEEE Floating Point notation is the standard representation in use. There are two
representations:
- Single precision.
- Double precision.
Both have an implied base of 2.
Single precision:
- 32 bits (23-bit mantissa, 8-bit exponent in excess-127 representation)
Double precision:
- 64 bits (52-bit mantissa, 11-bit exponent in excess-1023 representation)
Fractional mantissa, with an implied binary point at immediate left.

Sign Exponent Mantissa

1 8 or 11 23 or 52
Floating point numbers have to be represented in a normalized form to
maximize the use of available mantissa digits.
In a base-2 representation, this implies that the MSB of the mantissa is
always equal to 1.
If every number is normalized, then the MSB of the mantissa is always 1.
We can do away without storing the MSB.
IEEE notation assumes that all numbers are normalized so that the MSB
of the mantissa is a 1 and does not store this bit.
So the real MSB of a number in the IEEE notation is either a 0 or a 1.
The values of the numbers represented in the IEEE single precision
notation are of the form:
(+,-) 1.M x 2(E - 127)
The hidden 1 forms the integer part of the mantissa.
Note that excess-127 and excess-1023 (not excess-128 or excess-1024) are used
to represent the exponent.
 In the IEEE representation, the exponent is in excess-127 (excess-1023)
notation.
The actual exponents represented are:

-126 <= E <= 127 and -1022 <= E <= 1023

not
-127 <= E <= 128 and -1023 <= E <= 1024

This is because the IEEE uses the exponents -127 and 128 (and -1023 and
1024), that is the actual values 0 and 255 to represent special conditions:
- Exact zero
- Infinity
Addition:
3.1415 x 108 + 1.19 x 106 = 3.1415 x 108 + 0.0119 x 108 = 3.1534 x 108
Multiplication:
3.1415 x 108 x 1.19 x 106 = (3.1415 x 1.19 ) x 10(8+6)

Division:
3.1415 x 108 / 1.19 x 106 = (3.1415 / 1.19 ) x 10(8-6)

Biased exponent problem:

If a true exponent e is represented in excess-p notation, that is as e+p.
Then consider what happens under multiplication:

a. 10(x + p) * b. 10(y + p) = (a.b). 10(x + p + y +p) = (a.b). 10(x +y + 2p)

Representing the result in excess-p notation implies that the exponent

should be x+y+p. Instead it is x+y+2p.
Biases should be handled in floating point arithmetic.
Floating point arithmetic: ADD/SUB
rule
Choose the number with the smaller exponent.
Shift its mantissa right until the exponents of both the
numbers are equal.
Add or subtract the mantissas.
Determine the sign of the result.
Normalize the result if necessary and truncate/round
to the number of mantissa bits.

Note: This does not consider the possibility of overflow/underflow.

Floating point arithmetic: MUL rule
Add the exponents.
Subtract the bias.
Multiply the mantissas and determine the sign of the
result.
Normalize the result (if necessary).
Truncate/round the mantissa of the result.
Floating point arithmetic: DIV rule
Subtract the exponents
Add the bias.
Divide the mantissas and determine the sign of the
result.
Normalize the result if necessary.
Truncate/round the mantissa of the result.

Note: Multiplication and division does not require alignment of the

mantissas the way addition and subtraction does.
While adding two floating point numbers with 24-bit mantissas, we shift
the mantissa of the number with the smaller exponent to the right until
the two exponents are equalized.
This implies that mantissa bits may be lost during the right shift (that is,
bits of precision may be shifted out of the mantissa being shifted).
To prevent this, floating point operations are implemented by keeping
guard bits, that is, extra bits of precision at the least significant end
of the mantissa.
The arithmetic on the mantissas is performed with these extra bits of
precision.
After an arithmetic operation, the guarded mantissas are:
- Normalized (if necessary)
- Converted back by a process called truncation/rounding to a 24-bit
mantissa.
Truncation/rounding
Straight chopping:
The guard bits (excess bits of precision) are dropped.

Von Neumann rounding:

If the guard bits are all 0, they are dropped.
However, if any bit of the guard bit is a 1, then the LSB of the retained bit is
set to 1.
Rounding:
If there is a 1 in the MSB of the guard bit then a 1 is added to the LSB of the
retained bits.
Rounding
Rounding is evidently the most accurate truncation
method.
However,
Rounding requires an addition operation.
Rounding may require a renormalization, if the addition operation de-
normalizes the truncated number.
0.111111100000 rounds to 0.111111 + 0.000001
=1.000000 which must be renormalized to 0.100000

IEEE uses the rounding method.