1368 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 30, NO.

9, SEPTEMBER 2022

Transactions Brief
An Efficient Reconfigurable Encoder for the IEEE 1901 Standard
Yuxing Chen , Hangxuan Cui , and Zhongfeng Wang
Abstract— The IEEE 1901 standard for power line communica- LDPC-CC encoders for a single code rate are presented in [10]–[12].
tion (PLC) enables simple connection among Internet of Things devices. The LDPC-CC encoder for 1/2 code rate is described in [10]
The forward error correction (FEC) codes specified in the IEEE
and improved single-rate encoders with a higher throughput-to-area
1901 standard include low-density parity-check convolutional codes
(LDPC-CCs) and Reed-Solomon convolutional concatenated (RSCC) ratio (TAR) are proposed in [11] and [12]. However, not an encoder
codes. This work introduces an efficient reconfigurable encoder in fully compatible with the IEEE 1901 standard has been proposed.
full compliance with the IEEE 1901 standard. First, we propose a The design of standard-compatible encoders is the topic of ongoing
reconfigurable LDPC-CC encoder to fulfill the multirate requirement works. Lots of encoders (only encoders, no decoders) compatible with
and improve the architecture by fine-tuned parallelization, which takes
full advantage of the characteristics of the codeword structure. Then, established standards or potentially for next-generation standards are
for area reduction, the optimization regarding the RSCC encoder is proposed recently, for example, [1], [3], [13].
extensively exploited. Moreover, the commonality between the encoders In this work, we design an power- and area-efficient reconfigurable
is discovered, and some circuitries are shared to reduce the hardware encoder in full compliance with the IEEE 1901 standard. The
complexity. Equipped with these techniques, an efficient reconfigurable
encoder for the IEEE 1901 standard is developed and implemented with
contributions are summarized as follows.
28-nm technology. Implementation results demonstrate that the proposed 1) LDPC-CC encoder: A reconfigurable LDPC-CC encoder sup-
encoder can meet the throughput requirement of the IEEE 1901 standard porting all required code rates is proposed. By exploiting
and is both power- and area-efficient. the features of the IEEE 1901 standard, we improve the
Index Terms— Fine-tuning, IEEE 1901 standard, paralleliza- encoder by fine-tuned parallelization techniques. The imple-
tion, power line communication (PLC), reconfigurable hardware. mentation result shows that both the speed and the area are
improved.
I. I NTRODUCTION 2) RSCC encoder: For the RS encoder, we utilize common subex-
Standard-compatible forward error correction (FEC) coding imple- pression sharing (CSS) techniques to minimize the number of
mentations have been in high interest due to their practical value. XOR -gates. The number of XOR -gates is reduced by more than
Existing works focus on FEC designs for wireless communication 70%. In terms of the CC encoder, the registers in the puncturer
standards, for example, low-density parity-check encoders/decoders are reduced by 28.6% through step-by-step optimizations.
for IEEE 802.11 [1], 5G [2], and polar encoders/decoders 3) Reconfigurable encoder: A first reconfigurable multirate
for 5G [3], [4]. encoder complying with the IEEE 1901 standard is proposed
As for the power line communication (PLC), IEEE has released and optimized. Compared with the combination of individual
its PLC protocol, the IEEE 1901 standard [5], which has been encoders, the hardware complexity of the proposed reconfig-
widely applied in mainstream PLC devices [6]. PLC does not require urable encoder is improved.
complicated cabling and features in low-cost deployment [7]. Besides, The rest of the brief is organized as follows. Section II introduces
it is a simple way to link a large variety of Internet of Things the background. In Section III, the detailed design of the proposed
devices for the usage of sensing and controlling, in enterprise or encoder is described. Section IV presents implementation results.
home environments [8]. At last, Section V draws the conclusion.
The FEC codes specified in the IEEE 1901 standard include
low-density parity-check convolutional codes (LDPC-CCs) and
II. BACKGROUND
Reed-Solomon convolutional concatenated (RSCC) codes [5]. The
outer and inner codes of the RSCC code are the Reed-Solomon (RS) A. Overview of the LDPC-CC Encoder
code and the convolutional code (CC), respectively. Apart from vari- The codeword u of an LDPC-CC is denoted as [u(0),
ous codeword types, multiple code rates are required. The LDPC-CC u(1), . . . , u(t), . . .], where t is the time index. Each u(t) is a
needs to support four code rates, and the RSCC is required to support c-bit symbol, that is, u(t) = [u 0 (t), u 1 (t), . . . , u (c−1) (t)]. u(t) is
seven code rates [5]. Thus, to design FEC coding implementations in composed of c − b information bits, w(t), and b parity bits, p(t).
full support of the IEEE 1901 standard is challenging. The multirate The code rate R is (c − b/c). The memory size of the encoder
decoder for the IEEE 1901 standard LDPC-CC was introduced [9]. is denoted as m s . The LDPC-CC is with time period t p . The
time stamp ts is calculated by ts = t mod t p , where mod denotes
Manuscript received 11 January 2022; revised 29 March 2022 and 26 April the modulo operation. For the LDPC-CC specified in the IEEE
2022; accepted 19 May 2022. Date of publication 30 May 2022; date of
current version 1 September 2022. This work was supported in part by the 1901 standard, t p = 3, c ∈ {2, 3, 4, 5}, and b = 1, that is,
National Natural Science Foundation of China under Grant 62174084 and u(t) = [w0 (t), w1 (t), . . . , w(c−2) (t), p(t)]. The polynomial form of
Grant 62104097, in part by the High-Level Personnel Project of Jiangsu wi (t) and p(t) is Wi (D) and P(D), respectively. The calculation of
Province under Grant JSSCBS20210034, and in part by the Key Research P(D) for c = 2 defined in IEEE 1901 standard is
Plan of Jiangsu Province of China under Grant BE2019003-4. (Corresponding
t
author: Zhongfeng Wang.) Q Ws (D) W0 (D)
The authors are with the School of Electronic Science and Engineer- P (D) = 0
t (1)
ing, Nanjing University, Nanjing 210023, China (e-mail: yxing.chen@ Q Ps (D)
outlook.com; [email protected]; [email protected]).
t t
Color versions of one or more figures in this article are available at where delay polynomials Q Ws (D), Q Ps (D) are listed in Table I. The
0
https://doi.org/10.1109/TVLSI.2022.3177239.
Digital Object Identifier 10.1109/TVLSI.2022.3177239 calculation of P(D) for c ∈ {3, 4, 5} can be referred to [5]. Fig. 1(a)
1063-8210 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 30, NO. 9, SEPTEMBER 2022 1369

TABLE I
D ELAY P OLYNOMIALS Q tWs (D), Q tPs (D) OF THE LDPC-CC W ITH c = 2
0
S PECIFIED IN THE IEEE 1901 S TANDARD

Fig. 2. Puncturing process in the IEEE 1901 standard. (a) Rcc = 1/2.
(b) Rcc = 2/3. (c) Rcc = 3/4.

TABLE III
B INARY VALUES OF CR U NDER D IFFERENT C ODE R ATES

III. P ROPOSED E NCODING A RCHITECTURE

A. LDPC-CC Encoder Design

We first design an encoder to support all code rates of the
LDPC-CCs specified in IEEE 1901 standard. By exploiting the
commonality of the delay polynomials, we propose a reconfigurable
LDPC-CC encoder to meet the multirate need, as shown in Fig. 3(a).
The shift registers in the dashed box from left to right are in
control of the generation of p p (t), pw3 (t), pw2 (t), pw1 (t), and
Fig. 1. (a) Rate 1/2 LDPC-CC encoder. (b) RS encoder. (c) Shift registers
of the CC encoder. pw0 (t), respectively. The signal cr = {cr2 , cr1 , cr0 } together with the
AND -gates are designed to support multiple code rates. The binary
TABLE II values of cr under different code rates are listed in Table III. For
P UNCTURE PATTERNS IN IEEE 1901 S TANDARD example, when the code rate is 2/3, cr equals 001. Since cr2 and
cr1 are zero, pw3 (t) and pw2 (t) are also set to zero. pw1 (t) is
produced by the shift registers, because cr0 = 1. Besides, p p (t)
and pw0 (t) are outputted from the registers. Therefore, p(t) equals
pw0 (t) + pw1 (t) + p p (t). The termination of the encoder is done by
adding zero-value information bits, which leads to a stable encoder
state [5].
Moreover, we noticed two distinctive attributes of the LDPC-CC
encoder for the IEEE 1901 standard: 1) the registers are the most
area-consuming and 2) the time period is 3, which is relatively
illustrates a 1/2-rate LDPC-CC encoder. It consists of shift registers small. Based on these attributes, we optimize the encoder by fine-
for w0 (t) (SRw0 ), shift registers for p(t) (SR p ), multiplexers, and tuned parallelization. The fine-tuned parallelization features in the
adders. SRw0 (SR p ) dominates the generation of pw0 (t) ( p p (t)). The meticulous selection of the parallelization factor of the unfolding
delay polynomials determine the output patterns of the multiplexers. technique [14], and the hardware elimination. For circuits without
delays and multiplexers, unfolding performs the same as duplication.
B. Overview of the RSCC Encoder Thus, we mainly take the circuits involving delays and multiplexers
Fig. 1(b) shows the RS (255, 239) encoder over GF(28 ), where GF into concern. The detailed example for the fine-tuned parallelization
is the abbreviation for Galois field. It consists of the multiplication of SRw0 is provided below. The start point, the input of the first
module, the shift registers module, and the selector module. The register of SRw0 , is denoted as node A 0 . The endpoints, the outputs
initial values for registers are zeros. The encoding process occupies of the two multiplexers of SRw0 from left to right, are denoted as B 0
255 clock cycles. In the first 239 clock cycles, signals sfb = sout = 1. and B 1 , respectively. The outputs of the 62th, 143th, 160th, 185th,
Therefore, information symbols are delivered to the multiplication 196th, and 214th register of SRw0 are denoted as A 1 , A 2 , A 3 , A 4 , A 5 ,
module and outputted. In the last 16 cycles, sfb = sout = 0. The data and A 6 , respectively. First, the block diagram is transformed into the
in the shift registers module are serially shifted out as parity symbols. data-flow graph (DFG), as shown in Fig. 3(b). Second, we select the
Fig. 1(c) draws the shift registers of the CC encoder (SRcc ) in parallelization factor as t p and unfold the DFG. The unfolded DFG is
IEEE 1901 standard. In each cycle, the input is one information bit, shown in Fig. 3(c). As can be seen, the multiplexers are eliminated
and the outputs (y0 (t) and y1 (t)) are coded bits. The outputs of due to the meticulous selection of the parallelization factor. Third,
SRcc is delivered to a puncturer, the patterns of which are listed we discover that the D flip-flops in red dashed boxes are out of
in Table II. If the puncture value of a bit equals 0, it is deleted utilization. Therefore, we remove those D flip-flops for improvement
(puntured). Otherwise, it is reserved. The code rate of the CC encoder in hardware complexity. At last, the DFG is converted back to the
is written as Rcc . Fig. 2 illustrates the puncturing process for CCs of block diagram, as shown in the rightmost dashed box of Fig. 3(d).
Rcc = 1/2, 2/3, and 3/4. Similarly, we can obtain the fine-tuned parallelized circuits for the

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1370 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 30, NO. 9, SEPTEMBER 2022

Fig. 3. (a) Proposed reconfigurable LDPC-CC encoder. (b) DFG of SRw0 . (c) Unfolded DFG. (d) Fine-tuned parallelized LDPC-CC encoder.

TABLE IV
C OMPARISON B ETWEEN THE P ROPOSED R ECONFIGURABLE LDPC-CC E NCODER W ITH AND W ITHOUT F INE -T UNED PARALLELIZATION

other shift registers. Fig. 3(d) illustrates the fine-tuned parallelized TABLE V
LDPC-CC encoder. C OMPARISONS W ITH O THER LDPC-CC E NCODERS
The number of XOR-gates, AND-gates, 3-to-1 multiplexers, D flip-
flops are defined as NXOR , NAND , NMUX , and NDFF , respectively.
The critical paths are marked with dashed blue lines in Fig. 3, and
the critical path delay is denoted as Tc . The maximum throughput θm
−1
is calculated by (5J /Tc ), where J is the parallelization factor. θm is
the reciprocal of θm , whose meaning is the processing time required
per bit. We regard TAR as a figure-of-merit, which is calculated
by (θm /Area). A comparison between the proposed reconfigurable
design with and without fine-tuned parallelization is shown in
Table IV.1 The improved reconfigurable LDPC-CC encoder reduces
the area by 10.0% and enhances the TAR by 323.3%, compared
proposed encoder improves the TAR by more than 105.3%, and the
with the design without fine-tuned parallelization. Table V∗ compares
TARu by more than 21.0%.
the proposed encoder with previous designs. Areau denotes unit
area, calculated by (Area/m s ). TARu is the unit TAR, calculated by
B. RSCC Encoder Design
(θm /Areau ). The proposed fine-tuned parallelized encoder supports
The Galois field multiplication dominates the majority of arith-
various code rates, while other encoders are 1/2-rate. Besides, the
metic operations in the RSCC encoder. We utilize CSS techniques [1]
to minimize the number of XOR-gates. Table VI lists the number of
1 The implementation details will be discussed in Section IV. XOR -gates before and after CSS. The number of XOR -gates is also

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 30, NO. 9, SEPTEMBER 2022 1371

TABLE VI
N UMBER OF XOR -G ATES B EFORE AND A FTER CSS

Fig. 5. Detailed circuits of the shift registers module in the RS encoder.

can be removed for a better area. Furthermore, when taking into

all code rates except 6/7 into concern, data from D flip-flops 2, 6,
9, and 13 are not selected as the output. However, when the code
rate is 6/7, data from D flip-flops 6 and 9 are chosen as the output
in certain cycles. To handle this issue, the wa is modified to 000,
001, 010, 100, 101, and 110. Thus, the sel changes to 0, 1, 3, 5,
8, 11, and 12, in which 6 and 9 are excluded. The proposed design
is shown in Fig. 4(b), where the 3-to-7 decoder maintains the same
and, thus, is not drawn. The modified wa and sel are denoted as wam
and selm , the values of which are listed in Table VII. Compared with
the previous puncturer [16], the D flip-flops are reduced by 28.6%.
Besides, the multiplexer is simpler.

Fig. 4. (a) Original puncturer. (b) Proposed puncturer. C. Reconfigurable Encoder Design
The IEEE 1901 standard requires both LDPC-CC and RSCC
TABLE VII as channel coding schemes. To meet the need, a straightforward
A DDRESSING M ODES OF THE P UNCTURER implementation is to combine the LDPC-CC and RSCC encoders.
Differently, we propose the codesign method of individual encoders.
The proposed method reduces the hardware complexity by circuitries
sharing. The RS encoder and the LDPC-CC encoder both contain D
flip-flops. However, in the RS encoder, the adders and D flip-flops are
over GF(28 ). To explore the commonality, we investigate the detailed
circuits of the shift registers module of the RS encoder, as shown in
Fig. 5. It can be seen that the shift registers module consists of 16
8-bit D flip-flops and 15 GF(28 ) adders in between them. An 8-bit D
flip-flop is composed of eight 1-bit D flip-flops, and a GF(28 ) adder
is made up of eight GF(2) adders. To reduce the overall area, the first
to 16th 1-bit registers for w0 (3k), w0 (3k + 1), w0 (3k + 2), w1 (3k),
w1 (3k + 1), w1 (3k + 2), w2 (3k + 1), and w2 (3k + 2) of LDPC-CC
encoder are reused for the RS encoder, in which the GF(2) adders are
normalized by dividing the number of the original XOR-gates. It can inserted. When the reconfigurable encoder is in the LDPC-CC mode,
be seen that more than 70% of the XOR-gates are saved in total, the input of the multiplication module is selected as zero. Therefore,
compared with [15]. the outputs of the adders are the data from the Q-ports of the D
The puncturer has three parts, the 3-to-7 decoder, the buffer, and flip-flops. Through the proposed codesign method, all registers in
the multiplexer, as shown in Fig. 4(a). The inputs (outputs) of the the RS encoder cost no hardware overhead. Thus, the total hardware
3-to-7 decoder are binary (one-hot). If wa = 000, only the topmost complexity is reduced.
output values 1. Thus, only D flip-flops 0 and 1 are enabled. The
outputs from the CC encoder in Fig. 1(c), y0 (t) and y1 (t), are taken IV. I MPLEMENTATION R ESULTS
as inputs to the buffer. The architecture of the puncturer assumes The hardware architecture is described in RTL and synthesized
two different clock sources. One clock source is the input data clock under the TSMC 28-nm CMOS technology using the Synopsys
(denoted as clkpi ), and the other is the output data clock (denoted as Design Compiler. The synthesis results of the encoders in compliance
clkpo ). The clock ports of the D flip-flops in the buffer are connected with the IEEE 1901 standard are shown in Table VIII, where f
to clkpi . The sel signal varies each clkpo cycle. The clock frequency of denotes the clock frequency, θ is the encoding throughput, and L&R
clkpo is 1/Rcc of that of clkpi . The traditional puncturer needs 14 D denotes the combination of the LDPC-CC and RSCC encoders. The
flip-flops and a 14-to-1 multiplexer for CC with 7/8 code rate [16]. average time to process a bit is denoted as Tb and is calculated by
We optimize the puncturer step by step as follows. First, the Tb = (1/θ). The area–time product (ATP) and power–time prod-
addressing modes for each code rate are carefully investigated, uct (PTP) is defined as Area × Tb and Power × Tb , respectively. For
as listed in Table VII. In the original addressing mode, the data from a fair comparison and the speed requirement of IEEE 1901 standard
D flip-flops 2 and 13 are not chosen as the output. Therefore, they (500 Mbps), the throughput is set as 600 Mbps. The throughputs of

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1372 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 30, NO. 9, SEPTEMBER 2022

TABLE VIII power-efficient. The proposed reconfigurable encoder provides a good

S YNTHESIS R ESULTS OF THE IEEE 1901 S TANDARD E NCODERS reference for the design and application of PLC devices.

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